?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.1.16
[linux/fpc-iii.git] / sound / pci / ctxfi / cthw20k2.c
blob955ad871e9a861dfd444e5ec85f4b9736548778e
1 /**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthw20k2.c
9 *
10 * @Brief
11 * This file contains the implementation of hardware access method for 20k2.
12 *
13 * @Author Liu Chun
14 * @Date May 14 2008
15 *
16 */
17
18 #include <linux/types.h>
19 #include <linux/slab.h>
20 #include <linux/pci.h>
21 #include <linux/io.h>
22 #include <linux/string.h>
23 #include <linux/kernel.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include "cthw20k2.h"
27 #include "ct20k2reg.h"
28
29 #if BITS_PER_LONG == 32
30 #define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */
31 #else
32 #define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */
33 #endif
34
35 struct hw20k2 {
36 struct hw hw;
37 /* for i2c */
38 unsigned char dev_id;
39 unsigned char addr_size;
40 unsigned char data_size;
41
42 int mic_source;
43 };
44
45 static u32 hw_read_20kx(struct hw *hw, u32 reg);
46 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
47
48 /*
49 * Type definition block.
50 * The layout of control structures can be directly applied on 20k2 chip.
51 */
52
53 /*
54 * SRC control block definitions.
55 */
56
57 /* SRC resource control block */
58 #define SRCCTL_STATE 0x00000007
59 #define SRCCTL_BM 0x00000008
60 #define SRCCTL_RSR 0x00000030
61 #define SRCCTL_SF 0x000001C0
62 #define SRCCTL_WR 0x00000200
63 #define SRCCTL_PM 0x00000400
64 #define SRCCTL_ROM 0x00001800
65 #define SRCCTL_VO 0x00002000
66 #define SRCCTL_ST 0x00004000
67 #define SRCCTL_IE 0x00008000
68 #define SRCCTL_ILSZ 0x000F0000
69 #define SRCCTL_BP 0x00100000
70
71 #define SRCCCR_CISZ 0x000007FF
72 #define SRCCCR_CWA 0x001FF800
73 #define SRCCCR_D 0x00200000
74 #define SRCCCR_RS 0x01C00000
75 #define SRCCCR_NAL 0x3E000000
76 #define SRCCCR_RA 0xC0000000
77
78 #define SRCCA_CA 0x0FFFFFFF
79 #define SRCCA_RS 0xE0000000
80
81 #define SRCSA_SA 0x0FFFFFFF
82
83 #define SRCLA_LA 0x0FFFFFFF
84
85 /* Mixer Parameter Ring ram Low and Hight register.
86 * Fixed-point value in 8.24 format for parameter channel */
87 #define MPRLH_PITCH 0xFFFFFFFF
88
89 /* SRC resource register dirty flags */
90 union src_dirty {
91 struct {
92 u16 ctl:1;
93 u16 ccr:1;
94 u16 sa:1;
95 u16 la:1;
96 u16 ca:1;
97 u16 mpr:1;
98 u16 czbfs:1; /* Clear Z-Buffers */
99 u16 rsv:9;
100 } bf;
101 u16 data;
102 };
103
104 struct src_rsc_ctrl_blk {
105 unsigned int ctl;
106 unsigned int ccr;
107 unsigned int ca;
108 unsigned int sa;
109 unsigned int la;
110 unsigned int mpr;
111 union src_dirty dirty;
112 };
113
114 /* SRC manager control block */
115 union src_mgr_dirty {
116 struct {
117 u16 enb0:1;
118 u16 enb1:1;
119 u16 enb2:1;
120 u16 enb3:1;
121 u16 enb4:1;
122 u16 enb5:1;
123 u16 enb6:1;
124 u16 enb7:1;
125 u16 enbsa:1;
126 u16 rsv:7;
127 } bf;
128 u16 data;
129 };
130
131 struct src_mgr_ctrl_blk {
132 unsigned int enbsa;
133 unsigned int enb[8];
134 union src_mgr_dirty dirty;
135 };
136
137 /* SRCIMP manager control block */
138 #define SRCAIM_ARC 0x00000FFF
139 #define SRCAIM_NXT 0x00FF0000
140 #define SRCAIM_SRC 0xFF000000
141
142 struct srcimap {
143 unsigned int srcaim;
144 unsigned int idx;
145 };
146
147 /* SRCIMP manager register dirty flags */
148 union srcimp_mgr_dirty {
149 struct {
150 u16 srcimap:1;
151 u16 rsv:15;
152 } bf;
153 u16 data;
154 };
155
156 struct srcimp_mgr_ctrl_blk {
157 struct srcimap srcimap;
158 union srcimp_mgr_dirty dirty;
159 };
160
161 /*
162 * Function implementation block.
163 */
164
165 static int src_get_rsc_ctrl_blk(void **rblk)
166 {
167 struct src_rsc_ctrl_blk *blk;
168
169 *rblk = NULL;
170 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
171 if (!blk)
172 return -ENOMEM;
173
174 *rblk = blk;
175
176 return 0;
177 }
178
179 static int src_put_rsc_ctrl_blk(void *blk)
180 {
181 kfree(blk);
182
183 return 0;
184 }
185
186 static int src_set_state(void *blk, unsigned int state)
187 {
188 struct src_rsc_ctrl_blk *ctl = blk;
189
190 set_field(&ctl->ctl, SRCCTL_STATE, state);
191 ctl->dirty.bf.ctl = 1;
192 return 0;
193 }
194
195 static int src_set_bm(void *blk, unsigned int bm)
196 {
197 struct src_rsc_ctrl_blk *ctl = blk;
198
199 set_field(&ctl->ctl, SRCCTL_BM, bm);
200 ctl->dirty.bf.ctl = 1;
201 return 0;
202 }
203
204 static int src_set_rsr(void *blk, unsigned int rsr)
205 {
206 struct src_rsc_ctrl_blk *ctl = blk;
207
208 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
209 ctl->dirty.bf.ctl = 1;
210 return 0;
211 }
212
213 static int src_set_sf(void *blk, unsigned int sf)
214 {
215 struct src_rsc_ctrl_blk *ctl = blk;
216
217 set_field(&ctl->ctl, SRCCTL_SF, sf);
218 ctl->dirty.bf.ctl = 1;
219 return 0;
220 }
221
222 static int src_set_wr(void *blk, unsigned int wr)
223 {
224 struct src_rsc_ctrl_blk *ctl = blk;
225
226 set_field(&ctl->ctl, SRCCTL_WR, wr);
227 ctl->dirty.bf.ctl = 1;
228 return 0;
229 }
230
231 static int src_set_pm(void *blk, unsigned int pm)
232 {
233 struct src_rsc_ctrl_blk *ctl = blk;
234
235 set_field(&ctl->ctl, SRCCTL_PM, pm);
236 ctl->dirty.bf.ctl = 1;
237 return 0;
238 }
239
240 static int src_set_rom(void *blk, unsigned int rom)
241 {
242 struct src_rsc_ctrl_blk *ctl = blk;
243
244 set_field(&ctl->ctl, SRCCTL_ROM, rom);
245 ctl->dirty.bf.ctl = 1;
246 return 0;
247 }
248
249 static int src_set_vo(void *blk, unsigned int vo)
250 {
251 struct src_rsc_ctrl_blk *ctl = blk;
252
253 set_field(&ctl->ctl, SRCCTL_VO, vo);
254 ctl->dirty.bf.ctl = 1;
255 return 0;
256 }
257
258 static int src_set_st(void *blk, unsigned int st)
259 {
260 struct src_rsc_ctrl_blk *ctl = blk;
261
262 set_field(&ctl->ctl, SRCCTL_ST, st);
263 ctl->dirty.bf.ctl = 1;
264 return 0;
265 }
266
267 static int src_set_ie(void *blk, unsigned int ie)
268 {
269 struct src_rsc_ctrl_blk *ctl = blk;
270
271 set_field(&ctl->ctl, SRCCTL_IE, ie);
272 ctl->dirty.bf.ctl = 1;
273 return 0;
274 }
275
276 static int src_set_ilsz(void *blk, unsigned int ilsz)
277 {
278 struct src_rsc_ctrl_blk *ctl = blk;
279
280 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
281 ctl->dirty.bf.ctl = 1;
282 return 0;
283 }
284
285 static int src_set_bp(void *blk, unsigned int bp)
286 {
287 struct src_rsc_ctrl_blk *ctl = blk;
288
289 set_field(&ctl->ctl, SRCCTL_BP, bp);
290 ctl->dirty.bf.ctl = 1;
291 return 0;
292 }
293
294 static int src_set_cisz(void *blk, unsigned int cisz)
295 {
296 struct src_rsc_ctrl_blk *ctl = blk;
297
298 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
299 ctl->dirty.bf.ccr = 1;
300 return 0;
301 }
302
303 static int src_set_ca(void *blk, unsigned int ca)
304 {
305 struct src_rsc_ctrl_blk *ctl = blk;
306
307 set_field(&ctl->ca, SRCCA_CA, ca);
308 ctl->dirty.bf.ca = 1;
309 return 0;
310 }
311
312 static int src_set_sa(void *blk, unsigned int sa)
313 {
314 struct src_rsc_ctrl_blk *ctl = blk;
315
316 set_field(&ctl->sa, SRCSA_SA, sa);
317 ctl->dirty.bf.sa = 1;
318 return 0;
319 }
320
321 static int src_set_la(void *blk, unsigned int la)
322 {
323 struct src_rsc_ctrl_blk *ctl = blk;
324
325 set_field(&ctl->la, SRCLA_LA, la);
326 ctl->dirty.bf.la = 1;
327 return 0;
328 }
329
330 static int src_set_pitch(void *blk, unsigned int pitch)
331 {
332 struct src_rsc_ctrl_blk *ctl = blk;
333
334 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
335 ctl->dirty.bf.mpr = 1;
336 return 0;
337 }
338
339 static int src_set_clear_zbufs(void *blk, unsigned int clear)
340 {
341 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
342 return 0;
343 }
344
345 static int src_set_dirty(void *blk, unsigned int flags)
346 {
347 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
348 return 0;
349 }
350
351 static int src_set_dirty_all(void *blk)
352 {
353 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
354 return 0;
355 }
356
357 #define AR_SLOT_SIZE 4096
358 #define AR_SLOT_BLOCK_SIZE 16
359 #define AR_PTS_PITCH 6
360 #define AR_PARAM_SRC_OFFSET 0x60
361
362 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
363 {
364 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
365 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
366
367 }
368
369 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
370 {
371 struct src_rsc_ctrl_blk *ctl = blk;
372 int i;
373
374 if (ctl->dirty.bf.czbfs) {
375 /* Clear Z-Buffer registers */
376 for (i = 0; i < 8; i++)
377 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
378
379 for (i = 0; i < 4; i++)
380 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
381
382 for (i = 0; i < 8; i++)
383 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
384
385 ctl->dirty.bf.czbfs = 0;
386 }
387 if (ctl->dirty.bf.mpr) {
388 /* Take the parameter mixer resource in the same group as that
389 * the idx src is in for simplicity. Unlike src, all conjugate
390 * parameter mixer resources must be programmed for
391 * corresponding conjugate src resources. */
392 unsigned int pm_idx = src_param_pitch_mixer(idx);
393 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
394 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
395 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
396 ctl->dirty.bf.mpr = 0;
397 }
398 if (ctl->dirty.bf.sa) {
399 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
400 ctl->dirty.bf.sa = 0;
401 }
402 if (ctl->dirty.bf.la) {
403 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
404 ctl->dirty.bf.la = 0;
405 }
406 if (ctl->dirty.bf.ca) {
407 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
408 ctl->dirty.bf.ca = 0;
409 }
410
411 /* Write srccf register */
412 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
413
414 if (ctl->dirty.bf.ccr) {
415 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
416 ctl->dirty.bf.ccr = 0;
417 }
418 if (ctl->dirty.bf.ctl) {
419 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
420 ctl->dirty.bf.ctl = 0;
421 }
422
423 return 0;
424 }
425
426 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
427 {
428 struct src_rsc_ctrl_blk *ctl = blk;
429
430 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
431 ctl->dirty.bf.ca = 0;
432
433 return get_field(ctl->ca, SRCCA_CA);
434 }
435
436 static unsigned int src_get_dirty(void *blk)
437 {
438 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
439 }
440
441 static unsigned int src_dirty_conj_mask(void)
442 {
443 return 0x20;
444 }
445
446 static int src_mgr_enbs_src(void *blk, unsigned int idx)
447 {
448 ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
449 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
450 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
451 return 0;
452 }
453
454 static int src_mgr_enb_src(void *blk, unsigned int idx)
455 {
456 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
457 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
458 return 0;
459 }
460
461 static int src_mgr_dsb_src(void *blk, unsigned int idx)
462 {
463 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
464 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
465 return 0;
466 }
467
468 static int src_mgr_commit_write(struct hw *hw, void *blk)
469 {
470 struct src_mgr_ctrl_blk *ctl = blk;
471 int i;
472 unsigned int ret;
473
474 if (ctl->dirty.bf.enbsa) {
475 do {
476 ret = hw_read_20kx(hw, SRC_ENBSTAT);
477 } while (ret & 0x1);
478 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
479 ctl->dirty.bf.enbsa = 0;
480 }
481 for (i = 0; i < 8; i++) {
482 if ((ctl->dirty.data & (0x1 << i))) {
483 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
484 ctl->dirty.data &= ~(0x1 << i);
485 }
486 }
487
488 return 0;
489 }
490
491 static int src_mgr_get_ctrl_blk(void **rblk)
492 {
493 struct src_mgr_ctrl_blk *blk;
494
495 *rblk = NULL;
496 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
497 if (!blk)
498 return -ENOMEM;
499
500 *rblk = blk;
501
502 return 0;
503 }
504
505 static int src_mgr_put_ctrl_blk(void *blk)
506 {
507 kfree(blk);
508
509 return 0;
510 }
511
512 static int srcimp_mgr_get_ctrl_blk(void **rblk)
513 {
514 struct srcimp_mgr_ctrl_blk *blk;
515
516 *rblk = NULL;
517 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
518 if (!blk)
519 return -ENOMEM;
520
521 *rblk = blk;
522
523 return 0;
524 }
525
526 static int srcimp_mgr_put_ctrl_blk(void *blk)
527 {
528 kfree(blk);
529
530 return 0;
531 }
532
533 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
534 {
535 struct srcimp_mgr_ctrl_blk *ctl = blk;
536
537 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
538 ctl->dirty.bf.srcimap = 1;
539 return 0;
540 }
541
542 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
543 {
544 struct srcimp_mgr_ctrl_blk *ctl = blk;
545
546 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
547 ctl->dirty.bf.srcimap = 1;
548 return 0;
549 }
550
551 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
552 {
553 struct srcimp_mgr_ctrl_blk *ctl = blk;
554
555 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
556 ctl->dirty.bf.srcimap = 1;
557 return 0;
558 }
559
560 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
561 {
562 ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
563 ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
564 return 0;
565 }
566
567 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
568 {
569 struct srcimp_mgr_ctrl_blk *ctl = blk;
570
571 if (ctl->dirty.bf.srcimap) {
572 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
573 ctl->srcimap.srcaim);
574 ctl->dirty.bf.srcimap = 0;
575 }
576
577 return 0;
578 }
579
580 /*
581 * AMIXER control block definitions.
582 */
583
584 #define AMOPLO_M 0x00000003
585 #define AMOPLO_IV 0x00000004
586 #define AMOPLO_X 0x0003FFF0
587 #define AMOPLO_Y 0xFFFC0000
588
589 #define AMOPHI_SADR 0x000000FF
590 #define AMOPHI_SE 0x80000000
591
592 /* AMIXER resource register dirty flags */
593 union amixer_dirty {
594 struct {
595 u16 amoplo:1;
596 u16 amophi:1;
597 u16 rsv:14;
598 } bf;
599 u16 data;
600 };
601
602 /* AMIXER resource control block */
603 struct amixer_rsc_ctrl_blk {
604 unsigned int amoplo;
605 unsigned int amophi;
606 union amixer_dirty dirty;
607 };
608
609 static int amixer_set_mode(void *blk, unsigned int mode)
610 {
611 struct amixer_rsc_ctrl_blk *ctl = blk;
612
613 set_field(&ctl->amoplo, AMOPLO_M, mode);
614 ctl->dirty.bf.amoplo = 1;
615 return 0;
616 }
617
618 static int amixer_set_iv(void *blk, unsigned int iv)
619 {
620 struct amixer_rsc_ctrl_blk *ctl = blk;
621
622 set_field(&ctl->amoplo, AMOPLO_IV, iv);
623 ctl->dirty.bf.amoplo = 1;
624 return 0;
625 }
626
627 static int amixer_set_x(void *blk, unsigned int x)
628 {
629 struct amixer_rsc_ctrl_blk *ctl = blk;
630
631 set_field(&ctl->amoplo, AMOPLO_X, x);
632 ctl->dirty.bf.amoplo = 1;
633 return 0;
634 }
635
636 static int amixer_set_y(void *blk, unsigned int y)
637 {
638 struct amixer_rsc_ctrl_blk *ctl = blk;
639
640 set_field(&ctl->amoplo, AMOPLO_Y, y);
641 ctl->dirty.bf.amoplo = 1;
642 return 0;
643 }
644
645 static int amixer_set_sadr(void *blk, unsigned int sadr)
646 {
647 struct amixer_rsc_ctrl_blk *ctl = blk;
648
649 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
650 ctl->dirty.bf.amophi = 1;
651 return 0;
652 }
653
654 static int amixer_set_se(void *blk, unsigned int se)
655 {
656 struct amixer_rsc_ctrl_blk *ctl = blk;
657
658 set_field(&ctl->amophi, AMOPHI_SE, se);
659 ctl->dirty.bf.amophi = 1;
660 return 0;
661 }
662
663 static int amixer_set_dirty(void *blk, unsigned int flags)
664 {
665 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
666 return 0;
667 }
668
669 static int amixer_set_dirty_all(void *blk)
670 {
671 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
672 return 0;
673 }
674
675 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
676 {
677 struct amixer_rsc_ctrl_blk *ctl = blk;
678
679 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
680 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
681 ctl->dirty.bf.amoplo = 0;
682 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
683 ctl->dirty.bf.amophi = 0;
684 }
685
686 return 0;
687 }
688
689 static int amixer_get_y(void *blk)
690 {
691 struct amixer_rsc_ctrl_blk *ctl = blk;
692
693 return get_field(ctl->amoplo, AMOPLO_Y);
694 }
695
696 static unsigned int amixer_get_dirty(void *blk)
697 {
698 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
699 }
700
701 static int amixer_rsc_get_ctrl_blk(void **rblk)
702 {
703 struct amixer_rsc_ctrl_blk *blk;
704
705 *rblk = NULL;
706 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
707 if (!blk)
708 return -ENOMEM;
709
710 *rblk = blk;
711
712 return 0;
713 }
714
715 static int amixer_rsc_put_ctrl_blk(void *blk)
716 {
717 kfree(blk);
718
719 return 0;
720 }
721
722 static int amixer_mgr_get_ctrl_blk(void **rblk)
723 {
724 *rblk = NULL;
725
726 return 0;
727 }
728
729 static int amixer_mgr_put_ctrl_blk(void *blk)
730 {
731 return 0;
732 }
733
734 /*
735 * DAIO control block definitions.
736 */
737
738 /* Receiver Sample Rate Tracker Control register */
739 #define SRTCTL_SRCO 0x000000FF
740 #define SRTCTL_SRCM 0x0000FF00
741 #define SRTCTL_RSR 0x00030000
742 #define SRTCTL_DRAT 0x00300000
743 #define SRTCTL_EC 0x01000000
744 #define SRTCTL_ET 0x10000000
745
746 /* DAIO Receiver register dirty flags */
747 union dai_dirty {
748 struct {
749 u16 srt:1;
750 u16 rsv:15;
751 } bf;
752 u16 data;
753 };
754
755 /* DAIO Receiver control block */
756 struct dai_ctrl_blk {
757 unsigned int srt;
758 union dai_dirty dirty;
759 };
760
761 /* Audio Input Mapper RAM */
762 #define AIM_ARC 0x00000FFF
763 #define AIM_NXT 0x007F0000
764
765 struct daoimap {
766 unsigned int aim;
767 unsigned int idx;
768 };
769
770 /* Audio Transmitter Control and Status register */
771 #define ATXCTL_EN 0x00000001
772 #define ATXCTL_MODE 0x00000010
773 #define ATXCTL_CD 0x00000020
774 #define ATXCTL_RAW 0x00000100
775 #define ATXCTL_MT 0x00000200
776 #define ATXCTL_NUC 0x00003000
777 #define ATXCTL_BEN 0x00010000
778 #define ATXCTL_BMUX 0x00700000
779 #define ATXCTL_B24 0x01000000
780 #define ATXCTL_CPF 0x02000000
781 #define ATXCTL_RIV 0x10000000
782 #define ATXCTL_LIV 0x20000000
783 #define ATXCTL_RSAT 0x40000000
784 #define ATXCTL_LSAT 0x80000000
785
786 /* XDIF Transmitter register dirty flags */
787 union dao_dirty {
788 struct {
789 u16 atxcsl:1;
790 u16 rsv:15;
791 } bf;
792 u16 data;
793 };
794
795 /* XDIF Transmitter control block */
796 struct dao_ctrl_blk {
797 /* XDIF Transmitter Channel Status Low Register */
798 unsigned int atxcsl;
799 union dao_dirty dirty;
800 };
801
802 /* Audio Receiver Control register */
803 #define ARXCTL_EN 0x00000001
804
805 /* DAIO manager register dirty flags */
806 union daio_mgr_dirty {
807 struct {
808 u32 atxctl:8;
809 u32 arxctl:8;
810 u32 daoimap:1;
811 u32 rsv:15;
812 } bf;
813 u32 data;
814 };
815
816 /* DAIO manager control block */
817 struct daio_mgr_ctrl_blk {
818 struct daoimap daoimap;
819 unsigned int txctl[8];
820 unsigned int rxctl[8];
821 union daio_mgr_dirty dirty;
822 };
823
824 static int dai_srt_set_srco(void *blk, unsigned int src)
825 {
826 struct dai_ctrl_blk *ctl = blk;
827
828 set_field(&ctl->srt, SRTCTL_SRCO, src);
829 ctl->dirty.bf.srt = 1;
830 return 0;
831 }
832
833 static int dai_srt_set_srcm(void *blk, unsigned int src)
834 {
835 struct dai_ctrl_blk *ctl = blk;
836
837 set_field(&ctl->srt, SRTCTL_SRCM, src);
838 ctl->dirty.bf.srt = 1;
839 return 0;
840 }
841
842 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
843 {
844 struct dai_ctrl_blk *ctl = blk;
845
846 set_field(&ctl->srt, SRTCTL_RSR, rsr);
847 ctl->dirty.bf.srt = 1;
848 return 0;
849 }
850
851 static int dai_srt_set_drat(void *blk, unsigned int drat)
852 {
853 struct dai_ctrl_blk *ctl = blk;
854
855 set_field(&ctl->srt, SRTCTL_DRAT, drat);
856 ctl->dirty.bf.srt = 1;
857 return 0;
858 }
859
860 static int dai_srt_set_ec(void *blk, unsigned int ec)
861 {
862 struct dai_ctrl_blk *ctl = blk;
863
864 set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
865 ctl->dirty.bf.srt = 1;
866 return 0;
867 }
868
869 static int dai_srt_set_et(void *blk, unsigned int et)
870 {
871 struct dai_ctrl_blk *ctl = blk;
872
873 set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
874 ctl->dirty.bf.srt = 1;
875 return 0;
876 }
877
878 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
879 {
880 struct dai_ctrl_blk *ctl = blk;
881
882 if (ctl->dirty.bf.srt) {
883 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
884 ctl->dirty.bf.srt = 0;
885 }
886
887 return 0;
888 }
889
890 static int dai_get_ctrl_blk(void **rblk)
891 {
892 struct dai_ctrl_blk *blk;
893
894 *rblk = NULL;
895 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
896 if (!blk)
897 return -ENOMEM;
898
899 *rblk = blk;
900
901 return 0;
902 }
903
904 static int dai_put_ctrl_blk(void *blk)
905 {
906 kfree(blk);
907
908 return 0;
909 }
910
911 static int dao_set_spos(void *blk, unsigned int spos)
912 {
913 ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
914 ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
915 return 0;
916 }
917
918 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
919 {
920 struct dao_ctrl_blk *ctl = blk;
921
922 if (ctl->dirty.bf.atxcsl) {
923 if (idx < 4) {
924 /* S/PDIF SPOSx */
925 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
926 ctl->atxcsl);
927 }
928 ctl->dirty.bf.atxcsl = 0;
929 }
930
931 return 0;
932 }
933
934 static int dao_get_spos(void *blk, unsigned int *spos)
935 {
936 *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
937 return 0;
938 }
939
940 static int dao_get_ctrl_blk(void **rblk)
941 {
942 struct dao_ctrl_blk *blk;
943
944 *rblk = NULL;
945 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
946 if (!blk)
947 return -ENOMEM;
948
949 *rblk = blk;
950
951 return 0;
952 }
953
954 static int dao_put_ctrl_blk(void *blk)
955 {
956 kfree(blk);
957
958 return 0;
959 }
960
961 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
962 {
963 struct daio_mgr_ctrl_blk *ctl = blk;
964
965 set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
966 ctl->dirty.bf.arxctl |= (0x1 << idx);
967 return 0;
968 }
969
970 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
971 {
972 struct daio_mgr_ctrl_blk *ctl = blk;
973
974 set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
975
976 ctl->dirty.bf.arxctl |= (0x1 << idx);
977 return 0;
978 }
979
980 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
981 {
982 struct daio_mgr_ctrl_blk *ctl = blk;
983
984 set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
985 ctl->dirty.bf.atxctl |= (0x1 << idx);
986 return 0;
987 }
988
989 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
990 {
991 struct daio_mgr_ctrl_blk *ctl = blk;
992
993 set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
994 ctl->dirty.bf.atxctl |= (0x1 << idx);
995 return 0;
996 }
997
998 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
999 {
1000 struct daio_mgr_ctrl_blk *ctl = blk;
1001
1002 if (idx < 4) {
1003 /* S/PDIF output */
1004 switch ((conf & 0x7)) {
1005 case 1:
1006 set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
1007 break;
1008 case 2:
1009 set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
1010 break;
1011 case 4:
1012 set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
1013 break;
1014 case 8:
1015 set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1016 break;
1017 default:
1018 break;
1019 }
1020 /* CDIF */
1021 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1022 /* Non-audio */
1023 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1024 /* Non-audio */
1025 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1026 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1027 ((conf >> 3) & 0x1) ? 0 : 0);
1028 ctl->dirty.bf.atxctl |= (0x1 << idx);
1029 } else {
1030 /* I2S output */
1031 /*idx %= 4; */
1032 }
1033 return 0;
1034 }
1035
1036 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1037 {
1038 struct daio_mgr_ctrl_blk *ctl = blk;
1039
1040 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1041 ctl->dirty.bf.daoimap = 1;
1042 return 0;
1043 }
1044
1045 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1046 {
1047 struct daio_mgr_ctrl_blk *ctl = blk;
1048
1049 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1050 ctl->dirty.bf.daoimap = 1;
1051 return 0;
1052 }
1053
1054 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1055 {
1056 ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1057 ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1058 return 0;
1059 }
1060
1061 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1062 {
1063 struct daio_mgr_ctrl_blk *ctl = blk;
1064 unsigned int data;
1065 int i;
1066
1067 for (i = 0; i < 8; i++) {
1068 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1069 data = ctl->txctl[i];
1070 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1071 ctl->dirty.bf.atxctl &= ~(0x1 << i);
1072 mdelay(1);
1073 }
1074 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1075 data = ctl->rxctl[i];
1076 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1077 ctl->dirty.bf.arxctl &= ~(0x1 << i);
1078 mdelay(1);
1079 }
1080 }
1081 if (ctl->dirty.bf.daoimap) {
1082 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1083 ctl->daoimap.aim);
1084 ctl->dirty.bf.daoimap = 0;
1085 }
1086
1087 return 0;
1088 }
1089
1090 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1091 {
1092 struct daio_mgr_ctrl_blk *blk;
1093 int i;
1094
1095 *rblk = NULL;
1096 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1097 if (!blk)
1098 return -ENOMEM;
1099
1100 for (i = 0; i < 8; i++) {
1101 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1102 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1103 }
1104
1105 *rblk = blk;
1106
1107 return 0;
1108 }
1109
1110 static int daio_mgr_put_ctrl_blk(void *blk)
1111 {
1112 kfree(blk);
1113
1114 return 0;
1115 }
1116
1117 /* Timer interrupt */
1118 static int set_timer_irq(struct hw *hw, int enable)
1119 {
1120 hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1121 return 0;
1122 }
1123
1124 static int set_timer_tick(struct hw *hw, unsigned int ticks)
1125 {
1126 if (ticks)
1127 ticks |= TIMR_IE | TIMR_IP;
1128 hw_write_20kx(hw, TIMR, ticks);
1129 return 0;
1130 }
1131
1132 static unsigned int get_wc(struct hw *hw)
1133 {
1134 return hw_read_20kx(hw, WC);
1135 }
1136
1137 /* Card hardware initialization block */
1138 struct dac_conf {
1139 unsigned int msr; /* master sample rate in rsrs */
1140 };
1141
1142 struct adc_conf {
1143 unsigned int msr; /* master sample rate in rsrs */
1144 unsigned char input; /* the input source of ADC */
1145 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1146 };
1147
1148 struct daio_conf {
1149 unsigned int msr; /* master sample rate in rsrs */
1150 };
1151
1152 struct trn_conf {
1153 unsigned long vm_pgt_phys;
1154 };
1155
1156 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1157 {
1158 u32 data;
1159 int i;
1160
1161 /* Program I2S with proper sample rate and enable the correct I2S
1162 * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1163 if (1 == info->msr) {
1164 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1165 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1166 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1167 } else if (2 == info->msr) {
1168 if (hw->model != CTSB1270) {
1169 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1170 } else {
1171 /* PCM4220 on Titanium HD is different. */
1172 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111);
1173 }
1174 /* Specify all playing 96khz
1175 * EA [0] - Enabled
1176 * RTA [4:5] - 96kHz
1177 * EB [8] - Enabled
1178 * RTB [12:13] - 96kHz
1179 * EC [16] - Enabled
1180 * RTC [20:21] - 96kHz
1181 * ED [24] - Enabled
1182 * RTD [28:29] - 96kHz */
1183 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1184 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1185 } else if ((4 == info->msr) && (hw->model == CTSB1270)) {
1186 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111);
1187 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121);
1188 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1189 } else {
1190 dev_alert(hw->card->dev,
1191 "ERROR!!! Invalid sampling rate!!!\n");
1192 return -EINVAL;
1193 }
1194
1195 for (i = 0; i < 8; i++) {
1196 if (i <= 3) {
1197 /* This comment looks wrong since loop is over 4 */
1198 /* channels and emu20k2 supports 4 spdif IOs. */
1199 /* 1st 3 channels are SPDIFs (SB0960) */
1200 if (i == 3)
1201 data = 0x1001001;
1202 else
1203 data = 0x1000001;
1204
1205 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1206 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1207
1208 /* Initialize the SPDIF Out Channel status registers.
1209 * The value specified here is based on the typical
1210 * values provided in the specification, namely: Clock
1211 * Accuracy of 1000ppm, Sample Rate of 48KHz,
1212 * unspecified source number, Generation status = 1,
1213 * Category code = 0x12 (Digital Signal Mixer),
1214 * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1215 * (indicating that we're transmitting digital audio,
1216 * and the Professional Use bit is 0. */
1217
1218 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1219 0x02109204); /* Default to 48kHz */
1220
1221 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1222 } else {
1223 /* Again, loop is over 4 channels not 5. */
1224 /* Next 5 channels are I2S (SB0960) */
1225 data = 0x11;
1226 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
1227 if (2 == info->msr) {
1228 /* Four channels per sample period */
1229 data |= 0x1000;
1230 } else if (4 == info->msr) {
1231 /* FIXME: check this against the chip spec */
1232 data |= 0x2000;
1233 }
1234 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
1235 }
1236 }
1237
1238 return 0;
1239 }
1240
1241 /* TRANSPORT operations */
1242 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1243 {
1244 u32 vmctl, data;
1245 u32 ptp_phys_low, ptp_phys_high;
1246 int i;
1247
1248 /* Set up device page table */
1249 if ((~0UL) == info->vm_pgt_phys) {
1250 dev_alert(hw->card->dev,
1251 "Wrong device page table page address!!!\n");
1252 return -1;
1253 }
1254
1255 vmctl = 0x80000C0F; /* 32-bit, 4k-size page */
1256 ptp_phys_low = (u32)info->vm_pgt_phys;
1257 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1258 if (sizeof(void *) == 8) /* 64bit address */
1259 vmctl |= (3 << 8);
1260 /* Write page table physical address to all PTPAL registers */
1261 for (i = 0; i < 64; i++) {
1262 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1263 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1264 }
1265 /* Enable virtual memory transfer */
1266 hw_write_20kx(hw, VMEM_CTL, vmctl);
1267 /* Enable transport bus master and queueing of request */
1268 hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1269 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1270 /* Enable transport ring */
1271 data = hw_read_20kx(hw, TRANSPORT_ENB);
1272 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1273
1274 return 0;
1275 }
1276
1277 /* Card initialization */
1278 #define GCTL_AIE 0x00000001
1279 #define GCTL_UAA 0x00000002
1280 #define GCTL_DPC 0x00000004
1281 #define GCTL_DBP 0x00000008
1282 #define GCTL_ABP 0x00000010
1283 #define GCTL_TBP 0x00000020
1284 #define GCTL_SBP 0x00000040
1285 #define GCTL_FBP 0x00000080
1286 #define GCTL_ME 0x00000100
1287 #define GCTL_AID 0x00001000
1288
1289 #define PLLCTL_SRC 0x00000007
1290 #define PLLCTL_SPE 0x00000008
1291 #define PLLCTL_RD 0x000000F0
1292 #define PLLCTL_FD 0x0001FF00
1293 #define PLLCTL_OD 0x00060000
1294 #define PLLCTL_B 0x00080000
1295 #define PLLCTL_AS 0x00100000
1296 #define PLLCTL_LF 0x03E00000
1297 #define PLLCTL_SPS 0x1C000000
1298 #define PLLCTL_AD 0x60000000
1299
1300 #define PLLSTAT_CCS 0x00000007
1301 #define PLLSTAT_SPL 0x00000008
1302 #define PLLSTAT_CRD 0x000000F0
1303 #define PLLSTAT_CFD 0x0001FF00
1304 #define PLLSTAT_SL 0x00020000
1305 #define PLLSTAT_FAS 0x00040000
1306 #define PLLSTAT_B 0x00080000
1307 #define PLLSTAT_PD 0x00100000
1308 #define PLLSTAT_OCA 0x00200000
1309 #define PLLSTAT_NCA 0x00400000
1310
1311 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1312 {
1313 unsigned int pllenb;
1314 unsigned int pllctl;
1315 unsigned int pllstat;
1316 int i;
1317
1318 pllenb = 0xB;
1319 hw_write_20kx(hw, PLL_ENB, pllenb);
1320 pllctl = 0x20C00000;
1321 set_field(&pllctl, PLLCTL_B, 0);
1322 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4);
1323 set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1);
1324 hw_write_20kx(hw, PLL_CTL, pllctl);
1325 mdelay(40);
1326
1327 pllctl = hw_read_20kx(hw, PLL_CTL);
1328 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2);
1329 hw_write_20kx(hw, PLL_CTL, pllctl);
1330 mdelay(40);
1331
1332 for (i = 0; i < 1000; i++) {
1333 pllstat = hw_read_20kx(hw, PLL_STAT);
1334 if (get_field(pllstat, PLLSTAT_PD))
1335 continue;
1336
1337 if (get_field(pllstat, PLLSTAT_B) !=
1338 get_field(pllctl, PLLCTL_B))
1339 continue;
1340
1341 if (get_field(pllstat, PLLSTAT_CCS) !=
1342 get_field(pllctl, PLLCTL_SRC))
1343 continue;
1344
1345 if (get_field(pllstat, PLLSTAT_CRD) !=
1346 get_field(pllctl, PLLCTL_RD))
1347 continue;
1348
1349 if (get_field(pllstat, PLLSTAT_CFD) !=
1350 get_field(pllctl, PLLCTL_FD))
1351 continue;
1352
1353 break;
1354 }
1355 if (i >= 1000) {
1356 dev_alert(hw->card->dev,
1357 "PLL initialization failed!!!\n");
1358 return -EBUSY;
1359 }
1360
1361 return 0;
1362 }
1363
1364 static int hw_auto_init(struct hw *hw)
1365 {
1366 unsigned int gctl;
1367 int i;
1368
1369 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1370 set_field(&gctl, GCTL_AIE, 0);
1371 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1372 set_field(&gctl, GCTL_AIE, 1);
1373 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1374 mdelay(10);
1375 for (i = 0; i < 400000; i++) {
1376 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1377 if (get_field(gctl, GCTL_AID))
1378 break;
1379 }
1380 if (!get_field(gctl, GCTL_AID)) {
1381 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
1382 return -EBUSY;
1383 }
1384
1385 return 0;
1386 }
1387
1388 /* DAC operations */
1389
1390 #define CS4382_MC1 0x1
1391 #define CS4382_MC2 0x2
1392 #define CS4382_MC3 0x3
1393 #define CS4382_FC 0x4
1394 #define CS4382_IC 0x5
1395 #define CS4382_XC1 0x6
1396 #define CS4382_VCA1 0x7
1397 #define CS4382_VCB1 0x8
1398 #define CS4382_XC2 0x9
1399 #define CS4382_VCA2 0xA
1400 #define CS4382_VCB2 0xB
1401 #define CS4382_XC3 0xC
1402 #define CS4382_VCA3 0xD
1403 #define CS4382_VCB3 0xE
1404 #define CS4382_XC4 0xF
1405 #define CS4382_VCA4 0x10
1406 #define CS4382_VCB4 0x11
1407 #define CS4382_CREV 0x12
1408
1409 /* I2C status */
1410 #define STATE_LOCKED 0x00
1411 #define STATE_UNLOCKED 0xAA
1412 #define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */
1413 #define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */
1414
1415 #define I2C_STATUS_DCM 0x00000001
1416 #define I2C_STATUS_BC 0x00000006
1417 #define I2C_STATUS_APD 0x00000008
1418 #define I2C_STATUS_AB 0x00010000
1419 #define I2C_STATUS_DR 0x00800000
1420
1421 #define I2C_ADDRESS_PTAD 0x0000FFFF
1422 #define I2C_ADDRESS_SLAD 0x007F0000
1423
1424 struct regs_cs4382 {
1425 u32 mode_control_1;
1426 u32 mode_control_2;
1427 u32 mode_control_3;
1428
1429 u32 filter_control;
1430 u32 invert_control;
1431
1432 u32 mix_control_P1;
1433 u32 vol_control_A1;
1434 u32 vol_control_B1;
1435
1436 u32 mix_control_P2;
1437 u32 vol_control_A2;
1438 u32 vol_control_B2;
1439
1440 u32 mix_control_P3;
1441 u32 vol_control_A3;
1442 u32 vol_control_B3;
1443
1444 u32 mix_control_P4;
1445 u32 vol_control_A4;
1446 u32 vol_control_B4;
1447 };
1448
1449 static int hw20k2_i2c_unlock_full_access(struct hw *hw)
1450 {
1451 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
1452
1453 /* Send keys for forced BIOS mode */
1454 hw_write_20kx(hw, I2C_IF_WLOCK,
1455 UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1456 hw_write_20kx(hw, I2C_IF_WLOCK,
1457 UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1458 /* Check whether the chip is unlocked */
1459 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1460 return 0;
1461
1462 return -1;
1463 }
1464
1465 static int hw20k2_i2c_lock_chip(struct hw *hw)
1466 {
1467 /* Write twice */
1468 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1469 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1470 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1471 return 0;
1472
1473 return -1;
1474 }
1475
1476 static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
1477 {
1478 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1479 int err;
1480 unsigned int i2c_status;
1481 unsigned int i2c_addr;
1482
1483 err = hw20k2_i2c_unlock_full_access(hw);
1484 if (err < 0)
1485 return err;
1486
1487 hw20k2->addr_size = addr_size;
1488 hw20k2->data_size = data_size;
1489 hw20k2->dev_id = dev_id;
1490
1491 i2c_addr = 0;
1492 set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
1493
1494 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1495
1496 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1497
1498 set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */
1499
1500 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1501
1502 return 0;
1503 }
1504
1505 static int hw20k2_i2c_uninit(struct hw *hw)
1506 {
1507 unsigned int i2c_status;
1508 unsigned int i2c_addr;
1509
1510 i2c_addr = 0;
1511 set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1512
1513 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1514
1515 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1516
1517 set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */
1518
1519 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1520
1521 return hw20k2_i2c_lock_chip(hw);
1522 }
1523
1524 static int hw20k2_i2c_wait_data_ready(struct hw *hw)
1525 {
1526 int i = 0x400000;
1527 unsigned int ret;
1528
1529 do {
1530 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1531 } while ((!(ret & DATA_READY)) && --i);
1532
1533 return i;
1534 }
1535
1536 static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
1537 {
1538 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1539 unsigned int i2c_status;
1540
1541 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1542 set_field(&i2c_status, I2C_STATUS_BC,
1543 (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
1544 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1545 if (!hw20k2_i2c_wait_data_ready(hw))
1546 return -1;
1547
1548 hw_write_20kx(hw, I2C_IF_WDATA, addr);
1549 if (!hw20k2_i2c_wait_data_ready(hw))
1550 return -1;
1551
1552 /* Force a read operation */
1553 hw_write_20kx(hw, I2C_IF_RDATA, 0);
1554 if (!hw20k2_i2c_wait_data_ready(hw))
1555 return -1;
1556
1557 *datap = hw_read_20kx(hw, I2C_IF_RDATA);
1558
1559 return 0;
1560 }
1561
1562 static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
1563 {
1564 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1565 unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
1566 unsigned int i2c_status;
1567
1568 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1569
1570 set_field(&i2c_status, I2C_STATUS_BC,
1571 (4 == (hw20k2->addr_size + hw20k2->data_size)) ?
1572 0 : (hw20k2->addr_size + hw20k2->data_size));
1573
1574 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1575 hw20k2_i2c_wait_data_ready(hw);
1576 /* Dummy write to trigger the write operation */
1577 hw_write_20kx(hw, I2C_IF_WDATA, 0);
1578 hw20k2_i2c_wait_data_ready(hw);
1579
1580 /* This is the real data */
1581 hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
1582 hw20k2_i2c_wait_data_ready(hw);
1583
1584 return 0;
1585 }
1586
1587 static void hw_dac_stop(struct hw *hw)
1588 {
1589 u32 data;
1590 data = hw_read_20kx(hw, GPIO_DATA);
1591 data &= 0xFFFFFFFD;
1592 hw_write_20kx(hw, GPIO_DATA, data);
1593 mdelay(10);
1594 }
1595
1596 static void hw_dac_start(struct hw *hw)
1597 {
1598 u32 data;
1599 data = hw_read_20kx(hw, GPIO_DATA);
1600 data |= 0x2;
1601 hw_write_20kx(hw, GPIO_DATA, data);
1602 mdelay(50);
1603 }
1604
1605 static void hw_dac_reset(struct hw *hw)
1606 {
1607 hw_dac_stop(hw);
1608 hw_dac_start(hw);
1609 }
1610
1611 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1612 {
1613 int err;
1614 u32 data;
1615 int i;
1616 struct regs_cs4382 cs_read = {0};
1617 struct regs_cs4382 cs_def = {
1618 0x00000001, /* Mode Control 1 */
1619 0x00000000, /* Mode Control 2 */
1620 0x00000084, /* Mode Control 3 */
1621 0x00000000, /* Filter Control */
1622 0x00000000, /* Invert Control */
1623 0x00000024, /* Mixing Control Pair 1 */
1624 0x00000000, /* Vol Control A1 */
1625 0x00000000, /* Vol Control B1 */
1626 0x00000024, /* Mixing Control Pair 2 */
1627 0x00000000, /* Vol Control A2 */
1628 0x00000000, /* Vol Control B2 */
1629 0x00000024, /* Mixing Control Pair 3 */
1630 0x00000000, /* Vol Control A3 */
1631 0x00000000, /* Vol Control B3 */
1632 0x00000024, /* Mixing Control Pair 4 */
1633 0x00000000, /* Vol Control A4 */
1634 0x00000000 /* Vol Control B4 */
1635 };
1636
1637 if (hw->model == CTSB1270) {
1638 hw_dac_stop(hw);
1639 data = hw_read_20kx(hw, GPIO_DATA);
1640 data &= ~0x0600;
1641 if (1 == info->msr)
1642 data |= 0x0000; /* Single Speed Mode 0-50kHz */
1643 else if (2 == info->msr)
1644 data |= 0x0200; /* Double Speed Mode 50-100kHz */
1645 else
1646 data |= 0x0600; /* Quad Speed Mode 100-200kHz */
1647 hw_write_20kx(hw, GPIO_DATA, data);
1648 hw_dac_start(hw);
1649 return 0;
1650 }
1651
1652 /* Set DAC reset bit as output */
1653 data = hw_read_20kx(hw, GPIO_CTRL);
1654 data |= 0x02;
1655 hw_write_20kx(hw, GPIO_CTRL, data);
1656
1657 err = hw20k2_i2c_init(hw, 0x18, 1, 1);
1658 if (err < 0)
1659 goto End;
1660
1661 for (i = 0; i < 2; i++) {
1662 /* Reset DAC twice just in-case the chip
1663 * didn't initialized properly */
1664 hw_dac_reset(hw);
1665 hw_dac_reset(hw);
1666
1667 if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1))
1668 continue;
1669
1670 if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2))
1671 continue;
1672
1673 if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3))
1674 continue;
1675
1676 if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control))
1677 continue;
1678
1679 if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control))
1680 continue;
1681
1682 if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1))
1683 continue;
1684
1685 if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
1686 continue;
1687
1688 if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
1689 continue;
1690
1691 if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2))
1692 continue;
1693
1694 if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
1695 continue;
1696
1697 if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
1698 continue;
1699
1700 if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3))
1701 continue;
1702
1703 if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
1704 continue;
1705
1706 if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
1707 continue;
1708
1709 if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4))
1710 continue;
1711
1712 if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
1713 continue;
1714
1715 if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
1716 continue;
1717
1718 if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
1719 continue;
1720 else
1721 break;
1722 }
1723
1724 if (i >= 2)
1725 goto End;
1726
1727 /* Note: Every I2C write must have some delay.
1728 * This is not a requirement but the delay works here... */
1729 hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
1730 hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
1731 if (1 == info->msr) {
1732 hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
1733 hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
1734 hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
1735 hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
1736 } else if (2 == info->msr) {
1737 hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
1738 hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
1739 hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
1740 hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
1741 } else {
1742 hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
1743 hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
1744 hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
1745 hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
1746 }
1747
1748 return 0;
1749 End:
1750
1751 hw20k2_i2c_uninit(hw);
1752 return -1;
1753 }
1754
1755 /* ADC operations */
1756 #define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1757 #define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
1758
1759 #define WM8775_IC 0x0B
1760 #define WM8775_MMC 0x0C
1761 #define WM8775_AADCL 0x0E
1762 #define WM8775_AADCR 0x0F
1763 #define WM8775_ADCMC 0x15
1764 #define WM8775_RESET 0x17
1765
1766 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1767 {
1768 u32 data;
1769 if (hw->model == CTSB1270) {
1770 /* Titanium HD has two ADC chips, one for line in and one */
1771 /* for MIC. We don't need to switch the ADC input. */
1772 return 1;
1773 }
1774 data = hw_read_20kx(hw, GPIO_DATA);
1775 switch (type) {
1776 case ADC_MICIN:
1777 data = (data & (0x1 << 14)) ? 1 : 0;
1778 break;
1779 case ADC_LINEIN:
1780 data = (data & (0x1 << 14)) ? 0 : 1;
1781 break;
1782 default:
1783 data = 0;
1784 }
1785 return data;
1786 }
1787
1788 #define MIC_BOOST_0DB 0xCF
1789 #define MIC_BOOST_STEPS_PER_DB 2
1790
1791 static void hw_wm8775_input_select(struct hw *hw, u8 input, s8 gain_in_db)
1792 {
1793 u32 adcmc, gain;
1794
1795 if (input > 3)
1796 input = 3;
1797
1798 adcmc = ((u32)1 << input) | 0x100; /* Link L+R gain... */
1799
1800 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, adcmc),
1801 MAKE_WM8775_DATA(adcmc));
1802
1803 if (gain_in_db < -103)
1804 gain_in_db = -103;
1805 if (gain_in_db > 24)
1806 gain_in_db = 24;
1807
1808 gain = gain_in_db * MIC_BOOST_STEPS_PER_DB + MIC_BOOST_0DB;
1809
1810 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, gain),
1811 MAKE_WM8775_DATA(gain));
1812 /* ...so there should be no need for the following. */
1813 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, gain),
1814 MAKE_WM8775_DATA(gain));
1815 }
1816
1817 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1818 {
1819 u32 data;
1820 data = hw_read_20kx(hw, GPIO_DATA);
1821 switch (type) {
1822 case ADC_MICIN:
1823 data |= (0x1 << 14);
1824 hw_write_20kx(hw, GPIO_DATA, data);
1825 hw_wm8775_input_select(hw, 0, 20); /* Mic, 20dB */
1826 break;
1827 case ADC_LINEIN:
1828 data &= ~(0x1 << 14);
1829 hw_write_20kx(hw, GPIO_DATA, data);
1830 hw_wm8775_input_select(hw, 1, 0); /* Line-in, 0dB */
1831 break;
1832 default:
1833 break;
1834 }
1835
1836 return 0;
1837 }
1838
1839 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1840 {
1841 int err;
1842 u32 data, ctl;
1843
1844 /* Set ADC reset bit as output */
1845 data = hw_read_20kx(hw, GPIO_CTRL);
1846 data |= (0x1 << 15);
1847 hw_write_20kx(hw, GPIO_CTRL, data);
1848
1849 /* Initialize I2C */
1850 err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
1851 if (err < 0) {
1852 dev_alert(hw->card->dev, "Failure to acquire I2C!!!\n");
1853 goto error;
1854 }
1855
1856 /* Reset the ADC (reset is active low). */
1857 data = hw_read_20kx(hw, GPIO_DATA);
1858 data &= ~(0x1 << 15);
1859 hw_write_20kx(hw, GPIO_DATA, data);
1860
1861 if (hw->model == CTSB1270) {
1862 /* Set up the PCM4220 ADC on Titanium HD */
1863 data &= ~0x0C;
1864 if (1 == info->msr)
1865 data |= 0x00; /* Single Speed Mode 32-50kHz */
1866 else if (2 == info->msr)
1867 data |= 0x08; /* Double Speed Mode 50-108kHz */
1868 else
1869 data |= 0x04; /* Quad Speed Mode 108kHz-216kHz */
1870 hw_write_20kx(hw, GPIO_DATA, data);
1871 }
1872
1873 mdelay(10);
1874 /* Return the ADC to normal operation. */
1875 data |= (0x1 << 15);
1876 hw_write_20kx(hw, GPIO_DATA, data);
1877 mdelay(50);
1878
1879 /* I2C write to register offset 0x0B to set ADC LRCLK polarity */
1880 /* invert bit, interface format to I2S, word length to 24-bit, */
1881 /* enable ADC high pass filter. Fixes bug 5323? */
1882 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26),
1883 MAKE_WM8775_DATA(0x26));
1884
1885 /* Set the master mode (256fs) */
1886 if (1 == info->msr) {
1887 /* slave mode, 128x oversampling 256fs */
1888 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1889 MAKE_WM8775_DATA(0x02));
1890 } else if ((2 == info->msr) || (4 == info->msr)) {
1891 /* slave mode, 64x oversampling, 256fs */
1892 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1893 MAKE_WM8775_DATA(0x0A));
1894 } else {
1895 dev_alert(hw->card->dev,
1896 "Invalid master sampling rate (msr %d)!!!\n",
1897 info->msr);
1898 err = -EINVAL;
1899 goto error;
1900 }
1901
1902 if (hw->model != CTSB1270) {
1903 /* Configure GPIO bit 14 change to line-in/mic-in */
1904 ctl = hw_read_20kx(hw, GPIO_CTRL);
1905 ctl |= 0x1 << 14;
1906 hw_write_20kx(hw, GPIO_CTRL, ctl);
1907 hw_adc_input_select(hw, ADC_LINEIN);
1908 } else {
1909 hw_wm8775_input_select(hw, 0, 0);
1910 }
1911
1912 return 0;
1913 error:
1914 hw20k2_i2c_uninit(hw);
1915 return err;
1916 }
1917
1918 static struct capabilities hw_capabilities(struct hw *hw)
1919 {
1920 struct capabilities cap;
1921
1922 cap.digit_io_switch = 0;
1923 cap.dedicated_mic = hw->model == CTSB1270;
1924 cap.output_switch = hw->model == CTSB1270;
1925 cap.mic_source_switch = hw->model == CTSB1270;
1926
1927 return cap;
1928 }
1929
1930 static int hw_output_switch_get(struct hw *hw)
1931 {
1932 u32 data = hw_read_20kx(hw, GPIO_EXT_DATA);
1933
1934 switch (data & 0x30) {
1935 case 0x00:
1936 return 0;
1937 case 0x10:
1938 return 1;
1939 case 0x20:
1940 return 2;
1941 default:
1942 return 3;
1943 }
1944 }
1945
1946 static int hw_output_switch_put(struct hw *hw, int position)
1947 {
1948 u32 data;
1949
1950 if (position == hw_output_switch_get(hw))
1951 return 0;
1952
1953 /* Mute line and headphones (intended for anti-pop). */
1954 data = hw_read_20kx(hw, GPIO_DATA);
1955 data |= (0x03 << 11);
1956 hw_write_20kx(hw, GPIO_DATA, data);
1957
1958 data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30;
1959 switch (position) {
1960 case 0:
1961 break;
1962 case 1:
1963 data |= 0x10;
1964 break;
1965 default:
1966 data |= 0x20;
1967 }
1968 hw_write_20kx(hw, GPIO_EXT_DATA, data);
1969
1970 /* Unmute line and headphones. */
1971 data = hw_read_20kx(hw, GPIO_DATA);
1972 data &= ~(0x03 << 11);
1973 hw_write_20kx(hw, GPIO_DATA, data);
1974
1975 return 1;
1976 }
1977
1978 static int hw_mic_source_switch_get(struct hw *hw)
1979 {
1980 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1981
1982 return hw20k2->mic_source;
1983 }
1984
1985 static int hw_mic_source_switch_put(struct hw *hw, int position)
1986 {
1987 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1988
1989 if (position == hw20k2->mic_source)
1990 return 0;
1991
1992 switch (position) {
1993 case 0:
1994 hw_wm8775_input_select(hw, 0, 0); /* Mic, 0dB */
1995 break;
1996 case 1:
1997 hw_wm8775_input_select(hw, 1, 0); /* FP Mic, 0dB */
1998 break;
1999 case 2:
2000 hw_wm8775_input_select(hw, 3, 0); /* Aux Ext, 0dB */
2001 break;
2002 default:
2003 return 0;
2004 }
2005
2006 hw20k2->mic_source = position;
2007
2008 return 1;
2009 }
2010
2011 static irqreturn_t ct_20k2_interrupt(int irq, void *dev_id)
2012 {
2013 struct hw *hw = dev_id;
2014 unsigned int status;
2015
2016 status = hw_read_20kx(hw, GIP);
2017 if (!status)
2018 return IRQ_NONE;
2019
2020 if (hw->irq_callback)
2021 hw->irq_callback(hw->irq_callback_data, status);
2022
2023 hw_write_20kx(hw, GIP, status);
2024 return IRQ_HANDLED;
2025 }
2026
2027 static int hw_card_start(struct hw *hw)
2028 {
2029 int err = 0;
2030 struct pci_dev *pci = hw->pci;
2031 unsigned int gctl;
2032
2033 err = pci_enable_device(pci);
2034 if (err < 0)
2035 return err;
2036
2037 /* Set DMA transfer mask */
2038 if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 ||
2039 pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) {
2040 dev_err(hw->card->dev,
2041 "architecture does not support PCI busmaster DMA with mask 0x%llx\n",
2042 CT_XFI_DMA_MASK);
2043 err = -ENXIO;
2044 goto error1;
2045 }
2046
2047 if (!hw->io_base) {
2048 err = pci_request_regions(pci, "XFi");
2049 if (err < 0)
2050 goto error1;
2051
2052 hw->io_base = pci_resource_start(hw->pci, 2);
2053 hw->mem_base = ioremap(hw->io_base,
2054 pci_resource_len(hw->pci, 2));
2055 if (!hw->mem_base) {
2056 err = -ENOENT;
2057 goto error2;
2058 }
2059 }
2060
2061 /* Switch to 20k2 mode from UAA mode. */
2062 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
2063 set_field(&gctl, GCTL_UAA, 0);
2064 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
2065
2066 if (hw->irq < 0) {
2067 err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED,
2068 KBUILD_MODNAME, hw);
2069 if (err < 0) {
2070 dev_err(hw->card->dev,
2071 "XFi: Cannot get irq %d\n", pci->irq);
2072 goto error2;
2073 }
2074 hw->irq = pci->irq;
2075 }
2076
2077 pci_set_master(pci);
2078
2079 return 0;
2080
2081 /*error3:
2082 iounmap((void *)hw->mem_base);
2083 hw->mem_base = (unsigned long)NULL;*/
2084 error2:
2085 pci_release_regions(pci);
2086 hw->io_base = 0;
2087 error1:
2088 pci_disable_device(pci);
2089 return err;
2090 }
2091
2092 static int hw_card_stop(struct hw *hw)
2093 {
2094 unsigned int data;
2095
2096 /* disable transport bus master and queueing of request */
2097 hw_write_20kx(hw, TRANSPORT_CTL, 0x00);
2098
2099 /* disable pll */
2100 data = hw_read_20kx(hw, PLL_ENB);
2101 hw_write_20kx(hw, PLL_ENB, (data & (~0x07)));
2102
2103 /* TODO: Disable interrupt and so on... */
2104 return 0;
2105 }
2106
2107 static int hw_card_shutdown(struct hw *hw)
2108 {
2109 if (hw->irq >= 0)
2110 free_irq(hw->irq, hw);
2111
2112 hw->irq = -1;
2113 iounmap(hw->mem_base);
2114 hw->mem_base = NULL;
2115
2116 if (hw->io_base)
2117 pci_release_regions(hw->pci);
2118
2119 hw->io_base = 0;
2120
2121 pci_disable_device(hw->pci);
2122
2123 return 0;
2124 }
2125
2126 static int hw_card_init(struct hw *hw, struct card_conf *info)
2127 {
2128 int err;
2129 unsigned int gctl;
2130 u32 data = 0;
2131 struct dac_conf dac_info = {0};
2132 struct adc_conf adc_info = {0};
2133 struct daio_conf daio_info = {0};
2134 struct trn_conf trn_info = {0};
2135
2136 /* Get PCI io port/memory base address and
2137 * do 20kx core switch if needed. */
2138 err = hw_card_start(hw);
2139 if (err)
2140 return err;
2141
2142 /* PLL init */
2143 err = hw_pll_init(hw, info->rsr);
2144 if (err < 0)
2145 return err;
2146
2147 /* kick off auto-init */
2148 err = hw_auto_init(hw);
2149 if (err < 0)
2150 return err;
2151
2152 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
2153 set_field(&gctl, GCTL_DBP, 1);
2154 set_field(&gctl, GCTL_TBP, 1);
2155 set_field(&gctl, GCTL_FBP, 1);
2156 set_field(&gctl, GCTL_DPC, 0);
2157 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
2158
2159 /* Reset all global pending interrupts */
2160 hw_write_20kx(hw, GIE, 0);
2161 /* Reset all SRC pending interrupts */
2162 hw_write_20kx(hw, SRC_IP, 0);
2163
2164 if (hw->model != CTSB1270) {
2165 /* TODO: detect the card ID and configure GPIO accordingly. */
2166 /* Configures GPIO (0xD802 0x98028) */
2167 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
2168 /* Configures GPIO (SB0880) */
2169 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
2170 hw_write_20kx(hw, GPIO_CTRL, 0xD802);
2171 } else {
2172 hw_write_20kx(hw, GPIO_CTRL, 0x9E5F);
2173 }
2174 /* Enable audio ring */
2175 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
2176
2177 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2178 err = hw_trn_init(hw, &trn_info);
2179 if (err < 0)
2180 return err;
2181
2182 daio_info.msr = info->msr;
2183 err = hw_daio_init(hw, &daio_info);
2184 if (err < 0)
2185 return err;
2186
2187 dac_info.msr = info->msr;
2188 err = hw_dac_init(hw, &dac_info);
2189 if (err < 0)
2190 return err;
2191
2192 adc_info.msr = info->msr;
2193 adc_info.input = ADC_LINEIN;
2194 adc_info.mic20db = 0;
2195 err = hw_adc_init(hw, &adc_info);
2196 if (err < 0)
2197 return err;
2198
2199 data = hw_read_20kx(hw, SRC_MCTL);
2200 data |= 0x1; /* Enables input from the audio ring */
2201 hw_write_20kx(hw, SRC_MCTL, data);
2202
2203 return 0;
2204 }
2205
2206 #ifdef CONFIG_PM_SLEEP
2207 static int hw_suspend(struct hw *hw)
2208 {
2209 hw_card_stop(hw);
2210 return 0;
2211 }
2212
2213 static int hw_resume(struct hw *hw, struct card_conf *info)
2214 {
2215 /* Re-initialize card hardware. */
2216 return hw_card_init(hw, info);
2217 }
2218 #endif
2219
2220 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2221 {
2222 return readl(hw->mem_base + reg);
2223 }
2224
2225 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2226 {
2227 writel(data, hw->mem_base + reg);
2228 }
2229
2230 static struct hw ct20k2_preset = {
2231 .irq = -1,
2232
2233 .card_init = hw_card_init,
2234 .card_stop = hw_card_stop,
2235 .pll_init = hw_pll_init,
2236 .is_adc_source_selected = hw_is_adc_input_selected,
2237 .select_adc_source = hw_adc_input_select,
2238 .capabilities = hw_capabilities,
2239 .output_switch_get = hw_output_switch_get,
2240 .output_switch_put = hw_output_switch_put,
2241 .mic_source_switch_get = hw_mic_source_switch_get,
2242 .mic_source_switch_put = hw_mic_source_switch_put,
2243 #ifdef CONFIG_PM_SLEEP
2244 .suspend = hw_suspend,
2245 .resume = hw_resume,
2246 #endif
2247
2248 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2249 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2250 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2251 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2252 .src_set_state = src_set_state,
2253 .src_set_bm = src_set_bm,
2254 .src_set_rsr = src_set_rsr,
2255 .src_set_sf = src_set_sf,
2256 .src_set_wr = src_set_wr,
2257 .src_set_pm = src_set_pm,
2258 .src_set_rom = src_set_rom,
2259 .src_set_vo = src_set_vo,
2260 .src_set_st = src_set_st,
2261 .src_set_ie = src_set_ie,
2262 .src_set_ilsz = src_set_ilsz,
2263 .src_set_bp = src_set_bp,
2264 .src_set_cisz = src_set_cisz,
2265 .src_set_ca = src_set_ca,
2266 .src_set_sa = src_set_sa,
2267 .src_set_la = src_set_la,
2268 .src_set_pitch = src_set_pitch,
2269 .src_set_dirty = src_set_dirty,
2270 .src_set_clear_zbufs = src_set_clear_zbufs,
2271 .src_set_dirty_all = src_set_dirty_all,
2272 .src_commit_write = src_commit_write,
2273 .src_get_ca = src_get_ca,
2274 .src_get_dirty = src_get_dirty,
2275 .src_dirty_conj_mask = src_dirty_conj_mask,
2276 .src_mgr_enbs_src = src_mgr_enbs_src,
2277 .src_mgr_enb_src = src_mgr_enb_src,
2278 .src_mgr_dsb_src = src_mgr_dsb_src,
2279 .src_mgr_commit_write = src_mgr_commit_write,
2280
2281 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2282 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2283 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2284 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2285 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2286 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2287 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2288
2289 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2290 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2291 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2292 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2293 .amixer_set_mode = amixer_set_mode,
2294 .amixer_set_iv = amixer_set_iv,
2295 .amixer_set_x = amixer_set_x,
2296 .amixer_set_y = amixer_set_y,
2297 .amixer_set_sadr = amixer_set_sadr,
2298 .amixer_set_se = amixer_set_se,
2299 .amixer_set_dirty = amixer_set_dirty,
2300 .amixer_set_dirty_all = amixer_set_dirty_all,
2301 .amixer_commit_write = amixer_commit_write,
2302 .amixer_get_y = amixer_get_y,
2303 .amixer_get_dirty = amixer_get_dirty,
2304
2305 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2306 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2307 .dai_srt_set_srco = dai_srt_set_srco,
2308 .dai_srt_set_srcm = dai_srt_set_srcm,
2309 .dai_srt_set_rsr = dai_srt_set_rsr,
2310 .dai_srt_set_drat = dai_srt_set_drat,
2311 .dai_srt_set_ec = dai_srt_set_ec,
2312 .dai_srt_set_et = dai_srt_set_et,
2313 .dai_commit_write = dai_commit_write,
2314
2315 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2316 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2317 .dao_set_spos = dao_set_spos,
2318 .dao_commit_write = dao_commit_write,
2319 .dao_get_spos = dao_get_spos,
2320
2321 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2322 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2323 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2324 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2325 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2326 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2327 .daio_mgr_dao_init = daio_mgr_dao_init,
2328 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2329 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2330 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2331 .daio_mgr_commit_write = daio_mgr_commit_write,
2332
2333 .set_timer_irq = set_timer_irq,
2334 .set_timer_tick = set_timer_tick,
2335 .get_wc = get_wc,
2336 };
2337
2338 int create_20k2_hw_obj(struct hw **rhw)
2339 {
2340 struct hw20k2 *hw20k2;
2341
2342 *rhw = NULL;
2343 hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL);
2344 if (!hw20k2)
2345 return -ENOMEM;
2346
2347 hw20k2->hw = ct20k2_preset;
2348 *rhw = &hw20k2->hw;
2349
2350 return 0;
2351 }
2352
2353 int destroy_20k2_hw_obj(struct hw *hw)
2354 {
2355 if (hw->io_base)
2356 hw_card_shutdown(hw);
2357
2358 kfree(hw);
2359 return 0;
2360 }
Linux with added FPC-III support