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sit: use the right netns in ioctl handler
[linux/fpc-iii.git] / drivers / iommu / arm-smmu.c
blob8b89e33a89fe99057d99e322ce2c287b41c0eb2f
1 /*
2 * IOMMU API for ARM architected SMMU implementations.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 *
17 * Copyright (C) 2013 ARM Limited
18 *
19 * Author: Will Deacon <will.deacon@arm.com>
20 *
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - 4k and 64k pages, with contiguous pte hints.
27 * - Up to 42-bit addressing (dependent on VA_BITS)
28 * - Context fault reporting
29 */
30
31 #define pr_fmt(fmt) "arm-smmu: " fmt
32
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/err.h>
36 #include <linux/interrupt.h>
37 #include <linux/io.h>
38 #include <linux/iommu.h>
39 #include <linux/mm.h>
40 #include <linux/module.h>
41 #include <linux/of.h>
42 #include <linux/platform_device.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
45
46 #include <linux/amba/bus.h>
47
48 #include <asm/pgalloc.h>
49
50 /* Maximum number of stream IDs assigned to a single device */
51 #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
52
53 /* Maximum number of context banks per SMMU */
54 #define ARM_SMMU_MAX_CBS 128
55
56 /* Maximum number of mapping groups per SMMU */
57 #define ARM_SMMU_MAX_SMRS 128
58
59 /* SMMU global address space */
60 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
61 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
62
63 /*
64 * SMMU global address space with conditional offset to access secure
65 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
66 * nsGFSYNR0: 0x450)
67 */
68 #define ARM_SMMU_GR0_NS(smmu) \
69 ((smmu)->base + \
70 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
71 ? 0x400 : 0))
72
73 /* Page table bits */
74 #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
75 #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
76 #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10)
77 #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8)
78 #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8)
79 #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8)
80 #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
81
82 #if PAGE_SIZE == SZ_4K
83 #define ARM_SMMU_PTE_CONT_ENTRIES 16
84 #elif PAGE_SIZE == SZ_64K
85 #define ARM_SMMU_PTE_CONT_ENTRIES 32
86 #else
87 #define ARM_SMMU_PTE_CONT_ENTRIES 1
88 #endif
89
90 #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
91 #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1))
92
93 /* Stage-1 PTE */
94 #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6)
95 #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6)
96 #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2
97 #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11)
98
99 /* Stage-2 PTE */
100 #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6)
101 #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6)
102 #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6)
103 #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2)
104 #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2)
105 #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2)
106
107 /* Configuration registers */
108 #define ARM_SMMU_GR0_sCR0 0x0
109 #define sCR0_CLIENTPD (1 << 0)
110 #define sCR0_GFRE (1 << 1)
111 #define sCR0_GFIE (1 << 2)
112 #define sCR0_GCFGFRE (1 << 4)
113 #define sCR0_GCFGFIE (1 << 5)
114 #define sCR0_USFCFG (1 << 10)
115 #define sCR0_VMIDPNE (1 << 11)
116 #define sCR0_PTM (1 << 12)
117 #define sCR0_FB (1 << 13)
118 #define sCR0_BSU_SHIFT 14
119 #define sCR0_BSU_MASK 0x3
120
121 /* Identification registers */
122 #define ARM_SMMU_GR0_ID0 0x20
123 #define ARM_SMMU_GR0_ID1 0x24
124 #define ARM_SMMU_GR0_ID2 0x28
125 #define ARM_SMMU_GR0_ID3 0x2c
126 #define ARM_SMMU_GR0_ID4 0x30
127 #define ARM_SMMU_GR0_ID5 0x34
128 #define ARM_SMMU_GR0_ID6 0x38
129 #define ARM_SMMU_GR0_ID7 0x3c
130 #define ARM_SMMU_GR0_sGFSR 0x48
131 #define ARM_SMMU_GR0_sGFSYNR0 0x50
132 #define ARM_SMMU_GR0_sGFSYNR1 0x54
133 #define ARM_SMMU_GR0_sGFSYNR2 0x58
134 #define ARM_SMMU_GR0_PIDR0 0xfe0
135 #define ARM_SMMU_GR0_PIDR1 0xfe4
136 #define ARM_SMMU_GR0_PIDR2 0xfe8
137
138 #define ID0_S1TS (1 << 30)
139 #define ID0_S2TS (1 << 29)
140 #define ID0_NTS (1 << 28)
141 #define ID0_SMS (1 << 27)
142 #define ID0_PTFS_SHIFT 24
143 #define ID0_PTFS_MASK 0x2
144 #define ID0_PTFS_V8_ONLY 0x2
145 #define ID0_CTTW (1 << 14)
146 #define ID0_NUMIRPT_SHIFT 16
147 #define ID0_NUMIRPT_MASK 0xff
148 #define ID0_NUMSMRG_SHIFT 0
149 #define ID0_NUMSMRG_MASK 0xff
150
151 #define ID1_PAGESIZE (1 << 31)
152 #define ID1_NUMPAGENDXB_SHIFT 28
153 #define ID1_NUMPAGENDXB_MASK 7
154 #define ID1_NUMS2CB_SHIFT 16
155 #define ID1_NUMS2CB_MASK 0xff
156 #define ID1_NUMCB_SHIFT 0
157 #define ID1_NUMCB_MASK 0xff
158
159 #define ID2_OAS_SHIFT 4
160 #define ID2_OAS_MASK 0xf
161 #define ID2_IAS_SHIFT 0
162 #define ID2_IAS_MASK 0xf
163 #define ID2_UBS_SHIFT 8
164 #define ID2_UBS_MASK 0xf
165 #define ID2_PTFS_4K (1 << 12)
166 #define ID2_PTFS_16K (1 << 13)
167 #define ID2_PTFS_64K (1 << 14)
168
169 #define PIDR2_ARCH_SHIFT 4
170 #define PIDR2_ARCH_MASK 0xf
171
172 /* Global TLB invalidation */
173 #define ARM_SMMU_GR0_STLBIALL 0x60
174 #define ARM_SMMU_GR0_TLBIVMID 0x64
175 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
176 #define ARM_SMMU_GR0_TLBIALLH 0x6c
177 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
178 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
179 #define sTLBGSTATUS_GSACTIVE (1 << 0)
180 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
181
182 /* Stream mapping registers */
183 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
184 #define SMR_VALID (1 << 31)
185 #define SMR_MASK_SHIFT 16
186 #define SMR_MASK_MASK 0x7fff
187 #define SMR_ID_SHIFT 0
188 #define SMR_ID_MASK 0x7fff
189
190 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
191 #define S2CR_CBNDX_SHIFT 0
192 #define S2CR_CBNDX_MASK 0xff
193 #define S2CR_TYPE_SHIFT 16
194 #define S2CR_TYPE_MASK 0x3
195 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
196 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
197 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
198
199 /* Context bank attribute registers */
200 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
201 #define CBAR_VMID_SHIFT 0
202 #define CBAR_VMID_MASK 0xff
203 #define CBAR_S1_BPSHCFG_SHIFT 8
204 #define CBAR_S1_BPSHCFG_MASK 3
205 #define CBAR_S1_BPSHCFG_NSH 3
206 #define CBAR_S1_MEMATTR_SHIFT 12
207 #define CBAR_S1_MEMATTR_MASK 0xf
208 #define CBAR_S1_MEMATTR_WB 0xf
209 #define CBAR_TYPE_SHIFT 16
210 #define CBAR_TYPE_MASK 0x3
211 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
212 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
213 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
214 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
215 #define CBAR_IRPTNDX_SHIFT 24
216 #define CBAR_IRPTNDX_MASK 0xff
217
218 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
219 #define CBA2R_RW64_32BIT (0 << 0)
220 #define CBA2R_RW64_64BIT (1 << 0)
221
222 /* Translation context bank */
223 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
224 #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize)
225
226 #define ARM_SMMU_CB_SCTLR 0x0
227 #define ARM_SMMU_CB_RESUME 0x8
228 #define ARM_SMMU_CB_TTBCR2 0x10
229 #define ARM_SMMU_CB_TTBR0_LO 0x20
230 #define ARM_SMMU_CB_TTBR0_HI 0x24
231 #define ARM_SMMU_CB_TTBCR 0x30
232 #define ARM_SMMU_CB_S1_MAIR0 0x38
233 #define ARM_SMMU_CB_FSR 0x58
234 #define ARM_SMMU_CB_FAR_LO 0x60
235 #define ARM_SMMU_CB_FAR_HI 0x64
236 #define ARM_SMMU_CB_FSYNR0 0x68
237 #define ARM_SMMU_CB_S1_TLBIASID 0x610
238
239 #define SCTLR_S1_ASIDPNE (1 << 12)
240 #define SCTLR_CFCFG (1 << 7)
241 #define SCTLR_CFIE (1 << 6)
242 #define SCTLR_CFRE (1 << 5)
243 #define SCTLR_E (1 << 4)
244 #define SCTLR_AFE (1 << 2)
245 #define SCTLR_TRE (1 << 1)
246 #define SCTLR_M (1 << 0)
247 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
248
249 #define RESUME_RETRY (0 << 0)
250 #define RESUME_TERMINATE (1 << 0)
251
252 #define TTBCR_EAE (1 << 31)
253
254 #define TTBCR_PASIZE_SHIFT 16
255 #define TTBCR_PASIZE_MASK 0x7
256
257 #define TTBCR_TG0_4K (0 << 14)
258 #define TTBCR_TG0_64K (1 << 14)
259
260 #define TTBCR_SH0_SHIFT 12
261 #define TTBCR_SH0_MASK 0x3
262 #define TTBCR_SH_NS 0
263 #define TTBCR_SH_OS 2
264 #define TTBCR_SH_IS 3
265
266 #define TTBCR_ORGN0_SHIFT 10
267 #define TTBCR_IRGN0_SHIFT 8
268 #define TTBCR_RGN_MASK 0x3
269 #define TTBCR_RGN_NC 0
270 #define TTBCR_RGN_WBWA 1
271 #define TTBCR_RGN_WT 2
272 #define TTBCR_RGN_WB 3
273
274 #define TTBCR_SL0_SHIFT 6
275 #define TTBCR_SL0_MASK 0x3
276 #define TTBCR_SL0_LVL_2 0
277 #define TTBCR_SL0_LVL_1 1
278
279 #define TTBCR_T1SZ_SHIFT 16
280 #define TTBCR_T0SZ_SHIFT 0
281 #define TTBCR_SZ_MASK 0xf
282
283 #define TTBCR2_SEP_SHIFT 15
284 #define TTBCR2_SEP_MASK 0x7
285
286 #define TTBCR2_PASIZE_SHIFT 0
287 #define TTBCR2_PASIZE_MASK 0x7
288
289 /* Common definitions for PASize and SEP fields */
290 #define TTBCR2_ADDR_32 0
291 #define TTBCR2_ADDR_36 1
292 #define TTBCR2_ADDR_40 2
293 #define TTBCR2_ADDR_42 3
294 #define TTBCR2_ADDR_44 4
295 #define TTBCR2_ADDR_48 5
296
297 #define TTBRn_HI_ASID_SHIFT 16
298
299 #define MAIR_ATTR_SHIFT(n) ((n) << 3)
300 #define MAIR_ATTR_MASK 0xff
301 #define MAIR_ATTR_DEVICE 0x04
302 #define MAIR_ATTR_NC 0x44
303 #define MAIR_ATTR_WBRWA 0xff
304 #define MAIR_ATTR_IDX_NC 0
305 #define MAIR_ATTR_IDX_CACHE 1
306 #define MAIR_ATTR_IDX_DEV 2
307
308 #define FSR_MULTI (1 << 31)
309 #define FSR_SS (1 << 30)
310 #define FSR_UUT (1 << 8)
311 #define FSR_ASF (1 << 7)
312 #define FSR_TLBLKF (1 << 6)
313 #define FSR_TLBMCF (1 << 5)
314 #define FSR_EF (1 << 4)
315 #define FSR_PF (1 << 3)
316 #define FSR_AFF (1 << 2)
317 #define FSR_TF (1 << 1)
318
319 #define FSR_IGN (FSR_AFF | FSR_ASF | FSR_TLBMCF | \
320 FSR_TLBLKF)
321 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
322 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
323
324 #define FSYNR0_WNR (1 << 4)
325
326 struct arm_smmu_smr {
327 u8 idx;
328 u16 mask;
329 u16 id;
330 };
331
332 struct arm_smmu_master {
333 struct device_node *of_node;
334
335 /*
336 * The following is specific to the master's position in the
337 * SMMU chain.
338 */
339 struct rb_node node;
340 int num_streamids;
341 u16 streamids[MAX_MASTER_STREAMIDS];
342
343 /*
344 * We only need to allocate these on the root SMMU, as we
345 * configure unmatched streams to bypass translation.
346 */
347 struct arm_smmu_smr *smrs;
348 };
349
350 struct arm_smmu_device {
351 struct device *dev;
352 struct device_node *parent_of_node;
353
354 void __iomem *base;
355 unsigned long size;
356 unsigned long pagesize;
357
358 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
359 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
360 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
361 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
362 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
363 u32 features;
364
365 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
366 u32 options;
367 int version;
368
369 u32 num_context_banks;
370 u32 num_s2_context_banks;
371 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
372 atomic_t irptndx;
373
374 u32 num_mapping_groups;
375 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
376
377 unsigned long input_size;
378 unsigned long s1_output_size;
379 unsigned long s2_output_size;
380
381 u32 num_global_irqs;
382 u32 num_context_irqs;
383 unsigned int *irqs;
384
385 struct list_head list;
386 struct rb_root masters;
387 };
388
389 struct arm_smmu_cfg {
390 struct arm_smmu_device *smmu;
391 u8 cbndx;
392 u8 irptndx;
393 u32 cbar;
394 pgd_t *pgd;
395 };
396 #define INVALID_IRPTNDX 0xff
397
398 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
399 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
400
401 struct arm_smmu_domain {
402 /*
403 * A domain can span across multiple, chained SMMUs and requires
404 * all devices within the domain to follow the same translation
405 * path.
406 */
407 struct arm_smmu_device *leaf_smmu;
408 struct arm_smmu_cfg root_cfg;
409 phys_addr_t output_mask;
410
411 spinlock_t lock;
412 };
413
414 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
415 static LIST_HEAD(arm_smmu_devices);
416
417 struct arm_smmu_option_prop {
418 u32 opt;
419 const char *prop;
420 };
421
422 static struct arm_smmu_option_prop arm_smmu_options [] = {
423 { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
424 { 0, NULL},
425 };
426
427 static void parse_driver_options(struct arm_smmu_device *smmu)
428 {
429 int i = 0;
430 do {
431 if (of_property_read_bool(smmu->dev->of_node,
432 arm_smmu_options[i].prop)) {
433 smmu->options |= arm_smmu_options[i].opt;
434 dev_notice(smmu->dev, "option %s\n",
435 arm_smmu_options[i].prop);
436 }
437 } while (arm_smmu_options[++i].opt);
438 }
439
440 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
441 struct device_node *dev_node)
442 {
443 struct rb_node *node = smmu->masters.rb_node;
444
445 while (node) {
446 struct arm_smmu_master *master;
447 master = container_of(node, struct arm_smmu_master, node);
448
449 if (dev_node < master->of_node)
450 node = node->rb_left;
451 else if (dev_node > master->of_node)
452 node = node->rb_right;
453 else
454 return master;
455 }
456
457 return NULL;
458 }
459
460 static int insert_smmu_master(struct arm_smmu_device *smmu,
461 struct arm_smmu_master *master)
462 {
463 struct rb_node **new, *parent;
464
465 new = &smmu->masters.rb_node;
466 parent = NULL;
467 while (*new) {
468 struct arm_smmu_master *this;
469 this = container_of(*new, struct arm_smmu_master, node);
470
471 parent = *new;
472 if (master->of_node < this->of_node)
473 new = &((*new)->rb_left);
474 else if (master->of_node > this->of_node)
475 new = &((*new)->rb_right);
476 else
477 return -EEXIST;
478 }
479
480 rb_link_node(&master->node, parent, new);
481 rb_insert_color(&master->node, &smmu->masters);
482 return 0;
483 }
484
485 static int register_smmu_master(struct arm_smmu_device *smmu,
486 struct device *dev,
487 struct of_phandle_args *masterspec)
488 {
489 int i;
490 struct arm_smmu_master *master;
491
492 master = find_smmu_master(smmu, masterspec->np);
493 if (master) {
494 dev_err(dev,
495 "rejecting multiple registrations for master device %s\n",
496 masterspec->np->name);
497 return -EBUSY;
498 }
499
500 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
501 dev_err(dev,
502 "reached maximum number (%d) of stream IDs for master device %s\n",
503 MAX_MASTER_STREAMIDS, masterspec->np->name);
504 return -ENOSPC;
505 }
506
507 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
508 if (!master)
509 return -ENOMEM;
510
511 master->of_node = masterspec->np;
512 master->num_streamids = masterspec->args_count;
513
514 for (i = 0; i < master->num_streamids; ++i)
515 master->streamids[i] = masterspec->args[i];
516
517 return insert_smmu_master(smmu, master);
518 }
519
520 static struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu)
521 {
522 struct arm_smmu_device *parent;
523
524 if (!smmu->parent_of_node)
525 return NULL;
526
527 spin_lock(&arm_smmu_devices_lock);
528 list_for_each_entry(parent, &arm_smmu_devices, list)
529 if (parent->dev->of_node == smmu->parent_of_node)
530 goto out_unlock;
531
532 parent = NULL;
533 dev_warn(smmu->dev,
534 "Failed to find SMMU parent despite parent in DT\n");
535 out_unlock:
536 spin_unlock(&arm_smmu_devices_lock);
537 return parent;
538 }
539
540 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
541 {
542 int idx;
543
544 do {
545 idx = find_next_zero_bit(map, end, start);
546 if (idx == end)
547 return -ENOSPC;
548 } while (test_and_set_bit(idx, map));
549
550 return idx;
551 }
552
553 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
554 {
555 clear_bit(idx, map);
556 }
557
558 /* Wait for any pending TLB invalidations to complete */
559 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
560 {
561 int count = 0;
562 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
563
564 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
565 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
566 & sTLBGSTATUS_GSACTIVE) {
567 cpu_relax();
568 if (++count == TLB_LOOP_TIMEOUT) {
569 dev_err_ratelimited(smmu->dev,
570 "TLB sync timed out -- SMMU may be deadlocked\n");
571 return;
572 }
573 udelay(1);
574 }
575 }
576
577 static void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg)
578 {
579 struct arm_smmu_device *smmu = cfg->smmu;
580 void __iomem *base = ARM_SMMU_GR0(smmu);
581 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
582
583 if (stage1) {
584 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
585 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
586 base + ARM_SMMU_CB_S1_TLBIASID);
587 } else {
588 base = ARM_SMMU_GR0(smmu);
589 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
590 base + ARM_SMMU_GR0_TLBIVMID);
591 }
592
593 arm_smmu_tlb_sync(smmu);
594 }
595
596 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
597 {
598 int flags, ret;
599 u32 fsr, far, fsynr, resume;
600 unsigned long iova;
601 struct iommu_domain *domain = dev;
602 struct arm_smmu_domain *smmu_domain = domain->priv;
603 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
604 struct arm_smmu_device *smmu = root_cfg->smmu;
605 void __iomem *cb_base;
606
607 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
608 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
609
610 if (!(fsr & FSR_FAULT))
611 return IRQ_NONE;
612
613 if (fsr & FSR_IGN)
614 dev_err_ratelimited(smmu->dev,
615 "Unexpected context fault (fsr 0x%u)\n",
616 fsr);
617
618 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
619 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
620
621 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
622 iova = far;
623 #ifdef CONFIG_64BIT
624 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
625 iova |= ((unsigned long)far << 32);
626 #endif
627
628 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
629 ret = IRQ_HANDLED;
630 resume = RESUME_RETRY;
631 } else {
632 dev_err_ratelimited(smmu->dev,
633 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
634 iova, fsynr, root_cfg->cbndx);
635 ret = IRQ_NONE;
636 resume = RESUME_TERMINATE;
637 }
638
639 /* Clear the faulting FSR */
640 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
641
642 /* Retry or terminate any stalled transactions */
643 if (fsr & FSR_SS)
644 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
645
646 return ret;
647 }
648
649 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
650 {
651 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
652 struct arm_smmu_device *smmu = dev;
653 void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
654
655 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
656 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
657 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
658 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
659
660 if (!gfsr)
661 return IRQ_NONE;
662
663 dev_err_ratelimited(smmu->dev,
664 "Unexpected global fault, this could be serious\n");
665 dev_err_ratelimited(smmu->dev,
666 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
667 gfsr, gfsynr0, gfsynr1, gfsynr2);
668
669 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
670 return IRQ_HANDLED;
671 }
672
673 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
674 size_t size)
675 {
676 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
677
678
679 /* Ensure new page tables are visible to the hardware walker */
680 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
681 dsb(ishst);
682 } else {
683 /*
684 * If the SMMU can't walk tables in the CPU caches, treat them
685 * like non-coherent DMA since we need to flush the new entries
686 * all the way out to memory. There's no possibility of
687 * recursion here as the SMMU table walker will not be wired
688 * through another SMMU.
689 */
690 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
691 DMA_TO_DEVICE);
692 }
693 }
694
695 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
696 {
697 u32 reg;
698 bool stage1;
699 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
700 struct arm_smmu_device *smmu = root_cfg->smmu;
701 void __iomem *cb_base, *gr0_base, *gr1_base;
702
703 gr0_base = ARM_SMMU_GR0(smmu);
704 gr1_base = ARM_SMMU_GR1(smmu);
705 stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS;
706 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
707
708 /* CBAR */
709 reg = root_cfg->cbar;
710 if (smmu->version == 1)
711 reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT;
712
713 /*
714 * Use the weakest shareability/memory types, so they are
715 * overridden by the ttbcr/pte.
716 */
717 if (stage1) {
718 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
719 (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
720 } else {
721 reg |= ARM_SMMU_CB_VMID(root_cfg) << CBAR_VMID_SHIFT;
722 }
723 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx));
724
725 if (smmu->version > 1) {
726 /* CBA2R */
727 #ifdef CONFIG_64BIT
728 reg = CBA2R_RW64_64BIT;
729 #else
730 reg = CBA2R_RW64_32BIT;
731 #endif
732 writel_relaxed(reg,
733 gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx));
734
735 /* TTBCR2 */
736 switch (smmu->input_size) {
737 case 32:
738 reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
739 break;
740 case 36:
741 reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
742 break;
743 case 39:
744 reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
745 break;
746 case 42:
747 reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
748 break;
749 case 44:
750 reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
751 break;
752 case 48:
753 reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
754 break;
755 }
756
757 switch (smmu->s1_output_size) {
758 case 32:
759 reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
760 break;
761 case 36:
762 reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
763 break;
764 case 39:
765 reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
766 break;
767 case 42:
768 reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
769 break;
770 case 44:
771 reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
772 break;
773 case 48:
774 reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
775 break;
776 }
777
778 if (stage1)
779 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
780 }
781
782 /* TTBR0 */
783 arm_smmu_flush_pgtable(smmu, root_cfg->pgd,
784 PTRS_PER_PGD * sizeof(pgd_t));
785 reg = __pa(root_cfg->pgd);
786 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
787 reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32;
788 if (stage1)
789 reg |= ARM_SMMU_CB_ASID(root_cfg) << TTBRn_HI_ASID_SHIFT;
790 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
791
792 /*
793 * TTBCR
794 * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
795 */
796 if (smmu->version > 1) {
797 if (PAGE_SIZE == SZ_4K)
798 reg = TTBCR_TG0_4K;
799 else
800 reg = TTBCR_TG0_64K;
801
802 if (!stage1) {
803 switch (smmu->s2_output_size) {
804 case 32:
805 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
806 break;
807 case 36:
808 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
809 break;
810 case 40:
811 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
812 break;
813 case 42:
814 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
815 break;
816 case 44:
817 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
818 break;
819 case 48:
820 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
821 break;
822 }
823 } else {
824 reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
825 }
826 } else {
827 reg = 0;
828 }
829
830 reg |= TTBCR_EAE |
831 (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
832 (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
833 (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
834 (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
835 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
836
837 /* MAIR0 (stage-1 only) */
838 if (stage1) {
839 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
840 (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
841 (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
842 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
843 }
844
845 /* SCTLR */
846 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
847 if (stage1)
848 reg |= SCTLR_S1_ASIDPNE;
849 #ifdef __BIG_ENDIAN
850 reg |= SCTLR_E;
851 #endif
852 writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
853 }
854
855 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
856 struct device *dev)
857 {
858 int irq, ret, start;
859 struct arm_smmu_domain *smmu_domain = domain->priv;
860 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
861 struct arm_smmu_device *smmu, *parent;
862
863 /*
864 * Walk the SMMU chain to find the root device for this chain.
865 * We assume that no masters have translations which terminate
866 * early, and therefore check that the root SMMU does indeed have
867 * a StreamID for the master in question.
868 */
869 parent = dev->archdata.iommu;
870 smmu_domain->output_mask = -1;
871 do {
872 smmu = parent;
873 smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1;
874 } while ((parent = find_parent_smmu(smmu)));
875
876 if (!find_smmu_master(smmu, dev->of_node)) {
877 dev_err(dev, "unable to find root SMMU for device\n");
878 return -ENODEV;
879 }
880
881 if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
882 /*
883 * We will likely want to change this if/when KVM gets
884 * involved.
885 */
886 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
887 start = smmu->num_s2_context_banks;
888 } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) {
889 root_cfg->cbar = CBAR_TYPE_S2_TRANS;
890 start = 0;
891 } else {
892 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
893 start = smmu->num_s2_context_banks;
894 }
895
896 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
897 smmu->num_context_banks);
898 if (IS_ERR_VALUE(ret))
899 return ret;
900
901 root_cfg->cbndx = ret;
902 if (smmu->version == 1) {
903 root_cfg->irptndx = atomic_inc_return(&smmu->irptndx);
904 root_cfg->irptndx %= smmu->num_context_irqs;
905 } else {
906 root_cfg->irptndx = root_cfg->cbndx;
907 }
908
909 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
910 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
911 "arm-smmu-context-fault", domain);
912 if (IS_ERR_VALUE(ret)) {
913 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
914 root_cfg->irptndx, irq);
915 root_cfg->irptndx = INVALID_IRPTNDX;
916 goto out_free_context;
917 }
918
919 root_cfg->smmu = smmu;
920 arm_smmu_init_context_bank(smmu_domain);
921 return ret;
922
923 out_free_context:
924 __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
925 return ret;
926 }
927
928 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
929 {
930 struct arm_smmu_domain *smmu_domain = domain->priv;
931 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
932 struct arm_smmu_device *smmu = root_cfg->smmu;
933 void __iomem *cb_base;
934 int irq;
935
936 if (!smmu)
937 return;
938
939 /* Disable the context bank and nuke the TLB before freeing it. */
940 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
941 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
942 arm_smmu_tlb_inv_context(root_cfg);
943
944 if (root_cfg->irptndx != INVALID_IRPTNDX) {
945 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
946 free_irq(irq, domain);
947 }
948
949 __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
950 }
951
952 static int arm_smmu_domain_init(struct iommu_domain *domain)
953 {
954 struct arm_smmu_domain *smmu_domain;
955 pgd_t *pgd;
956
957 /*
958 * Allocate the domain and initialise some of its data structures.
959 * We can't really do anything meaningful until we've added a
960 * master.
961 */
962 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
963 if (!smmu_domain)
964 return -ENOMEM;
965
966 pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
967 if (!pgd)
968 goto out_free_domain;
969 smmu_domain->root_cfg.pgd = pgd;
970
971 spin_lock_init(&smmu_domain->lock);
972 domain->priv = smmu_domain;
973 return 0;
974
975 out_free_domain:
976 kfree(smmu_domain);
977 return -ENOMEM;
978 }
979
980 static void arm_smmu_free_ptes(pmd_t *pmd)
981 {
982 pgtable_t table = pmd_pgtable(*pmd);
983 pgtable_page_dtor(table);
984 __free_page(table);
985 }
986
987 static void arm_smmu_free_pmds(pud_t *pud)
988 {
989 int i;
990 pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
991
992 pmd = pmd_base;
993 for (i = 0; i < PTRS_PER_PMD; ++i) {
994 if (pmd_none(*pmd))
995 continue;
996
997 arm_smmu_free_ptes(pmd);
998 pmd++;
999 }
1000
1001 pmd_free(NULL, pmd_base);
1002 }
1003
1004 static void arm_smmu_free_puds(pgd_t *pgd)
1005 {
1006 int i;
1007 pud_t *pud, *pud_base = pud_offset(pgd, 0);
1008
1009 pud = pud_base;
1010 for (i = 0; i < PTRS_PER_PUD; ++i) {
1011 if (pud_none(*pud))
1012 continue;
1013
1014 arm_smmu_free_pmds(pud);
1015 pud++;
1016 }
1017
1018 pud_free(NULL, pud_base);
1019 }
1020
1021 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
1022 {
1023 int i;
1024 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1025 pgd_t *pgd, *pgd_base = root_cfg->pgd;
1026
1027 /*
1028 * Recursively free the page tables for this domain. We don't
1029 * care about speculative TLB filling because the tables should
1030 * not be active in any context bank at this point (SCTLR.M is 0).
1031 */
1032 pgd = pgd_base;
1033 for (i = 0; i < PTRS_PER_PGD; ++i) {
1034 if (pgd_none(*pgd))
1035 continue;
1036 arm_smmu_free_puds(pgd);
1037 pgd++;
1038 }
1039
1040 kfree(pgd_base);
1041 }
1042
1043 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1044 {
1045 struct arm_smmu_domain *smmu_domain = domain->priv;
1046
1047 /*
1048 * Free the domain resources. We assume that all devices have
1049 * already been detached.
1050 */
1051 arm_smmu_destroy_domain_context(domain);
1052 arm_smmu_free_pgtables(smmu_domain);
1053 kfree(smmu_domain);
1054 }
1055
1056 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1057 struct arm_smmu_master *master)
1058 {
1059 int i;
1060 struct arm_smmu_smr *smrs;
1061 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1062
1063 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1064 return 0;
1065
1066 if (master->smrs)
1067 return -EEXIST;
1068
1069 smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL);
1070 if (!smrs) {
1071 dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n",
1072 master->num_streamids, master->of_node->name);
1073 return -ENOMEM;
1074 }
1075
1076 /* Allocate the SMRs on the root SMMU */
1077 for (i = 0; i < master->num_streamids; ++i) {
1078 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1079 smmu->num_mapping_groups);
1080 if (IS_ERR_VALUE(idx)) {
1081 dev_err(smmu->dev, "failed to allocate free SMR\n");
1082 goto err_free_smrs;
1083 }
1084
1085 smrs[i] = (struct arm_smmu_smr) {
1086 .idx = idx,
1087 .mask = 0, /* We don't currently share SMRs */
1088 .id = master->streamids[i],
1089 };
1090 }
1091
1092 /* It worked! Now, poke the actual hardware */
1093 for (i = 0; i < master->num_streamids; ++i) {
1094 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1095 smrs[i].mask << SMR_MASK_SHIFT;
1096 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1097 }
1098
1099 master->smrs = smrs;
1100 return 0;
1101
1102 err_free_smrs:
1103 while (--i >= 0)
1104 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1105 kfree(smrs);
1106 return -ENOSPC;
1107 }
1108
1109 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1110 struct arm_smmu_master *master)
1111 {
1112 int i;
1113 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1114 struct arm_smmu_smr *smrs = master->smrs;
1115
1116 /* Invalidate the SMRs before freeing back to the allocator */
1117 for (i = 0; i < master->num_streamids; ++i) {
1118 u8 idx = smrs[i].idx;
1119 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1120 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1121 }
1122
1123 master->smrs = NULL;
1124 kfree(smrs);
1125 }
1126
1127 static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
1128 struct arm_smmu_master *master)
1129 {
1130 int i;
1131 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1132
1133 for (i = 0; i < master->num_streamids; ++i) {
1134 u16 sid = master->streamids[i];
1135 writel_relaxed(S2CR_TYPE_BYPASS,
1136 gr0_base + ARM_SMMU_GR0_S2CR(sid));
1137 }
1138 }
1139
1140 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1141 struct arm_smmu_master *master)
1142 {
1143 int i, ret;
1144 struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu;
1145 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1146
1147 ret = arm_smmu_master_configure_smrs(smmu, master);
1148 if (ret)
1149 return ret;
1150
1151 /* Bypass the leaves */
1152 smmu = smmu_domain->leaf_smmu;
1153 while ((parent = find_parent_smmu(smmu))) {
1154 /*
1155 * We won't have a StreamID match for anything but the root
1156 * smmu, so we only need to worry about StreamID indexing,
1157 * where we must install bypass entries in the S2CRs.
1158 */
1159 if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)
1160 continue;
1161
1162 arm_smmu_bypass_stream_mapping(smmu, master);
1163 smmu = parent;
1164 }
1165
1166 /* Now we're at the root, time to point at our context bank */
1167 for (i = 0; i < master->num_streamids; ++i) {
1168 u32 idx, s2cr;
1169 idx = master->smrs ? master->smrs[i].idx : master->streamids[i];
1170 s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) |
1171 (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT);
1172 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1173 }
1174
1175 return 0;
1176 }
1177
1178 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1179 struct arm_smmu_master *master)
1180 {
1181 struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu;
1182
1183 /*
1184 * We *must* clear the S2CR first, because freeing the SMR means
1185 * that it can be re-allocated immediately.
1186 */
1187 arm_smmu_bypass_stream_mapping(smmu, master);
1188 arm_smmu_master_free_smrs(smmu, master);
1189 }
1190
1191 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1192 {
1193 int ret = -EINVAL;
1194 struct arm_smmu_domain *smmu_domain = domain->priv;
1195 struct arm_smmu_device *device_smmu = dev->archdata.iommu;
1196 struct arm_smmu_master *master;
1197 unsigned long flags;
1198
1199 if (!device_smmu) {
1200 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1201 return -ENXIO;
1202 }
1203
1204 /*
1205 * Sanity check the domain. We don't currently support domains
1206 * that cross between different SMMU chains.
1207 */
1208 spin_lock_irqsave(&smmu_domain->lock, flags);
1209 if (!smmu_domain->leaf_smmu) {
1210 /* Now that we have a master, we can finalise the domain */
1211 ret = arm_smmu_init_domain_context(domain, dev);
1212 if (IS_ERR_VALUE(ret))
1213 goto err_unlock;
1214
1215 smmu_domain->leaf_smmu = device_smmu;
1216 } else if (smmu_domain->leaf_smmu != device_smmu) {
1217 dev_err(dev,
1218 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1219 dev_name(smmu_domain->leaf_smmu->dev),
1220 dev_name(device_smmu->dev));
1221 goto err_unlock;
1222 }
1223 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1224
1225 /* Looks ok, so add the device to the domain */
1226 master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1227 if (!master)
1228 return -ENODEV;
1229
1230 return arm_smmu_domain_add_master(smmu_domain, master);
1231
1232 err_unlock:
1233 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1234 return ret;
1235 }
1236
1237 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1238 {
1239 struct arm_smmu_domain *smmu_domain = domain->priv;
1240 struct arm_smmu_master *master;
1241
1242 master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1243 if (master)
1244 arm_smmu_domain_remove_master(smmu_domain, master);
1245 }
1246
1247 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1248 unsigned long end)
1249 {
1250 return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1251 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1252 }
1253
1254 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1255 unsigned long addr, unsigned long end,
1256 unsigned long pfn, int prot, int stage)
1257 {
1258 pte_t *pte, *start;
1259 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1260
1261 if (pmd_none(*pmd)) {
1262 /* Allocate a new set of tables */
1263 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1264 if (!table)
1265 return -ENOMEM;
1266
1267 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1268 if (!pgtable_page_ctor(table)) {
1269 __free_page(table);
1270 return -ENOMEM;
1271 }
1272 pmd_populate(NULL, pmd, table);
1273 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1274 }
1275
1276 if (stage == 1) {
1277 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1278 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1279 pteval |= ARM_SMMU_PTE_AP_RDONLY;
1280
1281 if (prot & IOMMU_CACHE)
1282 pteval |= (MAIR_ATTR_IDX_CACHE <<
1283 ARM_SMMU_PTE_ATTRINDX_SHIFT);
1284 } else {
1285 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1286 if (prot & IOMMU_READ)
1287 pteval |= ARM_SMMU_PTE_HAP_READ;
1288 if (prot & IOMMU_WRITE)
1289 pteval |= ARM_SMMU_PTE_HAP_WRITE;
1290 if (prot & IOMMU_CACHE)
1291 pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1292 else
1293 pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1294 }
1295
1296 /* If no access, create a faulting entry to avoid TLB fills */
1297 if (prot & IOMMU_EXEC)
1298 pteval &= ~ARM_SMMU_PTE_XN;
1299 else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1300 pteval &= ~ARM_SMMU_PTE_PAGE;
1301
1302 pteval |= ARM_SMMU_PTE_SH_IS;
1303 start = pmd_page_vaddr(*pmd) + pte_index(addr);
1304 pte = start;
1305
1306 /*
1307 * Install the page table entries. This is fairly complicated
1308 * since we attempt to make use of the contiguous hint in the
1309 * ptes where possible. The contiguous hint indicates a series
1310 * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1311 * contiguous region with the following constraints:
1312 *
1313 * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1314 * - Each pte in the region has the contiguous hint bit set
1315 *
1316 * This complicates unmapping (also handled by this code, when
1317 * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1318 * possible, yet highly unlikely, that a client may unmap only
1319 * part of a contiguous range. This requires clearing of the
1320 * contiguous hint bits in the range before installing the new
1321 * faulting entries.
1322 *
1323 * Note that re-mapping an address range without first unmapping
1324 * it is not supported, so TLB invalidation is not required here
1325 * and is instead performed at unmap and domain-init time.
1326 */
1327 do {
1328 int i = 1;
1329 pteval &= ~ARM_SMMU_PTE_CONT;
1330
1331 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1332 i = ARM_SMMU_PTE_CONT_ENTRIES;
1333 pteval |= ARM_SMMU_PTE_CONT;
1334 } else if (pte_val(*pte) &
1335 (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1336 int j;
1337 pte_t *cont_start;
1338 unsigned long idx = pte_index(addr);
1339
1340 idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1341 cont_start = pmd_page_vaddr(*pmd) + idx;
1342 for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1343 pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT;
1344
1345 arm_smmu_flush_pgtable(smmu, cont_start,
1346 sizeof(*pte) *
1347 ARM_SMMU_PTE_CONT_ENTRIES);
1348 }
1349
1350 do {
1351 *pte = pfn_pte(pfn, __pgprot(pteval));
1352 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1353 } while (addr != end);
1354
1355 arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1356 return 0;
1357 }
1358
1359 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1360 unsigned long addr, unsigned long end,
1361 phys_addr_t phys, int prot, int stage)
1362 {
1363 int ret;
1364 pmd_t *pmd;
1365 unsigned long next, pfn = __phys_to_pfn(phys);
1366
1367 #ifndef __PAGETABLE_PMD_FOLDED
1368 if (pud_none(*pud)) {
1369 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1370 if (!pmd)
1371 return -ENOMEM;
1372
1373 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1374 pud_populate(NULL, pud, pmd);
1375 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1376
1377 pmd += pmd_index(addr);
1378 } else
1379 #endif
1380 pmd = pmd_offset(pud, addr);
1381
1382 do {
1383 next = pmd_addr_end(addr, end);
1384 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn,
1385 prot, stage);
1386 phys += next - addr;
1387 } while (pmd++, addr = next, addr < end);
1388
1389 return ret;
1390 }
1391
1392 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1393 unsigned long addr, unsigned long end,
1394 phys_addr_t phys, int prot, int stage)
1395 {
1396 int ret = 0;
1397 pud_t *pud;
1398 unsigned long next;
1399
1400 #ifndef __PAGETABLE_PUD_FOLDED
1401 if (pgd_none(*pgd)) {
1402 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1403 if (!pud)
1404 return -ENOMEM;
1405
1406 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1407 pgd_populate(NULL, pgd, pud);
1408 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1409
1410 pud += pud_index(addr);
1411 } else
1412 #endif
1413 pud = pud_offset(pgd, addr);
1414
1415 do {
1416 next = pud_addr_end(addr, end);
1417 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1418 prot, stage);
1419 phys += next - addr;
1420 } while (pud++, addr = next, addr < end);
1421
1422 return ret;
1423 }
1424
1425 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1426 unsigned long iova, phys_addr_t paddr,
1427 size_t size, int prot)
1428 {
1429 int ret, stage;
1430 unsigned long end;
1431 phys_addr_t input_mask, output_mask;
1432 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1433 pgd_t *pgd = root_cfg->pgd;
1434 struct arm_smmu_device *smmu = root_cfg->smmu;
1435 unsigned long flags;
1436
1437 if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
1438 stage = 2;
1439 output_mask = (1ULL << smmu->s2_output_size) - 1;
1440 } else {
1441 stage = 1;
1442 output_mask = (1ULL << smmu->s1_output_size) - 1;
1443 }
1444
1445 if (!pgd)
1446 return -EINVAL;
1447
1448 if (size & ~PAGE_MASK)
1449 return -EINVAL;
1450
1451 input_mask = (1ULL << smmu->input_size) - 1;
1452 if ((phys_addr_t)iova & ~input_mask)
1453 return -ERANGE;
1454
1455 if (paddr & ~output_mask)
1456 return -ERANGE;
1457
1458 spin_lock_irqsave(&smmu_domain->lock, flags);
1459 pgd += pgd_index(iova);
1460 end = iova + size;
1461 do {
1462 unsigned long next = pgd_addr_end(iova, end);
1463
1464 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1465 prot, stage);
1466 if (ret)
1467 goto out_unlock;
1468
1469 paddr += next - iova;
1470 iova = next;
1471 } while (pgd++, iova != end);
1472
1473 out_unlock:
1474 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1475
1476 return ret;
1477 }
1478
1479 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1480 phys_addr_t paddr, size_t size, int prot)
1481 {
1482 struct arm_smmu_domain *smmu_domain = domain->priv;
1483
1484 if (!smmu_domain)
1485 return -ENODEV;
1486
1487 /* Check for silent address truncation up the SMMU chain. */
1488 if ((phys_addr_t)iova & ~smmu_domain->output_mask)
1489 return -ERANGE;
1490
1491 return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1492 }
1493
1494 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1495 size_t size)
1496 {
1497 int ret;
1498 struct arm_smmu_domain *smmu_domain = domain->priv;
1499
1500 ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1501 arm_smmu_tlb_inv_context(&smmu_domain->root_cfg);
1502 return ret ? ret : size;
1503 }
1504
1505 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1506 dma_addr_t iova)
1507 {
1508 pgd_t *pgdp, pgd;
1509 pud_t pud;
1510 pmd_t pmd;
1511 pte_t pte;
1512 struct arm_smmu_domain *smmu_domain = domain->priv;
1513 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1514
1515 pgdp = root_cfg->pgd;
1516 if (!pgdp)
1517 return 0;
1518
1519 pgd = *(pgdp + pgd_index(iova));
1520 if (pgd_none(pgd))
1521 return 0;
1522
1523 pud = *pud_offset(&pgd, iova);
1524 if (pud_none(pud))
1525 return 0;
1526
1527 pmd = *pmd_offset(&pud, iova);
1528 if (pmd_none(pmd))
1529 return 0;
1530
1531 pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1532 if (pte_none(pte))
1533 return 0;
1534
1535 return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1536 }
1537
1538 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1539 unsigned long cap)
1540 {
1541 unsigned long caps = 0;
1542 struct arm_smmu_domain *smmu_domain = domain->priv;
1543
1544 if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1545 caps |= IOMMU_CAP_CACHE_COHERENCY;
1546
1547 return !!(cap & caps);
1548 }
1549
1550 static int arm_smmu_add_device(struct device *dev)
1551 {
1552 struct arm_smmu_device *child, *parent, *smmu;
1553 struct arm_smmu_master *master = NULL;
1554 struct iommu_group *group;
1555 int ret;
1556
1557 if (dev->archdata.iommu) {
1558 dev_warn(dev, "IOMMU driver already assigned to device\n");
1559 return -EINVAL;
1560 }
1561
1562 spin_lock(&arm_smmu_devices_lock);
1563 list_for_each_entry(parent, &arm_smmu_devices, list) {
1564 smmu = parent;
1565
1566 /* Try to find a child of the current SMMU. */
1567 list_for_each_entry(child, &arm_smmu_devices, list) {
1568 if (child->parent_of_node == parent->dev->of_node) {
1569 /* Does the child sit above our master? */
1570 master = find_smmu_master(child, dev->of_node);
1571 if (master) {
1572 smmu = NULL;
1573 break;
1574 }
1575 }
1576 }
1577
1578 /* We found some children, so keep searching. */
1579 if (!smmu) {
1580 master = NULL;
1581 continue;
1582 }
1583
1584 master = find_smmu_master(smmu, dev->of_node);
1585 if (master)
1586 break;
1587 }
1588 spin_unlock(&arm_smmu_devices_lock);
1589
1590 if (!master)
1591 return -ENODEV;
1592
1593 group = iommu_group_alloc();
1594 if (IS_ERR(group)) {
1595 dev_err(dev, "Failed to allocate IOMMU group\n");
1596 return PTR_ERR(group);
1597 }
1598
1599 ret = iommu_group_add_device(group, dev);
1600 iommu_group_put(group);
1601 dev->archdata.iommu = smmu;
1602
1603 return ret;
1604 }
1605
1606 static void arm_smmu_remove_device(struct device *dev)
1607 {
1608 dev->archdata.iommu = NULL;
1609 iommu_group_remove_device(dev);
1610 }
1611
1612 static struct iommu_ops arm_smmu_ops = {
1613 .domain_init = arm_smmu_domain_init,
1614 .domain_destroy = arm_smmu_domain_destroy,
1615 .attach_dev = arm_smmu_attach_dev,
1616 .detach_dev = arm_smmu_detach_dev,
1617 .map = arm_smmu_map,
1618 .unmap = arm_smmu_unmap,
1619 .iova_to_phys = arm_smmu_iova_to_phys,
1620 .domain_has_cap = arm_smmu_domain_has_cap,
1621 .add_device = arm_smmu_add_device,
1622 .remove_device = arm_smmu_remove_device,
1623 .pgsize_bitmap = (SECTION_SIZE |
1624 ARM_SMMU_PTE_CONT_SIZE |
1625 PAGE_SIZE),
1626 };
1627
1628 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1629 {
1630 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1631 void __iomem *cb_base;
1632 int i = 0;
1633 u32 reg;
1634
1635 /* clear global FSR */
1636 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1637 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1638
1639 /* Mark all SMRn as invalid and all S2CRn as bypass */
1640 for (i = 0; i < smmu->num_mapping_groups; ++i) {
1641 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1642 writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i));
1643 }
1644
1645 /* Make sure all context banks are disabled and clear CB_FSR */
1646 for (i = 0; i < smmu->num_context_banks; ++i) {
1647 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1648 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1649 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1650 }
1651
1652 /* Invalidate the TLB, just in case */
1653 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1654 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1655 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1656
1657 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1658
1659 /* Enable fault reporting */
1660 reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1661
1662 /* Disable TLB broadcasting. */
1663 reg |= (sCR0_VMIDPNE | sCR0_PTM);
1664
1665 /* Enable client access, but bypass when no mapping is found */
1666 reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1667
1668 /* Disable forced broadcasting */
1669 reg &= ~sCR0_FB;
1670
1671 /* Don't upgrade barriers */
1672 reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1673
1674 /* Push the button */
1675 arm_smmu_tlb_sync(smmu);
1676 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1677 }
1678
1679 static int arm_smmu_id_size_to_bits(int size)
1680 {
1681 switch (size) {
1682 case 0:
1683 return 32;
1684 case 1:
1685 return 36;
1686 case 2:
1687 return 40;
1688 case 3:
1689 return 42;
1690 case 4:
1691 return 44;
1692 case 5:
1693 default:
1694 return 48;
1695 }
1696 }
1697
1698 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1699 {
1700 unsigned long size;
1701 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1702 u32 id;
1703
1704 dev_notice(smmu->dev, "probing hardware configuration...\n");
1705
1706 /* Primecell ID */
1707 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1708 smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1709 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1710
1711 /* ID0 */
1712 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1713 #ifndef CONFIG_64BIT
1714 if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1715 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1716 return -ENODEV;
1717 }
1718 #endif
1719 if (id & ID0_S1TS) {
1720 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1721 dev_notice(smmu->dev, "\tstage 1 translation\n");
1722 }
1723
1724 if (id & ID0_S2TS) {
1725 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1726 dev_notice(smmu->dev, "\tstage 2 translation\n");
1727 }
1728
1729 if (id & ID0_NTS) {
1730 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1731 dev_notice(smmu->dev, "\tnested translation\n");
1732 }
1733
1734 if (!(smmu->features &
1735 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1736 ARM_SMMU_FEAT_TRANS_NESTED))) {
1737 dev_err(smmu->dev, "\tno translation support!\n");
1738 return -ENODEV;
1739 }
1740
1741 if (id & ID0_CTTW) {
1742 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1743 dev_notice(smmu->dev, "\tcoherent table walk\n");
1744 }
1745
1746 if (id & ID0_SMS) {
1747 u32 smr, sid, mask;
1748
1749 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1750 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1751 ID0_NUMSMRG_MASK;
1752 if (smmu->num_mapping_groups == 0) {
1753 dev_err(smmu->dev,
1754 "stream-matching supported, but no SMRs present!\n");
1755 return -ENODEV;
1756 }
1757
1758 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1759 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1760 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1761 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1762
1763 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1764 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1765 if ((mask & sid) != sid) {
1766 dev_err(smmu->dev,
1767 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1768 mask, sid);
1769 return -ENODEV;
1770 }
1771
1772 dev_notice(smmu->dev,
1773 "\tstream matching with %u register groups, mask 0x%x",
1774 smmu->num_mapping_groups, mask);
1775 }
1776
1777 /* ID1 */
1778 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1779 smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1780
1781 /* Check for size mismatch of SMMU address space from mapped region */
1782 size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1783 size *= (smmu->pagesize << 1);
1784 if (smmu->size != size)
1785 dev_warn(smmu->dev, "SMMU address space size (0x%lx) differs "
1786 "from mapped region size (0x%lx)!\n", size, smmu->size);
1787
1788 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1789 ID1_NUMS2CB_MASK;
1790 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1791 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1792 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1793 return -ENODEV;
1794 }
1795 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1796 smmu->num_context_banks, smmu->num_s2_context_banks);
1797
1798 /* ID2 */
1799 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1800 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1801
1802 /*
1803 * Stage-1 output limited by stage-2 input size due to pgd
1804 * allocation (PTRS_PER_PGD).
1805 */
1806 #ifdef CONFIG_64BIT
1807 smmu->s1_output_size = min(39UL, size);
1808 #else
1809 smmu->s1_output_size = min(32UL, size);
1810 #endif
1811
1812 /* The stage-2 output mask is also applied for bypass */
1813 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1814 smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size);
1815
1816 if (smmu->version == 1) {
1817 smmu->input_size = 32;
1818 } else {
1819 #ifdef CONFIG_64BIT
1820 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1821 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1822 #else
1823 size = 32;
1824 #endif
1825 smmu->input_size = size;
1826
1827 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1828 (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1829 (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1830 dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1831 PAGE_SIZE);
1832 return -ENODEV;
1833 }
1834 }
1835
1836 dev_notice(smmu->dev,
1837 "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1838 smmu->input_size, smmu->s1_output_size, smmu->s2_output_size);
1839 return 0;
1840 }
1841
1842 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1843 {
1844 struct resource *res;
1845 struct arm_smmu_device *smmu;
1846 struct device_node *dev_node;
1847 struct device *dev = &pdev->dev;
1848 struct rb_node *node;
1849 struct of_phandle_args masterspec;
1850 int num_irqs, i, err;
1851
1852 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1853 if (!smmu) {
1854 dev_err(dev, "failed to allocate arm_smmu_device\n");
1855 return -ENOMEM;
1856 }
1857 smmu->dev = dev;
1858
1859 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1860 smmu->base = devm_ioremap_resource(dev, res);
1861 if (IS_ERR(smmu->base))
1862 return PTR_ERR(smmu->base);
1863 smmu->size = resource_size(res);
1864
1865 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1866 &smmu->num_global_irqs)) {
1867 dev_err(dev, "missing #global-interrupts property\n");
1868 return -ENODEV;
1869 }
1870
1871 num_irqs = 0;
1872 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1873 num_irqs++;
1874 if (num_irqs > smmu->num_global_irqs)
1875 smmu->num_context_irqs++;
1876 }
1877
1878 if (!smmu->num_context_irqs) {
1879 dev_err(dev, "found %d interrupts but expected at least %d\n",
1880 num_irqs, smmu->num_global_irqs + 1);
1881 return -ENODEV;
1882 }
1883
1884 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1885 GFP_KERNEL);
1886 if (!smmu->irqs) {
1887 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1888 return -ENOMEM;
1889 }
1890
1891 for (i = 0; i < num_irqs; ++i) {
1892 int irq = platform_get_irq(pdev, i);
1893 if (irq < 0) {
1894 dev_err(dev, "failed to get irq index %d\n", i);
1895 return -ENODEV;
1896 }
1897 smmu->irqs[i] = irq;
1898 }
1899
1900 i = 0;
1901 smmu->masters = RB_ROOT;
1902 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1903 "#stream-id-cells", i,
1904 &masterspec)) {
1905 err = register_smmu_master(smmu, dev, &masterspec);
1906 if (err) {
1907 dev_err(dev, "failed to add master %s\n",
1908 masterspec.np->name);
1909 goto out_put_masters;
1910 }
1911
1912 i++;
1913 }
1914 dev_notice(dev, "registered %d master devices\n", i);
1915
1916 if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0)))
1917 smmu->parent_of_node = dev_node;
1918
1919 err = arm_smmu_device_cfg_probe(smmu);
1920 if (err)
1921 goto out_put_parent;
1922
1923 parse_driver_options(smmu);
1924
1925 if (smmu->version > 1 &&
1926 smmu->num_context_banks != smmu->num_context_irqs) {
1927 dev_err(dev,
1928 "found only %d context interrupt(s) but %d required\n",
1929 smmu->num_context_irqs, smmu->num_context_banks);
1930 err = -ENODEV;
1931 goto out_put_parent;
1932 }
1933
1934 for (i = 0; i < smmu->num_global_irqs; ++i) {
1935 err = request_irq(smmu->irqs[i],
1936 arm_smmu_global_fault,
1937 IRQF_SHARED,
1938 "arm-smmu global fault",
1939 smmu);
1940 if (err) {
1941 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1942 i, smmu->irqs[i]);
1943 goto out_free_irqs;
1944 }
1945 }
1946
1947 INIT_LIST_HEAD(&smmu->list);
1948 spin_lock(&arm_smmu_devices_lock);
1949 list_add(&smmu->list, &arm_smmu_devices);
1950 spin_unlock(&arm_smmu_devices_lock);
1951
1952 arm_smmu_device_reset(smmu);
1953 return 0;
1954
1955 out_free_irqs:
1956 while (i--)
1957 free_irq(smmu->irqs[i], smmu);
1958
1959 out_put_parent:
1960 if (smmu->parent_of_node)
1961 of_node_put(smmu->parent_of_node);
1962
1963 out_put_masters:
1964 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1965 struct arm_smmu_master *master;
1966 master = container_of(node, struct arm_smmu_master, node);
1967 of_node_put(master->of_node);
1968 }
1969
1970 return err;
1971 }
1972
1973 static int arm_smmu_device_remove(struct platform_device *pdev)
1974 {
1975 int i;
1976 struct device *dev = &pdev->dev;
1977 struct arm_smmu_device *curr, *smmu = NULL;
1978 struct rb_node *node;
1979
1980 spin_lock(&arm_smmu_devices_lock);
1981 list_for_each_entry(curr, &arm_smmu_devices, list) {
1982 if (curr->dev == dev) {
1983 smmu = curr;
1984 list_del(&smmu->list);
1985 break;
1986 }
1987 }
1988 spin_unlock(&arm_smmu_devices_lock);
1989
1990 if (!smmu)
1991 return -ENODEV;
1992
1993 if (smmu->parent_of_node)
1994 of_node_put(smmu->parent_of_node);
1995
1996 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1997 struct arm_smmu_master *master;
1998 master = container_of(node, struct arm_smmu_master, node);
1999 of_node_put(master->of_node);
2000 }
2001
2002 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
2003 dev_err(dev, "removing device with active domains!\n");
2004
2005 for (i = 0; i < smmu->num_global_irqs; ++i)
2006 free_irq(smmu->irqs[i], smmu);
2007
2008 /* Turn the thing off */
2009 writel(sCR0_CLIENTPD,ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
2010 return 0;
2011 }
2012
2013 #ifdef CONFIG_OF
2014 static struct of_device_id arm_smmu_of_match[] = {
2015 { .compatible = "arm,smmu-v1", },
2016 { .compatible = "arm,smmu-v2", },
2017 { .compatible = "arm,mmu-400", },
2018 { .compatible = "arm,mmu-500", },
2019 { },
2020 };
2021 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2022 #endif
2023
2024 static struct platform_driver arm_smmu_driver = {
2025 .driver = {
2026 .owner = THIS_MODULE,
2027 .name = "arm-smmu",
2028 .of_match_table = of_match_ptr(arm_smmu_of_match),
2029 },
2030 .probe = arm_smmu_device_dt_probe,
2031 .remove = arm_smmu_device_remove,
2032 };
2033
2034 static int __init arm_smmu_init(void)
2035 {
2036 int ret;
2037
2038 ret = platform_driver_register(&arm_smmu_driver);
2039 if (ret)
2040 return ret;
2041
2042 /* Oh, for a proper bus abstraction */
2043 if (!iommu_present(&platform_bus_type))
2044 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2045
2046 #ifdef CONFIG_ARM_AMBA
2047 if (!iommu_present(&amba_bustype))
2048 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2049 #endif
2050
2051 return 0;
2052 }
2053
2054 static void __exit arm_smmu_exit(void)
2055 {
2056 return platform_driver_unregister(&arm_smmu_driver);
2057 }
2058
2059 subsys_initcall(arm_smmu_init);
2060 module_exit(arm_smmu_exit);
2061
2062 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2063 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2064 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support