drivers/ata/ahci_qoriq.c

   1 /*
   2  * Freescale QorIQ AHCI SATA platform driver
   3  *
   4  * Copyright 2015 Freescale, Inc.
   5  *   Tang Yuantian <Yuantian.Tang@freescale.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/pm.h>
  16 #include <linux/ahci_platform.h>
  17 #include <linux/device.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/libata.h>
  23 #include "ahci.h"
  24
  25 #define DRV_NAME "ahci-qoriq"
  26
  27 /* port register definition */
  28 #define PORT_PHY1       0xA8
  29 #define PORT_PHY2       0xAC
  30 #define PORT_PHY3       0xB0
  31 #define PORT_PHY4       0xB4
  32 #define PORT_PHY5       0xB8
  33 #define PORT_TRANS      0xC8
  34
  35 /* port register default value */
  36 #define AHCI_PORT_PHY_1_CFG     0xa003fffe
  37 #define AHCI_PORT_TRANS_CFG     0x08000029
  38
  39 /* for ls1021a */
  40 #define LS1021A_PORT_PHY2       0x28183414
  41 #define LS1021A_PORT_PHY3       0x0e080e06
  42 #define LS1021A_PORT_PHY4       0x064a080b
  43 #define LS1021A_PORT_PHY5       0x2aa86470
  44
  45 #define SATA_ECC_DISABLE        0x00020000
  46
  47 /* for ls1043a */
  48 #define LS1043A_PORT_PHY2       0x28184d1f
  49 #define LS1043A_PORT_PHY3       0x0e081509
  50
  51 enum ahci_qoriq_type {
  52         AHCI_LS1021A,
  53         AHCI_LS1043A,
  54         AHCI_LS2080A,
  55 };
  56
  57 struct ahci_qoriq_priv {
  58         struct ccsr_ahci *reg_base;
  59         enum ahci_qoriq_type type;
  60         void __iomem *ecc_addr;
  61 };
  62
  63 static const struct of_device_id ahci_qoriq_of_match[] = {
  64         { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
  65         { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
  66         { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
  67         {},
  68 };
  69 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
  70
  71 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
  72                           unsigned long deadline)
  73 {
  74         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  75         void __iomem *port_mmio = ahci_port_base(link->ap);
  76         u32 px_cmd, px_is, px_val;
  77         struct ata_port *ap = link->ap;
  78         struct ahci_port_priv *pp = ap->private_data;
  79         struct ahci_host_priv *hpriv = ap->host->private_data;
  80         struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
  81         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  82         struct ata_taskfile tf;
  83         bool online;
  84         int rc;
  85         bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
  86
  87         DPRINTK("ENTER\n");
  88
  89         ahci_stop_engine(ap);
  90
  91         /*
  92          * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
  93          * A-009042: The device detection initialization sequence
  94          * mistakenly resets some registers.
  95          *
  96          * Workaround for this is:
  97          * The software should read and store PxCMD and PxIS values
  98          * before issuing the device detection initialization sequence.
  99          * After the sequence is complete, software should restore the
 100          * PxCMD and PxIS with the stored values.
 101          */
 102         if (ls1021a_workaround) {
 103                 px_cmd = readl(port_mmio + PORT_CMD);
 104                 px_is = readl(port_mmio + PORT_IRQ_STAT);
 105         }
 106
 107         /* clear D2H reception area to properly wait for D2H FIS */
 108         ata_tf_init(link->device, &tf);
 109         tf.command = ATA_BUSY;
 110         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 111
 112         rc = sata_link_hardreset(link, timing, deadline, &online,
 113                                  ahci_check_ready);
 114
 115         /* restore the PxCMD and PxIS on ls1021 */
 116         if (ls1021a_workaround) {
 117                 px_val = readl(port_mmio + PORT_CMD);
 118                 if (px_val != px_cmd)
 119                         writel(px_cmd, port_mmio + PORT_CMD);
 120
 121                 px_val = readl(port_mmio + PORT_IRQ_STAT);
 122                 if (px_val != px_is)
 123                         writel(px_is, port_mmio + PORT_IRQ_STAT);
 124         }
 125
 126         hpriv->start_engine(ap);
 127
 128         if (online)
 129                 *class = ahci_dev_classify(ap);
 130
 131         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 132         return rc;
 133 }
 134
 135 static struct ata_port_operations ahci_qoriq_ops = {
 136         .inherits       = &ahci_ops,
 137         .hardreset      = ahci_qoriq_hardreset,
 138 };
 139
 140 static struct ata_port_info ahci_qoriq_port_info = {
 141         .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
 142         .pio_mask       = ATA_PIO4,
 143         .udma_mask      = ATA_UDMA6,
 144         .port_ops       = &ahci_qoriq_ops,
 145 };
 146
 147 static struct scsi_host_template ahci_qoriq_sht = {
 148         AHCI_SHT(DRV_NAME),
 149 };
 150
 151 static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
 152 {
 153         struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
 154         void __iomem *reg_base = hpriv->mmio;
 155
 156         switch (qpriv->type) {
 157         case AHCI_LS1021A:
 158                 writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
 159                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 160                 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
 161                 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
 162                 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
 163                 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
 164                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 165                 break;
 166
 167         case AHCI_LS1043A:
 168                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 169                 writel(LS1043A_PORT_PHY2, reg_base + PORT_PHY2);
 170                 writel(LS1043A_PORT_PHY3, reg_base + PORT_PHY3);
 171                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 172                 break;
 173
 174         case AHCI_LS2080A:
 175                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 176                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 177                 break;
 178         }
 179
 180         return 0;
 181 }
 182
 183 static int ahci_qoriq_probe(struct platform_device *pdev)
 184 {
 185         struct device_node *np = pdev->dev.of_node;
 186         struct device *dev = &pdev->dev;
 187         struct ahci_host_priv *hpriv;
 188         struct ahci_qoriq_priv *qoriq_priv;
 189         const struct of_device_id *of_id;
 190         struct resource *res;
 191         int rc;
 192
 193         hpriv = ahci_platform_get_resources(pdev);
 194         if (IS_ERR(hpriv))
 195                 return PTR_ERR(hpriv);
 196
 197         of_id = of_match_node(ahci_qoriq_of_match, np);
 198         if (!of_id)
 199                 return -ENODEV;
 200
 201         qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
 202         if (!qoriq_priv)
 203                 return -ENOMEM;
 204
 205         qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
 206
 207         if (qoriq_priv->type == AHCI_LS1021A) {
 208                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 209                                 "sata-ecc");
 210                 qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
 211                 if (IS_ERR(qoriq_priv->ecc_addr))
 212                         return PTR_ERR(qoriq_priv->ecc_addr);
 213         }
 214
 215         rc = ahci_platform_enable_resources(hpriv);
 216         if (rc)
 217                 return rc;
 218
 219         hpriv->plat_data = qoriq_priv;
 220         rc = ahci_qoriq_phy_init(hpriv);
 221         if (rc)
 222                 goto disable_resources;
 223
 224         /* Workaround for ls2080a */
 225         if (qoriq_priv->type == AHCI_LS2080A) {
 226                 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
 227                 ahci_qoriq_port_info.flags &= ~ATA_FLAG_NCQ;
 228         }
 229
 230         rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
 231                                      &ahci_qoriq_sht);
 232         if (rc)
 233                 goto disable_resources;
 234
 235         return 0;
 236
 237 disable_resources:
 238         ahci_platform_disable_resources(hpriv);
 239
 240         return rc;
 241 }
 242
 243 #ifdef CONFIG_PM_SLEEP
 244 static int ahci_qoriq_resume(struct device *dev)
 245 {
 246         struct ata_host *host = dev_get_drvdata(dev);
 247         struct ahci_host_priv *hpriv = host->private_data;
 248         int rc;
 249
 250         rc = ahci_platform_enable_resources(hpriv);
 251         if (rc)
 252                 return rc;
 253
 254         rc = ahci_qoriq_phy_init(hpriv);
 255         if (rc)
 256                 goto disable_resources;
 257
 258         rc = ahci_platform_resume_host(dev);
 259         if (rc)
 260                 goto disable_resources;
 261
 262         /* We resumed so update PM runtime state */
 263         pm_runtime_disable(dev);
 264         pm_runtime_set_active(dev);
 265         pm_runtime_enable(dev);
 266
 267         return 0;
 268
 269 disable_resources:
 270         ahci_platform_disable_resources(hpriv);
 271
 272         return rc;
 273 }
 274 #endif
 275
 276 static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
 277                          ahci_qoriq_resume);
 278
 279 static struct platform_driver ahci_qoriq_driver = {
 280         .probe = ahci_qoriq_probe,
 281         .remove = ata_platform_remove_one,
 282         .driver = {
 283                 .name = DRV_NAME,
 284                 .of_match_table = ahci_qoriq_of_match,
 285                 .pm = &ahci_qoriq_pm_ops,
 286         },
 287 };
 288 module_platform_driver(ahci_qoriq_driver);
 289
 290 MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
 291 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
 292 MODULE_LICENSE("GPL");