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mmc: rtsx_pci: Enable MMC_CAP_ERASE to allow erase/discard/trim requests
[linux/fpc-iii.git] / drivers / iio / accel / st_accel_core.c
blob4d95bfc4786cafc6de2fcc659950860596193877
1 /*
2 * STMicroelectronics accelerometers driver
3 *
4 * Copyright 2012-2013 STMicroelectronics Inc.
5 *
6 * Denis Ciocca <denis.ciocca@st.com>
7 *
8 * Licensed under the GPL-2.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/errno.h>
15 #include <linux/types.h>
16 #include <linux/mutex.h>
17 #include <linux/interrupt.h>
18 #include <linux/i2c.h>
19 #include <linux/gpio.h>
20 #include <linux/irq.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/buffer.h>
25
26 #include <linux/iio/common/st_sensors.h>
27 #include "st_accel.h"
28
29 #define ST_ACCEL_NUMBER_DATA_CHANNELS 3
30
31 /* DEFAULT VALUE FOR SENSORS */
32 #define ST_ACCEL_DEFAULT_OUT_X_L_ADDR 0x28
33 #define ST_ACCEL_DEFAULT_OUT_Y_L_ADDR 0x2a
34 #define ST_ACCEL_DEFAULT_OUT_Z_L_ADDR 0x2c
35
36 /* FULLSCALE */
37 #define ST_ACCEL_FS_AVL_2G 2
38 #define ST_ACCEL_FS_AVL_4G 4
39 #define ST_ACCEL_FS_AVL_6G 6
40 #define ST_ACCEL_FS_AVL_8G 8
41 #define ST_ACCEL_FS_AVL_16G 16
42 #define ST_ACCEL_FS_AVL_100G 100
43 #define ST_ACCEL_FS_AVL_200G 200
44 #define ST_ACCEL_FS_AVL_400G 400
45
46 /* CUSTOM VALUES FOR SENSOR 1 */
47 #define ST_ACCEL_1_WAI_EXP 0x33
48 #define ST_ACCEL_1_ODR_ADDR 0x20
49 #define ST_ACCEL_1_ODR_MASK 0xf0
50 #define ST_ACCEL_1_ODR_AVL_1HZ_VAL 0x01
51 #define ST_ACCEL_1_ODR_AVL_10HZ_VAL 0x02
52 #define ST_ACCEL_1_ODR_AVL_25HZ_VAL 0x03
53 #define ST_ACCEL_1_ODR_AVL_50HZ_VAL 0x04
54 #define ST_ACCEL_1_ODR_AVL_100HZ_VAL 0x05
55 #define ST_ACCEL_1_ODR_AVL_200HZ_VAL 0x06
56 #define ST_ACCEL_1_ODR_AVL_400HZ_VAL 0x07
57 #define ST_ACCEL_1_ODR_AVL_1600HZ_VAL 0x08
58 #define ST_ACCEL_1_FS_ADDR 0x23
59 #define ST_ACCEL_1_FS_MASK 0x30
60 #define ST_ACCEL_1_FS_AVL_2_VAL 0x00
61 #define ST_ACCEL_1_FS_AVL_4_VAL 0x01
62 #define ST_ACCEL_1_FS_AVL_8_VAL 0x02
63 #define ST_ACCEL_1_FS_AVL_16_VAL 0x03
64 #define ST_ACCEL_1_FS_AVL_2_GAIN IIO_G_TO_M_S_2(1000)
65 #define ST_ACCEL_1_FS_AVL_4_GAIN IIO_G_TO_M_S_2(2000)
66 #define ST_ACCEL_1_FS_AVL_8_GAIN IIO_G_TO_M_S_2(4000)
67 #define ST_ACCEL_1_FS_AVL_16_GAIN IIO_G_TO_M_S_2(12000)
68 #define ST_ACCEL_1_BDU_ADDR 0x23
69 #define ST_ACCEL_1_BDU_MASK 0x80
70 #define ST_ACCEL_1_DRDY_IRQ_ADDR 0x22
71 #define ST_ACCEL_1_DRDY_IRQ_INT1_MASK 0x10
72 #define ST_ACCEL_1_DRDY_IRQ_INT2_MASK 0x08
73 #define ST_ACCEL_1_IHL_IRQ_ADDR 0x25
74 #define ST_ACCEL_1_IHL_IRQ_MASK 0x02
75 #define ST_ACCEL_1_MULTIREAD_BIT true
76
77 /* CUSTOM VALUES FOR SENSOR 2 */
78 #define ST_ACCEL_2_WAI_EXP 0x32
79 #define ST_ACCEL_2_ODR_ADDR 0x20
80 #define ST_ACCEL_2_ODR_MASK 0x18
81 #define ST_ACCEL_2_ODR_AVL_50HZ_VAL 0x00
82 #define ST_ACCEL_2_ODR_AVL_100HZ_VAL 0x01
83 #define ST_ACCEL_2_ODR_AVL_400HZ_VAL 0x02
84 #define ST_ACCEL_2_ODR_AVL_1000HZ_VAL 0x03
85 #define ST_ACCEL_2_PW_ADDR 0x20
86 #define ST_ACCEL_2_PW_MASK 0xe0
87 #define ST_ACCEL_2_FS_ADDR 0x23
88 #define ST_ACCEL_2_FS_MASK 0x30
89 #define ST_ACCEL_2_FS_AVL_2_VAL 0X00
90 #define ST_ACCEL_2_FS_AVL_4_VAL 0X01
91 #define ST_ACCEL_2_FS_AVL_8_VAL 0x03
92 #define ST_ACCEL_2_FS_AVL_2_GAIN IIO_G_TO_M_S_2(1000)
93 #define ST_ACCEL_2_FS_AVL_4_GAIN IIO_G_TO_M_S_2(2000)
94 #define ST_ACCEL_2_FS_AVL_8_GAIN IIO_G_TO_M_S_2(3900)
95 #define ST_ACCEL_2_BDU_ADDR 0x23
96 #define ST_ACCEL_2_BDU_MASK 0x80
97 #define ST_ACCEL_2_DRDY_IRQ_ADDR 0x22
98 #define ST_ACCEL_2_DRDY_IRQ_INT1_MASK 0x02
99 #define ST_ACCEL_2_DRDY_IRQ_INT2_MASK 0x10
100 #define ST_ACCEL_2_IHL_IRQ_ADDR 0x22
101 #define ST_ACCEL_2_IHL_IRQ_MASK 0x80
102 #define ST_ACCEL_2_OD_IRQ_ADDR 0x22
103 #define ST_ACCEL_2_OD_IRQ_MASK 0x40
104 #define ST_ACCEL_2_MULTIREAD_BIT true
105
106 /* CUSTOM VALUES FOR SENSOR 3 */
107 #define ST_ACCEL_3_WAI_EXP 0x40
108 #define ST_ACCEL_3_ODR_ADDR 0x20
109 #define ST_ACCEL_3_ODR_MASK 0xf0
110 #define ST_ACCEL_3_ODR_AVL_3HZ_VAL 0x01
111 #define ST_ACCEL_3_ODR_AVL_6HZ_VAL 0x02
112 #define ST_ACCEL_3_ODR_AVL_12HZ_VAL 0x03
113 #define ST_ACCEL_3_ODR_AVL_25HZ_VAL 0x04
114 #define ST_ACCEL_3_ODR_AVL_50HZ_VAL 0x05
115 #define ST_ACCEL_3_ODR_AVL_100HZ_VAL 0x06
116 #define ST_ACCEL_3_ODR_AVL_200HZ_VAL 0x07
117 #define ST_ACCEL_3_ODR_AVL_400HZ_VAL 0x08
118 #define ST_ACCEL_3_ODR_AVL_800HZ_VAL 0x09
119 #define ST_ACCEL_3_ODR_AVL_1600HZ_VAL 0x0a
120 #define ST_ACCEL_3_FS_ADDR 0x24
121 #define ST_ACCEL_3_FS_MASK 0x38
122 #define ST_ACCEL_3_FS_AVL_2_VAL 0X00
123 #define ST_ACCEL_3_FS_AVL_4_VAL 0X01
124 #define ST_ACCEL_3_FS_AVL_6_VAL 0x02
125 #define ST_ACCEL_3_FS_AVL_8_VAL 0x03
126 #define ST_ACCEL_3_FS_AVL_16_VAL 0x04
127 #define ST_ACCEL_3_FS_AVL_2_GAIN IIO_G_TO_M_S_2(61)
128 #define ST_ACCEL_3_FS_AVL_4_GAIN IIO_G_TO_M_S_2(122)
129 #define ST_ACCEL_3_FS_AVL_6_GAIN IIO_G_TO_M_S_2(183)
130 #define ST_ACCEL_3_FS_AVL_8_GAIN IIO_G_TO_M_S_2(244)
131 #define ST_ACCEL_3_FS_AVL_16_GAIN IIO_G_TO_M_S_2(732)
132 #define ST_ACCEL_3_BDU_ADDR 0x20
133 #define ST_ACCEL_3_BDU_MASK 0x08
134 #define ST_ACCEL_3_DRDY_IRQ_ADDR 0x23
135 #define ST_ACCEL_3_DRDY_IRQ_INT1_MASK 0x80
136 #define ST_ACCEL_3_DRDY_IRQ_INT2_MASK 0x00
137 #define ST_ACCEL_3_IHL_IRQ_ADDR 0x23
138 #define ST_ACCEL_3_IHL_IRQ_MASK 0x40
139 #define ST_ACCEL_3_IG1_EN_ADDR 0x23
140 #define ST_ACCEL_3_IG1_EN_MASK 0x08
141 #define ST_ACCEL_3_MULTIREAD_BIT false
142
143 /* CUSTOM VALUES FOR SENSOR 4 */
144 #define ST_ACCEL_4_WAI_EXP 0x3a
145 #define ST_ACCEL_4_ODR_ADDR 0x20
146 #define ST_ACCEL_4_ODR_MASK 0x30 /* DF1 and DF0 */
147 #define ST_ACCEL_4_ODR_AVL_40HZ_VAL 0x00
148 #define ST_ACCEL_4_ODR_AVL_160HZ_VAL 0x01
149 #define ST_ACCEL_4_ODR_AVL_640HZ_VAL 0x02
150 #define ST_ACCEL_4_ODR_AVL_2560HZ_VAL 0x03
151 #define ST_ACCEL_4_PW_ADDR 0x20
152 #define ST_ACCEL_4_PW_MASK 0xc0
153 #define ST_ACCEL_4_FS_ADDR 0x21
154 #define ST_ACCEL_4_FS_MASK 0x80
155 #define ST_ACCEL_4_FS_AVL_2_VAL 0X00
156 #define ST_ACCEL_4_FS_AVL_6_VAL 0X01
157 #define ST_ACCEL_4_FS_AVL_2_GAIN IIO_G_TO_M_S_2(1024)
158 #define ST_ACCEL_4_FS_AVL_6_GAIN IIO_G_TO_M_S_2(340)
159 #define ST_ACCEL_4_BDU_ADDR 0x21
160 #define ST_ACCEL_4_BDU_MASK 0x40
161 #define ST_ACCEL_4_DRDY_IRQ_ADDR 0x21
162 #define ST_ACCEL_4_DRDY_IRQ_INT1_MASK 0x04
163 #define ST_ACCEL_4_MULTIREAD_BIT true
164
165 /* CUSTOM VALUES FOR SENSOR 5 */
166 #define ST_ACCEL_5_WAI_EXP 0x3b
167 #define ST_ACCEL_5_ODR_ADDR 0x20
168 #define ST_ACCEL_5_ODR_MASK 0x80
169 #define ST_ACCEL_5_ODR_AVL_100HZ_VAL 0x00
170 #define ST_ACCEL_5_ODR_AVL_400HZ_VAL 0x01
171 #define ST_ACCEL_5_PW_ADDR 0x20
172 #define ST_ACCEL_5_PW_MASK 0x40
173 #define ST_ACCEL_5_FS_ADDR 0x20
174 #define ST_ACCEL_5_FS_MASK 0x20
175 #define ST_ACCEL_5_FS_AVL_2_VAL 0X00
176 #define ST_ACCEL_5_FS_AVL_8_VAL 0X01
177 /* TODO: check these resulting gain settings, these are not in the datsheet */
178 #define ST_ACCEL_5_FS_AVL_2_GAIN IIO_G_TO_M_S_2(18000)
179 #define ST_ACCEL_5_FS_AVL_8_GAIN IIO_G_TO_M_S_2(72000)
180 #define ST_ACCEL_5_DRDY_IRQ_ADDR 0x22
181 #define ST_ACCEL_5_DRDY_IRQ_INT1_MASK 0x04
182 #define ST_ACCEL_5_DRDY_IRQ_INT2_MASK 0x20
183 #define ST_ACCEL_5_IHL_IRQ_ADDR 0x22
184 #define ST_ACCEL_5_IHL_IRQ_MASK 0x80
185 #define ST_ACCEL_5_OD_IRQ_ADDR 0x22
186 #define ST_ACCEL_5_OD_IRQ_MASK 0x40
187 #define ST_ACCEL_5_IG1_EN_ADDR 0x21
188 #define ST_ACCEL_5_IG1_EN_MASK 0x08
189 #define ST_ACCEL_5_MULTIREAD_BIT false
190
191 /* CUSTOM VALUES FOR SENSOR 6 */
192 #define ST_ACCEL_6_WAI_EXP 0x32
193 #define ST_ACCEL_6_ODR_ADDR 0x20
194 #define ST_ACCEL_6_ODR_MASK 0x18
195 #define ST_ACCEL_6_ODR_AVL_50HZ_VAL 0x00
196 #define ST_ACCEL_6_ODR_AVL_100HZ_VAL 0x01
197 #define ST_ACCEL_6_ODR_AVL_400HZ_VAL 0x02
198 #define ST_ACCEL_6_ODR_AVL_1000HZ_VAL 0x03
199 #define ST_ACCEL_6_PW_ADDR 0x20
200 #define ST_ACCEL_6_PW_MASK 0x20
201 #define ST_ACCEL_6_FS_ADDR 0x23
202 #define ST_ACCEL_6_FS_MASK 0x30
203 #define ST_ACCEL_6_FS_AVL_100_VAL 0x00
204 #define ST_ACCEL_6_FS_AVL_200_VAL 0x01
205 #define ST_ACCEL_6_FS_AVL_400_VAL 0x03
206 #define ST_ACCEL_6_FS_AVL_100_GAIN IIO_G_TO_M_S_2(49000)
207 #define ST_ACCEL_6_FS_AVL_200_GAIN IIO_G_TO_M_S_2(98000)
208 #define ST_ACCEL_6_FS_AVL_400_GAIN IIO_G_TO_M_S_2(195000)
209 #define ST_ACCEL_6_BDU_ADDR 0x23
210 #define ST_ACCEL_6_BDU_MASK 0x80
211 #define ST_ACCEL_6_DRDY_IRQ_ADDR 0x22
212 #define ST_ACCEL_6_DRDY_IRQ_INT1_MASK 0x02
213 #define ST_ACCEL_6_DRDY_IRQ_INT2_MASK 0x10
214 #define ST_ACCEL_6_IHL_IRQ_ADDR 0x22
215 #define ST_ACCEL_6_IHL_IRQ_MASK 0x80
216 #define ST_ACCEL_6_MULTIREAD_BIT true
217
218 static const struct iio_chan_spec st_accel_8bit_channels[] = {
219 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
220 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
221 ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_LE, 8, 8,
222 ST_ACCEL_DEFAULT_OUT_X_L_ADDR+1),
223 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
224 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
225 ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_LE, 8, 8,
226 ST_ACCEL_DEFAULT_OUT_Y_L_ADDR+1),
227 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
228 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
229 ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_LE, 8, 8,
230 ST_ACCEL_DEFAULT_OUT_Z_L_ADDR+1),
231 IIO_CHAN_SOFT_TIMESTAMP(3)
232 };
233
234 static const struct iio_chan_spec st_accel_12bit_channels[] = {
235 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
236 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
237 ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_LE, 12, 16,
238 ST_ACCEL_DEFAULT_OUT_X_L_ADDR),
239 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
240 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
241 ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_LE, 12, 16,
242 ST_ACCEL_DEFAULT_OUT_Y_L_ADDR),
243 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
244 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
245 ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_LE, 12, 16,
246 ST_ACCEL_DEFAULT_OUT_Z_L_ADDR),
247 IIO_CHAN_SOFT_TIMESTAMP(3)
248 };
249
250 static const struct iio_chan_spec st_accel_16bit_channels[] = {
251 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
252 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
253 ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_LE, 16, 16,
254 ST_ACCEL_DEFAULT_OUT_X_L_ADDR),
255 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
256 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
257 ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_LE, 16, 16,
258 ST_ACCEL_DEFAULT_OUT_Y_L_ADDR),
259 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
260 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
261 ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_LE, 16, 16,
262 ST_ACCEL_DEFAULT_OUT_Z_L_ADDR),
263 IIO_CHAN_SOFT_TIMESTAMP(3)
264 };
265
266 static const struct st_sensor_settings st_accel_sensors_settings[] = {
267 {
268 .wai = ST_ACCEL_1_WAI_EXP,
269 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
270 .sensors_supported = {
271 [0] = LIS3DH_ACCEL_DEV_NAME,
272 [1] = LSM303DLHC_ACCEL_DEV_NAME,
273 [2] = LSM330D_ACCEL_DEV_NAME,
274 [3] = LSM330DL_ACCEL_DEV_NAME,
275 [4] = LSM330DLC_ACCEL_DEV_NAME,
276 [5] = LSM303AGR_ACCEL_DEV_NAME,
277 [6] = LIS2DH12_ACCEL_DEV_NAME,
278 },
279 .ch = (struct iio_chan_spec *)st_accel_12bit_channels,
280 .odr = {
281 .addr = ST_ACCEL_1_ODR_ADDR,
282 .mask = ST_ACCEL_1_ODR_MASK,
283 .odr_avl = {
284 { 1, ST_ACCEL_1_ODR_AVL_1HZ_VAL, },
285 { 10, ST_ACCEL_1_ODR_AVL_10HZ_VAL, },
286 { 25, ST_ACCEL_1_ODR_AVL_25HZ_VAL, },
287 { 50, ST_ACCEL_1_ODR_AVL_50HZ_VAL, },
288 { 100, ST_ACCEL_1_ODR_AVL_100HZ_VAL, },
289 { 200, ST_ACCEL_1_ODR_AVL_200HZ_VAL, },
290 { 400, ST_ACCEL_1_ODR_AVL_400HZ_VAL, },
291 { 1600, ST_ACCEL_1_ODR_AVL_1600HZ_VAL, },
292 },
293 },
294 .pw = {
295 .addr = ST_ACCEL_1_ODR_ADDR,
296 .mask = ST_ACCEL_1_ODR_MASK,
297 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
298 },
299 .enable_axis = {
300 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
301 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
302 },
303 .fs = {
304 .addr = ST_ACCEL_1_FS_ADDR,
305 .mask = ST_ACCEL_1_FS_MASK,
306 .fs_avl = {
307 [0] = {
308 .num = ST_ACCEL_FS_AVL_2G,
309 .value = ST_ACCEL_1_FS_AVL_2_VAL,
310 .gain = ST_ACCEL_1_FS_AVL_2_GAIN,
311 },
312 [1] = {
313 .num = ST_ACCEL_FS_AVL_4G,
314 .value = ST_ACCEL_1_FS_AVL_4_VAL,
315 .gain = ST_ACCEL_1_FS_AVL_4_GAIN,
316 },
317 [2] = {
318 .num = ST_ACCEL_FS_AVL_8G,
319 .value = ST_ACCEL_1_FS_AVL_8_VAL,
320 .gain = ST_ACCEL_1_FS_AVL_8_GAIN,
321 },
322 [3] = {
323 .num = ST_ACCEL_FS_AVL_16G,
324 .value = ST_ACCEL_1_FS_AVL_16_VAL,
325 .gain = ST_ACCEL_1_FS_AVL_16_GAIN,
326 },
327 },
328 },
329 .bdu = {
330 .addr = ST_ACCEL_1_BDU_ADDR,
331 .mask = ST_ACCEL_1_BDU_MASK,
332 },
333 .drdy_irq = {
334 .addr = ST_ACCEL_1_DRDY_IRQ_ADDR,
335 .mask_int1 = ST_ACCEL_1_DRDY_IRQ_INT1_MASK,
336 .mask_int2 = ST_ACCEL_1_DRDY_IRQ_INT2_MASK,
337 .addr_ihl = ST_ACCEL_1_IHL_IRQ_ADDR,
338 .mask_ihl = ST_ACCEL_1_IHL_IRQ_MASK,
339 .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
340 },
341 .multi_read_bit = ST_ACCEL_1_MULTIREAD_BIT,
342 .bootime = 2,
343 },
344 {
345 .wai = ST_ACCEL_2_WAI_EXP,
346 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
347 .sensors_supported = {
348 [0] = LIS331DLH_ACCEL_DEV_NAME,
349 [1] = LSM303DL_ACCEL_DEV_NAME,
350 [2] = LSM303DLH_ACCEL_DEV_NAME,
351 [3] = LSM303DLM_ACCEL_DEV_NAME,
352 },
353 .ch = (struct iio_chan_spec *)st_accel_12bit_channels,
354 .odr = {
355 .addr = ST_ACCEL_2_ODR_ADDR,
356 .mask = ST_ACCEL_2_ODR_MASK,
357 .odr_avl = {
358 { 50, ST_ACCEL_2_ODR_AVL_50HZ_VAL, },
359 { 100, ST_ACCEL_2_ODR_AVL_100HZ_VAL, },
360 { 400, ST_ACCEL_2_ODR_AVL_400HZ_VAL, },
361 { 1000, ST_ACCEL_2_ODR_AVL_1000HZ_VAL, },
362 },
363 },
364 .pw = {
365 .addr = ST_ACCEL_2_PW_ADDR,
366 .mask = ST_ACCEL_2_PW_MASK,
367 .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE,
368 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
369 },
370 .enable_axis = {
371 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
372 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
373 },
374 .fs = {
375 .addr = ST_ACCEL_2_FS_ADDR,
376 .mask = ST_ACCEL_2_FS_MASK,
377 .fs_avl = {
378 [0] = {
379 .num = ST_ACCEL_FS_AVL_2G,
380 .value = ST_ACCEL_2_FS_AVL_2_VAL,
381 .gain = ST_ACCEL_2_FS_AVL_2_GAIN,
382 },
383 [1] = {
384 .num = ST_ACCEL_FS_AVL_4G,
385 .value = ST_ACCEL_2_FS_AVL_4_VAL,
386 .gain = ST_ACCEL_2_FS_AVL_4_GAIN,
387 },
388 [2] = {
389 .num = ST_ACCEL_FS_AVL_8G,
390 .value = ST_ACCEL_2_FS_AVL_8_VAL,
391 .gain = ST_ACCEL_2_FS_AVL_8_GAIN,
392 },
393 },
394 },
395 .bdu = {
396 .addr = ST_ACCEL_2_BDU_ADDR,
397 .mask = ST_ACCEL_2_BDU_MASK,
398 },
399 .drdy_irq = {
400 .addr = ST_ACCEL_2_DRDY_IRQ_ADDR,
401 .mask_int1 = ST_ACCEL_2_DRDY_IRQ_INT1_MASK,
402 .mask_int2 = ST_ACCEL_2_DRDY_IRQ_INT2_MASK,
403 .addr_ihl = ST_ACCEL_2_IHL_IRQ_ADDR,
404 .mask_ihl = ST_ACCEL_2_IHL_IRQ_MASK,
405 .addr_od = ST_ACCEL_2_OD_IRQ_ADDR,
406 .mask_od = ST_ACCEL_2_OD_IRQ_MASK,
407 .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
408 },
409 .multi_read_bit = ST_ACCEL_2_MULTIREAD_BIT,
410 .bootime = 2,
411 },
412 {
413 .wai = ST_ACCEL_3_WAI_EXP,
414 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
415 .sensors_supported = {
416 [0] = LSM330_ACCEL_DEV_NAME,
417 },
418 .ch = (struct iio_chan_spec *)st_accel_16bit_channels,
419 .odr = {
420 .addr = ST_ACCEL_3_ODR_ADDR,
421 .mask = ST_ACCEL_3_ODR_MASK,
422 .odr_avl = {
423 { 3, ST_ACCEL_3_ODR_AVL_3HZ_VAL },
424 { 6, ST_ACCEL_3_ODR_AVL_6HZ_VAL, },
425 { 12, ST_ACCEL_3_ODR_AVL_12HZ_VAL, },
426 { 25, ST_ACCEL_3_ODR_AVL_25HZ_VAL, },
427 { 50, ST_ACCEL_3_ODR_AVL_50HZ_VAL, },
428 { 100, ST_ACCEL_3_ODR_AVL_100HZ_VAL, },
429 { 200, ST_ACCEL_3_ODR_AVL_200HZ_VAL, },
430 { 400, ST_ACCEL_3_ODR_AVL_400HZ_VAL, },
431 { 800, ST_ACCEL_3_ODR_AVL_800HZ_VAL, },
432 { 1600, ST_ACCEL_3_ODR_AVL_1600HZ_VAL, },
433 },
434 },
435 .pw = {
436 .addr = ST_ACCEL_3_ODR_ADDR,
437 .mask = ST_ACCEL_3_ODR_MASK,
438 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
439 },
440 .enable_axis = {
441 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
442 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
443 },
444 .fs = {
445 .addr = ST_ACCEL_3_FS_ADDR,
446 .mask = ST_ACCEL_3_FS_MASK,
447 .fs_avl = {
448 [0] = {
449 .num = ST_ACCEL_FS_AVL_2G,
450 .value = ST_ACCEL_3_FS_AVL_2_VAL,
451 .gain = ST_ACCEL_3_FS_AVL_2_GAIN,
452 },
453 [1] = {
454 .num = ST_ACCEL_FS_AVL_4G,
455 .value = ST_ACCEL_3_FS_AVL_4_VAL,
456 .gain = ST_ACCEL_3_FS_AVL_4_GAIN,
457 },
458 [2] = {
459 .num = ST_ACCEL_FS_AVL_6G,
460 .value = ST_ACCEL_3_FS_AVL_6_VAL,
461 .gain = ST_ACCEL_3_FS_AVL_6_GAIN,
462 },
463 [3] = {
464 .num = ST_ACCEL_FS_AVL_8G,
465 .value = ST_ACCEL_3_FS_AVL_8_VAL,
466 .gain = ST_ACCEL_3_FS_AVL_8_GAIN,
467 },
468 [4] = {
469 .num = ST_ACCEL_FS_AVL_16G,
470 .value = ST_ACCEL_3_FS_AVL_16_VAL,
471 .gain = ST_ACCEL_3_FS_AVL_16_GAIN,
472 },
473 },
474 },
475 .bdu = {
476 .addr = ST_ACCEL_3_BDU_ADDR,
477 .mask = ST_ACCEL_3_BDU_MASK,
478 },
479 .drdy_irq = {
480 .addr = ST_ACCEL_3_DRDY_IRQ_ADDR,
481 .mask_int1 = ST_ACCEL_3_DRDY_IRQ_INT1_MASK,
482 .mask_int2 = ST_ACCEL_3_DRDY_IRQ_INT2_MASK,
483 .addr_ihl = ST_ACCEL_3_IHL_IRQ_ADDR,
484 .mask_ihl = ST_ACCEL_3_IHL_IRQ_MASK,
485 .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
486 .ig1 = {
487 .en_addr = ST_ACCEL_3_IG1_EN_ADDR,
488 .en_mask = ST_ACCEL_3_IG1_EN_MASK,
489 },
490 },
491 .multi_read_bit = ST_ACCEL_3_MULTIREAD_BIT,
492 .bootime = 2,
493 },
494 {
495 .wai = ST_ACCEL_4_WAI_EXP,
496 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
497 .sensors_supported = {
498 [0] = LIS3LV02DL_ACCEL_DEV_NAME,
499 },
500 .ch = (struct iio_chan_spec *)st_accel_12bit_channels,
501 .odr = {
502 .addr = ST_ACCEL_4_ODR_ADDR,
503 .mask = ST_ACCEL_4_ODR_MASK,
504 .odr_avl = {
505 { 40, ST_ACCEL_4_ODR_AVL_40HZ_VAL },
506 { 160, ST_ACCEL_4_ODR_AVL_160HZ_VAL, },
507 { 640, ST_ACCEL_4_ODR_AVL_640HZ_VAL, },
508 { 2560, ST_ACCEL_4_ODR_AVL_2560HZ_VAL, },
509 },
510 },
511 .pw = {
512 .addr = ST_ACCEL_4_PW_ADDR,
513 .mask = ST_ACCEL_4_PW_MASK,
514 .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE,
515 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
516 },
517 .enable_axis = {
518 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
519 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
520 },
521 .fs = {
522 .addr = ST_ACCEL_4_FS_ADDR,
523 .mask = ST_ACCEL_4_FS_MASK,
524 .fs_avl = {
525 [0] = {
526 .num = ST_ACCEL_FS_AVL_2G,
527 .value = ST_ACCEL_4_FS_AVL_2_VAL,
528 .gain = ST_ACCEL_4_FS_AVL_2_GAIN,
529 },
530 [1] = {
531 .num = ST_ACCEL_FS_AVL_6G,
532 .value = ST_ACCEL_4_FS_AVL_6_VAL,
533 .gain = ST_ACCEL_4_FS_AVL_6_GAIN,
534 },
535 },
536 },
537 .bdu = {
538 .addr = ST_ACCEL_4_BDU_ADDR,
539 .mask = ST_ACCEL_4_BDU_MASK,
540 },
541 .drdy_irq = {
542 .addr = ST_ACCEL_4_DRDY_IRQ_ADDR,
543 .mask_int1 = ST_ACCEL_4_DRDY_IRQ_INT1_MASK,
544 .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
545 },
546 .multi_read_bit = ST_ACCEL_4_MULTIREAD_BIT,
547 .bootime = 2, /* guess */
548 },
549 {
550 .wai = ST_ACCEL_5_WAI_EXP,
551 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
552 .sensors_supported = {
553 [0] = LIS331DL_ACCEL_DEV_NAME,
554 },
555 .ch = (struct iio_chan_spec *)st_accel_8bit_channels,
556 .odr = {
557 .addr = ST_ACCEL_5_ODR_ADDR,
558 .mask = ST_ACCEL_5_ODR_MASK,
559 .odr_avl = {
560 { 100, ST_ACCEL_5_ODR_AVL_100HZ_VAL },
561 { 400, ST_ACCEL_5_ODR_AVL_400HZ_VAL, },
562 },
563 },
564 .pw = {
565 .addr = ST_ACCEL_5_PW_ADDR,
566 .mask = ST_ACCEL_5_PW_MASK,
567 .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE,
568 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
569 },
570 .enable_axis = {
571 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
572 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
573 },
574 .fs = {
575 .addr = ST_ACCEL_5_FS_ADDR,
576 .mask = ST_ACCEL_5_FS_MASK,
577 .fs_avl = {
578 [0] = {
579 .num = ST_ACCEL_FS_AVL_2G,
580 .value = ST_ACCEL_5_FS_AVL_2_VAL,
581 .gain = ST_ACCEL_5_FS_AVL_2_GAIN,
582 },
583 [1] = {
584 .num = ST_ACCEL_FS_AVL_8G,
585 .value = ST_ACCEL_5_FS_AVL_8_VAL,
586 .gain = ST_ACCEL_5_FS_AVL_8_GAIN,
587 },
588 },
589 },
590 .drdy_irq = {
591 .addr = ST_ACCEL_5_DRDY_IRQ_ADDR,
592 .mask_int1 = ST_ACCEL_5_DRDY_IRQ_INT1_MASK,
593 .mask_int2 = ST_ACCEL_5_DRDY_IRQ_INT2_MASK,
594 .addr_ihl = ST_ACCEL_5_IHL_IRQ_ADDR,
595 .mask_ihl = ST_ACCEL_5_IHL_IRQ_MASK,
596 .addr_od = ST_ACCEL_5_OD_IRQ_ADDR,
597 .mask_od = ST_ACCEL_5_OD_IRQ_MASK,
598 .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
599 },
600 .multi_read_bit = ST_ACCEL_5_MULTIREAD_BIT,
601 .bootime = 2, /* guess */
602 },
603 {
604 .wai = ST_ACCEL_6_WAI_EXP,
605 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
606 .sensors_supported = {
607 [0] = H3LIS331DL_DRIVER_NAME,
608 },
609 .ch = (struct iio_chan_spec *)st_accel_12bit_channels,
610 .odr = {
611 .addr = ST_ACCEL_6_ODR_ADDR,
612 .mask = ST_ACCEL_6_ODR_MASK,
613 .odr_avl = {
614 { 50, ST_ACCEL_6_ODR_AVL_50HZ_VAL },
615 { 100, ST_ACCEL_6_ODR_AVL_100HZ_VAL, },
616 { 400, ST_ACCEL_6_ODR_AVL_400HZ_VAL, },
617 { 1000, ST_ACCEL_6_ODR_AVL_1000HZ_VAL, },
618 },
619 },
620 .pw = {
621 .addr = ST_ACCEL_6_PW_ADDR,
622 .mask = ST_ACCEL_6_PW_MASK,
623 .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE,
624 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
625 },
626 .enable_axis = {
627 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
628 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
629 },
630 .fs = {
631 .addr = ST_ACCEL_6_FS_ADDR,
632 .mask = ST_ACCEL_6_FS_MASK,
633 .fs_avl = {
634 [0] = {
635 .num = ST_ACCEL_FS_AVL_100G,
636 .value = ST_ACCEL_6_FS_AVL_100_VAL,
637 .gain = ST_ACCEL_6_FS_AVL_100_GAIN,
638 },
639 [1] = {
640 .num = ST_ACCEL_FS_AVL_200G,
641 .value = ST_ACCEL_6_FS_AVL_200_VAL,
642 .gain = ST_ACCEL_6_FS_AVL_200_GAIN,
643 },
644 [2] = {
645 .num = ST_ACCEL_FS_AVL_400G,
646 .value = ST_ACCEL_6_FS_AVL_400_VAL,
647 .gain = ST_ACCEL_6_FS_AVL_400_GAIN,
648 },
649 },
650 },
651 .bdu = {
652 .addr = ST_ACCEL_6_BDU_ADDR,
653 .mask = ST_ACCEL_6_BDU_MASK,
654 },
655 .drdy_irq = {
656 .addr = ST_ACCEL_6_DRDY_IRQ_ADDR,
657 .mask_int1 = ST_ACCEL_6_DRDY_IRQ_INT1_MASK,
658 .mask_int2 = ST_ACCEL_6_DRDY_IRQ_INT2_MASK,
659 .addr_ihl = ST_ACCEL_6_IHL_IRQ_ADDR,
660 .mask_ihl = ST_ACCEL_6_IHL_IRQ_MASK,
661 },
662 .multi_read_bit = ST_ACCEL_6_MULTIREAD_BIT,
663 .bootime = 2,
664 },
665 };
666
667 static int st_accel_read_raw(struct iio_dev *indio_dev,
668 struct iio_chan_spec const *ch, int *val,
669 int *val2, long mask)
670 {
671 int err;
672 struct st_sensor_data *adata = iio_priv(indio_dev);
673
674 switch (mask) {
675 case IIO_CHAN_INFO_RAW:
676 err = st_sensors_read_info_raw(indio_dev, ch, val);
677 if (err < 0)
678 goto read_error;
679
680 return IIO_VAL_INT;
681 case IIO_CHAN_INFO_SCALE:
682 *val = 0;
683 *val2 = adata->current_fullscale->gain;
684 return IIO_VAL_INT_PLUS_MICRO;
685 case IIO_CHAN_INFO_SAMP_FREQ:
686 *val = adata->odr;
687 return IIO_VAL_INT;
688 default:
689 return -EINVAL;
690 }
691
692 read_error:
693 return err;
694 }
695
696 static int st_accel_write_raw(struct iio_dev *indio_dev,
697 struct iio_chan_spec const *chan, int val, int val2, long mask)
698 {
699 int err;
700
701 switch (mask) {
702 case IIO_CHAN_INFO_SCALE:
703 err = st_sensors_set_fullscale_by_gain(indio_dev, val2);
704 break;
705 case IIO_CHAN_INFO_SAMP_FREQ:
706 if (val2)
707 return -EINVAL;
708 mutex_lock(&indio_dev->mlock);
709 err = st_sensors_set_odr(indio_dev, val);
710 mutex_unlock(&indio_dev->mlock);
711 return err;
712 default:
713 return -EINVAL;
714 }
715
716 return err;
717 }
718
719 static ST_SENSORS_DEV_ATTR_SAMP_FREQ_AVAIL();
720 static ST_SENSORS_DEV_ATTR_SCALE_AVAIL(in_accel_scale_available);
721
722 static struct attribute *st_accel_attributes[] = {
723 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
724 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
725 NULL,
726 };
727
728 static const struct attribute_group st_accel_attribute_group = {
729 .attrs = st_accel_attributes,
730 };
731
732 static const struct iio_info accel_info = {
733 .driver_module = THIS_MODULE,
734 .attrs = &st_accel_attribute_group,
735 .read_raw = &st_accel_read_raw,
736 .write_raw = &st_accel_write_raw,
737 .debugfs_reg_access = &st_sensors_debugfs_reg_access,
738 };
739
740 #ifdef CONFIG_IIO_TRIGGER
741 static const struct iio_trigger_ops st_accel_trigger_ops = {
742 .owner = THIS_MODULE,
743 .set_trigger_state = ST_ACCEL_TRIGGER_SET_STATE,
744 .validate_device = st_sensors_validate_device,
745 };
746 #define ST_ACCEL_TRIGGER_OPS (&st_accel_trigger_ops)
747 #else
748 #define ST_ACCEL_TRIGGER_OPS NULL
749 #endif
750
751 int st_accel_common_probe(struct iio_dev *indio_dev)
752 {
753 struct st_sensor_data *adata = iio_priv(indio_dev);
754 int irq = adata->get_irq_data_ready(indio_dev);
755 int err;
756
757 indio_dev->modes = INDIO_DIRECT_MODE;
758 indio_dev->info = &accel_info;
759 mutex_init(&adata->tb.buf_lock);
760
761 st_sensors_power_enable(indio_dev);
762
763 err = st_sensors_check_device_support(indio_dev,
764 ARRAY_SIZE(st_accel_sensors_settings),
765 st_accel_sensors_settings);
766 if (err < 0)
767 return err;
768
769 adata->num_data_channels = ST_ACCEL_NUMBER_DATA_CHANNELS;
770 adata->multiread_bit = adata->sensor_settings->multi_read_bit;
771 indio_dev->channels = adata->sensor_settings->ch;
772 indio_dev->num_channels = ST_SENSORS_NUMBER_ALL_CHANNELS;
773
774 adata->current_fullscale = (struct st_sensor_fullscale_avl *)
775 &adata->sensor_settings->fs.fs_avl[0];
776 adata->odr = adata->sensor_settings->odr.odr_avl[0].hz;
777
778 if (!adata->dev->platform_data)
779 adata->dev->platform_data =
780 (struct st_sensors_platform_data *)&default_accel_pdata;
781
782 err = st_sensors_init_sensor(indio_dev, adata->dev->platform_data);
783 if (err < 0)
784 return err;
785
786 err = st_accel_allocate_ring(indio_dev);
787 if (err < 0)
788 return err;
789
790 if (irq > 0) {
791 err = st_sensors_allocate_trigger(indio_dev,
792 ST_ACCEL_TRIGGER_OPS);
793 if (err < 0)
794 goto st_accel_probe_trigger_error;
795 }
796
797 err = iio_device_register(indio_dev);
798 if (err)
799 goto st_accel_device_register_error;
800
801 dev_info(&indio_dev->dev, "registered accelerometer %s\n",
802 indio_dev->name);
803
804 return 0;
805
806 st_accel_device_register_error:
807 if (irq > 0)
808 st_sensors_deallocate_trigger(indio_dev);
809 st_accel_probe_trigger_error:
810 st_accel_deallocate_ring(indio_dev);
811
812 return err;
813 }
814 EXPORT_SYMBOL(st_accel_common_probe);
815
816 void st_accel_common_remove(struct iio_dev *indio_dev)
817 {
818 struct st_sensor_data *adata = iio_priv(indio_dev);
819
820 st_sensors_power_disable(indio_dev);
821
822 iio_device_unregister(indio_dev);
823 if (adata->get_irq_data_ready(indio_dev) > 0)
824 st_sensors_deallocate_trigger(indio_dev);
825
826 st_accel_deallocate_ring(indio_dev);
827 }
828 EXPORT_SYMBOL(st_accel_common_remove);
829
830 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>");
831 MODULE_DESCRIPTION("STMicroelectronics accelerometers driver");
832 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support