drivers/iio/adc/nau7802.c

   1 /*
   2  * Driver for the Nuvoton NAU7802 ADC
   3  *
   4  * Copyright 2013 Free Electrons
   5  *
   6  * Licensed under the GPLv2 or later.
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/i2c.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/module.h>
  13 #include <linux/wait.h>
  14 #include <linux/log2.h>
  15 #include <linux/of.h>
  16
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/sysfs.h>
  19
  20 #define NAU7802_REG_PUCTRL      0x00
  21 #define NAU7802_PUCTRL_RR(x)            (x << 0)
  22 #define NAU7802_PUCTRL_RR_BIT           NAU7802_PUCTRL_RR(1)
  23 #define NAU7802_PUCTRL_PUD(x)           (x << 1)
  24 #define NAU7802_PUCTRL_PUD_BIT          NAU7802_PUCTRL_PUD(1)
  25 #define NAU7802_PUCTRL_PUA(x)           (x << 2)
  26 #define NAU7802_PUCTRL_PUA_BIT          NAU7802_PUCTRL_PUA(1)
  27 #define NAU7802_PUCTRL_PUR(x)           (x << 3)
  28 #define NAU7802_PUCTRL_PUR_BIT          NAU7802_PUCTRL_PUR(1)
  29 #define NAU7802_PUCTRL_CS(x)            (x << 4)
  30 #define NAU7802_PUCTRL_CS_BIT           NAU7802_PUCTRL_CS(1)
  31 #define NAU7802_PUCTRL_CR(x)            (x << 5)
  32 #define NAU7802_PUCTRL_CR_BIT           NAU7802_PUCTRL_CR(1)
  33 #define NAU7802_PUCTRL_AVDDS(x)         (x << 7)
  34 #define NAU7802_PUCTRL_AVDDS_BIT        NAU7802_PUCTRL_AVDDS(1)
  35 #define NAU7802_REG_CTRL1       0x01
  36 #define NAU7802_CTRL1_VLDO(x)           (x << 3)
  37 #define NAU7802_CTRL1_GAINS(x)          (x)
  38 #define NAU7802_CTRL1_GAINS_BITS        0x07
  39 #define NAU7802_REG_CTRL2       0x02
  40 #define NAU7802_CTRL2_CHS(x)            (x << 7)
  41 #define NAU7802_CTRL2_CRS(x)            (x << 4)
  42 #define NAU7802_SAMP_FREQ_320   0x07
  43 #define NAU7802_CTRL2_CHS_BIT           NAU7802_CTRL2_CHS(1)
  44 #define NAU7802_REG_ADC_B2      0x12
  45 #define NAU7802_REG_ADC_B1      0x13
  46 #define NAU7802_REG_ADC_B0      0x14
  47 #define NAU7802_REG_ADC_CTRL    0x15
  48
  49 #define NAU7802_MIN_CONVERSIONS 6
  50
  51 struct nau7802_state {
  52         struct i2c_client       *client;
  53         s32                     last_value;
  54         struct mutex            lock;
  55         struct mutex            data_lock;
  56         u32                     vref_mv;
  57         u32                     conversion_count;
  58         u32                     min_conversions;
  59         u8                      sample_rate;
  60         u32                     scale_avail[8];
  61         struct completion       value_ok;
  62 };
  63
  64 #define NAU7802_CHANNEL(chan) {                                 \
  65         .type = IIO_VOLTAGE,                                    \
  66         .indexed = 1,                                           \
  67         .channel = (chan),                                      \
  68         .scan_index = (chan),                                   \
  69         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
  70         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
  71                                 BIT(IIO_CHAN_INFO_SAMP_FREQ)    \
  72 }
  73
  74 static const struct iio_chan_spec nau7802_chan_array[] = {
  75         NAU7802_CHANNEL(0),
  76         NAU7802_CHANNEL(1),
  77 };
  78
  79 static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80,
  80                                                 10, 10, 10, 320};
  81
  82 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320");
  83
  84 static struct attribute *nau7802_attributes[] = {
  85         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
  86         NULL
  87 };
  88
  89 static const struct attribute_group nau7802_attribute_group = {
  90         .attrs = nau7802_attributes,
  91 };
  92
  93 static int nau7802_set_gain(struct nau7802_state *st, int gain)
  94 {
  95         int ret;
  96
  97         mutex_lock(&st->lock);
  98         st->conversion_count = 0;
  99
 100         ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
 101         if (ret < 0)
 102                 goto nau7802_sysfs_set_gain_out;
 103         ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
 104                                         (ret & (~NAU7802_CTRL1_GAINS_BITS)) |
 105                                         gain);
 106
 107 nau7802_sysfs_set_gain_out:
 108         mutex_unlock(&st->lock);
 109
 110         return ret;
 111 }
 112
 113 static int nau7802_read_conversion(struct nau7802_state *st)
 114 {
 115         int data;
 116
 117         mutex_lock(&st->data_lock);
 118         data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2);
 119         if (data < 0)
 120                 goto nau7802_read_conversion_out;
 121         st->last_value = data << 16;
 122
 123         data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1);
 124         if (data < 0)
 125                 goto nau7802_read_conversion_out;
 126         st->last_value |= data << 8;
 127
 128         data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0);
 129         if (data < 0)
 130                 goto nau7802_read_conversion_out;
 131         st->last_value |= data;
 132
 133         st->last_value = sign_extend32(st->last_value, 23);
 134
 135 nau7802_read_conversion_out:
 136         mutex_unlock(&st->data_lock);
 137
 138         return data;
 139 }
 140
 141 /*
 142  * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
 143  */
 144 static int nau7802_sync(struct nau7802_state *st)
 145 {
 146         int ret;
 147
 148         ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
 149         if (ret < 0)
 150                 return ret;
 151         ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
 152                                 ret | NAU7802_PUCTRL_CS_BIT);
 153
 154         return ret;
 155 }
 156
 157 static irqreturn_t nau7802_eoc_trigger(int irq, void *private)
 158 {
 159         struct iio_dev *indio_dev = private;
 160         struct nau7802_state *st = iio_priv(indio_dev);
 161         int status;
 162
 163         status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
 164         if (status < 0)
 165                 return IRQ_HANDLED;
 166
 167         if (!(status & NAU7802_PUCTRL_CR_BIT))
 168                 return IRQ_NONE;
 169
 170         if (nau7802_read_conversion(st) < 0)
 171                 return IRQ_HANDLED;
 172
 173         /*
 174          * Because there is actually only one ADC for both channels, we have to
 175          * wait for enough conversions to happen before getting a significant
 176          * value when changing channels and the values are far apart.
 177          */
 178         if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
 179                 st->conversion_count++;
 180         if (st->conversion_count >= NAU7802_MIN_CONVERSIONS)
 181                 complete_all(&st->value_ok);
 182
 183         return IRQ_HANDLED;
 184 }
 185
 186 static int nau7802_read_irq(struct iio_dev *indio_dev,
 187                         struct iio_chan_spec const *chan,
 188                         int *val)
 189 {
 190         struct nau7802_state *st = iio_priv(indio_dev);
 191         int ret;
 192
 193         reinit_completion(&st->value_ok);
 194         enable_irq(st->client->irq);
 195
 196         nau7802_sync(st);
 197
 198         /* read registers to ensure we flush everything */
 199         ret = nau7802_read_conversion(st);
 200         if (ret < 0)
 201                 goto read_chan_info_failure;
 202
 203         /* Wait for a conversion to finish */
 204         ret = wait_for_completion_interruptible_timeout(&st->value_ok,
 205                         msecs_to_jiffies(1000));
 206         if (ret == 0)
 207                 ret = -ETIMEDOUT;
 208
 209         if (ret < 0)
 210                 goto read_chan_info_failure;
 211
 212         disable_irq(st->client->irq);
 213
 214         *val = st->last_value;
 215
 216         return IIO_VAL_INT;
 217
 218 read_chan_info_failure:
 219         disable_irq(st->client->irq);
 220
 221         return ret;
 222 }
 223
 224 static int nau7802_read_poll(struct iio_dev *indio_dev,
 225                         struct iio_chan_spec const *chan,
 226                         int *val)
 227 {
 228         struct nau7802_state *st = iio_priv(indio_dev);
 229         int ret;
 230
 231         nau7802_sync(st);
 232
 233         /* read registers to ensure we flush everything */
 234         ret = nau7802_read_conversion(st);
 235         if (ret < 0)
 236                 return ret;
 237
 238         /*
 239          * Because there is actually only one ADC for both channels, we have to
 240          * wait for enough conversions to happen before getting a significant
 241          * value when changing channels and the values are far appart.
 242          */
 243         do {
 244                 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
 245                 if (ret < 0)
 246                         return ret;
 247
 248                 while (!(ret & NAU7802_PUCTRL_CR_BIT)) {
 249                         if (st->sample_rate != NAU7802_SAMP_FREQ_320)
 250                                 msleep(20);
 251                         else
 252                                 mdelay(4);
 253                         ret = i2c_smbus_read_byte_data(st->client,
 254                                                         NAU7802_REG_PUCTRL);
 255                         if (ret < 0)
 256                                 return ret;
 257                 }
 258
 259                 ret = nau7802_read_conversion(st);
 260                 if (ret < 0)
 261                         return ret;
 262                 if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
 263                         st->conversion_count++;
 264         } while (st->conversion_count < NAU7802_MIN_CONVERSIONS);
 265
 266         *val = st->last_value;
 267
 268         return IIO_VAL_INT;
 269 }
 270
 271 static int nau7802_read_raw(struct iio_dev *indio_dev,
 272                             struct iio_chan_spec const *chan,
 273                             int *val, int *val2, long mask)
 274 {
 275         struct nau7802_state *st = iio_priv(indio_dev);
 276         int ret;
 277
 278         switch (mask) {
 279         case IIO_CHAN_INFO_RAW:
 280                 mutex_lock(&st->lock);
 281                 /*
 282                  * Select the channel to use
 283                  *   - Channel 1 is value 0 in the CHS register
 284                  *   - Channel 2 is value 1 in the CHS register
 285                  */
 286                 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2);
 287                 if (ret < 0) {
 288                         mutex_unlock(&st->lock);
 289                         return ret;
 290                 }
 291
 292                 if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) ||
 293                                 (!(ret & NAU7802_CTRL2_CHS_BIT) &&
 294                                  chan->channel)) {
 295                         st->conversion_count = 0;
 296                         ret = i2c_smbus_write_byte_data(st->client,
 297                                         NAU7802_REG_CTRL2,
 298                                         NAU7802_CTRL2_CHS(chan->channel) |
 299                                         NAU7802_CTRL2_CRS(st->sample_rate));
 300
 301                         if (ret < 0) {
 302                                 mutex_unlock(&st->lock);
 303                                 return ret;
 304                         }
 305                 }
 306
 307                 if (st->client->irq)
 308                         ret = nau7802_read_irq(indio_dev, chan, val);
 309                 else
 310                         ret = nau7802_read_poll(indio_dev, chan, val);
 311
 312                 mutex_unlock(&st->lock);
 313                 return ret;
 314
 315         case IIO_CHAN_INFO_SCALE:
 316                 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
 317                 if (ret < 0)
 318                         return ret;
 319
 320                 /*
 321                  * We have 24 bits of signed data, that means 23 bits of data
 322                  * plus the sign bit
 323                  */
 324                 *val = st->vref_mv;
 325                 *val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS);
 326
 327                 return IIO_VAL_FRACTIONAL_LOG2;
 328
 329         case IIO_CHAN_INFO_SAMP_FREQ:
 330                 *val =  nau7802_sample_freq_avail[st->sample_rate];
 331                 *val2 = 0;
 332                 return IIO_VAL_INT;
 333
 334         default:
 335                 break;
 336         }
 337
 338         return -EINVAL;
 339 }
 340
 341 static int nau7802_write_raw(struct iio_dev *indio_dev,
 342                              struct iio_chan_spec const *chan,
 343                              int val, int val2, long mask)
 344 {
 345         struct nau7802_state *st = iio_priv(indio_dev);
 346         int i, ret;
 347
 348         switch (mask) {
 349         case IIO_CHAN_INFO_SCALE:
 350                 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
 351                         if (val2 == st->scale_avail[i])
 352                                 return nau7802_set_gain(st, i);
 353
 354                 break;
 355
 356         case IIO_CHAN_INFO_SAMP_FREQ:
 357                 for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++)
 358                         if (val == nau7802_sample_freq_avail[i]) {
 359                                 mutex_lock(&st->lock);
 360                                 st->sample_rate = i;
 361                                 st->conversion_count = 0;
 362                                 ret = i2c_smbus_write_byte_data(st->client,
 363                                         NAU7802_REG_CTRL2,
 364                                         NAU7802_CTRL2_CRS(st->sample_rate));
 365                                 mutex_unlock(&st->lock);
 366                                 return ret;
 367                         }
 368
 369                 break;
 370
 371         default:
 372                 break;
 373         }
 374
 375         return -EINVAL;
 376 }
 377
 378 static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
 379                                      struct iio_chan_spec const *chan,
 380                                      long mask)
 381 {
 382         return IIO_VAL_INT_PLUS_NANO;
 383 }
 384
 385 static const struct iio_info nau7802_info = {
 386         .driver_module = THIS_MODULE,
 387         .read_raw = &nau7802_read_raw,
 388         .write_raw = &nau7802_write_raw,
 389         .write_raw_get_fmt = nau7802_write_raw_get_fmt,
 390         .attrs = &nau7802_attribute_group,
 391 };
 392
 393 static int nau7802_probe(struct i2c_client *client,
 394                         const struct i2c_device_id *id)
 395 {
 396         struct iio_dev *indio_dev;
 397         struct nau7802_state *st;
 398         struct device_node *np = client->dev.of_node;
 399         int i, ret;
 400         u8 data;
 401         u32 tmp = 0;
 402
 403         if (!client->dev.of_node) {
 404                 dev_err(&client->dev, "No device tree node available.\n");
 405                 return -EINVAL;
 406         }
 407
 408         indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
 409         if (indio_dev == NULL)
 410                 return -ENOMEM;
 411
 412         st = iio_priv(indio_dev);
 413
 414         i2c_set_clientdata(client, indio_dev);
 415
 416         indio_dev->dev.parent = &client->dev;
 417         indio_dev->name = dev_name(&client->dev);
 418         indio_dev->modes = INDIO_DIRECT_MODE;
 419         indio_dev->info = &nau7802_info;
 420
 421         st->client = client;
 422
 423         /* Reset the device */
 424         ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
 425                                   NAU7802_PUCTRL_RR_BIT);
 426         if (ret < 0)
 427                 return ret;
 428
 429         /* Enter normal operation mode */
 430         ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
 431                                   NAU7802_PUCTRL_PUD_BIT);
 432         if (ret < 0)
 433                 return ret;
 434
 435         /*
 436          * After about 200 usecs, the device should be ready and then
 437          * the Power Up bit will be set to 1. If not, wait for it.
 438          */
 439         udelay(210);
 440         ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
 441         if (ret < 0)
 442                 return ret;
 443         if (!(ret & NAU7802_PUCTRL_PUR_BIT))
 444                 return ret;
 445
 446         of_property_read_u32(np, "nuvoton,vldo", &tmp);
 447         st->vref_mv = tmp;
 448
 449         data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT |
 450                 NAU7802_PUCTRL_CS_BIT;
 451         if (tmp >= 2400)
 452                 data |= NAU7802_PUCTRL_AVDDS_BIT;
 453
 454         ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data);
 455         if (ret < 0)
 456                 return ret;
 457         ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30);
 458         if (ret < 0)
 459                 return ret;
 460
 461         if (tmp >= 2400) {
 462                 data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300);
 463                 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
 464                                                 data);
 465                 if (ret < 0)
 466                         return ret;
 467         }
 468
 469         /* Populate available ADC input ranges */
 470         for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
 471                 st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL)
 472                                            >> (23 + i);
 473
 474         init_completion(&st->value_ok);
 475
 476         /*
 477          * The ADC fires continuously and we can't do anything about
 478          * it. So we need to have the IRQ disabled by default, and we
 479          * will enable them back when we will need them..
 480          */
 481         if (client->irq) {
 482                 ret = request_threaded_irq(client->irq,
 483                                 NULL,
 484                                 nau7802_eoc_trigger,
 485                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 486                                 client->dev.driver->name,
 487                                 indio_dev);
 488                 if (ret) {
 489                         /*
 490                          * What may happen here is that our IRQ controller is
 491                          * not able to get level interrupt but this is required
 492                          * by this ADC as when going over 40 sample per second,
 493                          * the interrupt line may stay high between conversions.
 494                          * So, we continue no matter what but we switch to
 495                          * polling mode.
 496                          */
 497                         dev_info(&client->dev,
 498                                 "Failed to allocate IRQ, using polling mode\n");
 499                         client->irq = 0;
 500                 } else
 501                         disable_irq(client->irq);
 502         }
 503
 504         if (!client->irq) {
 505                 /*
 506                  * We are polling, use the fastest sample rate by
 507                  * default
 508                  */
 509                 st->sample_rate = NAU7802_SAMP_FREQ_320;
 510                 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2,
 511                                           NAU7802_CTRL2_CRS(st->sample_rate));
 512                 if (ret)
 513                         goto error_free_irq;
 514         }
 515
 516         /* Setup the ADC channels available on the board */
 517         indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array);
 518         indio_dev->channels = nau7802_chan_array;
 519
 520         mutex_init(&st->lock);
 521         mutex_init(&st->data_lock);
 522
 523         ret = iio_device_register(indio_dev);
 524         if (ret < 0) {
 525                 dev_err(&client->dev, "Couldn't register the device.\n");
 526                 goto error_device_register;
 527         }
 528
 529         return 0;
 530
 531 error_device_register:
 532         mutex_destroy(&st->lock);
 533         mutex_destroy(&st->data_lock);
 534 error_free_irq:
 535         if (client->irq)
 536                 free_irq(client->irq, indio_dev);
 537
 538         return ret;
 539 }
 540
 541 static int nau7802_remove(struct i2c_client *client)
 542 {
 543         struct iio_dev *indio_dev = i2c_get_clientdata(client);
 544         struct nau7802_state *st = iio_priv(indio_dev);
 545
 546         iio_device_unregister(indio_dev);
 547         mutex_destroy(&st->lock);
 548         mutex_destroy(&st->data_lock);
 549         if (client->irq)
 550                 free_irq(client->irq, indio_dev);
 551
 552         return 0;
 553 }
 554
 555 static const struct i2c_device_id nau7802_i2c_id[] = {
 556         { "nau7802", 0 },
 557         { }
 558 };
 559 MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id);
 560
 561 static const struct of_device_id nau7802_dt_ids[] = {
 562         { .compatible = "nuvoton,nau7802" },
 563         {},
 564 };
 565 MODULE_DEVICE_TABLE(of, nau7802_dt_ids);
 566
 567 static struct i2c_driver nau7802_driver = {
 568         .probe = nau7802_probe,
 569         .remove = nau7802_remove,
 570         .id_table = nau7802_i2c_id,
 571         .driver = {
 572                    .name = "nau7802",
 573                    .of_match_table = nau7802_dt_ids,
 574         },
 575 };
 576
 577 module_i2c_driver(nau7802_driver);
 578
 579 MODULE_LICENSE("GPL");
 580 MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver");
 581 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 582 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");