?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mmc: rtsx_pci: Enable MMC_CAP_ERASE to allow erase/discard/trim requests
[linux/fpc-iii.git] / drivers / usb / gadget / udc / omap_udc.c
blob9b7d39484ed3afa55c95a254379b995341bc7ad4
1 /*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15 #undef DEBUG
16 #undef VERBOSE
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/timer.h>
26 #include <linux/list.h>
27 #include <linux/interrupt.h>
28 #include <linux/proc_fs.h>
29 #include <linux/mm.h>
30 #include <linux/moduleparam.h>
31 #include <linux/platform_device.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/clk.h>
37 #include <linux/err.h>
38 #include <linux/prefetch.h>
39 #include <linux/io.h>
40
41 #include <asm/byteorder.h>
42 #include <asm/irq.h>
43 #include <asm/unaligned.h>
44 #include <asm/mach-types.h>
45
46 #include <linux/omap-dma.h>
47
48 #include <mach/usb.h>
49
50 #include "omap_udc.h"
51
52 #undef USB_TRACE
53
54 /* bulk DMA seems to be behaving for both IN and OUT */
55 #define USE_DMA
56
57 /* ISO too */
58 #define USE_ISO
59
60 #define DRIVER_DESC "OMAP UDC driver"
61 #define DRIVER_VERSION "4 October 2004"
62
63 #define OMAP_DMA_USB_W2FC_TX0 29
64 #define OMAP_DMA_USB_W2FC_RX0 26
65
66 /*
67 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
68 * D+ pullup to allow enumeration. That's too early for the gadget
69 * framework to use from usb_endpoint_enable(), which happens after
70 * enumeration as part of activating an interface. (But if we add an
71 * optional new "UDC not yet running" state to the gadget driver model,
72 * even just during driver binding, the endpoint autoconfig logic is the
73 * natural spot to manufacture new endpoints.)
74 *
75 * So instead of using endpoint enable calls to control the hardware setup,
76 * this driver defines a "fifo mode" parameter. It's used during driver
77 * initialization to choose among a set of pre-defined endpoint configs.
78 * See omap_udc_setup() for available modes, or to add others. That code
79 * lives in an init section, so use this driver as a module if you need
80 * to change the fifo mode after the kernel boots.
81 *
82 * Gadget drivers normally ignore endpoints they don't care about, and
83 * won't include them in configuration descriptors. That means only
84 * misbehaving hosts would even notice they exist.
85 */
86 #ifdef USE_ISO
87 static unsigned fifo_mode = 3;
88 #else
89 static unsigned fifo_mode;
90 #endif
91
92 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
93 * boot parameter "omap_udc:fifo_mode=42"
94 */
95 module_param(fifo_mode, uint, 0);
96 MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
97
98 #ifdef USE_DMA
99 static bool use_dma = 1;
100
101 /* "modprobe omap_udc use_dma=y", or else as a kernel
102 * boot parameter "omap_udc:use_dma=y"
103 */
104 module_param(use_dma, bool, 0);
105 MODULE_PARM_DESC(use_dma, "enable/disable DMA");
106 #else /* !USE_DMA */
107
108 /* save a bit of code */
109 #define use_dma 0
110 #endif /* !USE_DMA */
111
112
113 static const char driver_name[] = "omap_udc";
114 static const char driver_desc[] = DRIVER_DESC;
115
116 /*-------------------------------------------------------------------------*/
117
118 /* there's a notion of "current endpoint" for modifying endpoint
119 * state, and PIO access to its FIFO.
120 */
121
122 static void use_ep(struct omap_ep *ep, u16 select)
123 {
124 u16 num = ep->bEndpointAddress & 0x0f;
125
126 if (ep->bEndpointAddress & USB_DIR_IN)
127 num |= UDC_EP_DIR;
128 omap_writew(num | select, UDC_EP_NUM);
129 /* when select, MUST deselect later !! */
130 }
131
132 static inline void deselect_ep(void)
133 {
134 u16 w;
135
136 w = omap_readw(UDC_EP_NUM);
137 w &= ~UDC_EP_SEL;
138 omap_writew(w, UDC_EP_NUM);
139 /* 6 wait states before TX will happen */
140 }
141
142 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
143
144 /*-------------------------------------------------------------------------*/
145
146 static int omap_ep_enable(struct usb_ep *_ep,
147 const struct usb_endpoint_descriptor *desc)
148 {
149 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
150 struct omap_udc *udc;
151 unsigned long flags;
152 u16 maxp;
153
154 /* catch various bogus parameters */
155 if (!_ep || !desc
156 || desc->bDescriptorType != USB_DT_ENDPOINT
157 || ep->bEndpointAddress != desc->bEndpointAddress
158 || ep->maxpacket < usb_endpoint_maxp(desc)) {
159 DBG("%s, bad ep or descriptor\n", __func__);
160 return -EINVAL;
161 }
162 maxp = usb_endpoint_maxp(desc);
163 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
164 && maxp != ep->maxpacket)
165 || usb_endpoint_maxp(desc) > ep->maxpacket
166 || !desc->wMaxPacketSize) {
167 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
168 return -ERANGE;
169 }
170
171 #ifdef USE_ISO
172 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
173 && desc->bInterval != 1)) {
174 /* hardware wants period = 1; USB allows 2^(Interval-1) */
175 DBG("%s, unsupported ISO period %dms\n", _ep->name,
176 1 << (desc->bInterval - 1));
177 return -EDOM;
178 }
179 #else
180 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
181 DBG("%s, ISO nyet\n", _ep->name);
182 return -EDOM;
183 }
184 #endif
185
186 /* xfer types must match, except that interrupt ~= bulk */
187 if (ep->bmAttributes != desc->bmAttributes
188 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
189 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
190 DBG("%s, %s type mismatch\n", __func__, _ep->name);
191 return -EINVAL;
192 }
193
194 udc = ep->udc;
195 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
196 DBG("%s, bogus device state\n", __func__);
197 return -ESHUTDOWN;
198 }
199
200 spin_lock_irqsave(&udc->lock, flags);
201
202 ep->ep.desc = desc;
203 ep->irqs = 0;
204 ep->stopped = 0;
205 ep->ep.maxpacket = maxp;
206
207 /* set endpoint to initial state */
208 ep->dma_channel = 0;
209 ep->has_dma = 0;
210 ep->lch = -1;
211 use_ep(ep, UDC_EP_SEL);
212 omap_writew(udc->clr_halt, UDC_CTRL);
213 ep->ackwait = 0;
214 deselect_ep();
215
216 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
217 list_add(&ep->iso, &udc->iso);
218
219 /* maybe assign a DMA channel to this endpoint */
220 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
221 /* FIXME ISO can dma, but prefers first channel */
222 dma_channel_claim(ep, 0);
223
224 /* PIO OUT may RX packets */
225 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
226 && !ep->has_dma
227 && !(ep->bEndpointAddress & USB_DIR_IN)) {
228 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
229 ep->ackwait = 1 + ep->double_buf;
230 }
231
232 spin_unlock_irqrestore(&udc->lock, flags);
233 VDBG("%s enabled\n", _ep->name);
234 return 0;
235 }
236
237 static void nuke(struct omap_ep *, int status);
238
239 static int omap_ep_disable(struct usb_ep *_ep)
240 {
241 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
242 unsigned long flags;
243
244 if (!_ep || !ep->ep.desc) {
245 DBG("%s, %s not enabled\n", __func__,
246 _ep ? ep->ep.name : NULL);
247 return -EINVAL;
248 }
249
250 spin_lock_irqsave(&ep->udc->lock, flags);
251 ep->ep.desc = NULL;
252 nuke(ep, -ESHUTDOWN);
253 ep->ep.maxpacket = ep->maxpacket;
254 ep->has_dma = 0;
255 omap_writew(UDC_SET_HALT, UDC_CTRL);
256 list_del_init(&ep->iso);
257 del_timer(&ep->timer);
258
259 spin_unlock_irqrestore(&ep->udc->lock, flags);
260
261 VDBG("%s disabled\n", _ep->name);
262 return 0;
263 }
264
265 /*-------------------------------------------------------------------------*/
266
267 static struct usb_request *
268 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
269 {
270 struct omap_req *req;
271
272 req = kzalloc(sizeof(*req), gfp_flags);
273 if (!req)
274 return NULL;
275
276 INIT_LIST_HEAD(&req->queue);
277
278 return &req->req;
279 }
280
281 static void
282 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
283 {
284 struct omap_req *req = container_of(_req, struct omap_req, req);
285
286 kfree(req);
287 }
288
289 /*-------------------------------------------------------------------------*/
290
291 static void
292 done(struct omap_ep *ep, struct omap_req *req, int status)
293 {
294 struct omap_udc *udc = ep->udc;
295 unsigned stopped = ep->stopped;
296
297 list_del_init(&req->queue);
298
299 if (req->req.status == -EINPROGRESS)
300 req->req.status = status;
301 else
302 status = req->req.status;
303
304 if (use_dma && ep->has_dma)
305 usb_gadget_unmap_request(&udc->gadget, &req->req,
306 (ep->bEndpointAddress & USB_DIR_IN));
307
308 #ifndef USB_TRACE
309 if (status && status != -ESHUTDOWN)
310 #endif
311 VDBG("complete %s req %p stat %d len %u/%u\n",
312 ep->ep.name, &req->req, status,
313 req->req.actual, req->req.length);
314
315 /* don't modify queue heads during completion callback */
316 ep->stopped = 1;
317 spin_unlock(&ep->udc->lock);
318 usb_gadget_giveback_request(&ep->ep, &req->req);
319 spin_lock(&ep->udc->lock);
320 ep->stopped = stopped;
321 }
322
323 /*-------------------------------------------------------------------------*/
324
325 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
326 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
327
328 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
329 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
330
331 static inline int
332 write_packet(u8 *buf, struct omap_req *req, unsigned max)
333 {
334 unsigned len;
335 u16 *wp;
336
337 len = min(req->req.length - req->req.actual, max);
338 req->req.actual += len;
339
340 max = len;
341 if (likely((((int)buf) & 1) == 0)) {
342 wp = (u16 *)buf;
343 while (max >= 2) {
344 omap_writew(*wp++, UDC_DATA);
345 max -= 2;
346 }
347 buf = (u8 *)wp;
348 }
349 while (max--)
350 omap_writeb(*buf++, UDC_DATA);
351 return len;
352 }
353
354 /* FIXME change r/w fifo calling convention */
355
356
357 /* return: 0 = still running, 1 = completed, negative = errno */
358 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
359 {
360 u8 *buf;
361 unsigned count;
362 int is_last;
363 u16 ep_stat;
364
365 buf = req->req.buf + req->req.actual;
366 prefetch(buf);
367
368 /* PIO-IN isn't double buffered except for iso */
369 ep_stat = omap_readw(UDC_STAT_FLG);
370 if (ep_stat & UDC_FIFO_UNWRITABLE)
371 return 0;
372
373 count = ep->ep.maxpacket;
374 count = write_packet(buf, req, count);
375 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
376 ep->ackwait = 1;
377
378 /* last packet is often short (sometimes a zlp) */
379 if (count != ep->ep.maxpacket)
380 is_last = 1;
381 else if (req->req.length == req->req.actual
382 && !req->req.zero)
383 is_last = 1;
384 else
385 is_last = 0;
386
387 /* NOTE: requests complete when all IN data is in a
388 * FIFO (or sometimes later, if a zlp was needed).
389 * Use usb_ep_fifo_status() where needed.
390 */
391 if (is_last)
392 done(ep, req, 0);
393 return is_last;
394 }
395
396 static inline int
397 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
398 {
399 unsigned len;
400 u16 *wp;
401
402 len = min(req->req.length - req->req.actual, avail);
403 req->req.actual += len;
404 avail = len;
405
406 if (likely((((int)buf) & 1) == 0)) {
407 wp = (u16 *)buf;
408 while (avail >= 2) {
409 *wp++ = omap_readw(UDC_DATA);
410 avail -= 2;
411 }
412 buf = (u8 *)wp;
413 }
414 while (avail--)
415 *buf++ = omap_readb(UDC_DATA);
416 return len;
417 }
418
419 /* return: 0 = still running, 1 = queue empty, negative = errno */
420 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
421 {
422 u8 *buf;
423 unsigned count, avail;
424 int is_last;
425
426 buf = req->req.buf + req->req.actual;
427 prefetchw(buf);
428
429 for (;;) {
430 u16 ep_stat = omap_readw(UDC_STAT_FLG);
431
432 is_last = 0;
433 if (ep_stat & FIFO_EMPTY) {
434 if (!ep->double_buf)
435 break;
436 ep->fnf = 1;
437 }
438 if (ep_stat & UDC_EP_HALTED)
439 break;
440
441 if (ep_stat & UDC_FIFO_FULL)
442 avail = ep->ep.maxpacket;
443 else {
444 avail = omap_readw(UDC_RXFSTAT);
445 ep->fnf = ep->double_buf;
446 }
447 count = read_packet(buf, req, avail);
448
449 /* partial packet reads may not be errors */
450 if (count < ep->ep.maxpacket) {
451 is_last = 1;
452 /* overflowed this request? flush extra data */
453 if (count != avail) {
454 req->req.status = -EOVERFLOW;
455 avail -= count;
456 while (avail--)
457 omap_readw(UDC_DATA);
458 }
459 } else if (req->req.length == req->req.actual)
460 is_last = 1;
461 else
462 is_last = 0;
463
464 if (!ep->bEndpointAddress)
465 break;
466 if (is_last)
467 done(ep, req, 0);
468 break;
469 }
470 return is_last;
471 }
472
473 /*-------------------------------------------------------------------------*/
474
475 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
476 {
477 dma_addr_t end;
478
479 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
480 * the last transfer's bytecount by more than a FIFO's worth.
481 */
482 if (cpu_is_omap15xx())
483 return 0;
484
485 end = omap_get_dma_src_pos(ep->lch);
486 if (end == ep->dma_counter)
487 return 0;
488
489 end |= start & (0xffff << 16);
490 if (end < start)
491 end += 0x10000;
492 return end - start;
493 }
494
495 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
496 {
497 dma_addr_t end;
498
499 end = omap_get_dma_dst_pos(ep->lch);
500 if (end == ep->dma_counter)
501 return 0;
502
503 end |= start & (0xffff << 16);
504 if (cpu_is_omap15xx())
505 end++;
506 if (end < start)
507 end += 0x10000;
508 return end - start;
509 }
510
511
512 /* Each USB transfer request using DMA maps to one or more DMA transfers.
513 * When DMA completion isn't request completion, the UDC continues with
514 * the next DMA transfer for that USB transfer.
515 */
516
517 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
518 {
519 u16 txdma_ctrl, w;
520 unsigned length = req->req.length - req->req.actual;
521 const int sync_mode = cpu_is_omap15xx()
522 ? OMAP_DMA_SYNC_FRAME
523 : OMAP_DMA_SYNC_ELEMENT;
524 int dma_trigger = 0;
525
526 /* measure length in either bytes or packets */
527 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
528 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
529 txdma_ctrl = UDC_TXN_EOT | length;
530 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
531 length, 1, sync_mode, dma_trigger, 0);
532 } else {
533 length = min(length / ep->maxpacket,
534 (unsigned) UDC_TXN_TSC + 1);
535 txdma_ctrl = length;
536 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
537 ep->ep.maxpacket >> 1, length, sync_mode,
538 dma_trigger, 0);
539 length *= ep->maxpacket;
540 }
541 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
542 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
543 0, 0);
544
545 omap_start_dma(ep->lch);
546 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
547 w = omap_readw(UDC_DMA_IRQ_EN);
548 w |= UDC_TX_DONE_IE(ep->dma_channel);
549 omap_writew(w, UDC_DMA_IRQ_EN);
550 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
551 req->dma_bytes = length;
552 }
553
554 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
555 {
556 u16 w;
557
558 if (status == 0) {
559 req->req.actual += req->dma_bytes;
560
561 /* return if this request needs to send data or zlp */
562 if (req->req.actual < req->req.length)
563 return;
564 if (req->req.zero
565 && req->dma_bytes != 0
566 && (req->req.actual % ep->maxpacket) == 0)
567 return;
568 } else
569 req->req.actual += dma_src_len(ep, req->req.dma
570 + req->req.actual);
571
572 /* tx completion */
573 omap_stop_dma(ep->lch);
574 w = omap_readw(UDC_DMA_IRQ_EN);
575 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
576 omap_writew(w, UDC_DMA_IRQ_EN);
577 done(ep, req, status);
578 }
579
580 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
581 {
582 unsigned packets = req->req.length - req->req.actual;
583 int dma_trigger = 0;
584 u16 w;
585
586 /* set up this DMA transfer, enable the fifo, start */
587 packets /= ep->ep.maxpacket;
588 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
589 req->dma_bytes = packets * ep->ep.maxpacket;
590 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
591 ep->ep.maxpacket >> 1, packets,
592 OMAP_DMA_SYNC_ELEMENT,
593 dma_trigger, 0);
594 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
595 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
596 0, 0);
597 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
598
599 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
600 w = omap_readw(UDC_DMA_IRQ_EN);
601 w |= UDC_RX_EOT_IE(ep->dma_channel);
602 omap_writew(w, UDC_DMA_IRQ_EN);
603 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
604 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
605
606 omap_start_dma(ep->lch);
607 }
608
609 static void
610 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
611 {
612 u16 count, w;
613
614 if (status == 0)
615 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
616 count = dma_dest_len(ep, req->req.dma + req->req.actual);
617 count += req->req.actual;
618 if (one)
619 count--;
620 if (count <= req->req.length)
621 req->req.actual = count;
622
623 if (count != req->dma_bytes || status)
624 omap_stop_dma(ep->lch);
625
626 /* if this wasn't short, request may need another transfer */
627 else if (req->req.actual < req->req.length)
628 return;
629
630 /* rx completion */
631 w = omap_readw(UDC_DMA_IRQ_EN);
632 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
633 omap_writew(w, UDC_DMA_IRQ_EN);
634 done(ep, req, status);
635 }
636
637 static void dma_irq(struct omap_udc *udc, u16 irq_src)
638 {
639 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
640 struct omap_ep *ep;
641 struct omap_req *req;
642
643 /* IN dma: tx to host */
644 if (irq_src & UDC_TXN_DONE) {
645 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
646 ep->irqs++;
647 /* can see TXN_DONE after dma abort */
648 if (!list_empty(&ep->queue)) {
649 req = container_of(ep->queue.next,
650 struct omap_req, queue);
651 finish_in_dma(ep, req, 0);
652 }
653 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
654
655 if (!list_empty(&ep->queue)) {
656 req = container_of(ep->queue.next,
657 struct omap_req, queue);
658 next_in_dma(ep, req);
659 }
660 }
661
662 /* OUT dma: rx from host */
663 if (irq_src & UDC_RXN_EOT) {
664 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
665 ep->irqs++;
666 /* can see RXN_EOT after dma abort */
667 if (!list_empty(&ep->queue)) {
668 req = container_of(ep->queue.next,
669 struct omap_req, queue);
670 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
671 }
672 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
673
674 if (!list_empty(&ep->queue)) {
675 req = container_of(ep->queue.next,
676 struct omap_req, queue);
677 next_out_dma(ep, req);
678 }
679 }
680
681 if (irq_src & UDC_RXN_CNT) {
682 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
683 ep->irqs++;
684 /* omap15xx does this unasked... */
685 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
686 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
687 }
688 }
689
690 static void dma_error(int lch, u16 ch_status, void *data)
691 {
692 struct omap_ep *ep = data;
693
694 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
695 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
696 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
697
698 /* complete current transfer ... */
699 }
700
701 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
702 {
703 u16 reg;
704 int status, restart, is_in;
705 int dma_channel;
706
707 is_in = ep->bEndpointAddress & USB_DIR_IN;
708 if (is_in)
709 reg = omap_readw(UDC_TXDMA_CFG);
710 else
711 reg = omap_readw(UDC_RXDMA_CFG);
712 reg |= UDC_DMA_REQ; /* "pulse" activated */
713
714 ep->dma_channel = 0;
715 ep->lch = -1;
716 if (channel == 0 || channel > 3) {
717 if ((reg & 0x0f00) == 0)
718 channel = 3;
719 else if ((reg & 0x00f0) == 0)
720 channel = 2;
721 else if ((reg & 0x000f) == 0) /* preferred for ISO */
722 channel = 1;
723 else {
724 status = -EMLINK;
725 goto just_restart;
726 }
727 }
728 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
729 ep->dma_channel = channel;
730
731 if (is_in) {
732 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
733 status = omap_request_dma(dma_channel,
734 ep->ep.name, dma_error, ep, &ep->lch);
735 if (status == 0) {
736 omap_writew(reg, UDC_TXDMA_CFG);
737 /* EMIFF or SDRC */
738 omap_set_dma_src_burst_mode(ep->lch,
739 OMAP_DMA_DATA_BURST_4);
740 omap_set_dma_src_data_pack(ep->lch, 1);
741 /* TIPB */
742 omap_set_dma_dest_params(ep->lch,
743 OMAP_DMA_PORT_TIPB,
744 OMAP_DMA_AMODE_CONSTANT,
745 UDC_DATA_DMA,
746 0, 0);
747 }
748 } else {
749 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
750 status = omap_request_dma(dma_channel,
751 ep->ep.name, dma_error, ep, &ep->lch);
752 if (status == 0) {
753 omap_writew(reg, UDC_RXDMA_CFG);
754 /* TIPB */
755 omap_set_dma_src_params(ep->lch,
756 OMAP_DMA_PORT_TIPB,
757 OMAP_DMA_AMODE_CONSTANT,
758 UDC_DATA_DMA,
759 0, 0);
760 /* EMIFF or SDRC */
761 omap_set_dma_dest_burst_mode(ep->lch,
762 OMAP_DMA_DATA_BURST_4);
763 omap_set_dma_dest_data_pack(ep->lch, 1);
764 }
765 }
766 if (status)
767 ep->dma_channel = 0;
768 else {
769 ep->has_dma = 1;
770 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
771
772 /* channel type P: hw synch (fifo) */
773 if (!cpu_is_omap15xx())
774 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
775 }
776
777 just_restart:
778 /* restart any queue, even if the claim failed */
779 restart = !ep->stopped && !list_empty(&ep->queue);
780
781 if (status)
782 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
783 restart ? " (restart)" : "");
784 else
785 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
786 is_in ? 't' : 'r',
787 ep->dma_channel - 1, ep->lch,
788 restart ? " (restart)" : "");
789
790 if (restart) {
791 struct omap_req *req;
792 req = container_of(ep->queue.next, struct omap_req, queue);
793 if (ep->has_dma)
794 (is_in ? next_in_dma : next_out_dma)(ep, req);
795 else {
796 use_ep(ep, UDC_EP_SEL);
797 (is_in ? write_fifo : read_fifo)(ep, req);
798 deselect_ep();
799 if (!is_in) {
800 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
801 ep->ackwait = 1 + ep->double_buf;
802 }
803 /* IN: 6 wait states before it'll tx */
804 }
805 }
806 }
807
808 static void dma_channel_release(struct omap_ep *ep)
809 {
810 int shift = 4 * (ep->dma_channel - 1);
811 u16 mask = 0x0f << shift;
812 struct omap_req *req;
813 int active;
814
815 /* abort any active usb transfer request */
816 if (!list_empty(&ep->queue))
817 req = container_of(ep->queue.next, struct omap_req, queue);
818 else
819 req = NULL;
820
821 active = omap_get_dma_active_status(ep->lch);
822
823 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
824 active ? "active" : "idle",
825 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
826 ep->dma_channel - 1, req);
827
828 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
829 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
830 */
831
832 /* wait till current packet DMA finishes, and fifo empties */
833 if (ep->bEndpointAddress & USB_DIR_IN) {
834 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
835 UDC_TXDMA_CFG);
836
837 if (req) {
838 finish_in_dma(ep, req, -ECONNRESET);
839
840 /* clear FIFO; hosts probably won't empty it */
841 use_ep(ep, UDC_EP_SEL);
842 omap_writew(UDC_CLR_EP, UDC_CTRL);
843 deselect_ep();
844 }
845 while (omap_readw(UDC_TXDMA_CFG) & mask)
846 udelay(10);
847 } else {
848 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
849 UDC_RXDMA_CFG);
850
851 /* dma empties the fifo */
852 while (omap_readw(UDC_RXDMA_CFG) & mask)
853 udelay(10);
854 if (req)
855 finish_out_dma(ep, req, -ECONNRESET, 0);
856 }
857 omap_free_dma(ep->lch);
858 ep->dma_channel = 0;
859 ep->lch = -1;
860 /* has_dma still set, till endpoint is fully quiesced */
861 }
862
863
864 /*-------------------------------------------------------------------------*/
865
866 static int
867 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
868 {
869 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
870 struct omap_req *req = container_of(_req, struct omap_req, req);
871 struct omap_udc *udc;
872 unsigned long flags;
873 int is_iso = 0;
874
875 /* catch various bogus parameters */
876 if (!_req || !req->req.complete || !req->req.buf
877 || !list_empty(&req->queue)) {
878 DBG("%s, bad params\n", __func__);
879 return -EINVAL;
880 }
881 if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
882 DBG("%s, bad ep\n", __func__);
883 return -EINVAL;
884 }
885 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
886 if (req->req.length > ep->ep.maxpacket)
887 return -EMSGSIZE;
888 is_iso = 1;
889 }
890
891 /* this isn't bogus, but OMAP DMA isn't the only hardware to
892 * have a hard time with partial packet reads... reject it.
893 */
894 if (use_dma
895 && ep->has_dma
896 && ep->bEndpointAddress != 0
897 && (ep->bEndpointAddress & USB_DIR_IN) == 0
898 && (req->req.length % ep->ep.maxpacket) != 0) {
899 DBG("%s, no partial packet OUT reads\n", __func__);
900 return -EMSGSIZE;
901 }
902
903 udc = ep->udc;
904 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
905 return -ESHUTDOWN;
906
907 if (use_dma && ep->has_dma)
908 usb_gadget_map_request(&udc->gadget, &req->req,
909 (ep->bEndpointAddress & USB_DIR_IN));
910
911 VDBG("%s queue req %p, len %d buf %p\n",
912 ep->ep.name, _req, _req->length, _req->buf);
913
914 spin_lock_irqsave(&udc->lock, flags);
915
916 req->req.status = -EINPROGRESS;
917 req->req.actual = 0;
918
919 /* maybe kickstart non-iso i/o queues */
920 if (is_iso) {
921 u16 w;
922
923 w = omap_readw(UDC_IRQ_EN);
924 w |= UDC_SOF_IE;
925 omap_writew(w, UDC_IRQ_EN);
926 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
927 int is_in;
928
929 if (ep->bEndpointAddress == 0) {
930 if (!udc->ep0_pending || !list_empty(&ep->queue)) {
931 spin_unlock_irqrestore(&udc->lock, flags);
932 return -EL2HLT;
933 }
934
935 /* empty DATA stage? */
936 is_in = udc->ep0_in;
937 if (!req->req.length) {
938
939 /* chip became CONFIGURED or ADDRESSED
940 * earlier; drivers may already have queued
941 * requests to non-control endpoints
942 */
943 if (udc->ep0_set_config) {
944 u16 irq_en = omap_readw(UDC_IRQ_EN);
945
946 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
947 if (!udc->ep0_reset_config)
948 irq_en |= UDC_EPN_RX_IE
949 | UDC_EPN_TX_IE;
950 omap_writew(irq_en, UDC_IRQ_EN);
951 }
952
953 /* STATUS for zero length DATA stages is
954 * always an IN ... even for IN transfers,
955 * a weird case which seem to stall OMAP.
956 */
957 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
958 UDC_EP_NUM);
959 omap_writew(UDC_CLR_EP, UDC_CTRL);
960 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
961 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
962
963 /* cleanup */
964 udc->ep0_pending = 0;
965 done(ep, req, 0);
966 req = NULL;
967
968 /* non-empty DATA stage */
969 } else if (is_in) {
970 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
971 UDC_EP_NUM);
972 } else {
973 if (udc->ep0_setup)
974 goto irq_wait;
975 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
976 }
977 } else {
978 is_in = ep->bEndpointAddress & USB_DIR_IN;
979 if (!ep->has_dma)
980 use_ep(ep, UDC_EP_SEL);
981 /* if ISO: SOF IRQs must be enabled/disabled! */
982 }
983
984 if (ep->has_dma)
985 (is_in ? next_in_dma : next_out_dma)(ep, req);
986 else if (req) {
987 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
988 req = NULL;
989 deselect_ep();
990 if (!is_in) {
991 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
992 ep->ackwait = 1 + ep->double_buf;
993 }
994 /* IN: 6 wait states before it'll tx */
995 }
996 }
997
998 irq_wait:
999 /* irq handler advances the queue */
1000 if (req != NULL)
1001 list_add_tail(&req->queue, &ep->queue);
1002 spin_unlock_irqrestore(&udc->lock, flags);
1003
1004 return 0;
1005 }
1006
1007 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1008 {
1009 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1010 struct omap_req *req;
1011 unsigned long flags;
1012
1013 if (!_ep || !_req)
1014 return -EINVAL;
1015
1016 spin_lock_irqsave(&ep->udc->lock, flags);
1017
1018 /* make sure it's actually queued on this endpoint */
1019 list_for_each_entry(req, &ep->queue, queue) {
1020 if (&req->req == _req)
1021 break;
1022 }
1023 if (&req->req != _req) {
1024 spin_unlock_irqrestore(&ep->udc->lock, flags);
1025 return -EINVAL;
1026 }
1027
1028 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1029 int channel = ep->dma_channel;
1030
1031 /* releasing the channel cancels the request,
1032 * reclaiming the channel restarts the queue
1033 */
1034 dma_channel_release(ep);
1035 dma_channel_claim(ep, channel);
1036 } else
1037 done(ep, req, -ECONNRESET);
1038 spin_unlock_irqrestore(&ep->udc->lock, flags);
1039 return 0;
1040 }
1041
1042 /*-------------------------------------------------------------------------*/
1043
1044 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1045 {
1046 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1047 unsigned long flags;
1048 int status = -EOPNOTSUPP;
1049
1050 spin_lock_irqsave(&ep->udc->lock, flags);
1051
1052 /* just use protocol stalls for ep0; real halts are annoying */
1053 if (ep->bEndpointAddress == 0) {
1054 if (!ep->udc->ep0_pending)
1055 status = -EINVAL;
1056 else if (value) {
1057 if (ep->udc->ep0_set_config) {
1058 WARNING("error changing config?\n");
1059 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1060 }
1061 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1062 ep->udc->ep0_pending = 0;
1063 status = 0;
1064 } else /* NOP */
1065 status = 0;
1066
1067 /* otherwise, all active non-ISO endpoints can halt */
1068 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1069
1070 /* IN endpoints must already be idle */
1071 if ((ep->bEndpointAddress & USB_DIR_IN)
1072 && !list_empty(&ep->queue)) {
1073 status = -EAGAIN;
1074 goto done;
1075 }
1076
1077 if (value) {
1078 int channel;
1079
1080 if (use_dma && ep->dma_channel
1081 && !list_empty(&ep->queue)) {
1082 channel = ep->dma_channel;
1083 dma_channel_release(ep);
1084 } else
1085 channel = 0;
1086
1087 use_ep(ep, UDC_EP_SEL);
1088 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1089 omap_writew(UDC_SET_HALT, UDC_CTRL);
1090 status = 0;
1091 } else
1092 status = -EAGAIN;
1093 deselect_ep();
1094
1095 if (channel)
1096 dma_channel_claim(ep, channel);
1097 } else {
1098 use_ep(ep, 0);
1099 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1100 ep->ackwait = 0;
1101 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1102 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1103 ep->ackwait = 1 + ep->double_buf;
1104 }
1105 }
1106 }
1107 done:
1108 VDBG("%s %s halt stat %d\n", ep->ep.name,
1109 value ? "set" : "clear", status);
1110
1111 spin_unlock_irqrestore(&ep->udc->lock, flags);
1112 return status;
1113 }
1114
1115 static struct usb_ep_ops omap_ep_ops = {
1116 .enable = omap_ep_enable,
1117 .disable = omap_ep_disable,
1118
1119 .alloc_request = omap_alloc_request,
1120 .free_request = omap_free_request,
1121
1122 .queue = omap_ep_queue,
1123 .dequeue = omap_ep_dequeue,
1124
1125 .set_halt = omap_ep_set_halt,
1126 /* fifo_status ... report bytes in fifo */
1127 /* fifo_flush ... flush fifo */
1128 };
1129
1130 /*-------------------------------------------------------------------------*/
1131
1132 static int omap_get_frame(struct usb_gadget *gadget)
1133 {
1134 u16 sof = omap_readw(UDC_SOF);
1135 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1136 }
1137
1138 static int omap_wakeup(struct usb_gadget *gadget)
1139 {
1140 struct omap_udc *udc;
1141 unsigned long flags;
1142 int retval = -EHOSTUNREACH;
1143
1144 udc = container_of(gadget, struct omap_udc, gadget);
1145
1146 spin_lock_irqsave(&udc->lock, flags);
1147 if (udc->devstat & UDC_SUS) {
1148 /* NOTE: OTG spec erratum says that OTG devices may
1149 * issue wakeups without host enable.
1150 */
1151 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1152 DBG("remote wakeup...\n");
1153 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1154 retval = 0;
1155 }
1156
1157 /* NOTE: non-OTG systems may use SRP TOO... */
1158 } else if (!(udc->devstat & UDC_ATT)) {
1159 if (!IS_ERR_OR_NULL(udc->transceiver))
1160 retval = otg_start_srp(udc->transceiver->otg);
1161 }
1162 spin_unlock_irqrestore(&udc->lock, flags);
1163
1164 return retval;
1165 }
1166
1167 static int
1168 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1169 {
1170 struct omap_udc *udc;
1171 unsigned long flags;
1172 u16 syscon1;
1173
1174 gadget->is_selfpowered = (is_selfpowered != 0);
1175 udc = container_of(gadget, struct omap_udc, gadget);
1176 spin_lock_irqsave(&udc->lock, flags);
1177 syscon1 = omap_readw(UDC_SYSCON1);
1178 if (is_selfpowered)
1179 syscon1 |= UDC_SELF_PWR;
1180 else
1181 syscon1 &= ~UDC_SELF_PWR;
1182 omap_writew(syscon1, UDC_SYSCON1);
1183 spin_unlock_irqrestore(&udc->lock, flags);
1184
1185 return 0;
1186 }
1187
1188 static int can_pullup(struct omap_udc *udc)
1189 {
1190 return udc->driver && udc->softconnect && udc->vbus_active;
1191 }
1192
1193 static void pullup_enable(struct omap_udc *udc)
1194 {
1195 u16 w;
1196
1197 w = omap_readw(UDC_SYSCON1);
1198 w |= UDC_PULLUP_EN;
1199 omap_writew(w, UDC_SYSCON1);
1200 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1201 u32 l;
1202
1203 l = omap_readl(OTG_CTRL);
1204 l |= OTG_BSESSVLD;
1205 omap_writel(l, OTG_CTRL);
1206 }
1207 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1208 }
1209
1210 static void pullup_disable(struct omap_udc *udc)
1211 {
1212 u16 w;
1213
1214 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1215 u32 l;
1216
1217 l = omap_readl(OTG_CTRL);
1218 l &= ~OTG_BSESSVLD;
1219 omap_writel(l, OTG_CTRL);
1220 }
1221 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1222 w = omap_readw(UDC_SYSCON1);
1223 w &= ~UDC_PULLUP_EN;
1224 omap_writew(w, UDC_SYSCON1);
1225 }
1226
1227 static struct omap_udc *udc;
1228
1229 static void omap_udc_enable_clock(int enable)
1230 {
1231 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1232 return;
1233
1234 if (enable) {
1235 clk_enable(udc->dc_clk);
1236 clk_enable(udc->hhc_clk);
1237 udelay(100);
1238 } else {
1239 clk_disable(udc->hhc_clk);
1240 clk_disable(udc->dc_clk);
1241 }
1242 }
1243
1244 /*
1245 * Called by whatever detects VBUS sessions: external transceiver
1246 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1247 */
1248 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1249 {
1250 struct omap_udc *udc;
1251 unsigned long flags;
1252 u32 l;
1253
1254 udc = container_of(gadget, struct omap_udc, gadget);
1255 spin_lock_irqsave(&udc->lock, flags);
1256 VDBG("VBUS %s\n", is_active ? "on" : "off");
1257 udc->vbus_active = (is_active != 0);
1258 if (cpu_is_omap15xx()) {
1259 /* "software" detect, ignored if !VBUS_MODE_1510 */
1260 l = omap_readl(FUNC_MUX_CTRL_0);
1261 if (is_active)
1262 l |= VBUS_CTRL_1510;
1263 else
1264 l &= ~VBUS_CTRL_1510;
1265 omap_writel(l, FUNC_MUX_CTRL_0);
1266 }
1267 if (udc->dc_clk != NULL && is_active) {
1268 if (!udc->clk_requested) {
1269 omap_udc_enable_clock(1);
1270 udc->clk_requested = 1;
1271 }
1272 }
1273 if (can_pullup(udc))
1274 pullup_enable(udc);
1275 else
1276 pullup_disable(udc);
1277 if (udc->dc_clk != NULL && !is_active) {
1278 if (udc->clk_requested) {
1279 omap_udc_enable_clock(0);
1280 udc->clk_requested = 0;
1281 }
1282 }
1283 spin_unlock_irqrestore(&udc->lock, flags);
1284 return 0;
1285 }
1286
1287 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1288 {
1289 struct omap_udc *udc;
1290
1291 udc = container_of(gadget, struct omap_udc, gadget);
1292 if (!IS_ERR_OR_NULL(udc->transceiver))
1293 return usb_phy_set_power(udc->transceiver, mA);
1294 return -EOPNOTSUPP;
1295 }
1296
1297 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1298 {
1299 struct omap_udc *udc;
1300 unsigned long flags;
1301
1302 udc = container_of(gadget, struct omap_udc, gadget);
1303 spin_lock_irqsave(&udc->lock, flags);
1304 udc->softconnect = (is_on != 0);
1305 if (can_pullup(udc))
1306 pullup_enable(udc);
1307 else
1308 pullup_disable(udc);
1309 spin_unlock_irqrestore(&udc->lock, flags);
1310 return 0;
1311 }
1312
1313 static int omap_udc_start(struct usb_gadget *g,
1314 struct usb_gadget_driver *driver);
1315 static int omap_udc_stop(struct usb_gadget *g);
1316
1317 static const struct usb_gadget_ops omap_gadget_ops = {
1318 .get_frame = omap_get_frame,
1319 .wakeup = omap_wakeup,
1320 .set_selfpowered = omap_set_selfpowered,
1321 .vbus_session = omap_vbus_session,
1322 .vbus_draw = omap_vbus_draw,
1323 .pullup = omap_pullup,
1324 .udc_start = omap_udc_start,
1325 .udc_stop = omap_udc_stop,
1326 };
1327
1328 /*-------------------------------------------------------------------------*/
1329
1330 /* dequeue ALL requests; caller holds udc->lock */
1331 static void nuke(struct omap_ep *ep, int status)
1332 {
1333 struct omap_req *req;
1334
1335 ep->stopped = 1;
1336
1337 if (use_dma && ep->dma_channel)
1338 dma_channel_release(ep);
1339
1340 use_ep(ep, 0);
1341 omap_writew(UDC_CLR_EP, UDC_CTRL);
1342 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1343 omap_writew(UDC_SET_HALT, UDC_CTRL);
1344
1345 while (!list_empty(&ep->queue)) {
1346 req = list_entry(ep->queue.next, struct omap_req, queue);
1347 done(ep, req, status);
1348 }
1349 }
1350
1351 /* caller holds udc->lock */
1352 static void udc_quiesce(struct omap_udc *udc)
1353 {
1354 struct omap_ep *ep;
1355
1356 udc->gadget.speed = USB_SPEED_UNKNOWN;
1357 nuke(&udc->ep[0], -ESHUTDOWN);
1358 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1359 nuke(ep, -ESHUTDOWN);
1360 }
1361
1362 /*-------------------------------------------------------------------------*/
1363
1364 static void update_otg(struct omap_udc *udc)
1365 {
1366 u16 devstat;
1367
1368 if (!gadget_is_otg(&udc->gadget))
1369 return;
1370
1371 if (omap_readl(OTG_CTRL) & OTG_ID)
1372 devstat = omap_readw(UDC_DEVSTAT);
1373 else
1374 devstat = 0;
1375
1376 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1377 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1378 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1379
1380 /* Enable HNP early, avoiding races on suspend irq path.
1381 * ASSUMES OTG state machine B_BUS_REQ input is true.
1382 */
1383 if (udc->gadget.b_hnp_enable) {
1384 u32 l;
1385
1386 l = omap_readl(OTG_CTRL);
1387 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1388 l &= ~OTG_PULLUP;
1389 omap_writel(l, OTG_CTRL);
1390 }
1391 }
1392
1393 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1394 {
1395 struct omap_ep *ep0 = &udc->ep[0];
1396 struct omap_req *req = NULL;
1397
1398 ep0->irqs++;
1399
1400 /* Clear any pending requests and then scrub any rx/tx state
1401 * before starting to handle the SETUP request.
1402 */
1403 if (irq_src & UDC_SETUP) {
1404 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1405
1406 nuke(ep0, 0);
1407 if (ack) {
1408 omap_writew(ack, UDC_IRQ_SRC);
1409 irq_src = UDC_SETUP;
1410 }
1411 }
1412
1413 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1414 * This driver uses only uses protocol stalls (ep0 never halts),
1415 * and if we got this far the gadget driver already had a
1416 * chance to stall. Tries to be forgiving of host oddities.
1417 *
1418 * NOTE: the last chance gadget drivers have to stall control
1419 * requests is during their request completion callback.
1420 */
1421 if (!list_empty(&ep0->queue))
1422 req = container_of(ep0->queue.next, struct omap_req, queue);
1423
1424 /* IN == TX to host */
1425 if (irq_src & UDC_EP0_TX) {
1426 int stat;
1427
1428 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1429 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1430 stat = omap_readw(UDC_STAT_FLG);
1431 if (stat & UDC_ACK) {
1432 if (udc->ep0_in) {
1433 /* write next IN packet from response,
1434 * or set up the status stage.
1435 */
1436 if (req)
1437 stat = write_fifo(ep0, req);
1438 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1439 if (!req && udc->ep0_pending) {
1440 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1441 omap_writew(UDC_CLR_EP, UDC_CTRL);
1442 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1443 omap_writew(0, UDC_EP_NUM);
1444 udc->ep0_pending = 0;
1445 } /* else: 6 wait states before it'll tx */
1446 } else {
1447 /* ack status stage of OUT transfer */
1448 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1449 if (req)
1450 done(ep0, req, 0);
1451 }
1452 req = NULL;
1453 } else if (stat & UDC_STALL) {
1454 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1455 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1456 } else {
1457 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1458 }
1459 }
1460
1461 /* OUT == RX from host */
1462 if (irq_src & UDC_EP0_RX) {
1463 int stat;
1464
1465 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1466 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1467 stat = omap_readw(UDC_STAT_FLG);
1468 if (stat & UDC_ACK) {
1469 if (!udc->ep0_in) {
1470 stat = 0;
1471 /* read next OUT packet of request, maybe
1472 * reactiviting the fifo; stall on errors.
1473 */
1474 stat = read_fifo(ep0, req);
1475 if (!req || stat < 0) {
1476 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1477 udc->ep0_pending = 0;
1478 stat = 0;
1479 } else if (stat == 0)
1480 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1481 omap_writew(0, UDC_EP_NUM);
1482
1483 /* activate status stage */
1484 if (stat == 1) {
1485 done(ep0, req, 0);
1486 /* that may have STALLed ep0... */
1487 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1488 UDC_EP_NUM);
1489 omap_writew(UDC_CLR_EP, UDC_CTRL);
1490 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1491 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1492 udc->ep0_pending = 0;
1493 }
1494 } else {
1495 /* ack status stage of IN transfer */
1496 omap_writew(0, UDC_EP_NUM);
1497 if (req)
1498 done(ep0, req, 0);
1499 }
1500 } else if (stat & UDC_STALL) {
1501 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1502 omap_writew(0, UDC_EP_NUM);
1503 } else {
1504 omap_writew(0, UDC_EP_NUM);
1505 }
1506 }
1507
1508 /* SETUP starts all control transfers */
1509 if (irq_src & UDC_SETUP) {
1510 union u {
1511 u16 word[4];
1512 struct usb_ctrlrequest r;
1513 } u;
1514 int status = -EINVAL;
1515 struct omap_ep *ep;
1516
1517 /* read the (latest) SETUP message */
1518 do {
1519 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1520 /* two bytes at a time */
1521 u.word[0] = omap_readw(UDC_DATA);
1522 u.word[1] = omap_readw(UDC_DATA);
1523 u.word[2] = omap_readw(UDC_DATA);
1524 u.word[3] = omap_readw(UDC_DATA);
1525 omap_writew(0, UDC_EP_NUM);
1526 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1527
1528 #define w_value le16_to_cpu(u.r.wValue)
1529 #define w_index le16_to_cpu(u.r.wIndex)
1530 #define w_length le16_to_cpu(u.r.wLength)
1531
1532 /* Delegate almost all control requests to the gadget driver,
1533 * except for a handful of ch9 status/feature requests that
1534 * hardware doesn't autodecode _and_ the gadget API hides.
1535 */
1536 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1537 udc->ep0_set_config = 0;
1538 udc->ep0_pending = 1;
1539 ep0->stopped = 0;
1540 ep0->ackwait = 0;
1541 switch (u.r.bRequest) {
1542 case USB_REQ_SET_CONFIGURATION:
1543 /* udc needs to know when ep != 0 is valid */
1544 if (u.r.bRequestType != USB_RECIP_DEVICE)
1545 goto delegate;
1546 if (w_length != 0)
1547 goto do_stall;
1548 udc->ep0_set_config = 1;
1549 udc->ep0_reset_config = (w_value == 0);
1550 VDBG("set config %d\n", w_value);
1551
1552 /* update udc NOW since gadget driver may start
1553 * queueing requests immediately; clear config
1554 * later if it fails the request.
1555 */
1556 if (udc->ep0_reset_config)
1557 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1558 else
1559 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1560 update_otg(udc);
1561 goto delegate;
1562 case USB_REQ_CLEAR_FEATURE:
1563 /* clear endpoint halt */
1564 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1565 goto delegate;
1566 if (w_value != USB_ENDPOINT_HALT
1567 || w_length != 0)
1568 goto do_stall;
1569 ep = &udc->ep[w_index & 0xf];
1570 if (ep != ep0) {
1571 if (w_index & USB_DIR_IN)
1572 ep += 16;
1573 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1574 || !ep->ep.desc)
1575 goto do_stall;
1576 use_ep(ep, 0);
1577 omap_writew(udc->clr_halt, UDC_CTRL);
1578 ep->ackwait = 0;
1579 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1580 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1581 ep->ackwait = 1 + ep->double_buf;
1582 }
1583 /* NOTE: assumes the host behaves sanely,
1584 * only clearing real halts. Else we may
1585 * need to kill pending transfers and then
1586 * restart the queue... very messy for DMA!
1587 */
1588 }
1589 VDBG("%s halt cleared by host\n", ep->name);
1590 goto ep0out_status_stage;
1591 case USB_REQ_SET_FEATURE:
1592 /* set endpoint halt */
1593 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1594 goto delegate;
1595 if (w_value != USB_ENDPOINT_HALT
1596 || w_length != 0)
1597 goto do_stall;
1598 ep = &udc->ep[w_index & 0xf];
1599 if (w_index & USB_DIR_IN)
1600 ep += 16;
1601 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1602 || ep == ep0 || !ep->ep.desc)
1603 goto do_stall;
1604 if (use_dma && ep->has_dma) {
1605 /* this has rude side-effects (aborts) and
1606 * can't really work if DMA-IN is active
1607 */
1608 DBG("%s host set_halt, NYET\n", ep->name);
1609 goto do_stall;
1610 }
1611 use_ep(ep, 0);
1612 /* can't halt if fifo isn't empty... */
1613 omap_writew(UDC_CLR_EP, UDC_CTRL);
1614 omap_writew(UDC_SET_HALT, UDC_CTRL);
1615 VDBG("%s halted by host\n", ep->name);
1616 ep0out_status_stage:
1617 status = 0;
1618 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1619 omap_writew(UDC_CLR_EP, UDC_CTRL);
1620 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1621 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1622 udc->ep0_pending = 0;
1623 break;
1624 case USB_REQ_GET_STATUS:
1625 /* USB_ENDPOINT_HALT status? */
1626 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1627 goto intf_status;
1628
1629 /* ep0 never stalls */
1630 if (!(w_index & 0xf))
1631 goto zero_status;
1632
1633 /* only active endpoints count */
1634 ep = &udc->ep[w_index & 0xf];
1635 if (w_index & USB_DIR_IN)
1636 ep += 16;
1637 if (!ep->ep.desc)
1638 goto do_stall;
1639
1640 /* iso never stalls */
1641 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1642 goto zero_status;
1643
1644 /* FIXME don't assume non-halted endpoints!! */
1645 ERR("%s status, can't report\n", ep->ep.name);
1646 goto do_stall;
1647
1648 intf_status:
1649 /* return interface status. if we were pedantic,
1650 * we'd detect non-existent interfaces, and stall.
1651 */
1652 if (u.r.bRequestType
1653 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1654 goto delegate;
1655
1656 zero_status:
1657 /* return two zero bytes */
1658 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1659 omap_writew(0, UDC_DATA);
1660 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1661 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1662 status = 0;
1663 VDBG("GET_STATUS, interface %d\n", w_index);
1664 /* next, status stage */
1665 break;
1666 default:
1667 delegate:
1668 /* activate the ep0out fifo right away */
1669 if (!udc->ep0_in && w_length) {
1670 omap_writew(0, UDC_EP_NUM);
1671 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1672 }
1673
1674 /* gadget drivers see class/vendor specific requests,
1675 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1676 * and more
1677 */
1678 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1679 u.r.bRequestType, u.r.bRequest,
1680 w_value, w_index, w_length);
1681
1682 #undef w_value
1683 #undef w_index
1684 #undef w_length
1685
1686 /* The gadget driver may return an error here,
1687 * causing an immediate protocol stall.
1688 *
1689 * Else it must issue a response, either queueing a
1690 * response buffer for the DATA stage, or halting ep0
1691 * (causing a protocol stall, not a real halt). A
1692 * zero length buffer means no DATA stage.
1693 *
1694 * It's fine to issue that response after the setup()
1695 * call returns, and this IRQ was handled.
1696 */
1697 udc->ep0_setup = 1;
1698 spin_unlock(&udc->lock);
1699 status = udc->driver->setup(&udc->gadget, &u.r);
1700 spin_lock(&udc->lock);
1701 udc->ep0_setup = 0;
1702 }
1703
1704 if (status < 0) {
1705 do_stall:
1706 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1707 u.r.bRequestType, u.r.bRequest, status);
1708 if (udc->ep0_set_config) {
1709 if (udc->ep0_reset_config)
1710 WARNING("error resetting config?\n");
1711 else
1712 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1713 }
1714 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1715 udc->ep0_pending = 0;
1716 }
1717 }
1718 }
1719
1720 /*-------------------------------------------------------------------------*/
1721
1722 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1723
1724 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1725 {
1726 u16 devstat, change;
1727
1728 devstat = omap_readw(UDC_DEVSTAT);
1729 change = devstat ^ udc->devstat;
1730 udc->devstat = devstat;
1731
1732 if (change & (UDC_USB_RESET|UDC_ATT)) {
1733 udc_quiesce(udc);
1734
1735 if (change & UDC_ATT) {
1736 /* driver for any external transceiver will
1737 * have called omap_vbus_session() already
1738 */
1739 if (devstat & UDC_ATT) {
1740 udc->gadget.speed = USB_SPEED_FULL;
1741 VDBG("connect\n");
1742 if (IS_ERR_OR_NULL(udc->transceiver))
1743 pullup_enable(udc);
1744 /* if (driver->connect) call it */
1745 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1746 udc->gadget.speed = USB_SPEED_UNKNOWN;
1747 if (IS_ERR_OR_NULL(udc->transceiver))
1748 pullup_disable(udc);
1749 DBG("disconnect, gadget %s\n",
1750 udc->driver->driver.name);
1751 if (udc->driver->disconnect) {
1752 spin_unlock(&udc->lock);
1753 udc->driver->disconnect(&udc->gadget);
1754 spin_lock(&udc->lock);
1755 }
1756 }
1757 change &= ~UDC_ATT;
1758 }
1759
1760 if (change & UDC_USB_RESET) {
1761 if (devstat & UDC_USB_RESET) {
1762 VDBG("RESET=1\n");
1763 } else {
1764 udc->gadget.speed = USB_SPEED_FULL;
1765 INFO("USB reset done, gadget %s\n",
1766 udc->driver->driver.name);
1767 /* ep0 traffic is legal from now on */
1768 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1769 UDC_IRQ_EN);
1770 }
1771 change &= ~UDC_USB_RESET;
1772 }
1773 }
1774 if (change & UDC_SUS) {
1775 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1776 /* FIXME tell isp1301 to suspend/resume (?) */
1777 if (devstat & UDC_SUS) {
1778 VDBG("suspend\n");
1779 update_otg(udc);
1780 /* HNP could be under way already */
1781 if (udc->gadget.speed == USB_SPEED_FULL
1782 && udc->driver->suspend) {
1783 spin_unlock(&udc->lock);
1784 udc->driver->suspend(&udc->gadget);
1785 spin_lock(&udc->lock);
1786 }
1787 if (!IS_ERR_OR_NULL(udc->transceiver))
1788 usb_phy_set_suspend(
1789 udc->transceiver, 1);
1790 } else {
1791 VDBG("resume\n");
1792 if (!IS_ERR_OR_NULL(udc->transceiver))
1793 usb_phy_set_suspend(
1794 udc->transceiver, 0);
1795 if (udc->gadget.speed == USB_SPEED_FULL
1796 && udc->driver->resume) {
1797 spin_unlock(&udc->lock);
1798 udc->driver->resume(&udc->gadget);
1799 spin_lock(&udc->lock);
1800 }
1801 }
1802 }
1803 change &= ~UDC_SUS;
1804 }
1805 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1806 update_otg(udc);
1807 change &= ~OTG_FLAGS;
1808 }
1809
1810 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1811 if (change)
1812 VDBG("devstat %03x, ignore change %03x\n",
1813 devstat, change);
1814
1815 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1816 }
1817
1818 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1819 {
1820 struct omap_udc *udc = _udc;
1821 u16 irq_src;
1822 irqreturn_t status = IRQ_NONE;
1823 unsigned long flags;
1824
1825 spin_lock_irqsave(&udc->lock, flags);
1826 irq_src = omap_readw(UDC_IRQ_SRC);
1827
1828 /* Device state change (usb ch9 stuff) */
1829 if (irq_src & UDC_DS_CHG) {
1830 devstate_irq(_udc, irq_src);
1831 status = IRQ_HANDLED;
1832 irq_src &= ~UDC_DS_CHG;
1833 }
1834
1835 /* EP0 control transfers */
1836 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1837 ep0_irq(_udc, irq_src);
1838 status = IRQ_HANDLED;
1839 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1840 }
1841
1842 /* DMA transfer completion */
1843 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1844 dma_irq(_udc, irq_src);
1845 status = IRQ_HANDLED;
1846 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1847 }
1848
1849 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1850 if (irq_src)
1851 DBG("udc_irq, unhandled %03x\n", irq_src);
1852 spin_unlock_irqrestore(&udc->lock, flags);
1853
1854 return status;
1855 }
1856
1857 /* workaround for seemingly-lost IRQs for RX ACKs... */
1858 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1859 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1860
1861 static void pio_out_timer(unsigned long _ep)
1862 {
1863 struct omap_ep *ep = (void *) _ep;
1864 unsigned long flags;
1865 u16 stat_flg;
1866
1867 spin_lock_irqsave(&ep->udc->lock, flags);
1868 if (!list_empty(&ep->queue) && ep->ackwait) {
1869 use_ep(ep, UDC_EP_SEL);
1870 stat_flg = omap_readw(UDC_STAT_FLG);
1871
1872 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1873 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1874 struct omap_req *req;
1875
1876 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1877 req = container_of(ep->queue.next,
1878 struct omap_req, queue);
1879 (void) read_fifo(ep, req);
1880 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1881 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1882 ep->ackwait = 1 + ep->double_buf;
1883 } else
1884 deselect_ep();
1885 }
1886 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1887 spin_unlock_irqrestore(&ep->udc->lock, flags);
1888 }
1889
1890 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1891 {
1892 u16 epn_stat, irq_src;
1893 irqreturn_t status = IRQ_NONE;
1894 struct omap_ep *ep;
1895 int epnum;
1896 struct omap_udc *udc = _dev;
1897 struct omap_req *req;
1898 unsigned long flags;
1899
1900 spin_lock_irqsave(&udc->lock, flags);
1901 epn_stat = omap_readw(UDC_EPN_STAT);
1902 irq_src = omap_readw(UDC_IRQ_SRC);
1903
1904 /* handle OUT first, to avoid some wasteful NAKs */
1905 if (irq_src & UDC_EPN_RX) {
1906 epnum = (epn_stat >> 8) & 0x0f;
1907 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1908 status = IRQ_HANDLED;
1909 ep = &udc->ep[epnum];
1910 ep->irqs++;
1911
1912 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1913 ep->fnf = 0;
1914 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1915 ep->ackwait--;
1916 if (!list_empty(&ep->queue)) {
1917 int stat;
1918 req = container_of(ep->queue.next,
1919 struct omap_req, queue);
1920 stat = read_fifo(ep, req);
1921 if (!ep->double_buf)
1922 ep->fnf = 1;
1923 }
1924 }
1925 /* min 6 clock delay before clearing EP_SEL ... */
1926 epn_stat = omap_readw(UDC_EPN_STAT);
1927 epn_stat = omap_readw(UDC_EPN_STAT);
1928 omap_writew(epnum, UDC_EP_NUM);
1929
1930 /* enabling fifo _after_ clearing ACK, contrary to docs,
1931 * reduces lossage; timer still needed though (sigh).
1932 */
1933 if (ep->fnf) {
1934 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1935 ep->ackwait = 1 + ep->double_buf;
1936 }
1937 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1938 }
1939
1940 /* then IN transfers */
1941 else if (irq_src & UDC_EPN_TX) {
1942 epnum = epn_stat & 0x0f;
1943 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1944 status = IRQ_HANDLED;
1945 ep = &udc->ep[16 + epnum];
1946 ep->irqs++;
1947
1948 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1949 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1950 ep->ackwait = 0;
1951 if (!list_empty(&ep->queue)) {
1952 req = container_of(ep->queue.next,
1953 struct omap_req, queue);
1954 (void) write_fifo(ep, req);
1955 }
1956 }
1957 /* min 6 clock delay before clearing EP_SEL ... */
1958 epn_stat = omap_readw(UDC_EPN_STAT);
1959 epn_stat = omap_readw(UDC_EPN_STAT);
1960 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1961 /* then 6 clocks before it'd tx */
1962 }
1963
1964 spin_unlock_irqrestore(&udc->lock, flags);
1965 return status;
1966 }
1967
1968 #ifdef USE_ISO
1969 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1970 {
1971 struct omap_udc *udc = _dev;
1972 struct omap_ep *ep;
1973 int pending = 0;
1974 unsigned long flags;
1975
1976 spin_lock_irqsave(&udc->lock, flags);
1977
1978 /* handle all non-DMA ISO transfers */
1979 list_for_each_entry(ep, &udc->iso, iso) {
1980 u16 stat;
1981 struct omap_req *req;
1982
1983 if (ep->has_dma || list_empty(&ep->queue))
1984 continue;
1985 req = list_entry(ep->queue.next, struct omap_req, queue);
1986
1987 use_ep(ep, UDC_EP_SEL);
1988 stat = omap_readw(UDC_STAT_FLG);
1989
1990 /* NOTE: like the other controller drivers, this isn't
1991 * currently reporting lost or damaged frames.
1992 */
1993 if (ep->bEndpointAddress & USB_DIR_IN) {
1994 if (stat & UDC_MISS_IN)
1995 /* done(ep, req, -EPROTO) */;
1996 else
1997 write_fifo(ep, req);
1998 } else {
1999 int status = 0;
2000
2001 if (stat & UDC_NO_RXPACKET)
2002 status = -EREMOTEIO;
2003 else if (stat & UDC_ISO_ERR)
2004 status = -EILSEQ;
2005 else if (stat & UDC_DATA_FLUSH)
2006 status = -ENOSR;
2007
2008 if (status)
2009 /* done(ep, req, status) */;
2010 else
2011 read_fifo(ep, req);
2012 }
2013 deselect_ep();
2014 /* 6 wait states before next EP */
2015
2016 ep->irqs++;
2017 if (!list_empty(&ep->queue))
2018 pending = 1;
2019 }
2020 if (!pending) {
2021 u16 w;
2022
2023 w = omap_readw(UDC_IRQ_EN);
2024 w &= ~UDC_SOF_IE;
2025 omap_writew(w, UDC_IRQ_EN);
2026 }
2027 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2028
2029 spin_unlock_irqrestore(&udc->lock, flags);
2030 return IRQ_HANDLED;
2031 }
2032 #endif
2033
2034 /*-------------------------------------------------------------------------*/
2035
2036 static inline int machine_without_vbus_sense(void)
2037 {
2038 return machine_is_omap_innovator()
2039 || machine_is_omap_osk()
2040 || machine_is_sx1()
2041 /* No known omap7xx boards with vbus sense */
2042 || cpu_is_omap7xx();
2043 }
2044
2045 static int omap_udc_start(struct usb_gadget *g,
2046 struct usb_gadget_driver *driver)
2047 {
2048 int status = -ENODEV;
2049 struct omap_ep *ep;
2050 unsigned long flags;
2051
2052
2053 spin_lock_irqsave(&udc->lock, flags);
2054 /* reset state */
2055 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2056 ep->irqs = 0;
2057 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2058 continue;
2059 use_ep(ep, 0);
2060 omap_writew(UDC_SET_HALT, UDC_CTRL);
2061 }
2062 udc->ep0_pending = 0;
2063 udc->ep[0].irqs = 0;
2064 udc->softconnect = 1;
2065
2066 /* hook up the driver */
2067 driver->driver.bus = NULL;
2068 udc->driver = driver;
2069 spin_unlock_irqrestore(&udc->lock, flags);
2070
2071 if (udc->dc_clk != NULL)
2072 omap_udc_enable_clock(1);
2073
2074 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2075
2076 /* connect to bus through transceiver */
2077 if (!IS_ERR_OR_NULL(udc->transceiver)) {
2078 status = otg_set_peripheral(udc->transceiver->otg,
2079 &udc->gadget);
2080 if (status < 0) {
2081 ERR("can't bind to transceiver\n");
2082 udc->driver = NULL;
2083 goto done;
2084 }
2085 } else {
2086 if (can_pullup(udc))
2087 pullup_enable(udc);
2088 else
2089 pullup_disable(udc);
2090 }
2091
2092 /* boards that don't have VBUS sensing can't autogate 48MHz;
2093 * can't enter deep sleep while a gadget driver is active.
2094 */
2095 if (machine_without_vbus_sense())
2096 omap_vbus_session(&udc->gadget, 1);
2097
2098 done:
2099 if (udc->dc_clk != NULL)
2100 omap_udc_enable_clock(0);
2101
2102 return status;
2103 }
2104
2105 static int omap_udc_stop(struct usb_gadget *g)
2106 {
2107 unsigned long flags;
2108 int status = -ENODEV;
2109
2110 if (udc->dc_clk != NULL)
2111 omap_udc_enable_clock(1);
2112
2113 if (machine_without_vbus_sense())
2114 omap_vbus_session(&udc->gadget, 0);
2115
2116 if (!IS_ERR_OR_NULL(udc->transceiver))
2117 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2118 else
2119 pullup_disable(udc);
2120
2121 spin_lock_irqsave(&udc->lock, flags);
2122 udc_quiesce(udc);
2123 spin_unlock_irqrestore(&udc->lock, flags);
2124
2125 udc->driver = NULL;
2126
2127 if (udc->dc_clk != NULL)
2128 omap_udc_enable_clock(0);
2129
2130 return status;
2131 }
2132
2133 /*-------------------------------------------------------------------------*/
2134
2135 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2136
2137 #include <linux/seq_file.h>
2138
2139 static const char proc_filename[] = "driver/udc";
2140
2141 #define FOURBITS "%s%s%s%s"
2142 #define EIGHTBITS "%s%s%s%s%s%s%s%s"
2143
2144 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2145 {
2146 u16 stat_flg;
2147 struct omap_req *req;
2148 char buf[20];
2149
2150 use_ep(ep, 0);
2151
2152 if (use_dma && ep->has_dma)
2153 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2154 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2155 ep->dma_channel - 1, ep->lch);
2156 else
2157 buf[0] = 0;
2158
2159 stat_flg = omap_readw(UDC_STAT_FLG);
2160 seq_printf(s,
2161 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2162 ep->name, buf,
2163 ep->double_buf ? "dbuf " : "",
2164 ({ char *s;
2165 switch (ep->ackwait) {
2166 case 0:
2167 s = "";
2168 break;
2169 case 1:
2170 s = "(ackw) ";
2171 break;
2172 case 2:
2173 s = "(ackw2) ";
2174 break;
2175 default:
2176 s = "(?) ";
2177 break;
2178 } s; }),
2179 ep->irqs, stat_flg,
2180 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2181 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2182 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2183 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2184 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2185 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2186 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2187 (stat_flg & UDC_STALL) ? "STALL " : "",
2188 (stat_flg & UDC_NAK) ? "NAK " : "",
2189 (stat_flg & UDC_ACK) ? "ACK " : "",
2190 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2191 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2192 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2193
2194 if (list_empty(&ep->queue))
2195 seq_printf(s, "\t(queue empty)\n");
2196 else
2197 list_for_each_entry(req, &ep->queue, queue) {
2198 unsigned length = req->req.actual;
2199
2200 if (use_dma && buf[0]) {
2201 length += ((ep->bEndpointAddress & USB_DIR_IN)
2202 ? dma_src_len : dma_dest_len)
2203 (ep, req->req.dma + length);
2204 buf[0] = 0;
2205 }
2206 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2207 &req->req, length,
2208 req->req.length, req->req.buf);
2209 }
2210 }
2211
2212 static char *trx_mode(unsigned m, int enabled)
2213 {
2214 switch (m) {
2215 case 0:
2216 return enabled ? "*6wire" : "unused";
2217 case 1:
2218 return "4wire";
2219 case 2:
2220 return "3wire";
2221 case 3:
2222 return "6wire";
2223 default:
2224 return "unknown";
2225 }
2226 }
2227
2228 static int proc_otg_show(struct seq_file *s)
2229 {
2230 u32 tmp;
2231 u32 trans = 0;
2232 char *ctrl_name = "(UNKNOWN)";
2233
2234 tmp = omap_readl(OTG_REV);
2235 ctrl_name = "tranceiver_ctrl";
2236 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2237 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2238 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2239 tmp = omap_readw(OTG_SYSCON_1);
2240 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2241 FOURBITS "\n", tmp,
2242 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2243 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2244 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2245 ? "internal"
2246 : trx_mode(USB0_TRX_MODE(tmp), 1),
2247 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2248 (tmp & HST_IDLE_EN) ? " !host" : "",
2249 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2250 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2251 tmp = omap_readl(OTG_SYSCON_2);
2252 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2253 " b_ase_brst=%d hmc=%d\n", tmp,
2254 (tmp & OTG_EN) ? " otg_en" : "",
2255 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2256 /* much more SRP stuff */
2257 (tmp & SRP_DATA) ? " srp_data" : "",
2258 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2259 (tmp & OTG_PADEN) ? " otg_paden" : "",
2260 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2261 (tmp & UHOST_EN) ? " uhost_en" : "",
2262 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2263 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2264 B_ASE_BRST(tmp),
2265 OTG_HMC(tmp));
2266 tmp = omap_readl(OTG_CTRL);
2267 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2268 (tmp & OTG_ASESSVLD) ? " asess" : "",
2269 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2270 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2271 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2272 (tmp & OTG_ID) ? " id" : "",
2273 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2274 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2275 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2276 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2277 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2278 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2279 (tmp & OTG_PULLDOWN) ? " down" : "",
2280 (tmp & OTG_PULLUP) ? " up" : "",
2281 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2282 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2283 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2284 (tmp & OTG_PU_ID) ? " pu_id" : ""
2285 );
2286 tmp = omap_readw(OTG_IRQ_EN);
2287 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2288 tmp = omap_readw(OTG_IRQ_SRC);
2289 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2290 tmp = omap_readw(OTG_OUTCTRL);
2291 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2292 tmp = omap_readw(OTG_TEST);
2293 seq_printf(s, "otg_test %04x" "\n", tmp);
2294 return 0;
2295 }
2296
2297 static int proc_udc_show(struct seq_file *s, void *_)
2298 {
2299 u32 tmp;
2300 struct omap_ep *ep;
2301 unsigned long flags;
2302
2303 spin_lock_irqsave(&udc->lock, flags);
2304
2305 seq_printf(s, "%s, version: " DRIVER_VERSION
2306 #ifdef USE_ISO
2307 " (iso)"
2308 #endif
2309 "%s\n",
2310 driver_desc,
2311 use_dma ? " (dma)" : "");
2312
2313 tmp = omap_readw(UDC_REV) & 0xff;
2314 seq_printf(s,
2315 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2316 "hmc %d, transceiver %s\n",
2317 tmp >> 4, tmp & 0xf,
2318 fifo_mode,
2319 udc->driver ? udc->driver->driver.name : "(none)",
2320 HMC,
2321 udc->transceiver
2322 ? udc->transceiver->label
2323 : (cpu_is_omap1710()
2324 ? "external" : "(none)"));
2325 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2326 omap_readw(ULPD_CLOCK_CTRL),
2327 omap_readw(ULPD_SOFT_REQ),
2328 omap_readw(ULPD_STATUS_REQ));
2329
2330 /* OTG controller registers */
2331 if (!cpu_is_omap15xx())
2332 proc_otg_show(s);
2333
2334 tmp = omap_readw(UDC_SYSCON1);
2335 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2336 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2337 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2338 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2339 (tmp & UDC_NAK_EN) ? " nak" : "",
2340 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2341 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2342 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2343 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2344 /* syscon2 is write-only */
2345
2346 /* UDC controller registers */
2347 if (!(tmp & UDC_PULLUP_EN)) {
2348 seq_printf(s, "(suspended)\n");
2349 spin_unlock_irqrestore(&udc->lock, flags);
2350 return 0;
2351 }
2352
2353 tmp = omap_readw(UDC_DEVSTAT);
2354 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2355 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2356 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2357 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2358 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2359 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2360 (tmp & UDC_SUS) ? " SUS" : "",
2361 (tmp & UDC_CFG) ? " CFG" : "",
2362 (tmp & UDC_ADD) ? " ADD" : "",
2363 (tmp & UDC_DEF) ? " DEF" : "",
2364 (tmp & UDC_ATT) ? " ATT" : "");
2365 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2366 tmp = omap_readw(UDC_IRQ_EN);
2367 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2368 (tmp & UDC_SOF_IE) ? " sof" : "",
2369 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2370 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2371 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2372 (tmp & UDC_EP0_IE) ? " ep0" : "");
2373 tmp = omap_readw(UDC_IRQ_SRC);
2374 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2375 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2376 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2377 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2378 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2379 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2380 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2381 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2382 (tmp & UDC_SETUP) ? " setup" : "",
2383 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2384 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2385 if (use_dma) {
2386 unsigned i;
2387
2388 tmp = omap_readw(UDC_DMA_IRQ_EN);
2389 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2390 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2391 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2392 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2393
2394 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2395 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2396 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2397
2398 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2399 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2400 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2401
2402 tmp = omap_readw(UDC_RXDMA_CFG);
2403 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2404 if (tmp) {
2405 for (i = 0; i < 3; i++) {
2406 if ((tmp & (0x0f << (i * 4))) == 0)
2407 continue;
2408 seq_printf(s, "rxdma[%d] %04x\n", i,
2409 omap_readw(UDC_RXDMA(i + 1)));
2410 }
2411 }
2412 tmp = omap_readw(UDC_TXDMA_CFG);
2413 seq_printf(s, "txdma_cfg %04x\n", tmp);
2414 if (tmp) {
2415 for (i = 0; i < 3; i++) {
2416 if (!(tmp & (0x0f << (i * 4))))
2417 continue;
2418 seq_printf(s, "txdma[%d] %04x\n", i,
2419 omap_readw(UDC_TXDMA(i + 1)));
2420 }
2421 }
2422 }
2423
2424 tmp = omap_readw(UDC_DEVSTAT);
2425 if (tmp & UDC_ATT) {
2426 proc_ep_show(s, &udc->ep[0]);
2427 if (tmp & UDC_ADD) {
2428 list_for_each_entry(ep, &udc->gadget.ep_list,
2429 ep.ep_list) {
2430 if (ep->ep.desc)
2431 proc_ep_show(s, ep);
2432 }
2433 }
2434 }
2435 spin_unlock_irqrestore(&udc->lock, flags);
2436 return 0;
2437 }
2438
2439 static int proc_udc_open(struct inode *inode, struct file *file)
2440 {
2441 return single_open(file, proc_udc_show, NULL);
2442 }
2443
2444 static const struct file_operations proc_ops = {
2445 .owner = THIS_MODULE,
2446 .open = proc_udc_open,
2447 .read = seq_read,
2448 .llseek = seq_lseek,
2449 .release = single_release,
2450 };
2451
2452 static void create_proc_file(void)
2453 {
2454 proc_create(proc_filename, 0, NULL, &proc_ops);
2455 }
2456
2457 static void remove_proc_file(void)
2458 {
2459 remove_proc_entry(proc_filename, NULL);
2460 }
2461
2462 #else
2463
2464 static inline void create_proc_file(void) {}
2465 static inline void remove_proc_file(void) {}
2466
2467 #endif
2468
2469 /*-------------------------------------------------------------------------*/
2470
2471 /* Before this controller can enumerate, we need to pick an endpoint
2472 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2473 * buffer space among the endpoints we'll be operating.
2474 *
2475 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2476 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2477 * capability yet though.
2478 */
2479 static unsigned
2480 omap_ep_setup(char *name, u8 addr, u8 type,
2481 unsigned buf, unsigned maxp, int dbuf)
2482 {
2483 struct omap_ep *ep;
2484 u16 epn_rxtx = 0;
2485
2486 /* OUT endpoints first, then IN */
2487 ep = &udc->ep[addr & 0xf];
2488 if (addr & USB_DIR_IN)
2489 ep += 16;
2490
2491 /* in case of ep init table bugs */
2492 BUG_ON(ep->name[0]);
2493
2494 /* chip setup ... bit values are same for IN, OUT */
2495 if (type == USB_ENDPOINT_XFER_ISOC) {
2496 switch (maxp) {
2497 case 8:
2498 epn_rxtx = 0 << 12;
2499 break;
2500 case 16:
2501 epn_rxtx = 1 << 12;
2502 break;
2503 case 32:
2504 epn_rxtx = 2 << 12;
2505 break;
2506 case 64:
2507 epn_rxtx = 3 << 12;
2508 break;
2509 case 128:
2510 epn_rxtx = 4 << 12;
2511 break;
2512 case 256:
2513 epn_rxtx = 5 << 12;
2514 break;
2515 case 512:
2516 epn_rxtx = 6 << 12;
2517 break;
2518 default:
2519 BUG();
2520 }
2521 epn_rxtx |= UDC_EPN_RX_ISO;
2522 dbuf = 1;
2523 } else {
2524 /* double-buffering "not supported" on 15xx,
2525 * and ignored for PIO-IN on newer chips
2526 * (for more reliable behavior)
2527 */
2528 if (!use_dma || cpu_is_omap15xx())
2529 dbuf = 0;
2530
2531 switch (maxp) {
2532 case 8:
2533 epn_rxtx = 0 << 12;
2534 break;
2535 case 16:
2536 epn_rxtx = 1 << 12;
2537 break;
2538 case 32:
2539 epn_rxtx = 2 << 12;
2540 break;
2541 case 64:
2542 epn_rxtx = 3 << 12;
2543 break;
2544 default:
2545 BUG();
2546 }
2547 if (dbuf && addr)
2548 epn_rxtx |= UDC_EPN_RX_DB;
2549 init_timer(&ep->timer);
2550 ep->timer.function = pio_out_timer;
2551 ep->timer.data = (unsigned long) ep;
2552 }
2553 if (addr)
2554 epn_rxtx |= UDC_EPN_RX_VALID;
2555 BUG_ON(buf & 0x07);
2556 epn_rxtx |= buf >> 3;
2557
2558 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2559 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2560
2561 if (addr & USB_DIR_IN)
2562 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2563 else
2564 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2565
2566 /* next endpoint's buffer starts after this one's */
2567 buf += maxp;
2568 if (dbuf)
2569 buf += maxp;
2570 BUG_ON(buf > 2048);
2571
2572 /* set up driver data structures */
2573 BUG_ON(strlen(name) >= sizeof ep->name);
2574 strlcpy(ep->name, name, sizeof ep->name);
2575 INIT_LIST_HEAD(&ep->queue);
2576 INIT_LIST_HEAD(&ep->iso);
2577 ep->bEndpointAddress = addr;
2578 ep->bmAttributes = type;
2579 ep->double_buf = dbuf;
2580 ep->udc = udc;
2581
2582 switch (type) {
2583 case USB_ENDPOINT_XFER_CONTROL:
2584 ep->ep.caps.type_control = true;
2585 ep->ep.caps.dir_in = true;
2586 ep->ep.caps.dir_out = true;
2587 break;
2588 case USB_ENDPOINT_XFER_ISOC:
2589 ep->ep.caps.type_iso = true;
2590 break;
2591 case USB_ENDPOINT_XFER_BULK:
2592 ep->ep.caps.type_bulk = true;
2593 break;
2594 case USB_ENDPOINT_XFER_INT:
2595 ep->ep.caps.type_int = true;
2596 break;
2597 };
2598
2599 if (addr & USB_DIR_IN)
2600 ep->ep.caps.dir_in = true;
2601 else
2602 ep->ep.caps.dir_out = true;
2603
2604 ep->ep.name = ep->name;
2605 ep->ep.ops = &omap_ep_ops;
2606 ep->maxpacket = maxp;
2607 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
2608 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2609
2610 return buf;
2611 }
2612
2613 static void omap_udc_release(struct device *dev)
2614 {
2615 complete(udc->done);
2616 kfree(udc);
2617 udc = NULL;
2618 }
2619
2620 static int
2621 omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2622 {
2623 unsigned tmp, buf;
2624
2625 /* abolish any previous hardware state */
2626 omap_writew(0, UDC_SYSCON1);
2627 omap_writew(0, UDC_IRQ_EN);
2628 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2629 omap_writew(0, UDC_DMA_IRQ_EN);
2630 omap_writew(0, UDC_RXDMA_CFG);
2631 omap_writew(0, UDC_TXDMA_CFG);
2632
2633 /* UDC_PULLUP_EN gates the chip clock */
2634 /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2635
2636 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2637 if (!udc)
2638 return -ENOMEM;
2639
2640 spin_lock_init(&udc->lock);
2641
2642 udc->gadget.ops = &omap_gadget_ops;
2643 udc->gadget.ep0 = &udc->ep[0].ep;
2644 INIT_LIST_HEAD(&udc->gadget.ep_list);
2645 INIT_LIST_HEAD(&udc->iso);
2646 udc->gadget.speed = USB_SPEED_UNKNOWN;
2647 udc->gadget.max_speed = USB_SPEED_FULL;
2648 udc->gadget.name = driver_name;
2649 udc->transceiver = xceiv;
2650
2651 /* ep0 is special; put it right after the SETUP buffer */
2652 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2653 8 /* after SETUP */, 64 /* maxpacket */, 0);
2654 list_del_init(&udc->ep[0].ep.ep_list);
2655
2656 /* initially disable all non-ep0 endpoints */
2657 for (tmp = 1; tmp < 15; tmp++) {
2658 omap_writew(0, UDC_EP_RX(tmp));
2659 omap_writew(0, UDC_EP_TX(tmp));
2660 }
2661
2662 #define OMAP_BULK_EP(name, addr) \
2663 buf = omap_ep_setup(name "-bulk", addr, \
2664 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2665 #define OMAP_INT_EP(name, addr, maxp) \
2666 buf = omap_ep_setup(name "-int", addr, \
2667 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2668 #define OMAP_ISO_EP(name, addr, maxp) \
2669 buf = omap_ep_setup(name "-iso", addr, \
2670 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2671
2672 switch (fifo_mode) {
2673 case 0:
2674 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2675 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2676 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2677 break;
2678 case 1:
2679 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2680 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2681 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2682
2683 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2684 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2685 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2686
2687 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2688 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2689 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2690
2691 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2692 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2693 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2694
2695 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2696 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2697 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2698 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2699
2700 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2701 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2702 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2703 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2704
2705 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2706 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2707
2708 break;
2709
2710 #ifdef USE_ISO
2711 case 2: /* mixed iso/bulk */
2712 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2713 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2714 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2715 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2716
2717 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2718
2719 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2720 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2721 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2722 break;
2723 case 3: /* mixed bulk/iso */
2724 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2725 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2726 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2727
2728 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2729 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2730 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2731
2732 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2733 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2734 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2735 break;
2736 #endif
2737
2738 /* add more modes as needed */
2739
2740 default:
2741 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2742 return -ENODEV;
2743 }
2744 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2745 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2746 return 0;
2747 }
2748
2749 static int omap_udc_probe(struct platform_device *pdev)
2750 {
2751 int status = -ENODEV;
2752 int hmc;
2753 struct usb_phy *xceiv = NULL;
2754 const char *type = NULL;
2755 struct omap_usb_config *config = dev_get_platdata(&pdev->dev);
2756 struct clk *dc_clk = NULL;
2757 struct clk *hhc_clk = NULL;
2758
2759 if (cpu_is_omap7xx())
2760 use_dma = 0;
2761
2762 /* NOTE: "knows" the order of the resources! */
2763 if (!request_mem_region(pdev->resource[0].start,
2764 pdev->resource[0].end - pdev->resource[0].start + 1,
2765 driver_name)) {
2766 DBG("request_mem_region failed\n");
2767 return -EBUSY;
2768 }
2769
2770 if (cpu_is_omap16xx()) {
2771 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2772 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2773 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2774 /* can't use omap_udc_enable_clock yet */
2775 clk_enable(dc_clk);
2776 clk_enable(hhc_clk);
2777 udelay(100);
2778 }
2779
2780 if (cpu_is_omap7xx()) {
2781 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2782 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2783 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2784 /* can't use omap_udc_enable_clock yet */
2785 clk_enable(dc_clk);
2786 clk_enable(hhc_clk);
2787 udelay(100);
2788 }
2789
2790 INFO("OMAP UDC rev %d.%d%s\n",
2791 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2792 config->otg ? ", Mini-AB" : "");
2793
2794 /* use the mode given to us by board init code */
2795 if (cpu_is_omap15xx()) {
2796 hmc = HMC_1510;
2797 type = "(unknown)";
2798
2799 if (machine_without_vbus_sense()) {
2800 /* just set up software VBUS detect, and then
2801 * later rig it so we always report VBUS.
2802 * FIXME without really sensing VBUS, we can't
2803 * know when to turn PULLUP_EN on/off; and that
2804 * means we always "need" the 48MHz clock.
2805 */
2806 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2807 tmp &= ~VBUS_CTRL_1510;
2808 omap_writel(tmp, FUNC_MUX_CTRL_0);
2809 tmp |= VBUS_MODE_1510;
2810 tmp &= ~VBUS_CTRL_1510;
2811 omap_writel(tmp, FUNC_MUX_CTRL_0);
2812 }
2813 } else {
2814 /* The transceiver may package some GPIO logic or handle
2815 * loopback and/or transceiverless setup; if we find one,
2816 * use it. Except for OTG, we don't _need_ to talk to one;
2817 * but not having one probably means no VBUS detection.
2818 */
2819 xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2820 if (!IS_ERR_OR_NULL(xceiv))
2821 type = xceiv->label;
2822 else if (config->otg) {
2823 DBG("OTG requires external transceiver!\n");
2824 goto cleanup0;
2825 }
2826
2827 hmc = HMC_1610;
2828
2829 switch (hmc) {
2830 case 0: /* POWERUP DEFAULT == 0 */
2831 case 4:
2832 case 12:
2833 case 20:
2834 if (!cpu_is_omap1710()) {
2835 type = "integrated";
2836 break;
2837 }
2838 /* FALL THROUGH */
2839 case 3:
2840 case 11:
2841 case 16:
2842 case 19:
2843 case 25:
2844 if (IS_ERR_OR_NULL(xceiv)) {
2845 DBG("external transceiver not registered!\n");
2846 type = "unknown";
2847 }
2848 break;
2849 case 21: /* internal loopback */
2850 type = "loopback";
2851 break;
2852 case 14: /* transceiverless */
2853 if (cpu_is_omap1710())
2854 goto bad_on_1710;
2855 /* FALL THROUGH */
2856 case 13:
2857 case 15:
2858 type = "no";
2859 break;
2860
2861 default:
2862 bad_on_1710:
2863 ERR("unrecognized UDC HMC mode %d\n", hmc);
2864 goto cleanup0;
2865 }
2866 }
2867
2868 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2869
2870 /* a "gadget" abstracts/virtualizes the controller */
2871 status = omap_udc_setup(pdev, xceiv);
2872 if (status)
2873 goto cleanup0;
2874
2875 xceiv = NULL;
2876 /* "udc" is now valid */
2877 pullup_disable(udc);
2878 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2879 udc->gadget.is_otg = (config->otg != 0);
2880 #endif
2881
2882 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2883 if (omap_readw(UDC_REV) >= 0x61)
2884 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2885 else
2886 udc->clr_halt = UDC_RESET_EP;
2887
2888 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2889 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2890 0, driver_name, udc);
2891 if (status != 0) {
2892 ERR("can't get irq %d, err %d\n",
2893 (int) pdev->resource[1].start, status);
2894 goto cleanup1;
2895 }
2896
2897 /* USB "non-iso" IRQ (PIO for all but ep0) */
2898 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2899 0, "omap_udc pio", udc);
2900 if (status != 0) {
2901 ERR("can't get irq %d, err %d\n",
2902 (int) pdev->resource[2].start, status);
2903 goto cleanup2;
2904 }
2905 #ifdef USE_ISO
2906 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2907 0, "omap_udc iso", udc);
2908 if (status != 0) {
2909 ERR("can't get irq %d, err %d\n",
2910 (int) pdev->resource[3].start, status);
2911 goto cleanup3;
2912 }
2913 #endif
2914 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2915 udc->dc_clk = dc_clk;
2916 udc->hhc_clk = hhc_clk;
2917 clk_disable(hhc_clk);
2918 clk_disable(dc_clk);
2919 }
2920
2921 create_proc_file();
2922 status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2923 omap_udc_release);
2924 if (status)
2925 goto cleanup4;
2926
2927 return 0;
2928
2929 cleanup4:
2930 remove_proc_file();
2931
2932 #ifdef USE_ISO
2933 cleanup3:
2934 free_irq(pdev->resource[2].start, udc);
2935 #endif
2936
2937 cleanup2:
2938 free_irq(pdev->resource[1].start, udc);
2939
2940 cleanup1:
2941 kfree(udc);
2942 udc = NULL;
2943
2944 cleanup0:
2945 if (!IS_ERR_OR_NULL(xceiv))
2946 usb_put_phy(xceiv);
2947
2948 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2949 clk_disable(hhc_clk);
2950 clk_disable(dc_clk);
2951 clk_put(hhc_clk);
2952 clk_put(dc_clk);
2953 }
2954
2955 release_mem_region(pdev->resource[0].start,
2956 pdev->resource[0].end - pdev->resource[0].start + 1);
2957
2958 return status;
2959 }
2960
2961 static int omap_udc_remove(struct platform_device *pdev)
2962 {
2963 DECLARE_COMPLETION_ONSTACK(done);
2964
2965 if (!udc)
2966 return -ENODEV;
2967
2968 usb_del_gadget_udc(&udc->gadget);
2969 if (udc->driver)
2970 return -EBUSY;
2971
2972 udc->done = &done;
2973
2974 pullup_disable(udc);
2975 if (!IS_ERR_OR_NULL(udc->transceiver)) {
2976 usb_put_phy(udc->transceiver);
2977 udc->transceiver = NULL;
2978 }
2979 omap_writew(0, UDC_SYSCON1);
2980
2981 remove_proc_file();
2982
2983 #ifdef USE_ISO
2984 free_irq(pdev->resource[3].start, udc);
2985 #endif
2986 free_irq(pdev->resource[2].start, udc);
2987 free_irq(pdev->resource[1].start, udc);
2988
2989 if (udc->dc_clk) {
2990 if (udc->clk_requested)
2991 omap_udc_enable_clock(0);
2992 clk_put(udc->hhc_clk);
2993 clk_put(udc->dc_clk);
2994 }
2995
2996 release_mem_region(pdev->resource[0].start,
2997 pdev->resource[0].end - pdev->resource[0].start + 1);
2998
2999 wait_for_completion(&done);
3000
3001 return 0;
3002 }
3003
3004 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3005 * system is forced into deep sleep
3006 *
3007 * REVISIT we should probably reject suspend requests when there's a host
3008 * session active, rather than disconnecting, at least on boards that can
3009 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3010 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3011 * may involve talking to an external transceiver (e.g. isp1301).
3012 */
3013
3014 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3015 {
3016 u32 devstat;
3017
3018 devstat = omap_readw(UDC_DEVSTAT);
3019
3020 /* we're requesting 48 MHz clock if the pullup is enabled
3021 * (== we're attached to the host) and we're not suspended,
3022 * which would prevent entry to deep sleep...
3023 */
3024 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3025 WARNING("session active; suspend requires disconnect\n");
3026 omap_pullup(&udc->gadget, 0);
3027 }
3028
3029 return 0;
3030 }
3031
3032 static int omap_udc_resume(struct platform_device *dev)
3033 {
3034 DBG("resume + wakeup/SRP\n");
3035 omap_pullup(&udc->gadget, 1);
3036
3037 /* maybe the host would enumerate us if we nudged it */
3038 msleep(100);
3039 return omap_wakeup(&udc->gadget);
3040 }
3041
3042 /*-------------------------------------------------------------------------*/
3043
3044 static struct platform_driver udc_driver = {
3045 .probe = omap_udc_probe,
3046 .remove = omap_udc_remove,
3047 .suspend = omap_udc_suspend,
3048 .resume = omap_udc_resume,
3049 .driver = {
3050 .name = (char *) driver_name,
3051 },
3052 };
3053
3054 module_platform_driver(udc_driver);
3055
3056 MODULE_DESCRIPTION(DRIVER_DESC);
3057 MODULE_LICENSE("GPL");
3058 MODULE_ALIAS("platform:omap_udc");
Linux with added FPC-III support