mmc: rtsx_pci: Enable MMC_CAP_ERASE to allow erase/discard/trim requests
[linux/fpc-iii.git] / drivers / usb / musb / da8xx.c
blobb03d3b867fca2f8b06f2340c3fffaf5c53a4da13
1 /*
2 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
4 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
9 * This file is part of the Inventra Controller Driver for Linux.
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/module.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/usb/usb_phy_generic.h>
37 #include <mach/da8xx.h>
38 #include <linux/platform_data/usb-davinci.h>
40 #include "musb_core.h"
43 * DA8XX specific definitions
46 /* USB 2.0 OTG module registers */
47 #define DA8XX_USB_REVISION_REG 0x00
48 #define DA8XX_USB_CTRL_REG 0x04
49 #define DA8XX_USB_STAT_REG 0x08
50 #define DA8XX_USB_EMULATION_REG 0x0c
51 #define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */
52 #define DA8XX_USB_AUTOREQ_REG 0x14
53 #define DA8XX_USB_SRP_FIX_TIME_REG 0x18
54 #define DA8XX_USB_TEARDOWN_REG 0x1c
55 #define DA8XX_USB_INTR_SRC_REG 0x20
56 #define DA8XX_USB_INTR_SRC_SET_REG 0x24
57 #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
58 #define DA8XX_USB_INTR_MASK_REG 0x2c
59 #define DA8XX_USB_INTR_MASK_SET_REG 0x30
60 #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
61 #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
62 #define DA8XX_USB_END_OF_INTR_REG 0x3c
63 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
65 /* Control register bits */
66 #define DA8XX_SOFT_RESET_MASK 1
68 #define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
69 #define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
71 /* USB interrupt register bits */
72 #define DA8XX_INTR_USB_SHIFT 16
73 #define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
74 /* interrupts and DRVVBUS interrupt */
75 #define DA8XX_INTR_DRVVBUS 0x100
76 #define DA8XX_INTR_RX_SHIFT 8
77 #define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
78 #define DA8XX_INTR_TX_SHIFT 0
79 #define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
81 #define DA8XX_MENTOR_CORE_OFFSET 0x400
83 #define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
85 struct da8xx_glue {
86 struct device *dev;
87 struct platform_device *musb;
88 struct platform_device *phy;
89 struct clk *clk;
93 * REVISIT (PM): we should be able to keep the PHY in low power mode most
94 * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
95 * and, when in host mode, autosuspending idle root ports... PHY_PLLON
96 * (overriding SUSPENDM?) then likely needs to stay off.
99 static inline void phy_on(void)
101 u32 cfgchip2 = __raw_readl(CFGCHIP2);
104 * Start the on-chip PHY and its PLL.
106 cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
107 cfgchip2 |= CFGCHIP2_PHY_PLLON;
108 __raw_writel(cfgchip2, CFGCHIP2);
110 pr_info("Waiting for USB PHY clock good...\n");
111 while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
112 cpu_relax();
115 static inline void phy_off(void)
117 u32 cfgchip2 = __raw_readl(CFGCHIP2);
120 * Ensure that USB 1.1 reference clock is not being sourced from
121 * USB 2.0 PHY. Otherwise do not power down the PHY.
123 if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
124 (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
125 pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
126 "can't power it down\n");
127 return;
131 * Power down the on-chip PHY.
133 cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
134 __raw_writel(cfgchip2, CFGCHIP2);
138 * Because we don't set CTRL.UINT, it's "important" to:
139 * - not read/write INTRUSB/INTRUSBE (except during
140 * initial setup, as a workaround);
141 * - use INTSET/INTCLR instead.
145 * da8xx_musb_enable - enable interrupts
147 static void da8xx_musb_enable(struct musb *musb)
149 void __iomem *reg_base = musb->ctrl_base;
150 u32 mask;
152 /* Workaround: setup IRQs through both register sets. */
153 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
154 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
155 DA8XX_INTR_USB_MASK;
156 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
158 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
159 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
160 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
164 * da8xx_musb_disable - disable HDRC and flush interrupts
166 static void da8xx_musb_disable(struct musb *musb)
168 void __iomem *reg_base = musb->ctrl_base;
170 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
171 DA8XX_INTR_USB_MASK |
172 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
173 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
174 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
177 #define portstate(stmt) stmt
179 static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
181 WARN_ON(is_on && is_peripheral_active(musb));
184 #define POLL_SECONDS 2
186 static struct timer_list otg_workaround;
188 static void otg_timer(unsigned long _musb)
190 struct musb *musb = (void *)_musb;
191 void __iomem *mregs = musb->mregs;
192 u8 devctl;
193 unsigned long flags;
196 * We poll because DaVinci's won't expose several OTG-critical
197 * status change events (from the transceiver) otherwise.
199 devctl = musb_readb(mregs, MUSB_DEVCTL);
200 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
201 usb_otg_state_string(musb->xceiv->otg->state));
203 spin_lock_irqsave(&musb->lock, flags);
204 switch (musb->xceiv->otg->state) {
205 case OTG_STATE_A_WAIT_BCON:
206 devctl &= ~MUSB_DEVCTL_SESSION;
207 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
209 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
210 if (devctl & MUSB_DEVCTL_BDEVICE) {
211 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
212 MUSB_DEV_MODE(musb);
213 } else {
214 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
215 MUSB_HST_MODE(musb);
217 break;
218 case OTG_STATE_A_WAIT_VFALL:
220 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
221 * RTL seems to mis-handle session "start" otherwise (or in
222 * our case "recover"), in routine "VBUS was valid by the time
223 * VBUSERR got reported during enumeration" cases.
225 if (devctl & MUSB_DEVCTL_VBUS) {
226 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
227 break;
229 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
230 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
231 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
232 break;
233 case OTG_STATE_B_IDLE:
235 * There's no ID-changed IRQ, so we have no good way to tell
236 * when to switch to the A-Default state machine (by setting
237 * the DEVCTL.Session bit).
239 * Workaround: whenever we're in B_IDLE, try setting the
240 * session flag every few seconds. If it works, ID was
241 * grounded and we're now in the A-Default state machine.
243 * NOTE: setting the session flag is _supposed_ to trigger
244 * SRP but clearly it doesn't.
246 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
247 devctl = musb_readb(mregs, MUSB_DEVCTL);
248 if (devctl & MUSB_DEVCTL_BDEVICE)
249 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
250 else
251 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
252 break;
253 default:
254 break;
256 spin_unlock_irqrestore(&musb->lock, flags);
259 static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
261 static unsigned long last_timer;
263 if (timeout == 0)
264 timeout = jiffies + msecs_to_jiffies(3);
266 /* Never idle if active, or when VBUS timeout is not set as host */
267 if (musb->is_active || (musb->a_wait_bcon == 0 &&
268 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
269 dev_dbg(musb->controller, "%s active, deleting timer\n",
270 usb_otg_state_string(musb->xceiv->otg->state));
271 del_timer(&otg_workaround);
272 last_timer = jiffies;
273 return;
276 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
277 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
278 return;
280 last_timer = timeout;
282 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
283 usb_otg_state_string(musb->xceiv->otg->state),
284 jiffies_to_msecs(timeout - jiffies));
285 mod_timer(&otg_workaround, timeout);
288 static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
290 struct musb *musb = hci;
291 void __iomem *reg_base = musb->ctrl_base;
292 struct usb_otg *otg = musb->xceiv->otg;
293 unsigned long flags;
294 irqreturn_t ret = IRQ_NONE;
295 u32 status;
297 spin_lock_irqsave(&musb->lock, flags);
300 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
301 * the Mentor registers (except for setup), use the TI ones and EOI.
304 /* Acknowledge and handle non-CPPI interrupts */
305 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
306 if (!status)
307 goto eoi;
309 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
310 dev_dbg(musb->controller, "USB IRQ %08x\n", status);
312 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
313 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
314 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
317 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
318 * DA8xx's missing ID change IRQ. We need an ID change IRQ to
319 * switch appropriately between halves of the OTG state machine.
320 * Managing DEVCTL.Session per Mentor docs requires that we know its
321 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
322 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
324 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
325 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
326 void __iomem *mregs = musb->mregs;
327 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
328 int err;
330 err = musb->int_usb & MUSB_INTR_VBUSERROR;
331 if (err) {
333 * The Mentor core doesn't debounce VBUS as needed
334 * to cope with device connect current spikes. This
335 * means it's not uncommon for bus-powered devices
336 * to get VBUS errors during enumeration.
338 * This is a workaround, but newer RTL from Mentor
339 * seems to allow a better one: "re"-starting sessions
340 * without waiting for VBUS to stop registering in
341 * devctl.
343 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
344 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
345 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
346 WARNING("VBUS error workaround (delay coming)\n");
347 } else if (drvvbus) {
348 MUSB_HST_MODE(musb);
349 otg->default_a = 1;
350 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
351 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
352 del_timer(&otg_workaround);
353 } else {
354 musb->is_active = 0;
355 MUSB_DEV_MODE(musb);
356 otg->default_a = 0;
357 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
358 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
361 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
362 drvvbus ? "on" : "off",
363 usb_otg_state_string(musb->xceiv->otg->state),
364 err ? " ERROR" : "",
365 devctl);
366 ret = IRQ_HANDLED;
369 if (musb->int_tx || musb->int_rx || musb->int_usb)
370 ret |= musb_interrupt(musb);
372 eoi:
373 /* EOI needs to be written for the IRQ to be re-asserted. */
374 if (ret == IRQ_HANDLED || status)
375 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
377 /* Poll for ID change */
378 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
379 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
381 spin_unlock_irqrestore(&musb->lock, flags);
383 return ret;
386 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
388 u32 cfgchip2 = __raw_readl(CFGCHIP2);
390 cfgchip2 &= ~CFGCHIP2_OTGMODE;
391 switch (musb_mode) {
392 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
393 cfgchip2 |= CFGCHIP2_FORCE_HOST;
394 break;
395 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
396 cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
397 break;
398 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
399 cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
400 break;
401 default:
402 dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
405 __raw_writel(cfgchip2, CFGCHIP2);
406 return 0;
409 static int da8xx_musb_init(struct musb *musb)
411 void __iomem *reg_base = musb->ctrl_base;
412 u32 rev;
413 int ret = -ENODEV;
415 musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
417 /* Returns zero if e.g. not clocked */
418 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
419 if (!rev)
420 goto fail;
422 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
423 if (IS_ERR_OR_NULL(musb->xceiv)) {
424 ret = -EPROBE_DEFER;
425 goto fail;
428 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
430 /* Reset the controller */
431 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
433 /* Start the on-chip PHY and its PLL. */
434 phy_on();
436 msleep(5);
438 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
439 pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
440 rev, __raw_readl(CFGCHIP2),
441 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
443 musb->isr = da8xx_musb_interrupt;
444 return 0;
445 fail:
446 return ret;
449 static int da8xx_musb_exit(struct musb *musb)
451 del_timer_sync(&otg_workaround);
453 phy_off();
455 usb_put_phy(musb->xceiv);
457 return 0;
460 static const struct musb_platform_ops da8xx_ops = {
461 .quirks = MUSB_DMA_CPPI | MUSB_INDEXED_EP,
462 .init = da8xx_musb_init,
463 .exit = da8xx_musb_exit,
465 .fifo_mode = 2,
466 #ifdef CONFIG_USB_TI_CPPI_DMA
467 .dma_init = cppi_dma_controller_create,
468 .dma_exit = cppi_dma_controller_destroy,
469 #endif
470 .enable = da8xx_musb_enable,
471 .disable = da8xx_musb_disable,
473 .set_mode = da8xx_musb_set_mode,
474 .try_idle = da8xx_musb_try_idle,
476 .set_vbus = da8xx_musb_set_vbus,
479 static const struct platform_device_info da8xx_dev_info = {
480 .name = "musb-hdrc",
481 .id = PLATFORM_DEVID_AUTO,
482 .dma_mask = DMA_BIT_MASK(32),
485 static int da8xx_probe(struct platform_device *pdev)
487 struct resource musb_resources[2];
488 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
489 struct platform_device *musb;
490 struct da8xx_glue *glue;
491 struct platform_device_info pinfo;
492 struct clk *clk;
494 int ret = -ENOMEM;
496 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
497 if (!glue) {
498 dev_err(&pdev->dev, "failed to allocate glue context\n");
499 goto err0;
502 clk = clk_get(&pdev->dev, "usb20");
503 if (IS_ERR(clk)) {
504 dev_err(&pdev->dev, "failed to get clock\n");
505 ret = PTR_ERR(clk);
506 goto err3;
509 ret = clk_enable(clk);
510 if (ret) {
511 dev_err(&pdev->dev, "failed to enable clock\n");
512 goto err4;
515 glue->dev = &pdev->dev;
516 glue->clk = clk;
518 pdata->platform_ops = &da8xx_ops;
520 glue->phy = usb_phy_generic_register();
521 if (IS_ERR(glue->phy)) {
522 ret = PTR_ERR(glue->phy);
523 goto err5;
525 platform_set_drvdata(pdev, glue);
527 memset(musb_resources, 0x00, sizeof(*musb_resources) *
528 ARRAY_SIZE(musb_resources));
530 musb_resources[0].name = pdev->resource[0].name;
531 musb_resources[0].start = pdev->resource[0].start;
532 musb_resources[0].end = pdev->resource[0].end;
533 musb_resources[0].flags = pdev->resource[0].flags;
535 musb_resources[1].name = pdev->resource[1].name;
536 musb_resources[1].start = pdev->resource[1].start;
537 musb_resources[1].end = pdev->resource[1].end;
538 musb_resources[1].flags = pdev->resource[1].flags;
540 pinfo = da8xx_dev_info;
541 pinfo.parent = &pdev->dev;
542 pinfo.res = musb_resources;
543 pinfo.num_res = ARRAY_SIZE(musb_resources);
544 pinfo.data = pdata;
545 pinfo.size_data = sizeof(*pdata);
547 glue->musb = musb = platform_device_register_full(&pinfo);
548 if (IS_ERR(musb)) {
549 ret = PTR_ERR(musb);
550 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
551 goto err6;
554 return 0;
556 err6:
557 usb_phy_generic_unregister(glue->phy);
559 err5:
560 clk_disable(clk);
562 err4:
563 clk_put(clk);
565 err3:
566 kfree(glue);
568 err0:
569 return ret;
572 static int da8xx_remove(struct platform_device *pdev)
574 struct da8xx_glue *glue = platform_get_drvdata(pdev);
576 platform_device_unregister(glue->musb);
577 usb_phy_generic_unregister(glue->phy);
578 clk_disable(glue->clk);
579 clk_put(glue->clk);
580 kfree(glue);
582 return 0;
585 static struct platform_driver da8xx_driver = {
586 .probe = da8xx_probe,
587 .remove = da8xx_remove,
588 .driver = {
589 .name = "musb-da8xx",
593 MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
594 MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
595 MODULE_LICENSE("GPL v2");
596 module_platform_driver(da8xx_driver);