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mmc: rtsx_pci: Enable MMC_CAP_ERASE to allow erase/discard/trim requests
[linux/fpc-iii.git] / drivers / usb / musb / sunxi.c
blob76500515dd8ba0884eae778253527f52601f2219
1 /*
2 * Allwinner sun4i MUSB Glue Layer
3 *
4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
5 *
6 * Based on code from
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/clk.h>
21 #include <linux/err.h>
22 #include <linux/extcon.h>
23 #include <linux/io.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/phy/phy-sun4i-usb.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/soc/sunxi/sunxi_sram.h>
31 #include <linux/usb/musb.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/usb_phy_generic.h>
34 #include <linux/workqueue.h>
35 #include "musb_core.h"
36
37 /*
38 * Register offsets, note sunxi musb has a different layout then most
39 * musb implementations, we translate the layout in musb_readb & friends.
40 */
41 #define SUNXI_MUSB_POWER 0x0040
42 #define SUNXI_MUSB_DEVCTL 0x0041
43 #define SUNXI_MUSB_INDEX 0x0042
44 #define SUNXI_MUSB_VEND0 0x0043
45 #define SUNXI_MUSB_INTRTX 0x0044
46 #define SUNXI_MUSB_INTRRX 0x0046
47 #define SUNXI_MUSB_INTRTXE 0x0048
48 #define SUNXI_MUSB_INTRRXE 0x004a
49 #define SUNXI_MUSB_INTRUSB 0x004c
50 #define SUNXI_MUSB_INTRUSBE 0x0050
51 #define SUNXI_MUSB_FRAME 0x0054
52 #define SUNXI_MUSB_TXFIFOSZ 0x0090
53 #define SUNXI_MUSB_TXFIFOADD 0x0092
54 #define SUNXI_MUSB_RXFIFOSZ 0x0094
55 #define SUNXI_MUSB_RXFIFOADD 0x0096
56 #define SUNXI_MUSB_FADDR 0x0098
57 #define SUNXI_MUSB_TXFUNCADDR 0x0098
58 #define SUNXI_MUSB_TXHUBADDR 0x009a
59 #define SUNXI_MUSB_TXHUBPORT 0x009b
60 #define SUNXI_MUSB_RXFUNCADDR 0x009c
61 #define SUNXI_MUSB_RXHUBADDR 0x009e
62 #define SUNXI_MUSB_RXHUBPORT 0x009f
63 #define SUNXI_MUSB_CONFIGDATA 0x00c0
64
65 /* VEND0 bits */
66 #define SUNXI_MUSB_VEND0_PIO_MODE 0
67
68 /* flags */
69 #define SUNXI_MUSB_FL_ENABLED 0
70 #define SUNXI_MUSB_FL_HOSTMODE 1
71 #define SUNXI_MUSB_FL_HOSTMODE_PEND 2
72 #define SUNXI_MUSB_FL_VBUS_ON 3
73 #define SUNXI_MUSB_FL_PHY_ON 4
74 #define SUNXI_MUSB_FL_HAS_SRAM 5
75 #define SUNXI_MUSB_FL_HAS_RESET 6
76 #define SUNXI_MUSB_FL_NO_CONFIGDATA 7
77
78 /* Our read/write methods need access and do not get passed in a musb ref :| */
79 static struct musb *sunxi_musb;
80
81 struct sunxi_glue {
82 struct device *dev;
83 struct musb *musb;
84 struct platform_device *musb_pdev;
85 struct clk *clk;
86 struct reset_control *rst;
87 struct phy *phy;
88 struct platform_device *usb_phy;
89 struct usb_phy *xceiv;
90 unsigned long flags;
91 struct work_struct work;
92 struct extcon_dev *extcon;
93 struct notifier_block host_nb;
94 };
95
96 /* phy_power_on / off may sleep, so we use a workqueue */
97 static void sunxi_musb_work(struct work_struct *work)
98 {
99 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
100 bool vbus_on, phy_on;
101
102 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
103 return;
104
105 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
106 struct musb *musb = glue->musb;
107 unsigned long flags;
108 u8 devctl;
109
110 spin_lock_irqsave(&musb->lock, flags);
111
112 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
113 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
114 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
115 musb->xceiv->otg->default_a = 1;
116 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
117 MUSB_HST_MODE(musb);
118 devctl |= MUSB_DEVCTL_SESSION;
119 } else {
120 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
121 musb->xceiv->otg->default_a = 0;
122 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
123 MUSB_DEV_MODE(musb);
124 devctl &= ~MUSB_DEVCTL_SESSION;
125 }
126 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
127
128 spin_unlock_irqrestore(&musb->lock, flags);
129 }
130
131 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
132 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
133
134 if (phy_on != vbus_on) {
135 if (vbus_on) {
136 phy_power_on(glue->phy);
137 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
138 } else {
139 phy_power_off(glue->phy);
140 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
141 }
142 }
143 }
144
145 static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
146 {
147 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
148
149 if (is_on) {
150 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
151 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
152 } else {
153 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
154 }
155
156 schedule_work(&glue->work);
157 }
158
159 static void sunxi_musb_pre_root_reset_end(struct musb *musb)
160 {
161 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
162
163 sun4i_usb_phy_set_squelch_detect(glue->phy, false);
164 }
165
166 static void sunxi_musb_post_root_reset_end(struct musb *musb)
167 {
168 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
169
170 sun4i_usb_phy_set_squelch_detect(glue->phy, true);
171 }
172
173 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
174 {
175 struct musb *musb = __hci;
176 unsigned long flags;
177
178 spin_lock_irqsave(&musb->lock, flags);
179
180 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
181 if (musb->int_usb)
182 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
183
184 /*
185 * sunxi musb often signals babble on low / full speed device
186 * disconnect, without ever raising MUSB_INTR_DISCONNECT, since
187 * normally babble never happens treat it as disconnect.
188 */
189 if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
190 musb->int_usb &= ~MUSB_INTR_BABBLE;
191 musb->int_usb |= MUSB_INTR_DISCONNECT;
192 }
193
194 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
195 /* ep0 FADDR must be 0 when (re)entering peripheral mode */
196 musb_ep_select(musb->mregs, 0);
197 musb_writeb(musb->mregs, MUSB_FADDR, 0);
198 }
199
200 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
201 if (musb->int_tx)
202 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
203
204 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
205 if (musb->int_rx)
206 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
207
208 musb_interrupt(musb);
209
210 spin_unlock_irqrestore(&musb->lock, flags);
211
212 return IRQ_HANDLED;
213 }
214
215 static int sunxi_musb_host_notifier(struct notifier_block *nb,
216 unsigned long event, void *ptr)
217 {
218 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
219
220 if (event)
221 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
222 else
223 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
224
225 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
226 schedule_work(&glue->work);
227
228 return NOTIFY_DONE;
229 }
230
231 static int sunxi_musb_init(struct musb *musb)
232 {
233 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
234 int ret;
235
236 sunxi_musb = musb;
237 musb->phy = glue->phy;
238 musb->xceiv = glue->xceiv;
239
240 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) {
241 ret = sunxi_sram_claim(musb->controller->parent);
242 if (ret)
243 return ret;
244 }
245
246 ret = clk_prepare_enable(glue->clk);
247 if (ret)
248 goto error_sram_release;
249
250 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
251 ret = reset_control_deassert(glue->rst);
252 if (ret)
253 goto error_clk_disable;
254 }
255
256 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
257
258 /* Register notifier before calling phy_init() */
259 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) {
260 ret = extcon_register_notifier(glue->extcon, EXTCON_USB_HOST,
261 &glue->host_nb);
262 if (ret)
263 goto error_reset_assert;
264 }
265
266 ret = phy_init(glue->phy);
267 if (ret)
268 goto error_unregister_notifier;
269
270 musb->isr = sunxi_musb_interrupt;
271
272 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */
273 pm_runtime_get(musb->controller);
274
275 return 0;
276
277 error_unregister_notifier:
278 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
279 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
280 &glue->host_nb);
281 error_reset_assert:
282 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
283 reset_control_assert(glue->rst);
284 error_clk_disable:
285 clk_disable_unprepare(glue->clk);
286 error_sram_release:
287 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
288 sunxi_sram_release(musb->controller->parent);
289 return ret;
290 }
291
292 static int sunxi_musb_exit(struct musb *musb)
293 {
294 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
295
296 pm_runtime_put(musb->controller);
297
298 cancel_work_sync(&glue->work);
299 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
300 phy_power_off(glue->phy);
301
302 phy_exit(glue->phy);
303
304 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
305 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
306 &glue->host_nb);
307
308 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
309 reset_control_assert(glue->rst);
310
311 clk_disable_unprepare(glue->clk);
312 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
313 sunxi_sram_release(musb->controller->parent);
314
315 return 0;
316 }
317
318 static int sunxi_set_mode(struct musb *musb, u8 mode)
319 {
320 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
321 int ret;
322
323 if (mode == MUSB_HOST) {
324 ret = phy_power_on(glue->phy);
325 if (ret)
326 return ret;
327
328 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
329 /* Stop musb work from turning vbus off again */
330 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
331 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
332 }
333
334 return 0;
335 }
336
337 static void sunxi_musb_enable(struct musb *musb)
338 {
339 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
340
341 glue->musb = musb;
342
343 /* musb_core does not call us in a balanced manner */
344 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
345 return;
346
347 schedule_work(&glue->work);
348 }
349
350 static void sunxi_musb_disable(struct musb *musb)
351 {
352 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
353
354 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
355 }
356
357 struct dma_controller *sunxi_musb_dma_controller_create(struct musb *musb,
358 void __iomem *base)
359 {
360 return NULL;
361 }
362
363 void sunxi_musb_dma_controller_destroy(struct dma_controller *c)
364 {
365 }
366
367 /*
368 * sunxi musb register layout
369 * 0x00 - 0x17 fifo regs, 1 long per fifo
370 * 0x40 - 0x57 generic control regs (power - frame)
371 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
372 * 0x90 - 0x97 fifo control regs (indexed)
373 * 0x98 - 0x9f multipoint / busctl regs (indexed)
374 * 0xc0 configdata reg
375 */
376
377 static u32 sunxi_musb_fifo_offset(u8 epnum)
378 {
379 return (epnum * 4);
380 }
381
382 static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
383 {
384 WARN_ONCE(offset != 0,
385 "sunxi_musb_ep_offset called with non 0 offset\n");
386
387 return 0x80; /* indexed, so ignore epnum */
388 }
389
390 static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
391 {
392 return SUNXI_MUSB_TXFUNCADDR + offset;
393 }
394
395 static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset)
396 {
397 struct sunxi_glue *glue;
398
399 if (addr == sunxi_musb->mregs) {
400 /* generic control or fifo control reg access */
401 switch (offset) {
402 case MUSB_FADDR:
403 return readb(addr + SUNXI_MUSB_FADDR);
404 case MUSB_POWER:
405 return readb(addr + SUNXI_MUSB_POWER);
406 case MUSB_INTRUSB:
407 return readb(addr + SUNXI_MUSB_INTRUSB);
408 case MUSB_INTRUSBE:
409 return readb(addr + SUNXI_MUSB_INTRUSBE);
410 case MUSB_INDEX:
411 return readb(addr + SUNXI_MUSB_INDEX);
412 case MUSB_TESTMODE:
413 return 0; /* No testmode on sunxi */
414 case MUSB_DEVCTL:
415 return readb(addr + SUNXI_MUSB_DEVCTL);
416 case MUSB_TXFIFOSZ:
417 return readb(addr + SUNXI_MUSB_TXFIFOSZ);
418 case MUSB_RXFIFOSZ:
419 return readb(addr + SUNXI_MUSB_RXFIFOSZ);
420 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
421 glue = dev_get_drvdata(sunxi_musb->controller->parent);
422 /* A33 saves a reg, and we get to hardcode this */
423 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA,
424 &glue->flags))
425 return 0xde;
426
427 return readb(addr + SUNXI_MUSB_CONFIGDATA);
428 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
429 case SUNXI_MUSB_TXFUNCADDR:
430 case SUNXI_MUSB_TXHUBADDR:
431 case SUNXI_MUSB_TXHUBPORT:
432 case SUNXI_MUSB_RXFUNCADDR:
433 case SUNXI_MUSB_RXHUBADDR:
434 case SUNXI_MUSB_RXHUBPORT:
435 /* multipoint / busctl reg access */
436 return readb(addr + offset);
437 default:
438 dev_err(sunxi_musb->controller->parent,
439 "Error unknown readb offset %u\n", offset);
440 return 0;
441 }
442 } else if (addr == (sunxi_musb->mregs + 0x80)) {
443 /* ep control reg access */
444 /* sunxi has a 2 byte hole before the txtype register */
445 if (offset >= MUSB_TXTYPE)
446 offset += 2;
447 return readb(addr + offset);
448 }
449
450 dev_err(sunxi_musb->controller->parent,
451 "Error unknown readb at 0x%x bytes offset\n",
452 (int)(addr - sunxi_musb->mregs));
453 return 0;
454 }
455
456 static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
457 {
458 if (addr == sunxi_musb->mregs) {
459 /* generic control or fifo control reg access */
460 switch (offset) {
461 case MUSB_FADDR:
462 return writeb(data, addr + SUNXI_MUSB_FADDR);
463 case MUSB_POWER:
464 return writeb(data, addr + SUNXI_MUSB_POWER);
465 case MUSB_INTRUSB:
466 return writeb(data, addr + SUNXI_MUSB_INTRUSB);
467 case MUSB_INTRUSBE:
468 return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
469 case MUSB_INDEX:
470 return writeb(data, addr + SUNXI_MUSB_INDEX);
471 case MUSB_TESTMODE:
472 if (data)
473 dev_warn(sunxi_musb->controller->parent,
474 "sunxi-musb does not have testmode\n");
475 return;
476 case MUSB_DEVCTL:
477 return writeb(data, addr + SUNXI_MUSB_DEVCTL);
478 case MUSB_TXFIFOSZ:
479 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
480 case MUSB_RXFIFOSZ:
481 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
482 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
483 case SUNXI_MUSB_TXFUNCADDR:
484 case SUNXI_MUSB_TXHUBADDR:
485 case SUNXI_MUSB_TXHUBPORT:
486 case SUNXI_MUSB_RXFUNCADDR:
487 case SUNXI_MUSB_RXHUBADDR:
488 case SUNXI_MUSB_RXHUBPORT:
489 /* multipoint / busctl reg access */
490 return writeb(data, addr + offset);
491 default:
492 dev_err(sunxi_musb->controller->parent,
493 "Error unknown writeb offset %u\n", offset);
494 return;
495 }
496 } else if (addr == (sunxi_musb->mregs + 0x80)) {
497 /* ep control reg access */
498 if (offset >= MUSB_TXTYPE)
499 offset += 2;
500 return writeb(data, addr + offset);
501 }
502
503 dev_err(sunxi_musb->controller->parent,
504 "Error unknown writeb at 0x%x bytes offset\n",
505 (int)(addr - sunxi_musb->mregs));
506 }
507
508 static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset)
509 {
510 if (addr == sunxi_musb->mregs) {
511 /* generic control or fifo control reg access */
512 switch (offset) {
513 case MUSB_INTRTX:
514 return readw(addr + SUNXI_MUSB_INTRTX);
515 case MUSB_INTRRX:
516 return readw(addr + SUNXI_MUSB_INTRRX);
517 case MUSB_INTRTXE:
518 return readw(addr + SUNXI_MUSB_INTRTXE);
519 case MUSB_INTRRXE:
520 return readw(addr + SUNXI_MUSB_INTRRXE);
521 case MUSB_FRAME:
522 return readw(addr + SUNXI_MUSB_FRAME);
523 case MUSB_TXFIFOADD:
524 return readw(addr + SUNXI_MUSB_TXFIFOADD);
525 case MUSB_RXFIFOADD:
526 return readw(addr + SUNXI_MUSB_RXFIFOADD);
527 case MUSB_HWVERS:
528 return 0; /* sunxi musb version is not known */
529 default:
530 dev_err(sunxi_musb->controller->parent,
531 "Error unknown readw offset %u\n", offset);
532 return 0;
533 }
534 } else if (addr == (sunxi_musb->mregs + 0x80)) {
535 /* ep control reg access */
536 return readw(addr + offset);
537 }
538
539 dev_err(sunxi_musb->controller->parent,
540 "Error unknown readw at 0x%x bytes offset\n",
541 (int)(addr - sunxi_musb->mregs));
542 return 0;
543 }
544
545 static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
546 {
547 if (addr == sunxi_musb->mregs) {
548 /* generic control or fifo control reg access */
549 switch (offset) {
550 case MUSB_INTRTX:
551 return writew(data, addr + SUNXI_MUSB_INTRTX);
552 case MUSB_INTRRX:
553 return writew(data, addr + SUNXI_MUSB_INTRRX);
554 case MUSB_INTRTXE:
555 return writew(data, addr + SUNXI_MUSB_INTRTXE);
556 case MUSB_INTRRXE:
557 return writew(data, addr + SUNXI_MUSB_INTRRXE);
558 case MUSB_FRAME:
559 return writew(data, addr + SUNXI_MUSB_FRAME);
560 case MUSB_TXFIFOADD:
561 return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
562 case MUSB_RXFIFOADD:
563 return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
564 default:
565 dev_err(sunxi_musb->controller->parent,
566 "Error unknown writew offset %u\n", offset);
567 return;
568 }
569 } else if (addr == (sunxi_musb->mregs + 0x80)) {
570 /* ep control reg access */
571 return writew(data, addr + offset);
572 }
573
574 dev_err(sunxi_musb->controller->parent,
575 "Error unknown writew at 0x%x bytes offset\n",
576 (int)(addr - sunxi_musb->mregs));
577 }
578
579 static const struct musb_platform_ops sunxi_musb_ops = {
580 .quirks = MUSB_INDEXED_EP,
581 .init = sunxi_musb_init,
582 .exit = sunxi_musb_exit,
583 .enable = sunxi_musb_enable,
584 .disable = sunxi_musb_disable,
585 .set_mode = sunxi_set_mode,
586 .fifo_offset = sunxi_musb_fifo_offset,
587 .ep_offset = sunxi_musb_ep_offset,
588 .busctl_offset = sunxi_musb_busctl_offset,
589 .readb = sunxi_musb_readb,
590 .writeb = sunxi_musb_writeb,
591 .readw = sunxi_musb_readw,
592 .writew = sunxi_musb_writew,
593 .dma_init = sunxi_musb_dma_controller_create,
594 .dma_exit = sunxi_musb_dma_controller_destroy,
595 .set_vbus = sunxi_musb_set_vbus,
596 .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
597 .post_root_reset_end = sunxi_musb_post_root_reset_end,
598 };
599
600 /* Allwinner OTG supports up to 5 endpoints */
601 #define SUNXI_MUSB_MAX_EP_NUM 6
602 #define SUNXI_MUSB_RAM_BITS 11
603
604 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
605 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
606 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
607 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
608 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
609 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
610 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
611 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
612 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
613 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
614 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
615 };
616
617 static struct musb_hdrc_config sunxi_musb_hdrc_config = {
618 .fifo_cfg = sunxi_musb_mode_cfg,
619 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
620 .multipoint = true,
621 .dyn_fifo = true,
622 .soft_con = true,
623 .num_eps = SUNXI_MUSB_MAX_EP_NUM,
624 .ram_bits = SUNXI_MUSB_RAM_BITS,
625 .dma = 0,
626 };
627
628 static int sunxi_musb_probe(struct platform_device *pdev)
629 {
630 struct musb_hdrc_platform_data pdata;
631 struct platform_device_info pinfo;
632 struct sunxi_glue *glue;
633 struct device_node *np = pdev->dev.of_node;
634 int ret;
635
636 if (!np) {
637 dev_err(&pdev->dev, "Error no device tree node found\n");
638 return -EINVAL;
639 }
640
641 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
642 if (!glue)
643 return -ENOMEM;
644
645 memset(&pdata, 0, sizeof(pdata));
646 switch (usb_get_dr_mode(&pdev->dev)) {
647 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
648 case USB_DR_MODE_HOST:
649 pdata.mode = MUSB_PORT_MODE_HOST;
650 break;
651 #endif
652 #ifdef CONFIG_USB_MUSB_DUAL_ROLE
653 case USB_DR_MODE_OTG:
654 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
655 if (IS_ERR(glue->extcon)) {
656 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
657 return -EPROBE_DEFER;
658 dev_err(&pdev->dev, "Invalid or missing extcon\n");
659 return PTR_ERR(glue->extcon);
660 }
661 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE;
662 break;
663 #endif
664 default:
665 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
666 return -EINVAL;
667 }
668 pdata.platform_ops = &sunxi_musb_ops;
669 pdata.config = &sunxi_musb_hdrc_config;
670
671 glue->dev = &pdev->dev;
672 INIT_WORK(&glue->work, sunxi_musb_work);
673 glue->host_nb.notifier_call = sunxi_musb_host_notifier;
674
675 if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
676 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
677
678 if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
679 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
680
681 if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb")) {
682 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
683 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
684 }
685
686 glue->clk = devm_clk_get(&pdev->dev, NULL);
687 if (IS_ERR(glue->clk)) {
688 dev_err(&pdev->dev, "Error getting clock: %ld\n",
689 PTR_ERR(glue->clk));
690 return PTR_ERR(glue->clk);
691 }
692
693 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
694 glue->rst = devm_reset_control_get(&pdev->dev, NULL);
695 if (IS_ERR(glue->rst)) {
696 if (PTR_ERR(glue->rst) == -EPROBE_DEFER)
697 return -EPROBE_DEFER;
698 dev_err(&pdev->dev, "Error getting reset %ld\n",
699 PTR_ERR(glue->rst));
700 return PTR_ERR(glue->rst);
701 }
702 }
703
704 glue->phy = devm_phy_get(&pdev->dev, "usb");
705 if (IS_ERR(glue->phy)) {
706 if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
707 return -EPROBE_DEFER;
708 dev_err(&pdev->dev, "Error getting phy %ld\n",
709 PTR_ERR(glue->phy));
710 return PTR_ERR(glue->phy);
711 }
712
713 glue->usb_phy = usb_phy_generic_register();
714 if (IS_ERR(glue->usb_phy)) {
715 dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
716 PTR_ERR(glue->usb_phy));
717 return PTR_ERR(glue->usb_phy);
718 }
719
720 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
721 if (IS_ERR(glue->xceiv)) {
722 ret = PTR_ERR(glue->xceiv);
723 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
724 goto err_unregister_usb_phy;
725 }
726
727 platform_set_drvdata(pdev, glue);
728
729 memset(&pinfo, 0, sizeof(pinfo));
730 pinfo.name = "musb-hdrc";
731 pinfo.id = PLATFORM_DEVID_AUTO;
732 pinfo.parent = &pdev->dev;
733 pinfo.res = pdev->resource;
734 pinfo.num_res = pdev->num_resources;
735 pinfo.data = &pdata;
736 pinfo.size_data = sizeof(pdata);
737
738 glue->musb_pdev = platform_device_register_full(&pinfo);
739 if (IS_ERR(glue->musb_pdev)) {
740 ret = PTR_ERR(glue->musb_pdev);
741 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
742 goto err_unregister_usb_phy;
743 }
744
745 return 0;
746
747 err_unregister_usb_phy:
748 usb_phy_generic_unregister(glue->usb_phy);
749 return ret;
750 }
751
752 static int sunxi_musb_remove(struct platform_device *pdev)
753 {
754 struct sunxi_glue *glue = platform_get_drvdata(pdev);
755 struct platform_device *usb_phy = glue->usb_phy;
756
757 platform_device_unregister(glue->musb_pdev);
758 usb_phy_generic_unregister(usb_phy);
759
760 return 0;
761 }
762
763 static const struct of_device_id sunxi_musb_match[] = {
764 { .compatible = "allwinner,sun4i-a10-musb", },
765 { .compatible = "allwinner,sun6i-a31-musb", },
766 { .compatible = "allwinner,sun8i-a33-musb", },
767 {}
768 };
769 MODULE_DEVICE_TABLE(of, sunxi_musb_match);
770
771 static struct platform_driver sunxi_musb_driver = {
772 .probe = sunxi_musb_probe,
773 .remove = sunxi_musb_remove,
774 .driver = {
775 .name = "musb-sunxi",
776 .of_match_table = sunxi_musb_match,
777 },
778 };
779 module_platform_driver(sunxi_musb_driver);
780
781 MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
782 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
783 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support