1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/slab.h>
25 #include <linux/interrupt.h>
26 #include <linux/err.h>
27 #include <linux/delay.h>
29 #include <linux/ioport.h>
30 #include <linux/uaccess.h>
31 #include <linux/debugfs.h>
32 #include <linux/seq_file.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/of_device.h>
36 #include <linux/reboot.h>
37 #include <linux/reset.h>
39 #include <linux/usb.h>
40 #include <linux/usb/otg.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/ulpi.h>
43 #include <linux/usb/gadget.h>
44 #include <linux/usb/hcd.h>
45 #include <linux/usb/msm_hsusb.h>
46 #include <linux/usb/msm_hsusb_hw.h>
47 #include <linux/regulator/consumer.h>
49 #define MSM_USB_BASE (motg->regs)
50 #define DRIVER_NAME "msm_otg"
52 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
53 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
55 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
56 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
57 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
58 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
60 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
61 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
62 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
63 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
65 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
66 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
67 #define USB_PHY_SUSP_DIG_VOL 500000 /* uV */
75 static int msm_hsusb_init_vddcx(struct msm_otg
*motg
, int init
)
80 ret
= regulator_set_voltage(motg
->vddcx
,
81 motg
->vdd_levels
[VDD_LEVEL_MIN
],
82 motg
->vdd_levels
[VDD_LEVEL_MAX
]);
84 dev_err(motg
->phy
.dev
, "Cannot set vddcx voltage\n");
88 ret
= regulator_enable(motg
->vddcx
);
90 dev_err(motg
->phy
.dev
, "unable to enable hsusb vddcx\n");
92 ret
= regulator_set_voltage(motg
->vddcx
, 0,
93 motg
->vdd_levels
[VDD_LEVEL_MAX
]);
95 dev_err(motg
->phy
.dev
, "Cannot set vddcx voltage\n");
96 ret
= regulator_disable(motg
->vddcx
);
98 dev_err(motg
->phy
.dev
, "unable to disable hsusb vddcx\n");
104 static int msm_hsusb_ldo_init(struct msm_otg
*motg
, int init
)
109 rc
= regulator_set_voltage(motg
->v3p3
, USB_PHY_3P3_VOL_MIN
,
110 USB_PHY_3P3_VOL_MAX
);
112 dev_err(motg
->phy
.dev
, "Cannot set v3p3 voltage\n");
115 rc
= regulator_enable(motg
->v3p3
);
117 dev_err(motg
->phy
.dev
, "unable to enable the hsusb 3p3\n");
120 rc
= regulator_set_voltage(motg
->v1p8
, USB_PHY_1P8_VOL_MIN
,
121 USB_PHY_1P8_VOL_MAX
);
123 dev_err(motg
->phy
.dev
, "Cannot set v1p8 voltage\n");
126 rc
= regulator_enable(motg
->v1p8
);
128 dev_err(motg
->phy
.dev
, "unable to enable the hsusb 1p8\n");
135 regulator_disable(motg
->v1p8
);
137 regulator_disable(motg
->v3p3
);
142 static int msm_hsusb_ldo_set_mode(struct msm_otg
*motg
, int on
)
147 ret
= regulator_set_load(motg
->v1p8
, USB_PHY_1P8_HPM_LOAD
);
149 pr_err("Could not set HPM for v1p8\n");
152 ret
= regulator_set_load(motg
->v3p3
, USB_PHY_3P3_HPM_LOAD
);
154 pr_err("Could not set HPM for v3p3\n");
155 regulator_set_load(motg
->v1p8
, USB_PHY_1P8_LPM_LOAD
);
159 ret
= regulator_set_load(motg
->v1p8
, USB_PHY_1P8_LPM_LOAD
);
161 pr_err("Could not set LPM for v1p8\n");
162 ret
= regulator_set_load(motg
->v3p3
, USB_PHY_3P3_LPM_LOAD
);
164 pr_err("Could not set LPM for v3p3\n");
167 pr_debug("reg (%s)\n", on
? "HPM" : "LPM");
168 return ret
< 0 ? ret
: 0;
171 static int ulpi_read(struct usb_phy
*phy
, u32 reg
)
173 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
176 /* initiate read operation */
177 writel(ULPI_RUN
| ULPI_READ
| ULPI_ADDR(reg
),
180 /* wait for completion */
181 while (cnt
< ULPI_IO_TIMEOUT_USEC
) {
182 if (!(readl(USB_ULPI_VIEWPORT
) & ULPI_RUN
))
188 if (cnt
>= ULPI_IO_TIMEOUT_USEC
) {
189 dev_err(phy
->dev
, "ulpi_read: timeout %08x\n",
190 readl(USB_ULPI_VIEWPORT
));
193 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT
));
196 static int ulpi_write(struct usb_phy
*phy
, u32 val
, u32 reg
)
198 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
201 /* initiate write operation */
202 writel(ULPI_RUN
| ULPI_WRITE
|
203 ULPI_ADDR(reg
) | ULPI_DATA(val
),
206 /* wait for completion */
207 while (cnt
< ULPI_IO_TIMEOUT_USEC
) {
208 if (!(readl(USB_ULPI_VIEWPORT
) & ULPI_RUN
))
214 if (cnt
>= ULPI_IO_TIMEOUT_USEC
) {
215 dev_err(phy
->dev
, "ulpi_write: timeout\n");
221 static struct usb_phy_io_ops msm_otg_io_ops
= {
226 static void ulpi_init(struct msm_otg
*motg
)
228 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
229 int *seq
= pdata
->phy_init_seq
, idx
;
230 u32 addr
= ULPI_EXT_VENDOR_SPECIFIC
;
232 for (idx
= 0; idx
< pdata
->phy_init_sz
; idx
++) {
236 dev_vdbg(motg
->phy
.dev
, "ulpi: write 0x%02x to 0x%02x\n",
237 seq
[idx
], addr
+ idx
);
238 ulpi_write(&motg
->phy
, seq
[idx
], addr
+ idx
);
242 static int msm_phy_notify_disconnect(struct usb_phy
*phy
,
243 enum usb_device_speed speed
)
245 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
248 if (motg
->manual_pullup
) {
249 val
= ULPI_MISC_A_VBUSVLDEXT
| ULPI_MISC_A_VBUSVLDEXTSEL
;
250 usb_phy_io_write(phy
, val
, ULPI_CLR(ULPI_MISC_A
));
254 * Put the transceiver in non-driving mode. Otherwise host
255 * may not detect soft-disconnection.
257 val
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
258 val
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
259 val
|= ULPI_FUNC_CTRL_OPMODE_NONDRIVING
;
260 ulpi_write(phy
, val
, ULPI_FUNC_CTRL
);
265 static int msm_otg_link_clk_reset(struct msm_otg
*motg
, bool assert)
270 ret
= reset_control_assert(motg
->link_rst
);
272 ret
= reset_control_deassert(motg
->link_rst
);
275 dev_err(motg
->phy
.dev
, "usb link clk reset %s failed\n",
276 assert ? "assert" : "deassert");
281 static int msm_otg_phy_clk_reset(struct msm_otg
*motg
)
286 ret
= reset_control_reset(motg
->phy_rst
);
289 dev_err(motg
->phy
.dev
, "usb phy clk reset failed\n");
294 static int msm_link_reset(struct msm_otg
*motg
)
299 ret
= msm_otg_link_clk_reset(motg
, 1);
303 /* wait for 1ms delay as suggested in HPG. */
304 usleep_range(1000, 1200);
306 ret
= msm_otg_link_clk_reset(motg
, 0);
310 if (motg
->phy_number
)
311 writel(readl(USB_PHY_CTRL2
) | BIT(16), USB_PHY_CTRL2
);
313 /* put transceiver in serial mode as part of reset */
314 val
= readl(USB_PORTSC
) & ~PORTSC_PTS_MASK
;
315 writel(val
| PORTSC_PTS_SERIAL
, USB_PORTSC
);
320 static int msm_otg_reset(struct usb_phy
*phy
)
322 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
325 writel(USBCMD_RESET
, USB_USBCMD
);
326 while (cnt
< LINK_RESET_TIMEOUT_USEC
) {
327 if (!(readl(USB_USBCMD
) & USBCMD_RESET
))
332 if (cnt
>= LINK_RESET_TIMEOUT_USEC
)
335 /* select ULPI phy and clear other status/control bits in PORTSC */
336 writel(PORTSC_PTS_ULPI
, USB_PORTSC
);
338 writel(0x0, USB_AHBBURST
);
339 writel(0x08, USB_AHBMODE
);
341 if (motg
->phy_number
)
342 writel(readl(USB_PHY_CTRL2
) | BIT(16), USB_PHY_CTRL2
);
346 static void msm_phy_reset(struct msm_otg
*motg
)
350 if (motg
->pdata
->phy_type
!= SNPS_28NM_INTEGRATED_PHY
) {
351 msm_otg_phy_clk_reset(motg
);
356 if (motg
->phy_number
)
357 addr
= USB_PHY_CTRL2
;
359 /* Assert USB PHY_POR */
360 writel(readl(addr
) | PHY_POR_ASSERT
, addr
);
363 * wait for minimum 10 microseconds as suggested in HPG.
364 * Use a slightly larger value since the exact value didn't
365 * work 100% of the time.
369 /* Deassert USB PHY_POR */
370 writel(readl(addr
) & ~PHY_POR_ASSERT
, addr
);
373 static int msm_usb_reset(struct usb_phy
*phy
)
375 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
378 if (!IS_ERR(motg
->core_clk
))
379 clk_prepare_enable(motg
->core_clk
);
381 ret
= msm_link_reset(motg
);
383 dev_err(phy
->dev
, "phy_reset failed\n");
387 ret
= msm_otg_reset(&motg
->phy
);
389 dev_err(phy
->dev
, "link reset failed\n");
395 /* Reset USB PHY after performing USB Link RESET */
398 if (!IS_ERR(motg
->core_clk
))
399 clk_disable_unprepare(motg
->core_clk
);
404 static int msm_phy_init(struct usb_phy
*phy
)
406 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
407 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
408 u32 val
, ulpi_val
= 0;
410 /* Program USB PHY Override registers. */
414 * It is recommended in HPG to reset USB PHY after programming
415 * USB PHY Override registers.
419 if (pdata
->otg_control
== OTG_PHY_CONTROL
) {
420 val
= readl(USB_OTGSC
);
421 if (pdata
->mode
== USB_DR_MODE_OTG
) {
422 ulpi_val
= ULPI_INT_IDGRD
| ULPI_INT_SESS_VALID
;
423 val
|= OTGSC_IDIE
| OTGSC_BSVIE
;
424 } else if (pdata
->mode
== USB_DR_MODE_PERIPHERAL
) {
425 ulpi_val
= ULPI_INT_SESS_VALID
;
428 writel(val
, USB_OTGSC
);
429 ulpi_write(phy
, ulpi_val
, ULPI_USB_INT_EN_RISE
);
430 ulpi_write(phy
, ulpi_val
, ULPI_USB_INT_EN_FALL
);
433 if (motg
->manual_pullup
) {
434 val
= ULPI_MISC_A_VBUSVLDEXTSEL
| ULPI_MISC_A_VBUSVLDEXT
;
435 ulpi_write(phy
, val
, ULPI_SET(ULPI_MISC_A
));
437 val
= readl(USB_GENCONFIG_2
);
438 val
|= GENCONFIG_2_SESS_VLD_CTRL_EN
;
439 writel(val
, USB_GENCONFIG_2
);
441 val
= readl(USB_USBCMD
);
442 val
|= USBCMD_SESS_VLD_CTRL
;
443 writel(val
, USB_USBCMD
);
445 val
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
446 val
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
447 val
|= ULPI_FUNC_CTRL_OPMODE_NORMAL
;
448 ulpi_write(phy
, val
, ULPI_FUNC_CTRL
);
451 if (motg
->phy_number
)
452 writel(readl(USB_PHY_CTRL2
) | BIT(16), USB_PHY_CTRL2
);
457 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
458 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
462 static int msm_hsusb_config_vddcx(struct msm_otg
*motg
, int high
)
464 int max_vol
= motg
->vdd_levels
[VDD_LEVEL_MAX
];
469 min_vol
= motg
->vdd_levels
[VDD_LEVEL_MIN
];
471 min_vol
= motg
->vdd_levels
[VDD_LEVEL_NONE
];
473 ret
= regulator_set_voltage(motg
->vddcx
, min_vol
, max_vol
);
475 pr_err("Cannot set vddcx voltage\n");
479 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__
, min_vol
, max_vol
);
484 static int msm_otg_suspend(struct msm_otg
*motg
)
486 struct usb_phy
*phy
= &motg
->phy
;
487 struct usb_bus
*bus
= phy
->otg
->host
;
488 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
492 if (atomic_read(&motg
->in_lpm
))
495 disable_irq(motg
->irq
);
497 * Chipidea 45-nm PHY suspend sequence:
499 * Interrupt Latch Register auto-clear feature is not present
500 * in all PHY versions. Latch register is clear on read type.
501 * Clear latch register to avoid spurious wakeup from
502 * low power mode (LPM).
504 * PHY comparators are disabled when PHY enters into low power
505 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
506 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
507 * PHY comparators. This save significant amount of power.
509 * PLL is not turned off when PHY enters into low power mode (LPM).
510 * Disable PLL for maximum power savings.
513 if (motg
->pdata
->phy_type
== CI_45NM_INTEGRATED_PHY
) {
514 ulpi_read(phy
, 0x14);
515 if (pdata
->otg_control
== OTG_PHY_CONTROL
)
516 ulpi_write(phy
, 0x01, 0x30);
517 ulpi_write(phy
, 0x08, 0x09);
521 * PHY may take some time or even fail to enter into low power
522 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
525 writel(readl(USB_PORTSC
) | PORTSC_PHCD
, USB_PORTSC
);
526 while (cnt
< PHY_SUSPEND_TIMEOUT_USEC
) {
527 if (readl(USB_PORTSC
) & PORTSC_PHCD
)
533 if (cnt
>= PHY_SUSPEND_TIMEOUT_USEC
) {
534 dev_err(phy
->dev
, "Unable to suspend PHY\n");
536 enable_irq(motg
->irq
);
541 * PHY has capability to generate interrupt asynchronously in low
542 * power mode (LPM). This interrupt is level triggered. So USB IRQ
543 * line must be disabled till async interrupt enable bit is cleared
544 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
545 * block data communication from PHY.
547 writel(readl(USB_USBCMD
) | ASYNC_INTR_CTRL
| ULPI_STP_CTRL
, USB_USBCMD
);
550 if (motg
->phy_number
)
551 addr
= USB_PHY_CTRL2
;
553 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
554 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
)
555 writel(readl(addr
) | PHY_RETEN
, addr
);
557 clk_disable_unprepare(motg
->pclk
);
558 clk_disable_unprepare(motg
->clk
);
559 if (!IS_ERR(motg
->core_clk
))
560 clk_disable_unprepare(motg
->core_clk
);
562 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
563 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
) {
564 msm_hsusb_ldo_set_mode(motg
, 0);
565 msm_hsusb_config_vddcx(motg
, 0);
568 if (device_may_wakeup(phy
->dev
))
569 enable_irq_wake(motg
->irq
);
571 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &(bus_to_hcd(bus
))->flags
);
573 atomic_set(&motg
->in_lpm
, 1);
574 enable_irq(motg
->irq
);
576 dev_info(phy
->dev
, "USB in low power mode\n");
581 static int msm_otg_resume(struct msm_otg
*motg
)
583 struct usb_phy
*phy
= &motg
->phy
;
584 struct usb_bus
*bus
= phy
->otg
->host
;
589 if (!atomic_read(&motg
->in_lpm
))
592 clk_prepare_enable(motg
->pclk
);
593 clk_prepare_enable(motg
->clk
);
594 if (!IS_ERR(motg
->core_clk
))
595 clk_prepare_enable(motg
->core_clk
);
597 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
598 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
) {
601 if (motg
->phy_number
)
602 addr
= USB_PHY_CTRL2
;
604 msm_hsusb_ldo_set_mode(motg
, 1);
605 msm_hsusb_config_vddcx(motg
, 1);
606 writel(readl(addr
) & ~PHY_RETEN
, addr
);
609 temp
= readl(USB_USBCMD
);
610 temp
&= ~ASYNC_INTR_CTRL
;
611 temp
&= ~ULPI_STP_CTRL
;
612 writel(temp
, USB_USBCMD
);
615 * PHY comes out of low power mode (LPM) in case of wakeup
616 * from asynchronous interrupt.
618 if (!(readl(USB_PORTSC
) & PORTSC_PHCD
))
619 goto skip_phy_resume
;
621 writel(readl(USB_PORTSC
) & ~PORTSC_PHCD
, USB_PORTSC
);
622 while (cnt
< PHY_RESUME_TIMEOUT_USEC
) {
623 if (!(readl(USB_PORTSC
) & PORTSC_PHCD
))
629 if (cnt
>= PHY_RESUME_TIMEOUT_USEC
) {
631 * This is a fatal error. Reset the link and
632 * PHY. USB state can not be restored. Re-insertion
633 * of USB cable is the only way to get USB working.
635 dev_err(phy
->dev
, "Unable to resume USB. Re-plugin the cable\n");
640 if (device_may_wakeup(phy
->dev
))
641 disable_irq_wake(motg
->irq
);
643 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &(bus_to_hcd(bus
))->flags
);
645 atomic_set(&motg
->in_lpm
, 0);
647 if (motg
->async_int
) {
649 pm_runtime_put(phy
->dev
);
650 enable_irq(motg
->irq
);
653 dev_info(phy
->dev
, "USB exited from low power mode\n");
659 static void msm_otg_notify_charger(struct msm_otg
*motg
, unsigned mA
)
661 if (motg
->cur_power
== mA
)
664 /* TODO: Notify PMIC about available current */
665 dev_info(motg
->phy
.dev
, "Avail curr from USB = %u\n", mA
);
666 motg
->cur_power
= mA
;
669 static int msm_otg_set_power(struct usb_phy
*phy
, unsigned mA
)
671 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
674 * Gadget driver uses set_power method to notify about the
675 * available current based on suspend/configured states.
677 * IDEV_CHG can be drawn irrespective of suspend/un-configured
678 * states when CDP/ACA is connected.
680 if (motg
->chg_type
== USB_SDP_CHARGER
)
681 msm_otg_notify_charger(motg
, mA
);
686 static void msm_otg_start_host(struct usb_phy
*phy
, int on
)
688 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
689 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
695 hcd
= bus_to_hcd(phy
->otg
->host
);
698 dev_dbg(phy
->dev
, "host on\n");
700 if (pdata
->vbus_power
)
701 pdata
->vbus_power(1);
703 * Some boards have a switch cotrolled by gpio
704 * to enable/disable internal HUB. Enable internal
705 * HUB before kicking the host.
707 if (pdata
->setup_gpio
)
708 pdata
->setup_gpio(OTG_STATE_A_HOST
);
710 usb_add_hcd(hcd
, hcd
->irq
, IRQF_SHARED
);
711 device_wakeup_enable(hcd
->self
.controller
);
714 dev_dbg(phy
->dev
, "host off\n");
719 if (pdata
->setup_gpio
)
720 pdata
->setup_gpio(OTG_STATE_UNDEFINED
);
721 if (pdata
->vbus_power
)
722 pdata
->vbus_power(0);
726 static int msm_otg_set_host(struct usb_otg
*otg
, struct usb_bus
*host
)
728 struct msm_otg
*motg
= container_of(otg
->usb_phy
, struct msm_otg
, phy
);
732 * Fail host registration if this board can support
733 * only peripheral configuration.
735 if (motg
->pdata
->mode
== USB_DR_MODE_PERIPHERAL
) {
736 dev_info(otg
->usb_phy
->dev
, "Host mode is not supported\n");
741 if (otg
->state
== OTG_STATE_A_HOST
) {
742 pm_runtime_get_sync(otg
->usb_phy
->dev
);
743 msm_otg_start_host(otg
->usb_phy
, 0);
745 otg
->state
= OTG_STATE_UNDEFINED
;
746 schedule_work(&motg
->sm_work
);
754 hcd
= bus_to_hcd(host
);
755 hcd
->power_budget
= motg
->pdata
->power_budget
;
758 dev_dbg(otg
->usb_phy
->dev
, "host driver registered w/ tranceiver\n");
760 pm_runtime_get_sync(otg
->usb_phy
->dev
);
761 schedule_work(&motg
->sm_work
);
766 static void msm_otg_start_peripheral(struct usb_phy
*phy
, int on
)
768 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
769 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
771 if (!phy
->otg
->gadget
)
775 dev_dbg(phy
->dev
, "gadget on\n");
777 * Some boards have a switch cotrolled by gpio
778 * to enable/disable internal HUB. Disable internal
779 * HUB before kicking the gadget.
781 if (pdata
->setup_gpio
)
782 pdata
->setup_gpio(OTG_STATE_B_PERIPHERAL
);
783 usb_gadget_vbus_connect(phy
->otg
->gadget
);
785 dev_dbg(phy
->dev
, "gadget off\n");
786 usb_gadget_vbus_disconnect(phy
->otg
->gadget
);
787 if (pdata
->setup_gpio
)
788 pdata
->setup_gpio(OTG_STATE_UNDEFINED
);
793 static int msm_otg_set_peripheral(struct usb_otg
*otg
,
794 struct usb_gadget
*gadget
)
796 struct msm_otg
*motg
= container_of(otg
->usb_phy
, struct msm_otg
, phy
);
799 * Fail peripheral registration if this board can support
800 * only host configuration.
802 if (motg
->pdata
->mode
== USB_DR_MODE_HOST
) {
803 dev_info(otg
->usb_phy
->dev
, "Peripheral mode is not supported\n");
808 if (otg
->state
== OTG_STATE_B_PERIPHERAL
) {
809 pm_runtime_get_sync(otg
->usb_phy
->dev
);
810 msm_otg_start_peripheral(otg
->usb_phy
, 0);
812 otg
->state
= OTG_STATE_UNDEFINED
;
813 schedule_work(&motg
->sm_work
);
820 otg
->gadget
= gadget
;
821 dev_dbg(otg
->usb_phy
->dev
,
822 "peripheral driver registered w/ tranceiver\n");
824 pm_runtime_get_sync(otg
->usb_phy
->dev
);
825 schedule_work(&motg
->sm_work
);
830 static bool msm_chg_check_secondary_det(struct msm_otg
*motg
)
832 struct usb_phy
*phy
= &motg
->phy
;
836 switch (motg
->pdata
->phy_type
) {
837 case CI_45NM_INTEGRATED_PHY
:
838 chg_det
= ulpi_read(phy
, 0x34);
839 ret
= chg_det
& (1 << 4);
841 case SNPS_28NM_INTEGRATED_PHY
:
842 chg_det
= ulpi_read(phy
, 0x87);
851 static void msm_chg_enable_secondary_det(struct msm_otg
*motg
)
853 struct usb_phy
*phy
= &motg
->phy
;
856 switch (motg
->pdata
->phy_type
) {
857 case CI_45NM_INTEGRATED_PHY
:
858 chg_det
= ulpi_read(phy
, 0x34);
859 /* Turn off charger block */
860 chg_det
|= ~(1 << 1);
861 ulpi_write(phy
, chg_det
, 0x34);
863 /* control chg block via ULPI */
864 chg_det
&= ~(1 << 3);
865 ulpi_write(phy
, chg_det
, 0x34);
866 /* put it in host mode for enabling D- source */
867 chg_det
&= ~(1 << 2);
868 ulpi_write(phy
, chg_det
, 0x34);
869 /* Turn on chg detect block */
870 chg_det
&= ~(1 << 1);
871 ulpi_write(phy
, chg_det
, 0x34);
873 /* enable chg detection */
874 chg_det
&= ~(1 << 0);
875 ulpi_write(phy
, chg_det
, 0x34);
877 case SNPS_28NM_INTEGRATED_PHY
:
879 * Configure DM as current source, DP as current sink
880 * and enable battery charging comparators.
882 ulpi_write(phy
, 0x8, 0x85);
883 ulpi_write(phy
, 0x2, 0x85);
884 ulpi_write(phy
, 0x1, 0x85);
891 static bool msm_chg_check_primary_det(struct msm_otg
*motg
)
893 struct usb_phy
*phy
= &motg
->phy
;
897 switch (motg
->pdata
->phy_type
) {
898 case CI_45NM_INTEGRATED_PHY
:
899 chg_det
= ulpi_read(phy
, 0x34);
900 ret
= chg_det
& (1 << 4);
902 case SNPS_28NM_INTEGRATED_PHY
:
903 chg_det
= ulpi_read(phy
, 0x87);
912 static void msm_chg_enable_primary_det(struct msm_otg
*motg
)
914 struct usb_phy
*phy
= &motg
->phy
;
917 switch (motg
->pdata
->phy_type
) {
918 case CI_45NM_INTEGRATED_PHY
:
919 chg_det
= ulpi_read(phy
, 0x34);
920 /* enable chg detection */
921 chg_det
&= ~(1 << 0);
922 ulpi_write(phy
, chg_det
, 0x34);
924 case SNPS_28NM_INTEGRATED_PHY
:
926 * Configure DP as current source, DM as current sink
927 * and enable battery charging comparators.
929 ulpi_write(phy
, 0x2, 0x85);
930 ulpi_write(phy
, 0x1, 0x85);
937 static bool msm_chg_check_dcd(struct msm_otg
*motg
)
939 struct usb_phy
*phy
= &motg
->phy
;
943 switch (motg
->pdata
->phy_type
) {
944 case CI_45NM_INTEGRATED_PHY
:
945 line_state
= ulpi_read(phy
, 0x15);
946 ret
= !(line_state
& 1);
948 case SNPS_28NM_INTEGRATED_PHY
:
949 line_state
= ulpi_read(phy
, 0x87);
950 ret
= line_state
& 2;
958 static void msm_chg_disable_dcd(struct msm_otg
*motg
)
960 struct usb_phy
*phy
= &motg
->phy
;
963 switch (motg
->pdata
->phy_type
) {
964 case CI_45NM_INTEGRATED_PHY
:
965 chg_det
= ulpi_read(phy
, 0x34);
966 chg_det
&= ~(1 << 5);
967 ulpi_write(phy
, chg_det
, 0x34);
969 case SNPS_28NM_INTEGRATED_PHY
:
970 ulpi_write(phy
, 0x10, 0x86);
977 static void msm_chg_enable_dcd(struct msm_otg
*motg
)
979 struct usb_phy
*phy
= &motg
->phy
;
982 switch (motg
->pdata
->phy_type
) {
983 case CI_45NM_INTEGRATED_PHY
:
984 chg_det
= ulpi_read(phy
, 0x34);
985 /* Turn on D+ current source */
987 ulpi_write(phy
, chg_det
, 0x34);
989 case SNPS_28NM_INTEGRATED_PHY
:
990 /* Data contact detection enable */
991 ulpi_write(phy
, 0x10, 0x85);
998 static void msm_chg_block_on(struct msm_otg
*motg
)
1000 struct usb_phy
*phy
= &motg
->phy
;
1001 u32 func_ctrl
, chg_det
;
1003 /* put the controller in non-driving mode */
1004 func_ctrl
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
1005 func_ctrl
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
1006 func_ctrl
|= ULPI_FUNC_CTRL_OPMODE_NONDRIVING
;
1007 ulpi_write(phy
, func_ctrl
, ULPI_FUNC_CTRL
);
1009 switch (motg
->pdata
->phy_type
) {
1010 case CI_45NM_INTEGRATED_PHY
:
1011 chg_det
= ulpi_read(phy
, 0x34);
1012 /* control chg block via ULPI */
1013 chg_det
&= ~(1 << 3);
1014 ulpi_write(phy
, chg_det
, 0x34);
1015 /* Turn on chg detect block */
1016 chg_det
&= ~(1 << 1);
1017 ulpi_write(phy
, chg_det
, 0x34);
1020 case SNPS_28NM_INTEGRATED_PHY
:
1021 /* Clear charger detecting control bits */
1022 ulpi_write(phy
, 0x3F, 0x86);
1023 /* Clear alt interrupt latch and enable bits */
1024 ulpi_write(phy
, 0x1F, 0x92);
1025 ulpi_write(phy
, 0x1F, 0x95);
1033 static void msm_chg_block_off(struct msm_otg
*motg
)
1035 struct usb_phy
*phy
= &motg
->phy
;
1036 u32 func_ctrl
, chg_det
;
1038 switch (motg
->pdata
->phy_type
) {
1039 case CI_45NM_INTEGRATED_PHY
:
1040 chg_det
= ulpi_read(phy
, 0x34);
1041 /* Turn off charger block */
1042 chg_det
|= ~(1 << 1);
1043 ulpi_write(phy
, chg_det
, 0x34);
1045 case SNPS_28NM_INTEGRATED_PHY
:
1046 /* Clear charger detecting control bits */
1047 ulpi_write(phy
, 0x3F, 0x86);
1048 /* Clear alt interrupt latch and enable bits */
1049 ulpi_write(phy
, 0x1F, 0x92);
1050 ulpi_write(phy
, 0x1F, 0x95);
1056 /* put the controller in normal mode */
1057 func_ctrl
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
1058 func_ctrl
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
1059 func_ctrl
|= ULPI_FUNC_CTRL_OPMODE_NORMAL
;
1060 ulpi_write(phy
, func_ctrl
, ULPI_FUNC_CTRL
);
1063 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1064 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1065 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1066 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1067 static void msm_chg_detect_work(struct work_struct
*w
)
1069 struct msm_otg
*motg
= container_of(w
, struct msm_otg
, chg_work
.work
);
1070 struct usb_phy
*phy
= &motg
->phy
;
1071 bool is_dcd
, tmout
, vout
;
1072 unsigned long delay
;
1074 dev_dbg(phy
->dev
, "chg detection work\n");
1075 switch (motg
->chg_state
) {
1076 case USB_CHG_STATE_UNDEFINED
:
1077 pm_runtime_get_sync(phy
->dev
);
1078 msm_chg_block_on(motg
);
1079 msm_chg_enable_dcd(motg
);
1080 motg
->chg_state
= USB_CHG_STATE_WAIT_FOR_DCD
;
1081 motg
->dcd_retries
= 0;
1082 delay
= MSM_CHG_DCD_POLL_TIME
;
1084 case USB_CHG_STATE_WAIT_FOR_DCD
:
1085 is_dcd
= msm_chg_check_dcd(motg
);
1086 tmout
= ++motg
->dcd_retries
== MSM_CHG_DCD_MAX_RETRIES
;
1087 if (is_dcd
|| tmout
) {
1088 msm_chg_disable_dcd(motg
);
1089 msm_chg_enable_primary_det(motg
);
1090 delay
= MSM_CHG_PRIMARY_DET_TIME
;
1091 motg
->chg_state
= USB_CHG_STATE_DCD_DONE
;
1093 delay
= MSM_CHG_DCD_POLL_TIME
;
1096 case USB_CHG_STATE_DCD_DONE
:
1097 vout
= msm_chg_check_primary_det(motg
);
1099 msm_chg_enable_secondary_det(motg
);
1100 delay
= MSM_CHG_SECONDARY_DET_TIME
;
1101 motg
->chg_state
= USB_CHG_STATE_PRIMARY_DONE
;
1103 motg
->chg_type
= USB_SDP_CHARGER
;
1104 motg
->chg_state
= USB_CHG_STATE_DETECTED
;
1108 case USB_CHG_STATE_PRIMARY_DONE
:
1109 vout
= msm_chg_check_secondary_det(motg
);
1111 motg
->chg_type
= USB_DCP_CHARGER
;
1113 motg
->chg_type
= USB_CDP_CHARGER
;
1114 motg
->chg_state
= USB_CHG_STATE_SECONDARY_DONE
;
1116 case USB_CHG_STATE_SECONDARY_DONE
:
1117 motg
->chg_state
= USB_CHG_STATE_DETECTED
;
1118 case USB_CHG_STATE_DETECTED
:
1119 msm_chg_block_off(motg
);
1120 dev_dbg(phy
->dev
, "charger = %d\n", motg
->chg_type
);
1121 schedule_work(&motg
->sm_work
);
1127 schedule_delayed_work(&motg
->chg_work
, delay
);
1131 * We support OTG, Peripheral only and Host only configurations. In case
1132 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1133 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1134 * enabled when switch is controlled by user and default mode is supplied
1135 * by board file, which can be changed by userspace later.
1137 static void msm_otg_init_sm(struct msm_otg
*motg
)
1139 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
1140 u32 otgsc
= readl(USB_OTGSC
);
1142 switch (pdata
->mode
) {
1143 case USB_DR_MODE_OTG
:
1144 if (pdata
->otg_control
== OTG_PHY_CONTROL
) {
1145 if (otgsc
& OTGSC_ID
)
1146 set_bit(ID
, &motg
->inputs
);
1148 clear_bit(ID
, &motg
->inputs
);
1150 if (otgsc
& OTGSC_BSV
)
1151 set_bit(B_SESS_VLD
, &motg
->inputs
);
1153 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1154 } else if (pdata
->otg_control
== OTG_USER_CONTROL
) {
1155 set_bit(ID
, &motg
->inputs
);
1156 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1159 case USB_DR_MODE_HOST
:
1160 clear_bit(ID
, &motg
->inputs
);
1162 case USB_DR_MODE_PERIPHERAL
:
1163 set_bit(ID
, &motg
->inputs
);
1164 if (otgsc
& OTGSC_BSV
)
1165 set_bit(B_SESS_VLD
, &motg
->inputs
);
1167 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1174 static void msm_otg_sm_work(struct work_struct
*w
)
1176 struct msm_otg
*motg
= container_of(w
, struct msm_otg
, sm_work
);
1177 struct usb_otg
*otg
= motg
->phy
.otg
;
1179 switch (otg
->state
) {
1180 case OTG_STATE_UNDEFINED
:
1181 dev_dbg(otg
->usb_phy
->dev
, "OTG_STATE_UNDEFINED state\n");
1182 msm_otg_reset(otg
->usb_phy
);
1183 msm_otg_init_sm(motg
);
1184 otg
->state
= OTG_STATE_B_IDLE
;
1186 case OTG_STATE_B_IDLE
:
1187 dev_dbg(otg
->usb_phy
->dev
, "OTG_STATE_B_IDLE state\n");
1188 if (!test_bit(ID
, &motg
->inputs
) && otg
->host
) {
1189 /* disable BSV bit */
1190 writel(readl(USB_OTGSC
) & ~OTGSC_BSVIE
, USB_OTGSC
);
1191 msm_otg_start_host(otg
->usb_phy
, 1);
1192 otg
->state
= OTG_STATE_A_HOST
;
1193 } else if (test_bit(B_SESS_VLD
, &motg
->inputs
)) {
1194 switch (motg
->chg_state
) {
1195 case USB_CHG_STATE_UNDEFINED
:
1196 msm_chg_detect_work(&motg
->chg_work
.work
);
1198 case USB_CHG_STATE_DETECTED
:
1199 switch (motg
->chg_type
) {
1200 case USB_DCP_CHARGER
:
1201 msm_otg_notify_charger(motg
,
1204 case USB_CDP_CHARGER
:
1205 msm_otg_notify_charger(motg
,
1207 msm_otg_start_peripheral(otg
->usb_phy
,
1210 = OTG_STATE_B_PERIPHERAL
;
1212 case USB_SDP_CHARGER
:
1213 msm_otg_notify_charger(motg
, IUNIT
);
1214 msm_otg_start_peripheral(otg
->usb_phy
,
1217 = OTG_STATE_B_PERIPHERAL
;
1228 * If charger detection work is pending, decrement
1229 * the pm usage counter to balance with the one that
1230 * is incremented in charger detection work.
1232 if (cancel_delayed_work_sync(&motg
->chg_work
)) {
1233 pm_runtime_put_sync(otg
->usb_phy
->dev
);
1234 msm_otg_reset(otg
->usb_phy
);
1236 msm_otg_notify_charger(motg
, 0);
1237 motg
->chg_state
= USB_CHG_STATE_UNDEFINED
;
1238 motg
->chg_type
= USB_INVALID_CHARGER
;
1241 if (otg
->state
== OTG_STATE_B_IDLE
)
1242 pm_runtime_put_sync(otg
->usb_phy
->dev
);
1244 case OTG_STATE_B_PERIPHERAL
:
1245 dev_dbg(otg
->usb_phy
->dev
, "OTG_STATE_B_PERIPHERAL state\n");
1246 if (!test_bit(B_SESS_VLD
, &motg
->inputs
) ||
1247 !test_bit(ID
, &motg
->inputs
)) {
1248 msm_otg_notify_charger(motg
, 0);
1249 msm_otg_start_peripheral(otg
->usb_phy
, 0);
1250 motg
->chg_state
= USB_CHG_STATE_UNDEFINED
;
1251 motg
->chg_type
= USB_INVALID_CHARGER
;
1252 otg
->state
= OTG_STATE_B_IDLE
;
1253 msm_otg_reset(otg
->usb_phy
);
1257 case OTG_STATE_A_HOST
:
1258 dev_dbg(otg
->usb_phy
->dev
, "OTG_STATE_A_HOST state\n");
1259 if (test_bit(ID
, &motg
->inputs
)) {
1260 msm_otg_start_host(otg
->usb_phy
, 0);
1261 otg
->state
= OTG_STATE_B_IDLE
;
1262 msm_otg_reset(otg
->usb_phy
);
1271 static irqreturn_t
msm_otg_irq(int irq
, void *data
)
1273 struct msm_otg
*motg
= data
;
1274 struct usb_phy
*phy
= &motg
->phy
;
1277 if (atomic_read(&motg
->in_lpm
)) {
1278 disable_irq_nosync(irq
);
1279 motg
->async_int
= 1;
1280 pm_runtime_get(phy
->dev
);
1284 otgsc
= readl(USB_OTGSC
);
1285 if (!(otgsc
& (OTGSC_IDIS
| OTGSC_BSVIS
)))
1288 if ((otgsc
& OTGSC_IDIS
) && (otgsc
& OTGSC_IDIE
)) {
1289 if (otgsc
& OTGSC_ID
)
1290 set_bit(ID
, &motg
->inputs
);
1292 clear_bit(ID
, &motg
->inputs
);
1293 dev_dbg(phy
->dev
, "ID set/clear\n");
1294 pm_runtime_get_noresume(phy
->dev
);
1295 } else if ((otgsc
& OTGSC_BSVIS
) && (otgsc
& OTGSC_BSVIE
)) {
1296 if (otgsc
& OTGSC_BSV
)
1297 set_bit(B_SESS_VLD
, &motg
->inputs
);
1299 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1300 dev_dbg(phy
->dev
, "BSV set/clear\n");
1301 pm_runtime_get_noresume(phy
->dev
);
1304 writel(otgsc
, USB_OTGSC
);
1305 schedule_work(&motg
->sm_work
);
1309 static int msm_otg_mode_show(struct seq_file
*s
, void *unused
)
1311 struct msm_otg
*motg
= s
->private;
1312 struct usb_otg
*otg
= motg
->phy
.otg
;
1314 switch (otg
->state
) {
1315 case OTG_STATE_A_HOST
:
1316 seq_puts(s
, "host\n");
1318 case OTG_STATE_B_PERIPHERAL
:
1319 seq_puts(s
, "peripheral\n");
1322 seq_puts(s
, "none\n");
1329 static int msm_otg_mode_open(struct inode
*inode
, struct file
*file
)
1331 return single_open(file
, msm_otg_mode_show
, inode
->i_private
);
1334 static ssize_t
msm_otg_mode_write(struct file
*file
, const char __user
*ubuf
,
1335 size_t count
, loff_t
*ppos
)
1337 struct seq_file
*s
= file
->private_data
;
1338 struct msm_otg
*motg
= s
->private;
1340 struct usb_otg
*otg
= motg
->phy
.otg
;
1342 enum usb_dr_mode req_mode
;
1344 memset(buf
, 0x00, sizeof(buf
));
1346 if (copy_from_user(&buf
, ubuf
, min_t(size_t, sizeof(buf
) - 1, count
))) {
1351 if (!strncmp(buf
, "host", 4)) {
1352 req_mode
= USB_DR_MODE_HOST
;
1353 } else if (!strncmp(buf
, "peripheral", 10)) {
1354 req_mode
= USB_DR_MODE_PERIPHERAL
;
1355 } else if (!strncmp(buf
, "none", 4)) {
1356 req_mode
= USB_DR_MODE_UNKNOWN
;
1363 case USB_DR_MODE_UNKNOWN
:
1364 switch (otg
->state
) {
1365 case OTG_STATE_A_HOST
:
1366 case OTG_STATE_B_PERIPHERAL
:
1367 set_bit(ID
, &motg
->inputs
);
1368 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1374 case USB_DR_MODE_PERIPHERAL
:
1375 switch (otg
->state
) {
1376 case OTG_STATE_B_IDLE
:
1377 case OTG_STATE_A_HOST
:
1378 set_bit(ID
, &motg
->inputs
);
1379 set_bit(B_SESS_VLD
, &motg
->inputs
);
1385 case USB_DR_MODE_HOST
:
1386 switch (otg
->state
) {
1387 case OTG_STATE_B_IDLE
:
1388 case OTG_STATE_B_PERIPHERAL
:
1389 clear_bit(ID
, &motg
->inputs
);
1399 pm_runtime_get_sync(otg
->usb_phy
->dev
);
1400 schedule_work(&motg
->sm_work
);
1405 static const struct file_operations msm_otg_mode_fops
= {
1406 .open
= msm_otg_mode_open
,
1408 .write
= msm_otg_mode_write
,
1409 .llseek
= seq_lseek
,
1410 .release
= single_release
,
1413 static struct dentry
*msm_otg_dbg_root
;
1414 static struct dentry
*msm_otg_dbg_mode
;
1416 static int msm_otg_debugfs_init(struct msm_otg
*motg
)
1418 msm_otg_dbg_root
= debugfs_create_dir("msm_otg", NULL
);
1420 if (!msm_otg_dbg_root
|| IS_ERR(msm_otg_dbg_root
))
1423 msm_otg_dbg_mode
= debugfs_create_file("mode", S_IRUGO
| S_IWUSR
,
1424 msm_otg_dbg_root
, motg
, &msm_otg_mode_fops
);
1425 if (!msm_otg_dbg_mode
) {
1426 debugfs_remove(msm_otg_dbg_root
);
1427 msm_otg_dbg_root
= NULL
;
1434 static void msm_otg_debugfs_cleanup(void)
1436 debugfs_remove(msm_otg_dbg_mode
);
1437 debugfs_remove(msm_otg_dbg_root
);
1440 static const struct of_device_id msm_otg_dt_match
[] = {
1442 .compatible
= "qcom,usb-otg-ci",
1443 .data
= (void *) CI_45NM_INTEGRATED_PHY
1446 .compatible
= "qcom,usb-otg-snps",
1447 .data
= (void *) SNPS_28NM_INTEGRATED_PHY
1451 MODULE_DEVICE_TABLE(of
, msm_otg_dt_match
);
1453 static int msm_otg_vbus_notifier(struct notifier_block
*nb
, unsigned long event
,
1456 struct msm_usb_cable
*vbus
= container_of(nb
, struct msm_usb_cable
, nb
);
1457 struct msm_otg
*motg
= container_of(vbus
, struct msm_otg
, vbus
);
1460 set_bit(B_SESS_VLD
, &motg
->inputs
);
1462 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1464 if (test_bit(B_SESS_VLD
, &motg
->inputs
)) {
1465 /* Switch D+/D- lines to Device connector */
1466 gpiod_set_value_cansleep(motg
->switch_gpio
, 0);
1468 /* Switch D+/D- lines to Hub */
1469 gpiod_set_value_cansleep(motg
->switch_gpio
, 1);
1472 schedule_work(&motg
->sm_work
);
1477 static int msm_otg_id_notifier(struct notifier_block
*nb
, unsigned long event
,
1480 struct msm_usb_cable
*id
= container_of(nb
, struct msm_usb_cable
, nb
);
1481 struct msm_otg
*motg
= container_of(id
, struct msm_otg
, id
);
1484 clear_bit(ID
, &motg
->inputs
);
1486 set_bit(ID
, &motg
->inputs
);
1488 schedule_work(&motg
->sm_work
);
1493 static int msm_otg_read_dt(struct platform_device
*pdev
, struct msm_otg
*motg
)
1495 struct msm_otg_platform_data
*pdata
;
1496 struct extcon_dev
*ext_id
, *ext_vbus
;
1497 struct device_node
*node
= pdev
->dev
.of_node
;
1498 struct property
*prop
;
1499 int len
, ret
, words
;
1502 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1506 motg
->pdata
= pdata
;
1508 pdata
->phy_type
= (enum msm_usb_phy_type
)of_device_get_match_data(&pdev
->dev
);
1509 if (!pdata
->phy_type
)
1512 motg
->link_rst
= devm_reset_control_get(&pdev
->dev
, "link");
1513 if (IS_ERR(motg
->link_rst
))
1514 return PTR_ERR(motg
->link_rst
);
1516 motg
->phy_rst
= devm_reset_control_get(&pdev
->dev
, "phy");
1517 if (IS_ERR(motg
->phy_rst
))
1518 motg
->phy_rst
= NULL
;
1520 pdata
->mode
= usb_get_dr_mode(&pdev
->dev
);
1521 if (pdata
->mode
== USB_DR_MODE_UNKNOWN
)
1522 pdata
->mode
= USB_DR_MODE_OTG
;
1524 pdata
->otg_control
= OTG_PHY_CONTROL
;
1525 if (!of_property_read_u32(node
, "qcom,otg-control", &val
))
1526 if (val
== OTG_PMIC_CONTROL
)
1527 pdata
->otg_control
= val
;
1529 if (!of_property_read_u32(node
, "qcom,phy-num", &val
) && val
< 2)
1530 motg
->phy_number
= val
;
1532 motg
->vdd_levels
[VDD_LEVEL_NONE
] = USB_PHY_SUSP_DIG_VOL
;
1533 motg
->vdd_levels
[VDD_LEVEL_MIN
] = USB_PHY_VDD_DIG_VOL_MIN
;
1534 motg
->vdd_levels
[VDD_LEVEL_MAX
] = USB_PHY_VDD_DIG_VOL_MAX
;
1536 if (of_get_property(node
, "qcom,vdd-levels", &len
) &&
1537 len
== sizeof(tmp
)) {
1538 of_property_read_u32_array(node
, "qcom,vdd-levels",
1539 tmp
, len
/ sizeof(*tmp
));
1540 motg
->vdd_levels
[VDD_LEVEL_NONE
] = tmp
[VDD_LEVEL_NONE
];
1541 motg
->vdd_levels
[VDD_LEVEL_MIN
] = tmp
[VDD_LEVEL_MIN
];
1542 motg
->vdd_levels
[VDD_LEVEL_MAX
] = tmp
[VDD_LEVEL_MAX
];
1545 motg
->manual_pullup
= of_property_read_bool(node
, "qcom,manual-pullup");
1547 motg
->switch_gpio
= devm_gpiod_get_optional(&pdev
->dev
, "switch",
1549 if (IS_ERR(motg
->switch_gpio
))
1550 return PTR_ERR(motg
->switch_gpio
);
1552 ext_id
= ERR_PTR(-ENODEV
);
1553 ext_vbus
= ERR_PTR(-ENODEV
);
1554 if (of_property_read_bool(node
, "extcon")) {
1556 /* Each one of them is not mandatory */
1557 ext_vbus
= extcon_get_edev_by_phandle(&pdev
->dev
, 0);
1558 if (IS_ERR(ext_vbus
) && PTR_ERR(ext_vbus
) != -ENODEV
)
1559 return PTR_ERR(ext_vbus
);
1561 ext_id
= extcon_get_edev_by_phandle(&pdev
->dev
, 1);
1562 if (IS_ERR(ext_id
) && PTR_ERR(ext_id
) != -ENODEV
)
1563 return PTR_ERR(ext_id
);
1566 if (!IS_ERR(ext_vbus
)) {
1567 motg
->vbus
.extcon
= ext_vbus
;
1568 motg
->vbus
.nb
.notifier_call
= msm_otg_vbus_notifier
;
1569 ret
= extcon_register_notifier(ext_vbus
, EXTCON_USB
,
1572 dev_err(&pdev
->dev
, "register VBUS notifier failed\n");
1576 ret
= extcon_get_cable_state_(ext_vbus
, EXTCON_USB
);
1578 set_bit(B_SESS_VLD
, &motg
->inputs
);
1580 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1583 if (!IS_ERR(ext_id
)) {
1584 motg
->id
.extcon
= ext_id
;
1585 motg
->id
.nb
.notifier_call
= msm_otg_id_notifier
;
1586 ret
= extcon_register_notifier(ext_id
, EXTCON_USB_HOST
,
1589 dev_err(&pdev
->dev
, "register ID notifier failed\n");
1590 extcon_unregister_notifier(motg
->vbus
.extcon
,
1591 EXTCON_USB
, &motg
->vbus
.nb
);
1595 ret
= extcon_get_cable_state_(ext_id
, EXTCON_USB_HOST
);
1597 clear_bit(ID
, &motg
->inputs
);
1599 set_bit(ID
, &motg
->inputs
);
1602 prop
= of_find_property(node
, "qcom,phy-init-sequence", &len
);
1606 words
= len
/ sizeof(u32
);
1608 if (words
>= ULPI_EXT_VENDOR_SPECIFIC
) {
1609 dev_warn(&pdev
->dev
, "Too big PHY init sequence %d\n", words
);
1613 pdata
->phy_init_seq
= devm_kzalloc(&pdev
->dev
, len
, GFP_KERNEL
);
1614 if (!pdata
->phy_init_seq
)
1617 ret
= of_property_read_u32_array(node
, "qcom,phy-init-sequence",
1618 pdata
->phy_init_seq
, words
);
1620 pdata
->phy_init_sz
= words
;
1625 static int msm_otg_reboot_notify(struct notifier_block
*this,
1626 unsigned long code
, void *unused
)
1628 struct msm_otg
*motg
= container_of(this, struct msm_otg
, reboot
);
1631 * Ensure that D+/D- lines are routed to uB connector, so
1632 * we could load bootloader/kernel at next reboot
1634 gpiod_set_value_cansleep(motg
->switch_gpio
, 0);
1638 static int msm_otg_probe(struct platform_device
*pdev
)
1640 struct regulator_bulk_data regs
[3];
1642 struct device_node
*np
= pdev
->dev
.of_node
;
1643 struct msm_otg_platform_data
*pdata
;
1644 struct resource
*res
;
1645 struct msm_otg
*motg
;
1646 struct usb_phy
*phy
;
1647 void __iomem
*phy_select
;
1649 motg
= devm_kzalloc(&pdev
->dev
, sizeof(struct msm_otg
), GFP_KERNEL
);
1653 motg
->phy
.otg
= devm_kzalloc(&pdev
->dev
, sizeof(struct usb_otg
),
1659 phy
->dev
= &pdev
->dev
;
1661 motg
->clk
= devm_clk_get(&pdev
->dev
, np
? "core" : "usb_hs_clk");
1662 if (IS_ERR(motg
->clk
)) {
1663 dev_err(&pdev
->dev
, "failed to get usb_hs_clk\n");
1664 return PTR_ERR(motg
->clk
);
1668 * If USB Core is running its protocol engine based on CORE CLK,
1669 * CORE CLK must be running at >55Mhz for correct HSUSB
1670 * operation and USB core cannot tolerate frequency changes on
1673 motg
->pclk
= devm_clk_get(&pdev
->dev
, np
? "iface" : "usb_hs_pclk");
1674 if (IS_ERR(motg
->pclk
)) {
1675 dev_err(&pdev
->dev
, "failed to get usb_hs_pclk\n");
1676 return PTR_ERR(motg
->pclk
);
1680 * USB core clock is not present on all MSM chips. This
1681 * clock is introduced to remove the dependency on AXI
1684 motg
->core_clk
= devm_clk_get(&pdev
->dev
,
1685 np
? "alt_core" : "usb_hs_core_clk");
1687 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1690 motg
->regs
= devm_ioremap(&pdev
->dev
, res
->start
, resource_size(res
));
1694 pdata
= dev_get_platdata(&pdev
->dev
);
1698 ret
= msm_otg_read_dt(pdev
, motg
);
1704 * NOTE: The PHYs can be multiplexed between the chipidea controller
1705 * and the dwc3 controller, using a single bit. It is important that
1706 * the dwc3 driver does not set this bit in an incompatible way.
1708 if (motg
->phy_number
) {
1709 phy_select
= devm_ioremap_nocache(&pdev
->dev
, USB2_PHY_SEL
, 4);
1712 goto unregister_extcon
;
1714 /* Enable second PHY with the OTG port */
1715 writel(0x1, phy_select
);
1718 dev_info(&pdev
->dev
, "OTG regs = %p\n", motg
->regs
);
1720 motg
->irq
= platform_get_irq(pdev
, 0);
1721 if (motg
->irq
< 0) {
1722 dev_err(&pdev
->dev
, "platform_get_irq failed\n");
1724 goto unregister_extcon
;
1727 regs
[0].supply
= "vddcx";
1728 regs
[1].supply
= "v3p3";
1729 regs
[2].supply
= "v1p8";
1731 ret
= devm_regulator_bulk_get(motg
->phy
.dev
, ARRAY_SIZE(regs
), regs
);
1733 goto unregister_extcon
;
1735 motg
->vddcx
= regs
[0].consumer
;
1736 motg
->v3p3
= regs
[1].consumer
;
1737 motg
->v1p8
= regs
[2].consumer
;
1739 clk_set_rate(motg
->clk
, 60000000);
1741 clk_prepare_enable(motg
->clk
);
1742 clk_prepare_enable(motg
->pclk
);
1744 if (!IS_ERR(motg
->core_clk
))
1745 clk_prepare_enable(motg
->core_clk
);
1747 ret
= msm_hsusb_init_vddcx(motg
, 1);
1749 dev_err(&pdev
->dev
, "hsusb vddcx configuration failed\n");
1753 ret
= msm_hsusb_ldo_init(motg
, 1);
1755 dev_err(&pdev
->dev
, "hsusb vreg configuration failed\n");
1758 ret
= msm_hsusb_ldo_set_mode(motg
, 1);
1760 dev_err(&pdev
->dev
, "hsusb vreg enable failed\n");
1764 writel(0, USB_USBINTR
);
1765 writel(0, USB_OTGSC
);
1767 INIT_WORK(&motg
->sm_work
, msm_otg_sm_work
);
1768 INIT_DELAYED_WORK(&motg
->chg_work
, msm_chg_detect_work
);
1769 ret
= devm_request_irq(&pdev
->dev
, motg
->irq
, msm_otg_irq
, IRQF_SHARED
,
1772 dev_err(&pdev
->dev
, "request irq failed\n");
1776 phy
->init
= msm_phy_init
;
1777 phy
->set_power
= msm_otg_set_power
;
1778 phy
->notify_disconnect
= msm_phy_notify_disconnect
;
1779 phy
->type
= USB_PHY_TYPE_USB2
;
1781 phy
->io_ops
= &msm_otg_io_ops
;
1783 phy
->otg
->usb_phy
= &motg
->phy
;
1784 phy
->otg
->set_host
= msm_otg_set_host
;
1785 phy
->otg
->set_peripheral
= msm_otg_set_peripheral
;
1789 ret
= usb_add_phy_dev(&motg
->phy
);
1791 dev_err(&pdev
->dev
, "usb_add_phy failed\n");
1795 platform_set_drvdata(pdev
, motg
);
1796 device_init_wakeup(&pdev
->dev
, 1);
1798 if (motg
->pdata
->mode
== USB_DR_MODE_OTG
&&
1799 motg
->pdata
->otg_control
== OTG_USER_CONTROL
) {
1800 ret
= msm_otg_debugfs_init(motg
);
1802 dev_dbg(&pdev
->dev
, "Can not create mode change file\n");
1805 if (test_bit(B_SESS_VLD
, &motg
->inputs
)) {
1806 /* Switch D+/D- lines to Device connector */
1807 gpiod_set_value_cansleep(motg
->switch_gpio
, 0);
1809 /* Switch D+/D- lines to Hub */
1810 gpiod_set_value_cansleep(motg
->switch_gpio
, 1);
1813 motg
->reboot
.notifier_call
= msm_otg_reboot_notify
;
1814 register_reboot_notifier(&motg
->reboot
);
1816 pm_runtime_set_active(&pdev
->dev
);
1817 pm_runtime_enable(&pdev
->dev
);
1822 msm_hsusb_ldo_init(motg
, 0);
1824 msm_hsusb_init_vddcx(motg
, 0);
1826 clk_disable_unprepare(motg
->pclk
);
1827 clk_disable_unprepare(motg
->clk
);
1828 if (!IS_ERR(motg
->core_clk
))
1829 clk_disable_unprepare(motg
->core_clk
);
1831 extcon_unregister_notifier(motg
->id
.extcon
,
1832 EXTCON_USB_HOST
, &motg
->id
.nb
);
1833 extcon_unregister_notifier(motg
->vbus
.extcon
,
1834 EXTCON_USB
, &motg
->vbus
.nb
);
1839 static int msm_otg_remove(struct platform_device
*pdev
)
1841 struct msm_otg
*motg
= platform_get_drvdata(pdev
);
1842 struct usb_phy
*phy
= &motg
->phy
;
1845 if (phy
->otg
->host
|| phy
->otg
->gadget
)
1848 unregister_reboot_notifier(&motg
->reboot
);
1851 * Ensure that D+/D- lines are routed to uB connector, so
1852 * we could load bootloader/kernel at next reboot
1854 gpiod_set_value_cansleep(motg
->switch_gpio
, 0);
1856 extcon_unregister_notifier(motg
->id
.extcon
, EXTCON_USB_HOST
, &motg
->id
.nb
);
1857 extcon_unregister_notifier(motg
->vbus
.extcon
, EXTCON_USB
, &motg
->vbus
.nb
);
1859 msm_otg_debugfs_cleanup();
1860 cancel_delayed_work_sync(&motg
->chg_work
);
1861 cancel_work_sync(&motg
->sm_work
);
1863 pm_runtime_resume(&pdev
->dev
);
1865 device_init_wakeup(&pdev
->dev
, 0);
1866 pm_runtime_disable(&pdev
->dev
);
1868 usb_remove_phy(phy
);
1869 disable_irq(motg
->irq
);
1872 * Put PHY in low power mode.
1874 ulpi_read(phy
, 0x14);
1875 ulpi_write(phy
, 0x08, 0x09);
1877 writel(readl(USB_PORTSC
) | PORTSC_PHCD
, USB_PORTSC
);
1878 while (cnt
< PHY_SUSPEND_TIMEOUT_USEC
) {
1879 if (readl(USB_PORTSC
) & PORTSC_PHCD
)
1884 if (cnt
>= PHY_SUSPEND_TIMEOUT_USEC
)
1885 dev_err(phy
->dev
, "Unable to suspend PHY\n");
1887 clk_disable_unprepare(motg
->pclk
);
1888 clk_disable_unprepare(motg
->clk
);
1889 if (!IS_ERR(motg
->core_clk
))
1890 clk_disable_unprepare(motg
->core_clk
);
1891 msm_hsusb_ldo_init(motg
, 0);
1893 pm_runtime_set_suspended(&pdev
->dev
);
1899 static int msm_otg_runtime_idle(struct device
*dev
)
1901 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1902 struct usb_otg
*otg
= motg
->phy
.otg
;
1904 dev_dbg(dev
, "OTG runtime idle\n");
1907 * It is observed some times that a spurious interrupt
1908 * comes when PHY is put into LPM immediately after PHY reset.
1909 * This 1 sec delay also prevents entering into LPM immediately
1910 * after asynchronous interrupt.
1912 if (otg
->state
!= OTG_STATE_UNDEFINED
)
1913 pm_schedule_suspend(dev
, 1000);
1918 static int msm_otg_runtime_suspend(struct device
*dev
)
1920 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1922 dev_dbg(dev
, "OTG runtime suspend\n");
1923 return msm_otg_suspend(motg
);
1926 static int msm_otg_runtime_resume(struct device
*dev
)
1928 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1930 dev_dbg(dev
, "OTG runtime resume\n");
1931 return msm_otg_resume(motg
);
1935 #ifdef CONFIG_PM_SLEEP
1936 static int msm_otg_pm_suspend(struct device
*dev
)
1938 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1940 dev_dbg(dev
, "OTG PM suspend\n");
1941 return msm_otg_suspend(motg
);
1944 static int msm_otg_pm_resume(struct device
*dev
)
1946 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1949 dev_dbg(dev
, "OTG PM resume\n");
1951 ret
= msm_otg_resume(motg
);
1956 * Runtime PM Documentation recommends bringing the
1957 * device to full powered state upon resume.
1959 pm_runtime_disable(dev
);
1960 pm_runtime_set_active(dev
);
1961 pm_runtime_enable(dev
);
1967 static const struct dev_pm_ops msm_otg_dev_pm_ops
= {
1968 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend
, msm_otg_pm_resume
)
1969 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend
, msm_otg_runtime_resume
,
1970 msm_otg_runtime_idle
)
1973 static struct platform_driver msm_otg_driver
= {
1974 .probe
= msm_otg_probe
,
1975 .remove
= msm_otg_remove
,
1977 .name
= DRIVER_NAME
,
1978 .pm
= &msm_otg_dev_pm_ops
,
1979 .of_match_table
= msm_otg_dt_match
,
1983 module_platform_driver(msm_otg_driver
);
1985 MODULE_LICENSE("GPL v2");
1986 MODULE_DESCRIPTION("MSM USB transceiver driver");