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mmc: rtsx_pci: Enable MMC_CAP_ERASE to allow erase/discard/trim requests
[linux/fpc-iii.git] / drivers / vme / bridges / vme_ca91cx42.c
blob9f2c834e43e002bdaab5344c4d16e980f057692d
1 /*
2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
3 *
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * Derived from ca91c042.c by Michael Wyrick
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18 #include <linux/module.h>
19 #include <linux/mm.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/pci.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/poll.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/time.h>
30 #include <linux/io.h>
31 #include <linux/uaccess.h>
32 #include <linux/vme.h>
33
34 #include "../vme_bridge.h"
35 #include "vme_ca91cx42.h"
36
37 static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
38 static void ca91cx42_remove(struct pci_dev *);
39
40 /* Module parameters */
41 static int geoid;
42
43 static const char driver_name[] = "vme_ca91cx42";
44
45 static const struct pci_device_id ca91cx42_ids[] = {
46 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
47 { },
48 };
49
50 static struct pci_driver ca91cx42_driver = {
51 .name = driver_name,
52 .id_table = ca91cx42_ids,
53 .probe = ca91cx42_probe,
54 .remove = ca91cx42_remove,
55 };
56
57 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
58 {
59 wake_up(&bridge->dma_queue);
60
61 return CA91CX42_LINT_DMA;
62 }
63
64 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
65 {
66 int i;
67 u32 serviced = 0;
68
69 for (i = 0; i < 4; i++) {
70 if (stat & CA91CX42_LINT_LM[i]) {
71 /* We only enable interrupts if the callback is set */
72 bridge->lm_callback[i](i);
73 serviced |= CA91CX42_LINT_LM[i];
74 }
75 }
76
77 return serviced;
78 }
79
80 /* XXX This needs to be split into 4 queues */
81 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
82 {
83 wake_up(&bridge->mbox_queue);
84
85 return CA91CX42_LINT_MBOX;
86 }
87
88 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
89 {
90 wake_up(&bridge->iack_queue);
91
92 return CA91CX42_LINT_SW_IACK;
93 }
94
95 static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
96 {
97 int val;
98 struct ca91cx42_driver *bridge;
99
100 bridge = ca91cx42_bridge->driver_priv;
101
102 val = ioread32(bridge->base + DGCS);
103
104 if (!(val & 0x00000800)) {
105 dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA "
106 "Read Error DGCS=%08X\n", val);
107 }
108
109 return CA91CX42_LINT_VERR;
110 }
111
112 static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
113 {
114 int val;
115 struct ca91cx42_driver *bridge;
116
117 bridge = ca91cx42_bridge->driver_priv;
118
119 val = ioread32(bridge->base + DGCS);
120
121 if (!(val & 0x00000800))
122 dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA "
123 "Read Error DGCS=%08X\n", val);
124
125 return CA91CX42_LINT_LERR;
126 }
127
128
129 static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
130 int stat)
131 {
132 int vec, i, serviced = 0;
133 struct ca91cx42_driver *bridge;
134
135 bridge = ca91cx42_bridge->driver_priv;
136
137
138 for (i = 7; i > 0; i--) {
139 if (stat & (1 << i)) {
140 vec = ioread32(bridge->base +
141 CA91CX42_V_STATID[i]) & 0xff;
142
143 vme_irq_handler(ca91cx42_bridge, i, vec);
144
145 serviced |= (1 << i);
146 }
147 }
148
149 return serviced;
150 }
151
152 static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
153 {
154 u32 stat, enable, serviced = 0;
155 struct vme_bridge *ca91cx42_bridge;
156 struct ca91cx42_driver *bridge;
157
158 ca91cx42_bridge = ptr;
159
160 bridge = ca91cx42_bridge->driver_priv;
161
162 enable = ioread32(bridge->base + LINT_EN);
163 stat = ioread32(bridge->base + LINT_STAT);
164
165 /* Only look at unmasked interrupts */
166 stat &= enable;
167
168 if (unlikely(!stat))
169 return IRQ_NONE;
170
171 if (stat & CA91CX42_LINT_DMA)
172 serviced |= ca91cx42_DMA_irqhandler(bridge);
173 if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
174 CA91CX42_LINT_LM3))
175 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
176 if (stat & CA91CX42_LINT_MBOX)
177 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
178 if (stat & CA91CX42_LINT_SW_IACK)
179 serviced |= ca91cx42_IACK_irqhandler(bridge);
180 if (stat & CA91CX42_LINT_VERR)
181 serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge);
182 if (stat & CA91CX42_LINT_LERR)
183 serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge);
184 if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
185 CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
186 CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
187 CA91CX42_LINT_VIRQ7))
188 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
189
190 /* Clear serviced interrupts */
191 iowrite32(serviced, bridge->base + LINT_STAT);
192
193 return IRQ_HANDLED;
194 }
195
196 static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
197 {
198 int result, tmp;
199 struct pci_dev *pdev;
200 struct ca91cx42_driver *bridge;
201
202 bridge = ca91cx42_bridge->driver_priv;
203
204 /* Need pdev */
205 pdev = to_pci_dev(ca91cx42_bridge->parent);
206
207 /* Disable interrupts from PCI to VME */
208 iowrite32(0, bridge->base + VINT_EN);
209
210 /* Disable PCI interrupts */
211 iowrite32(0, bridge->base + LINT_EN);
212 /* Clear Any Pending PCI Interrupts */
213 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
214
215 result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
216 driver_name, ca91cx42_bridge);
217 if (result) {
218 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
219 pdev->irq);
220 return result;
221 }
222
223 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
224 iowrite32(0, bridge->base + LINT_MAP0);
225 iowrite32(0, bridge->base + LINT_MAP1);
226 iowrite32(0, bridge->base + LINT_MAP2);
227
228 /* Enable DMA, mailbox & LM Interrupts */
229 tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
230 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
231 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
232
233 iowrite32(tmp, bridge->base + LINT_EN);
234
235 return 0;
236 }
237
238 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
239 struct pci_dev *pdev)
240 {
241 struct vme_bridge *ca91cx42_bridge;
242
243 /* Disable interrupts from PCI to VME */
244 iowrite32(0, bridge->base + VINT_EN);
245
246 /* Disable PCI interrupts */
247 iowrite32(0, bridge->base + LINT_EN);
248 /* Clear Any Pending PCI Interrupts */
249 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
250
251 ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge,
252 driver_priv);
253 free_irq(pdev->irq, ca91cx42_bridge);
254 }
255
256 static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level)
257 {
258 u32 tmp;
259
260 tmp = ioread32(bridge->base + LINT_STAT);
261
262 if (tmp & (1 << level))
263 return 0;
264 else
265 return 1;
266 }
267
268 /*
269 * Set up an VME interrupt
270 */
271 static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level,
272 int state, int sync)
273
274 {
275 struct pci_dev *pdev;
276 u32 tmp;
277 struct ca91cx42_driver *bridge;
278
279 bridge = ca91cx42_bridge->driver_priv;
280
281 /* Enable IRQ level */
282 tmp = ioread32(bridge->base + LINT_EN);
283
284 if (state == 0)
285 tmp &= ~CA91CX42_LINT_VIRQ[level];
286 else
287 tmp |= CA91CX42_LINT_VIRQ[level];
288
289 iowrite32(tmp, bridge->base + LINT_EN);
290
291 if ((state == 0) && (sync != 0)) {
292 pdev = to_pci_dev(ca91cx42_bridge->parent);
293
294 synchronize_irq(pdev->irq);
295 }
296 }
297
298 static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
299 int statid)
300 {
301 u32 tmp;
302 struct ca91cx42_driver *bridge;
303
304 bridge = ca91cx42_bridge->driver_priv;
305
306 /* Universe can only generate even vectors */
307 if (statid & 1)
308 return -EINVAL;
309
310 mutex_lock(&bridge->vme_int);
311
312 tmp = ioread32(bridge->base + VINT_EN);
313
314 /* Set Status/ID */
315 iowrite32(statid << 24, bridge->base + STATID);
316
317 /* Assert VMEbus IRQ */
318 tmp = tmp | (1 << (level + 24));
319 iowrite32(tmp, bridge->base + VINT_EN);
320
321 /* Wait for IACK */
322 wait_event_interruptible(bridge->iack_queue,
323 ca91cx42_iack_received(bridge, level));
324
325 /* Return interrupt to low state */
326 tmp = ioread32(bridge->base + VINT_EN);
327 tmp = tmp & ~(1 << (level + 24));
328 iowrite32(tmp, bridge->base + VINT_EN);
329
330 mutex_unlock(&bridge->vme_int);
331
332 return 0;
333 }
334
335 static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
336 unsigned long long vme_base, unsigned long long size,
337 dma_addr_t pci_base, u32 aspace, u32 cycle)
338 {
339 unsigned int i, addr = 0, granularity;
340 unsigned int temp_ctl = 0;
341 unsigned int vme_bound, pci_offset;
342 struct vme_bridge *ca91cx42_bridge;
343 struct ca91cx42_driver *bridge;
344
345 ca91cx42_bridge = image->parent;
346
347 bridge = ca91cx42_bridge->driver_priv;
348
349 i = image->number;
350
351 switch (aspace) {
352 case VME_A16:
353 addr |= CA91CX42_VSI_CTL_VAS_A16;
354 break;
355 case VME_A24:
356 addr |= CA91CX42_VSI_CTL_VAS_A24;
357 break;
358 case VME_A32:
359 addr |= CA91CX42_VSI_CTL_VAS_A32;
360 break;
361 case VME_USER1:
362 addr |= CA91CX42_VSI_CTL_VAS_USER1;
363 break;
364 case VME_USER2:
365 addr |= CA91CX42_VSI_CTL_VAS_USER2;
366 break;
367 case VME_A64:
368 case VME_CRCSR:
369 case VME_USER3:
370 case VME_USER4:
371 default:
372 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
373 return -EINVAL;
374 break;
375 }
376
377 /*
378 * Bound address is a valid address for the window, adjust
379 * accordingly
380 */
381 vme_bound = vme_base + size;
382 pci_offset = pci_base - vme_base;
383
384 if ((i == 0) || (i == 4))
385 granularity = 0x1000;
386 else
387 granularity = 0x10000;
388
389 if (vme_base & (granularity - 1)) {
390 dev_err(ca91cx42_bridge->parent, "Invalid VME base "
391 "alignment\n");
392 return -EINVAL;
393 }
394 if (vme_bound & (granularity - 1)) {
395 dev_err(ca91cx42_bridge->parent, "Invalid VME bound "
396 "alignment\n");
397 return -EINVAL;
398 }
399 if (pci_offset & (granularity - 1)) {
400 dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset "
401 "alignment\n");
402 return -EINVAL;
403 }
404
405 /* Disable while we are mucking around */
406 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
407 temp_ctl &= ~CA91CX42_VSI_CTL_EN;
408 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
409
410 /* Setup mapping */
411 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
412 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
413 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
414
415 /* Setup address space */
416 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
417 temp_ctl |= addr;
418
419 /* Setup cycle types */
420 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
421 if (cycle & VME_SUPER)
422 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
423 if (cycle & VME_USER)
424 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
425 if (cycle & VME_PROG)
426 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
427 if (cycle & VME_DATA)
428 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
429
430 /* Write ctl reg without enable */
431 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
432
433 if (enabled)
434 temp_ctl |= CA91CX42_VSI_CTL_EN;
435
436 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
437
438 return 0;
439 }
440
441 static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
442 unsigned long long *vme_base, unsigned long long *size,
443 dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
444 {
445 unsigned int i, granularity = 0, ctl = 0;
446 unsigned long long vme_bound, pci_offset;
447 struct ca91cx42_driver *bridge;
448
449 bridge = image->parent->driver_priv;
450
451 i = image->number;
452
453 if ((i == 0) || (i == 4))
454 granularity = 0x1000;
455 else
456 granularity = 0x10000;
457
458 /* Read Registers */
459 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
460
461 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
462 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
463 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
464
465 *pci_base = (dma_addr_t)vme_base + pci_offset;
466 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
467
468 *enabled = 0;
469 *aspace = 0;
470 *cycle = 0;
471
472 if (ctl & CA91CX42_VSI_CTL_EN)
473 *enabled = 1;
474
475 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
476 *aspace = VME_A16;
477 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
478 *aspace = VME_A24;
479 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
480 *aspace = VME_A32;
481 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
482 *aspace = VME_USER1;
483 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
484 *aspace = VME_USER2;
485
486 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
487 *cycle |= VME_SUPER;
488 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
489 *cycle |= VME_USER;
490 if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
491 *cycle |= VME_PROG;
492 if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
493 *cycle |= VME_DATA;
494
495 return 0;
496 }
497
498 /*
499 * Allocate and map PCI Resource
500 */
501 static int ca91cx42_alloc_resource(struct vme_master_resource *image,
502 unsigned long long size)
503 {
504 unsigned long long existing_size;
505 int retval = 0;
506 struct pci_dev *pdev;
507 struct vme_bridge *ca91cx42_bridge;
508
509 ca91cx42_bridge = image->parent;
510
511 /* Find pci_dev container of dev */
512 if (ca91cx42_bridge->parent == NULL) {
513 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
514 return -EINVAL;
515 }
516 pdev = to_pci_dev(ca91cx42_bridge->parent);
517
518 existing_size = (unsigned long long)(image->bus_resource.end -
519 image->bus_resource.start);
520
521 /* If the existing size is OK, return */
522 if (existing_size == (size - 1))
523 return 0;
524
525 if (existing_size != 0) {
526 iounmap(image->kern_base);
527 image->kern_base = NULL;
528 kfree(image->bus_resource.name);
529 release_resource(&image->bus_resource);
530 memset(&image->bus_resource, 0, sizeof(struct resource));
531 }
532
533 if (image->bus_resource.name == NULL) {
534 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
535 if (image->bus_resource.name == NULL) {
536 dev_err(ca91cx42_bridge->parent, "Unable to allocate "
537 "memory for resource name\n");
538 retval = -ENOMEM;
539 goto err_name;
540 }
541 }
542
543 sprintf((char *)image->bus_resource.name, "%s.%d",
544 ca91cx42_bridge->name, image->number);
545
546 image->bus_resource.start = 0;
547 image->bus_resource.end = (unsigned long)size;
548 image->bus_resource.flags = IORESOURCE_MEM;
549
550 retval = pci_bus_alloc_resource(pdev->bus,
551 &image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM,
552 0, NULL, NULL);
553 if (retval) {
554 dev_err(ca91cx42_bridge->parent, "Failed to allocate mem "
555 "resource for window %d size 0x%lx start 0x%lx\n",
556 image->number, (unsigned long)size,
557 (unsigned long)image->bus_resource.start);
558 goto err_resource;
559 }
560
561 image->kern_base = ioremap_nocache(
562 image->bus_resource.start, size);
563 if (image->kern_base == NULL) {
564 dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n");
565 retval = -ENOMEM;
566 goto err_remap;
567 }
568
569 return 0;
570
571 err_remap:
572 release_resource(&image->bus_resource);
573 err_resource:
574 kfree(image->bus_resource.name);
575 memset(&image->bus_resource, 0, sizeof(struct resource));
576 err_name:
577 return retval;
578 }
579
580 /*
581 * Free and unmap PCI Resource
582 */
583 static void ca91cx42_free_resource(struct vme_master_resource *image)
584 {
585 iounmap(image->kern_base);
586 image->kern_base = NULL;
587 release_resource(&image->bus_resource);
588 kfree(image->bus_resource.name);
589 memset(&image->bus_resource, 0, sizeof(struct resource));
590 }
591
592
593 static int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
594 unsigned long long vme_base, unsigned long long size, u32 aspace,
595 u32 cycle, u32 dwidth)
596 {
597 int retval = 0;
598 unsigned int i, granularity = 0;
599 unsigned int temp_ctl = 0;
600 unsigned long long pci_bound, vme_offset, pci_base;
601 struct vme_bridge *ca91cx42_bridge;
602 struct ca91cx42_driver *bridge;
603
604 ca91cx42_bridge = image->parent;
605
606 bridge = ca91cx42_bridge->driver_priv;
607
608 i = image->number;
609
610 if ((i == 0) || (i == 4))
611 granularity = 0x1000;
612 else
613 granularity = 0x10000;
614
615 /* Verify input data */
616 if (vme_base & (granularity - 1)) {
617 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
618 "alignment\n");
619 retval = -EINVAL;
620 goto err_window;
621 }
622 if (size & (granularity - 1)) {
623 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
624 "alignment\n");
625 retval = -EINVAL;
626 goto err_window;
627 }
628
629 spin_lock(&image->lock);
630
631 /*
632 * Let's allocate the resource here rather than further up the stack as
633 * it avoids pushing loads of bus dependent stuff up the stack
634 */
635 retval = ca91cx42_alloc_resource(image, size);
636 if (retval) {
637 spin_unlock(&image->lock);
638 dev_err(ca91cx42_bridge->parent, "Unable to allocate memory "
639 "for resource name\n");
640 retval = -ENOMEM;
641 goto err_res;
642 }
643
644 pci_base = (unsigned long long)image->bus_resource.start;
645
646 /*
647 * Bound address is a valid address for the window, adjust
648 * according to window granularity.
649 */
650 pci_bound = pci_base + size;
651 vme_offset = vme_base - pci_base;
652
653 /* Disable while we are mucking around */
654 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
655 temp_ctl &= ~CA91CX42_LSI_CTL_EN;
656 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
657
658 /* Setup cycle types */
659 temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
660 if (cycle & VME_BLT)
661 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
662 if (cycle & VME_MBLT)
663 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
664
665 /* Setup data width */
666 temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
667 switch (dwidth) {
668 case VME_D8:
669 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
670 break;
671 case VME_D16:
672 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
673 break;
674 case VME_D32:
675 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
676 break;
677 case VME_D64:
678 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
679 break;
680 default:
681 spin_unlock(&image->lock);
682 dev_err(ca91cx42_bridge->parent, "Invalid data width\n");
683 retval = -EINVAL;
684 goto err_dwidth;
685 break;
686 }
687
688 /* Setup address space */
689 temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
690 switch (aspace) {
691 case VME_A16:
692 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
693 break;
694 case VME_A24:
695 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
696 break;
697 case VME_A32:
698 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
699 break;
700 case VME_CRCSR:
701 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
702 break;
703 case VME_USER1:
704 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
705 break;
706 case VME_USER2:
707 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
708 break;
709 case VME_A64:
710 case VME_USER3:
711 case VME_USER4:
712 default:
713 spin_unlock(&image->lock);
714 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
715 retval = -EINVAL;
716 goto err_aspace;
717 break;
718 }
719
720 temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
721 if (cycle & VME_SUPER)
722 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
723 if (cycle & VME_PROG)
724 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
725
726 /* Setup mapping */
727 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
728 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
729 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
730
731 /* Write ctl reg without enable */
732 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
733
734 if (enabled)
735 temp_ctl |= CA91CX42_LSI_CTL_EN;
736
737 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
738
739 spin_unlock(&image->lock);
740 return 0;
741
742 err_aspace:
743 err_dwidth:
744 ca91cx42_free_resource(image);
745 err_res:
746 err_window:
747 return retval;
748 }
749
750 static int __ca91cx42_master_get(struct vme_master_resource *image,
751 int *enabled, unsigned long long *vme_base, unsigned long long *size,
752 u32 *aspace, u32 *cycle, u32 *dwidth)
753 {
754 unsigned int i, ctl;
755 unsigned long long pci_base, pci_bound, vme_offset;
756 struct ca91cx42_driver *bridge;
757
758 bridge = image->parent->driver_priv;
759
760 i = image->number;
761
762 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
763
764 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
765 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
766 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
767
768 *vme_base = pci_base + vme_offset;
769 *size = (unsigned long long)(pci_bound - pci_base);
770
771 *enabled = 0;
772 *aspace = 0;
773 *cycle = 0;
774 *dwidth = 0;
775
776 if (ctl & CA91CX42_LSI_CTL_EN)
777 *enabled = 1;
778
779 /* Setup address space */
780 switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
781 case CA91CX42_LSI_CTL_VAS_A16:
782 *aspace = VME_A16;
783 break;
784 case CA91CX42_LSI_CTL_VAS_A24:
785 *aspace = VME_A24;
786 break;
787 case CA91CX42_LSI_CTL_VAS_A32:
788 *aspace = VME_A32;
789 break;
790 case CA91CX42_LSI_CTL_VAS_CRCSR:
791 *aspace = VME_CRCSR;
792 break;
793 case CA91CX42_LSI_CTL_VAS_USER1:
794 *aspace = VME_USER1;
795 break;
796 case CA91CX42_LSI_CTL_VAS_USER2:
797 *aspace = VME_USER2;
798 break;
799 }
800
801 /* XXX Not sure howto check for MBLT */
802 /* Setup cycle types */
803 if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
804 *cycle |= VME_BLT;
805 else
806 *cycle |= VME_SCT;
807
808 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
809 *cycle |= VME_SUPER;
810 else
811 *cycle |= VME_USER;
812
813 if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
814 *cycle = VME_PROG;
815 else
816 *cycle = VME_DATA;
817
818 /* Setup data width */
819 switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
820 case CA91CX42_LSI_CTL_VDW_D8:
821 *dwidth = VME_D8;
822 break;
823 case CA91CX42_LSI_CTL_VDW_D16:
824 *dwidth = VME_D16;
825 break;
826 case CA91CX42_LSI_CTL_VDW_D32:
827 *dwidth = VME_D32;
828 break;
829 case CA91CX42_LSI_CTL_VDW_D64:
830 *dwidth = VME_D64;
831 break;
832 }
833
834 return 0;
835 }
836
837 static int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
838 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
839 u32 *cycle, u32 *dwidth)
840 {
841 int retval;
842
843 spin_lock(&image->lock);
844
845 retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
846 cycle, dwidth);
847
848 spin_unlock(&image->lock);
849
850 return retval;
851 }
852
853 static ssize_t ca91cx42_master_read(struct vme_master_resource *image,
854 void *buf, size_t count, loff_t offset)
855 {
856 ssize_t retval;
857 void __iomem *addr = image->kern_base + offset;
858 unsigned int done = 0;
859 unsigned int count32;
860
861 if (count == 0)
862 return 0;
863
864 spin_lock(&image->lock);
865
866 /* The following code handles VME address alignment. We cannot use
867 * memcpy_xxx here because it may cut data transfers in to 8-bit
868 * cycles when D16 or D32 cycles are required on the VME bus.
869 * On the other hand, the bridge itself assures that the maximum data
870 * cycle configured for the transfer is used and splits it
871 * automatically for non-aligned addresses, so we don't want the
872 * overhead of needlessly forcing small transfers for the entire cycle.
873 */
874 if ((uintptr_t)addr & 0x1) {
875 *(u8 *)buf = ioread8(addr);
876 done += 1;
877 if (done == count)
878 goto out;
879 }
880 if ((uintptr_t)(addr + done) & 0x2) {
881 if ((count - done) < 2) {
882 *(u8 *)(buf + done) = ioread8(addr + done);
883 done += 1;
884 goto out;
885 } else {
886 *(u16 *)(buf + done) = ioread16(addr + done);
887 done += 2;
888 }
889 }
890
891 count32 = (count - done) & ~0x3;
892 while (done < count32) {
893 *(u32 *)(buf + done) = ioread32(addr + done);
894 done += 4;
895 }
896
897 if ((count - done) & 0x2) {
898 *(u16 *)(buf + done) = ioread16(addr + done);
899 done += 2;
900 }
901 if ((count - done) & 0x1) {
902 *(u8 *)(buf + done) = ioread8(addr + done);
903 done += 1;
904 }
905 out:
906 retval = count;
907 spin_unlock(&image->lock);
908
909 return retval;
910 }
911
912 static ssize_t ca91cx42_master_write(struct vme_master_resource *image,
913 void *buf, size_t count, loff_t offset)
914 {
915 ssize_t retval;
916 void __iomem *addr = image->kern_base + offset;
917 unsigned int done = 0;
918 unsigned int count32;
919
920 if (count == 0)
921 return 0;
922
923 spin_lock(&image->lock);
924
925 /* Here we apply for the same strategy we do in master_read
926 * function in order to assure the correct cycles.
927 */
928 if ((uintptr_t)addr & 0x1) {
929 iowrite8(*(u8 *)buf, addr);
930 done += 1;
931 if (done == count)
932 goto out;
933 }
934 if ((uintptr_t)(addr + done) & 0x2) {
935 if ((count - done) < 2) {
936 iowrite8(*(u8 *)(buf + done), addr + done);
937 done += 1;
938 goto out;
939 } else {
940 iowrite16(*(u16 *)(buf + done), addr + done);
941 done += 2;
942 }
943 }
944
945 count32 = (count - done) & ~0x3;
946 while (done < count32) {
947 iowrite32(*(u32 *)(buf + done), addr + done);
948 done += 4;
949 }
950
951 if ((count - done) & 0x2) {
952 iowrite16(*(u16 *)(buf + done), addr + done);
953 done += 2;
954 }
955 if ((count - done) & 0x1) {
956 iowrite8(*(u8 *)(buf + done), addr + done);
957 done += 1;
958 }
959 out:
960 retval = count;
961
962 spin_unlock(&image->lock);
963
964 return retval;
965 }
966
967 static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
968 unsigned int mask, unsigned int compare, unsigned int swap,
969 loff_t offset)
970 {
971 u32 result;
972 uintptr_t pci_addr;
973 int i;
974 struct ca91cx42_driver *bridge;
975 struct device *dev;
976
977 bridge = image->parent->driver_priv;
978 dev = image->parent->parent;
979
980 /* Find the PCI address that maps to the desired VME address */
981 i = image->number;
982
983 /* Locking as we can only do one of these at a time */
984 mutex_lock(&bridge->vme_rmw);
985
986 /* Lock image */
987 spin_lock(&image->lock);
988
989 pci_addr = (uintptr_t)image->kern_base + offset;
990
991 /* Address must be 4-byte aligned */
992 if (pci_addr & 0x3) {
993 dev_err(dev, "RMW Address not 4-byte aligned\n");
994 result = -EINVAL;
995 goto out;
996 }
997
998 /* Ensure RMW Disabled whilst configuring */
999 iowrite32(0, bridge->base + SCYC_CTL);
1000
1001 /* Configure registers */
1002 iowrite32(mask, bridge->base + SCYC_EN);
1003 iowrite32(compare, bridge->base + SCYC_CMP);
1004 iowrite32(swap, bridge->base + SCYC_SWP);
1005 iowrite32(pci_addr, bridge->base + SCYC_ADDR);
1006
1007 /* Enable RMW */
1008 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
1009
1010 /* Kick process off with a read to the required address. */
1011 result = ioread32(image->kern_base + offset);
1012
1013 /* Disable RMW */
1014 iowrite32(0, bridge->base + SCYC_CTL);
1015
1016 out:
1017 spin_unlock(&image->lock);
1018
1019 mutex_unlock(&bridge->vme_rmw);
1020
1021 return result;
1022 }
1023
1024 static int ca91cx42_dma_list_add(struct vme_dma_list *list,
1025 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1026 {
1027 struct ca91cx42_dma_entry *entry, *prev;
1028 struct vme_dma_pci *pci_attr;
1029 struct vme_dma_vme *vme_attr;
1030 dma_addr_t desc_ptr;
1031 int retval = 0;
1032 struct device *dev;
1033
1034 dev = list->parent->parent->parent;
1035
1036 /* XXX descriptor must be aligned on 64-bit boundaries */
1037 entry = kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
1038 if (entry == NULL) {
1039 dev_err(dev, "Failed to allocate memory for dma resource "
1040 "structure\n");
1041 retval = -ENOMEM;
1042 goto err_mem;
1043 }
1044
1045 /* Test descriptor alignment */
1046 if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {
1047 dev_err(dev, "Descriptor not aligned to 16 byte boundary as "
1048 "required: %p\n", &entry->descriptor);
1049 retval = -EINVAL;
1050 goto err_align;
1051 }
1052
1053 memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor));
1054
1055 if (dest->type == VME_DMA_VME) {
1056 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
1057 vme_attr = dest->private;
1058 pci_attr = src->private;
1059 } else {
1060 vme_attr = src->private;
1061 pci_attr = dest->private;
1062 }
1063
1064 /* Check we can do fulfill required attributes */
1065 if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1066 VME_USER2)) != 0) {
1067
1068 dev_err(dev, "Unsupported cycle type\n");
1069 retval = -EINVAL;
1070 goto err_aspace;
1071 }
1072
1073 if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1074 VME_PROG | VME_DATA)) != 0) {
1075
1076 dev_err(dev, "Unsupported cycle type\n");
1077 retval = -EINVAL;
1078 goto err_cycle;
1079 }
1080
1081 /* Check to see if we can fulfill source and destination */
1082 if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1083 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1084
1085 dev_err(dev, "Cannot perform transfer with this "
1086 "source-destination combination\n");
1087 retval = -EINVAL;
1088 goto err_direct;
1089 }
1090
1091 /* Setup cycle types */
1092 if (vme_attr->cycle & VME_BLT)
1093 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1094
1095 /* Setup data width */
1096 switch (vme_attr->dwidth) {
1097 case VME_D8:
1098 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1099 break;
1100 case VME_D16:
1101 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1102 break;
1103 case VME_D32:
1104 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1105 break;
1106 case VME_D64:
1107 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1108 break;
1109 default:
1110 dev_err(dev, "Invalid data width\n");
1111 return -EINVAL;
1112 }
1113
1114 /* Setup address space */
1115 switch (vme_attr->aspace) {
1116 case VME_A16:
1117 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1118 break;
1119 case VME_A24:
1120 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1121 break;
1122 case VME_A32:
1123 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1124 break;
1125 case VME_USER1:
1126 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1127 break;
1128 case VME_USER2:
1129 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1130 break;
1131 default:
1132 dev_err(dev, "Invalid address space\n");
1133 return -EINVAL;
1134 break;
1135 }
1136
1137 if (vme_attr->cycle & VME_SUPER)
1138 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1139 if (vme_attr->cycle & VME_PROG)
1140 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1141
1142 entry->descriptor.dtbc = count;
1143 entry->descriptor.dla = pci_attr->address;
1144 entry->descriptor.dva = vme_attr->address;
1145 entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1146
1147 /* Add to list */
1148 list_add_tail(&entry->list, &list->entries);
1149
1150 /* Fill out previous descriptors "Next Address" */
1151 if (entry->list.prev != &list->entries) {
1152 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1153 list);
1154 /* We need the bus address for the pointer */
1155 desc_ptr = virt_to_bus(&entry->descriptor);
1156 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1157 }
1158
1159 return 0;
1160
1161 err_cycle:
1162 err_aspace:
1163 err_direct:
1164 err_align:
1165 kfree(entry);
1166 err_mem:
1167 return retval;
1168 }
1169
1170 static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1171 {
1172 u32 tmp;
1173 struct ca91cx42_driver *bridge;
1174
1175 bridge = ca91cx42_bridge->driver_priv;
1176
1177 tmp = ioread32(bridge->base + DGCS);
1178
1179 if (tmp & CA91CX42_DGCS_ACT)
1180 return 0;
1181 else
1182 return 1;
1183 }
1184
1185 static int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1186 {
1187 struct vme_dma_resource *ctrlr;
1188 struct ca91cx42_dma_entry *entry;
1189 int retval;
1190 dma_addr_t bus_addr;
1191 u32 val;
1192 struct device *dev;
1193 struct ca91cx42_driver *bridge;
1194
1195 ctrlr = list->parent;
1196
1197 bridge = ctrlr->parent->driver_priv;
1198 dev = ctrlr->parent->parent;
1199
1200 mutex_lock(&ctrlr->mtx);
1201
1202 if (!(list_empty(&ctrlr->running))) {
1203 /*
1204 * XXX We have an active DMA transfer and currently haven't
1205 * sorted out the mechanism for "pending" DMA transfers.
1206 * Return busy.
1207 */
1208 /* Need to add to pending here */
1209 mutex_unlock(&ctrlr->mtx);
1210 return -EBUSY;
1211 } else {
1212 list_add(&list->list, &ctrlr->running);
1213 }
1214
1215 /* Get first bus address and write into registers */
1216 entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry,
1217 list);
1218
1219 bus_addr = virt_to_bus(&entry->descriptor);
1220
1221 mutex_unlock(&ctrlr->mtx);
1222
1223 iowrite32(0, bridge->base + DTBC);
1224 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1225
1226 /* Start the operation */
1227 val = ioread32(bridge->base + DGCS);
1228
1229 /* XXX Could set VMEbus On and Off Counters here */
1230 val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1231
1232 val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1233 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1234 CA91CX42_DGCS_PERR);
1235
1236 iowrite32(val, bridge->base + DGCS);
1237
1238 val |= CA91CX42_DGCS_GO;
1239
1240 iowrite32(val, bridge->base + DGCS);
1241
1242 retval = wait_event_interruptible(bridge->dma_queue,
1243 ca91cx42_dma_busy(ctrlr->parent));
1244
1245 if (retval) {
1246 val = ioread32(bridge->base + DGCS);
1247 iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS);
1248 /* Wait for the operation to abort */
1249 wait_event(bridge->dma_queue,
1250 ca91cx42_dma_busy(ctrlr->parent));
1251 retval = -EINTR;
1252 goto exit;
1253 }
1254
1255 /*
1256 * Read status register, this register is valid until we kick off a
1257 * new transfer.
1258 */
1259 val = ioread32(bridge->base + DGCS);
1260
1261 if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1262 CA91CX42_DGCS_PERR)) {
1263
1264 dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val);
1265 val = ioread32(bridge->base + DCTL);
1266 retval = -EIO;
1267 }
1268
1269 exit:
1270 /* Remove list from running list */
1271 mutex_lock(&ctrlr->mtx);
1272 list_del(&list->list);
1273 mutex_unlock(&ctrlr->mtx);
1274
1275 return retval;
1276
1277 }
1278
1279 static int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1280 {
1281 struct list_head *pos, *temp;
1282 struct ca91cx42_dma_entry *entry;
1283
1284 /* detach and free each entry */
1285 list_for_each_safe(pos, temp, &list->entries) {
1286 list_del(pos);
1287 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1288 kfree(entry);
1289 }
1290
1291 return 0;
1292 }
1293
1294 /*
1295 * All 4 location monitors reside at the same base - this is therefore a
1296 * system wide configuration.
1297 *
1298 * This does not enable the LM monitor - that should be done when the first
1299 * callback is attached and disabled when the last callback is removed.
1300 */
1301 static int ca91cx42_lm_set(struct vme_lm_resource *lm,
1302 unsigned long long lm_base, u32 aspace, u32 cycle)
1303 {
1304 u32 temp_base, lm_ctl = 0;
1305 int i;
1306 struct ca91cx42_driver *bridge;
1307 struct device *dev;
1308
1309 bridge = lm->parent->driver_priv;
1310 dev = lm->parent->parent;
1311
1312 /* Check the alignment of the location monitor */
1313 temp_base = (u32)lm_base;
1314 if (temp_base & 0xffff) {
1315 dev_err(dev, "Location monitor must be aligned to 64KB "
1316 "boundary");
1317 return -EINVAL;
1318 }
1319
1320 mutex_lock(&lm->mtx);
1321
1322 /* If we already have a callback attached, we can't move it! */
1323 for (i = 0; i < lm->monitors; i++) {
1324 if (bridge->lm_callback[i] != NULL) {
1325 mutex_unlock(&lm->mtx);
1326 dev_err(dev, "Location monitor callback attached, "
1327 "can't reset\n");
1328 return -EBUSY;
1329 }
1330 }
1331
1332 switch (aspace) {
1333 case VME_A16:
1334 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1335 break;
1336 case VME_A24:
1337 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1338 break;
1339 case VME_A32:
1340 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1341 break;
1342 default:
1343 mutex_unlock(&lm->mtx);
1344 dev_err(dev, "Invalid address space\n");
1345 return -EINVAL;
1346 break;
1347 }
1348
1349 if (cycle & VME_SUPER)
1350 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1351 if (cycle & VME_USER)
1352 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1353 if (cycle & VME_PROG)
1354 lm_ctl |= CA91CX42_LM_CTL_PGM;
1355 if (cycle & VME_DATA)
1356 lm_ctl |= CA91CX42_LM_CTL_DATA;
1357
1358 iowrite32(lm_base, bridge->base + LM_BS);
1359 iowrite32(lm_ctl, bridge->base + LM_CTL);
1360
1361 mutex_unlock(&lm->mtx);
1362
1363 return 0;
1364 }
1365
1366 /* Get configuration of the callback monitor and return whether it is enabled
1367 * or disabled.
1368 */
1369 static int ca91cx42_lm_get(struct vme_lm_resource *lm,
1370 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
1371 {
1372 u32 lm_ctl, enabled = 0;
1373 struct ca91cx42_driver *bridge;
1374
1375 bridge = lm->parent->driver_priv;
1376
1377 mutex_lock(&lm->mtx);
1378
1379 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1380 lm_ctl = ioread32(bridge->base + LM_CTL);
1381
1382 if (lm_ctl & CA91CX42_LM_CTL_EN)
1383 enabled = 1;
1384
1385 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1386 *aspace = VME_A16;
1387 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1388 *aspace = VME_A24;
1389 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1390 *aspace = VME_A32;
1391
1392 *cycle = 0;
1393 if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1394 *cycle |= VME_SUPER;
1395 if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1396 *cycle |= VME_USER;
1397 if (lm_ctl & CA91CX42_LM_CTL_PGM)
1398 *cycle |= VME_PROG;
1399 if (lm_ctl & CA91CX42_LM_CTL_DATA)
1400 *cycle |= VME_DATA;
1401
1402 mutex_unlock(&lm->mtx);
1403
1404 return enabled;
1405 }
1406
1407 /*
1408 * Attach a callback to a specific location monitor.
1409 *
1410 * Callback will be passed the monitor triggered.
1411 */
1412 static int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1413 void (*callback)(int))
1414 {
1415 u32 lm_ctl, tmp;
1416 struct ca91cx42_driver *bridge;
1417 struct device *dev;
1418
1419 bridge = lm->parent->driver_priv;
1420 dev = lm->parent->parent;
1421
1422 mutex_lock(&lm->mtx);
1423
1424 /* Ensure that the location monitor is configured - need PGM or DATA */
1425 lm_ctl = ioread32(bridge->base + LM_CTL);
1426 if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1427 mutex_unlock(&lm->mtx);
1428 dev_err(dev, "Location monitor not properly configured\n");
1429 return -EINVAL;
1430 }
1431
1432 /* Check that a callback isn't already attached */
1433 if (bridge->lm_callback[monitor] != NULL) {
1434 mutex_unlock(&lm->mtx);
1435 dev_err(dev, "Existing callback attached\n");
1436 return -EBUSY;
1437 }
1438
1439 /* Attach callback */
1440 bridge->lm_callback[monitor] = callback;
1441
1442 /* Enable Location Monitor interrupt */
1443 tmp = ioread32(bridge->base + LINT_EN);
1444 tmp |= CA91CX42_LINT_LM[monitor];
1445 iowrite32(tmp, bridge->base + LINT_EN);
1446
1447 /* Ensure that global Location Monitor Enable set */
1448 if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1449 lm_ctl |= CA91CX42_LM_CTL_EN;
1450 iowrite32(lm_ctl, bridge->base + LM_CTL);
1451 }
1452
1453 mutex_unlock(&lm->mtx);
1454
1455 return 0;
1456 }
1457
1458 /*
1459 * Detach a callback function forn a specific location monitor.
1460 */
1461 static int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1462 {
1463 u32 tmp;
1464 struct ca91cx42_driver *bridge;
1465
1466 bridge = lm->parent->driver_priv;
1467
1468 mutex_lock(&lm->mtx);
1469
1470 /* Disable Location Monitor and ensure previous interrupts are clear */
1471 tmp = ioread32(bridge->base + LINT_EN);
1472 tmp &= ~CA91CX42_LINT_LM[monitor];
1473 iowrite32(tmp, bridge->base + LINT_EN);
1474
1475 iowrite32(CA91CX42_LINT_LM[monitor],
1476 bridge->base + LINT_STAT);
1477
1478 /* Detach callback */
1479 bridge->lm_callback[monitor] = NULL;
1480
1481 /* If all location monitors disabled, disable global Location Monitor */
1482 if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1483 CA91CX42_LINT_LM3)) == 0) {
1484 tmp = ioread32(bridge->base + LM_CTL);
1485 tmp &= ~CA91CX42_LM_CTL_EN;
1486 iowrite32(tmp, bridge->base + LM_CTL);
1487 }
1488
1489 mutex_unlock(&lm->mtx);
1490
1491 return 0;
1492 }
1493
1494 static int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1495 {
1496 u32 slot = 0;
1497 struct ca91cx42_driver *bridge;
1498
1499 bridge = ca91cx42_bridge->driver_priv;
1500
1501 if (!geoid) {
1502 slot = ioread32(bridge->base + VCSR_BS);
1503 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1504 } else
1505 slot = geoid;
1506
1507 return (int)slot;
1508
1509 }
1510
1511 static void *ca91cx42_alloc_consistent(struct device *parent, size_t size,
1512 dma_addr_t *dma)
1513 {
1514 struct pci_dev *pdev;
1515
1516 /* Find pci_dev container of dev */
1517 pdev = to_pci_dev(parent);
1518
1519 return pci_alloc_consistent(pdev, size, dma);
1520 }
1521
1522 static void ca91cx42_free_consistent(struct device *parent, size_t size,
1523 void *vaddr, dma_addr_t dma)
1524 {
1525 struct pci_dev *pdev;
1526
1527 /* Find pci_dev container of dev */
1528 pdev = to_pci_dev(parent);
1529
1530 pci_free_consistent(pdev, size, vaddr, dma);
1531 }
1532
1533 /*
1534 * Configure CR/CSR space
1535 *
1536 * Access to the CR/CSR can be configured at power-up. The location of the
1537 * CR/CSR registers in the CR/CSR address space is determined by the boards
1538 * Auto-ID or Geographic address. This function ensures that the window is
1539 * enabled at an offset consistent with the boards geopgraphic address.
1540 */
1541 static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1542 struct pci_dev *pdev)
1543 {
1544 unsigned int crcsr_addr;
1545 int tmp, slot;
1546 struct ca91cx42_driver *bridge;
1547
1548 bridge = ca91cx42_bridge->driver_priv;
1549
1550 slot = ca91cx42_slot_get(ca91cx42_bridge);
1551
1552 /* Write CSR Base Address if slot ID is supplied as a module param */
1553 if (geoid)
1554 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1555
1556 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1557 if (slot == 0) {
1558 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1559 "CR/CSR space\n");
1560 return -EINVAL;
1561 }
1562
1563 /* Allocate mem for CR/CSR image */
1564 bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1565 &bridge->crcsr_bus);
1566 if (bridge->crcsr_kernel == NULL) {
1567 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1568 "image\n");
1569 return -ENOMEM;
1570 }
1571
1572 crcsr_addr = slot * (512 * 1024);
1573 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1574
1575 tmp = ioread32(bridge->base + VCSR_CTL);
1576 tmp |= CA91CX42_VCSR_CTL_EN;
1577 iowrite32(tmp, bridge->base + VCSR_CTL);
1578
1579 return 0;
1580 }
1581
1582 static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1583 struct pci_dev *pdev)
1584 {
1585 u32 tmp;
1586 struct ca91cx42_driver *bridge;
1587
1588 bridge = ca91cx42_bridge->driver_priv;
1589
1590 /* Turn off CR/CSR space */
1591 tmp = ioread32(bridge->base + VCSR_CTL);
1592 tmp &= ~CA91CX42_VCSR_CTL_EN;
1593 iowrite32(tmp, bridge->base + VCSR_CTL);
1594
1595 /* Free image */
1596 iowrite32(0, bridge->base + VCSR_TO);
1597
1598 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1599 bridge->crcsr_bus);
1600 }
1601
1602 static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1603 {
1604 int retval, i;
1605 u32 data;
1606 struct list_head *pos = NULL, *n;
1607 struct vme_bridge *ca91cx42_bridge;
1608 struct ca91cx42_driver *ca91cx42_device;
1609 struct vme_master_resource *master_image;
1610 struct vme_slave_resource *slave_image;
1611 struct vme_dma_resource *dma_ctrlr;
1612 struct vme_lm_resource *lm;
1613
1614 /* We want to support more than one of each bridge so we need to
1615 * dynamically allocate the bridge structure
1616 */
1617 ca91cx42_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1618
1619 if (ca91cx42_bridge == NULL) {
1620 dev_err(&pdev->dev, "Failed to allocate memory for device "
1621 "structure\n");
1622 retval = -ENOMEM;
1623 goto err_struct;
1624 }
1625 vme_init_bridge(ca91cx42_bridge);
1626
1627 ca91cx42_device = kzalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1628
1629 if (ca91cx42_device == NULL) {
1630 dev_err(&pdev->dev, "Failed to allocate memory for device "
1631 "structure\n");
1632 retval = -ENOMEM;
1633 goto err_driver;
1634 }
1635
1636 ca91cx42_bridge->driver_priv = ca91cx42_device;
1637
1638 /* Enable the device */
1639 retval = pci_enable_device(pdev);
1640 if (retval) {
1641 dev_err(&pdev->dev, "Unable to enable device\n");
1642 goto err_enable;
1643 }
1644
1645 /* Map Registers */
1646 retval = pci_request_regions(pdev, driver_name);
1647 if (retval) {
1648 dev_err(&pdev->dev, "Unable to reserve resources\n");
1649 goto err_resource;
1650 }
1651
1652 /* map registers in BAR 0 */
1653 ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1654 4096);
1655 if (!ca91cx42_device->base) {
1656 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1657 retval = -EIO;
1658 goto err_remap;
1659 }
1660
1661 /* Check to see if the mapping worked out */
1662 data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1663 if (data != PCI_VENDOR_ID_TUNDRA) {
1664 dev_err(&pdev->dev, "PCI_ID check failed\n");
1665 retval = -EIO;
1666 goto err_test;
1667 }
1668
1669 /* Initialize wait queues & mutual exclusion flags */
1670 init_waitqueue_head(&ca91cx42_device->dma_queue);
1671 init_waitqueue_head(&ca91cx42_device->iack_queue);
1672 mutex_init(&ca91cx42_device->vme_int);
1673 mutex_init(&ca91cx42_device->vme_rmw);
1674
1675 ca91cx42_bridge->parent = &pdev->dev;
1676 strcpy(ca91cx42_bridge->name, driver_name);
1677
1678 /* Setup IRQ */
1679 retval = ca91cx42_irq_init(ca91cx42_bridge);
1680 if (retval != 0) {
1681 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1682 goto err_irq;
1683 }
1684
1685 /* Add master windows to list */
1686 for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1687 master_image = kmalloc(sizeof(struct vme_master_resource),
1688 GFP_KERNEL);
1689 if (master_image == NULL) {
1690 dev_err(&pdev->dev, "Failed to allocate memory for "
1691 "master resource structure\n");
1692 retval = -ENOMEM;
1693 goto err_master;
1694 }
1695 master_image->parent = ca91cx42_bridge;
1696 spin_lock_init(&master_image->lock);
1697 master_image->locked = 0;
1698 master_image->number = i;
1699 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1700 VME_CRCSR | VME_USER1 | VME_USER2;
1701 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1702 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1703 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1704 memset(&master_image->bus_resource, 0,
1705 sizeof(struct resource));
1706 master_image->kern_base = NULL;
1707 list_add_tail(&master_image->list,
1708 &ca91cx42_bridge->master_resources);
1709 }
1710
1711 /* Add slave windows to list */
1712 for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1713 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1714 GFP_KERNEL);
1715 if (slave_image == NULL) {
1716 dev_err(&pdev->dev, "Failed to allocate memory for "
1717 "slave resource structure\n");
1718 retval = -ENOMEM;
1719 goto err_slave;
1720 }
1721 slave_image->parent = ca91cx42_bridge;
1722 mutex_init(&slave_image->mtx);
1723 slave_image->locked = 0;
1724 slave_image->number = i;
1725 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1726 VME_USER2;
1727
1728 /* Only windows 0 and 4 support A16 */
1729 if (i == 0 || i == 4)
1730 slave_image->address_attr |= VME_A16;
1731
1732 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1733 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1734 list_add_tail(&slave_image->list,
1735 &ca91cx42_bridge->slave_resources);
1736 }
1737
1738 /* Add dma engines to list */
1739 for (i = 0; i < CA91C142_MAX_DMA; i++) {
1740 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1741 GFP_KERNEL);
1742 if (dma_ctrlr == NULL) {
1743 dev_err(&pdev->dev, "Failed to allocate memory for "
1744 "dma resource structure\n");
1745 retval = -ENOMEM;
1746 goto err_dma;
1747 }
1748 dma_ctrlr->parent = ca91cx42_bridge;
1749 mutex_init(&dma_ctrlr->mtx);
1750 dma_ctrlr->locked = 0;
1751 dma_ctrlr->number = i;
1752 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1753 VME_DMA_MEM_TO_VME;
1754 INIT_LIST_HEAD(&dma_ctrlr->pending);
1755 INIT_LIST_HEAD(&dma_ctrlr->running);
1756 list_add_tail(&dma_ctrlr->list,
1757 &ca91cx42_bridge->dma_resources);
1758 }
1759
1760 /* Add location monitor to list */
1761 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1762 if (lm == NULL) {
1763 dev_err(&pdev->dev, "Failed to allocate memory for "
1764 "location monitor resource structure\n");
1765 retval = -ENOMEM;
1766 goto err_lm;
1767 }
1768 lm->parent = ca91cx42_bridge;
1769 mutex_init(&lm->mtx);
1770 lm->locked = 0;
1771 lm->number = 1;
1772 lm->monitors = 4;
1773 list_add_tail(&lm->list, &ca91cx42_bridge->lm_resources);
1774
1775 ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1776 ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1777 ca91cx42_bridge->master_get = ca91cx42_master_get;
1778 ca91cx42_bridge->master_set = ca91cx42_master_set;
1779 ca91cx42_bridge->master_read = ca91cx42_master_read;
1780 ca91cx42_bridge->master_write = ca91cx42_master_write;
1781 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1782 ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1783 ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1784 ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1785 ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1786 ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1787 ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1788 ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1789 ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1790 ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1791 ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1792 ca91cx42_bridge->alloc_consistent = ca91cx42_alloc_consistent;
1793 ca91cx42_bridge->free_consistent = ca91cx42_free_consistent;
1794
1795 data = ioread32(ca91cx42_device->base + MISC_CTL);
1796 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1797 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1798 dev_info(&pdev->dev, "Slot ID is %d\n",
1799 ca91cx42_slot_get(ca91cx42_bridge));
1800
1801 if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
1802 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1803
1804 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1805 * ca91cx42_remove()
1806 */
1807 retval = vme_register_bridge(ca91cx42_bridge);
1808 if (retval != 0) {
1809 dev_err(&pdev->dev, "Chip Registration failed.\n");
1810 goto err_reg;
1811 }
1812
1813 pci_set_drvdata(pdev, ca91cx42_bridge);
1814
1815 return 0;
1816
1817 err_reg:
1818 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1819 err_lm:
1820 /* resources are stored in link list */
1821 list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
1822 lm = list_entry(pos, struct vme_lm_resource, list);
1823 list_del(pos);
1824 kfree(lm);
1825 }
1826 err_dma:
1827 /* resources are stored in link list */
1828 list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
1829 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1830 list_del(pos);
1831 kfree(dma_ctrlr);
1832 }
1833 err_slave:
1834 /* resources are stored in link list */
1835 list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
1836 slave_image = list_entry(pos, struct vme_slave_resource, list);
1837 list_del(pos);
1838 kfree(slave_image);
1839 }
1840 err_master:
1841 /* resources are stored in link list */
1842 list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
1843 master_image = list_entry(pos, struct vme_master_resource,
1844 list);
1845 list_del(pos);
1846 kfree(master_image);
1847 }
1848
1849 ca91cx42_irq_exit(ca91cx42_device, pdev);
1850 err_irq:
1851 err_test:
1852 iounmap(ca91cx42_device->base);
1853 err_remap:
1854 pci_release_regions(pdev);
1855 err_resource:
1856 pci_disable_device(pdev);
1857 err_enable:
1858 kfree(ca91cx42_device);
1859 err_driver:
1860 kfree(ca91cx42_bridge);
1861 err_struct:
1862 return retval;
1863
1864 }
1865
1866 static void ca91cx42_remove(struct pci_dev *pdev)
1867 {
1868 struct list_head *pos = NULL, *n;
1869 struct vme_master_resource *master_image;
1870 struct vme_slave_resource *slave_image;
1871 struct vme_dma_resource *dma_ctrlr;
1872 struct vme_lm_resource *lm;
1873 struct ca91cx42_driver *bridge;
1874 struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1875
1876 bridge = ca91cx42_bridge->driver_priv;
1877
1878
1879 /* Turn off Ints */
1880 iowrite32(0, bridge->base + LINT_EN);
1881
1882 /* Turn off the windows */
1883 iowrite32(0x00800000, bridge->base + LSI0_CTL);
1884 iowrite32(0x00800000, bridge->base + LSI1_CTL);
1885 iowrite32(0x00800000, bridge->base + LSI2_CTL);
1886 iowrite32(0x00800000, bridge->base + LSI3_CTL);
1887 iowrite32(0x00800000, bridge->base + LSI4_CTL);
1888 iowrite32(0x00800000, bridge->base + LSI5_CTL);
1889 iowrite32(0x00800000, bridge->base + LSI6_CTL);
1890 iowrite32(0x00800000, bridge->base + LSI7_CTL);
1891 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1892 iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1893 iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1894 iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1895 iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1896 iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1897 iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1898 iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1899
1900 vme_unregister_bridge(ca91cx42_bridge);
1901
1902 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1903
1904 /* resources are stored in link list */
1905 list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
1906 lm = list_entry(pos, struct vme_lm_resource, list);
1907 list_del(pos);
1908 kfree(lm);
1909 }
1910
1911 /* resources are stored in link list */
1912 list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
1913 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1914 list_del(pos);
1915 kfree(dma_ctrlr);
1916 }
1917
1918 /* resources are stored in link list */
1919 list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
1920 slave_image = list_entry(pos, struct vme_slave_resource, list);
1921 list_del(pos);
1922 kfree(slave_image);
1923 }
1924
1925 /* resources are stored in link list */
1926 list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
1927 master_image = list_entry(pos, struct vme_master_resource,
1928 list);
1929 list_del(pos);
1930 kfree(master_image);
1931 }
1932
1933 ca91cx42_irq_exit(bridge, pdev);
1934
1935 iounmap(bridge->base);
1936
1937 pci_release_regions(pdev);
1938
1939 pci_disable_device(pdev);
1940
1941 kfree(ca91cx42_bridge);
1942 }
1943
1944 module_pci_driver(ca91cx42_driver);
1945
1946 MODULE_PARM_DESC(geoid, "Override geographical addressing");
1947 module_param(geoid, int, 0);
1948
1949 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1950 MODULE_LICENSE("GPL");
Linux with added FPC-III support