drivers/dma/xilinx/zynqmp_dma.c

   1 /*
   2  * DMA driver for Xilinx ZynqMP DMA Engine
   3  *
   4  * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/dmapool.h>
  14 #include <linux/dma/xilinx_dma.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_dma.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/io-64-nonatomic-lo-hi.h>
  26 #include <linux/pm_runtime.h>
  27
  28 #include "../dmaengine.h"
  29
  30 /* Register Offsets */
  31 #define ZYNQMP_DMA_ISR                  0x100
  32 #define ZYNQMP_DMA_IMR                  0x104
  33 #define ZYNQMP_DMA_IER                  0x108
  34 #define ZYNQMP_DMA_IDS                  0x10C
  35 #define ZYNQMP_DMA_CTRL0                0x110
  36 #define ZYNQMP_DMA_CTRL1                0x114
  37 #define ZYNQMP_DMA_DATA_ATTR            0x120
  38 #define ZYNQMP_DMA_DSCR_ATTR            0x124
  39 #define ZYNQMP_DMA_SRC_DSCR_WRD0        0x128
  40 #define ZYNQMP_DMA_SRC_DSCR_WRD1        0x12C
  41 #define ZYNQMP_DMA_SRC_DSCR_WRD2        0x130
  42 #define ZYNQMP_DMA_SRC_DSCR_WRD3        0x134
  43 #define ZYNQMP_DMA_DST_DSCR_WRD0        0x138
  44 #define ZYNQMP_DMA_DST_DSCR_WRD1        0x13C
  45 #define ZYNQMP_DMA_DST_DSCR_WRD2        0x140
  46 #define ZYNQMP_DMA_DST_DSCR_WRD3        0x144
  47 #define ZYNQMP_DMA_SRC_START_LSB        0x158
  48 #define ZYNQMP_DMA_SRC_START_MSB        0x15C
  49 #define ZYNQMP_DMA_DST_START_LSB        0x160
  50 #define ZYNQMP_DMA_DST_START_MSB        0x164
  51 #define ZYNQMP_DMA_TOTAL_BYTE           0x188
  52 #define ZYNQMP_DMA_RATE_CTRL            0x18C
  53 #define ZYNQMP_DMA_IRQ_SRC_ACCT         0x190
  54 #define ZYNQMP_DMA_IRQ_DST_ACCT         0x194
  55 #define ZYNQMP_DMA_CTRL2                0x200
  56
  57 /* Interrupt registers bit field definitions */
  58 #define ZYNQMP_DMA_DONE                 BIT(10)
  59 #define ZYNQMP_DMA_AXI_WR_DATA          BIT(9)
  60 #define ZYNQMP_DMA_AXI_RD_DATA          BIT(8)
  61 #define ZYNQMP_DMA_AXI_RD_DST_DSCR      BIT(7)
  62 #define ZYNQMP_DMA_AXI_RD_SRC_DSCR      BIT(6)
  63 #define ZYNQMP_DMA_IRQ_DST_ACCT_ERR     BIT(5)
  64 #define ZYNQMP_DMA_IRQ_SRC_ACCT_ERR     BIT(4)
  65 #define ZYNQMP_DMA_BYTE_CNT_OVRFL       BIT(3)
  66 #define ZYNQMP_DMA_DST_DSCR_DONE        BIT(2)
  67 #define ZYNQMP_DMA_INV_APB              BIT(0)
  68
  69 /* Control 0 register bit field definitions */
  70 #define ZYNQMP_DMA_OVR_FETCH            BIT(7)
  71 #define ZYNQMP_DMA_POINT_TYPE_SG        BIT(6)
  72 #define ZYNQMP_DMA_RATE_CTRL_EN         BIT(3)
  73
  74 /* Control 1 register bit field definitions */
  75 #define ZYNQMP_DMA_SRC_ISSUE            GENMASK(4, 0)
  76
  77 /* Data Attribute register bit field definitions */
  78 #define ZYNQMP_DMA_ARBURST              GENMASK(27, 26)
  79 #define ZYNQMP_DMA_ARCACHE              GENMASK(25, 22)
  80 #define ZYNQMP_DMA_ARCACHE_OFST         22
  81 #define ZYNQMP_DMA_ARQOS                GENMASK(21, 18)
  82 #define ZYNQMP_DMA_ARQOS_OFST           18
  83 #define ZYNQMP_DMA_ARLEN                GENMASK(17, 14)
  84 #define ZYNQMP_DMA_ARLEN_OFST           14
  85 #define ZYNQMP_DMA_AWBURST              GENMASK(13, 12)
  86 #define ZYNQMP_DMA_AWCACHE              GENMASK(11, 8)
  87 #define ZYNQMP_DMA_AWCACHE_OFST         8
  88 #define ZYNQMP_DMA_AWQOS                GENMASK(7, 4)
  89 #define ZYNQMP_DMA_AWQOS_OFST           4
  90 #define ZYNQMP_DMA_AWLEN                GENMASK(3, 0)
  91 #define ZYNQMP_DMA_AWLEN_OFST           0
  92
  93 /* Descriptor Attribute register bit field definitions */
  94 #define ZYNQMP_DMA_AXCOHRNT             BIT(8)
  95 #define ZYNQMP_DMA_AXCACHE              GENMASK(7, 4)
  96 #define ZYNQMP_DMA_AXCACHE_OFST         4
  97 #define ZYNQMP_DMA_AXQOS                GENMASK(3, 0)
  98 #define ZYNQMP_DMA_AXQOS_OFST           0
  99
 100 /* Control register 2 bit field definitions */
 101 #define ZYNQMP_DMA_ENABLE               BIT(0)
 102
 103 /* Buffer Descriptor definitions */
 104 #define ZYNQMP_DMA_DESC_CTRL_STOP       0x10
 105 #define ZYNQMP_DMA_DESC_CTRL_COMP_INT   0x4
 106 #define ZYNQMP_DMA_DESC_CTRL_SIZE_256   0x2
 107 #define ZYNQMP_DMA_DESC_CTRL_COHRNT     0x1
 108
 109 /* Interrupt Mask specific definitions */
 110 #define ZYNQMP_DMA_INT_ERR      (ZYNQMP_DMA_AXI_RD_DATA | \
 111                                 ZYNQMP_DMA_AXI_WR_DATA | \
 112                                 ZYNQMP_DMA_AXI_RD_DST_DSCR | \
 113                                 ZYNQMP_DMA_AXI_RD_SRC_DSCR | \
 114                                 ZYNQMP_DMA_INV_APB)
 115 #define ZYNQMP_DMA_INT_OVRFL    (ZYNQMP_DMA_BYTE_CNT_OVRFL | \
 116                                 ZYNQMP_DMA_IRQ_SRC_ACCT_ERR | \
 117                                 ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
 118 #define ZYNQMP_DMA_INT_DONE     (ZYNQMP_DMA_DONE | ZYNQMP_DMA_DST_DSCR_DONE)
 119 #define ZYNQMP_DMA_INT_EN_DEFAULT_MASK  (ZYNQMP_DMA_INT_DONE | \
 120                                         ZYNQMP_DMA_INT_ERR | \
 121                                         ZYNQMP_DMA_INT_OVRFL | \
 122                                         ZYNQMP_DMA_DST_DSCR_DONE)
 123
 124 /* Max number of descriptors per channel */
 125 #define ZYNQMP_DMA_NUM_DESCS    32
 126
 127 /* Max transfer size per descriptor */
 128 #define ZYNQMP_DMA_MAX_TRANS_LEN        0x40000000
 129
 130 /* Reset values for data attributes */
 131 #define ZYNQMP_DMA_AXCACHE_VAL          0xF
 132 #define ZYNQMP_DMA_ARLEN_RST_VAL        0xF
 133 #define ZYNQMP_DMA_AWLEN_RST_VAL        0xF
 134
 135 #define ZYNQMP_DMA_SRC_ISSUE_RST_VAL    0x1F
 136
 137 #define ZYNQMP_DMA_IDS_DEFAULT_MASK     0xFFF
 138
 139 /* Bus width in bits */
 140 #define ZYNQMP_DMA_BUS_WIDTH_64         64
 141 #define ZYNQMP_DMA_BUS_WIDTH_128        128
 142
 143 #define ZDMA_PM_TIMEOUT                 100
 144
 145 #define ZYNQMP_DMA_DESC_SIZE(chan)      (chan->desc_size)
 146
 147 #define to_chan(chan)           container_of(chan, struct zynqmp_dma_chan, \
 148                                              common)
 149 #define tx_to_desc(tx)          container_of(tx, struct zynqmp_dma_desc_sw, \
 150                                              async_tx)
 151
 152 /**
 153  * struct zynqmp_dma_desc_ll - Hw linked list descriptor
 154  * @addr: Buffer address
 155  * @size: Size of the buffer
 156  * @ctrl: Control word
 157  * @nxtdscraddr: Next descriptor base address
 158  * @rsvd: Reserved field and for Hw internal use.
 159  */
 160 struct zynqmp_dma_desc_ll {
 161         u64 addr;
 162         u32 size;
 163         u32 ctrl;
 164         u64 nxtdscraddr;
 165         u64 rsvd;
 166 };
 167
 168 /**
 169  * struct zynqmp_dma_desc_sw - Per Transaction structure
 170  * @src: Source address for simple mode dma
 171  * @dst: Destination address for simple mode dma
 172  * @len: Transfer length for simple mode dma
 173  * @node: Node in the channel descriptor list
 174  * @tx_list: List head for the current transfer
 175  * @async_tx: Async transaction descriptor
 176  * @src_v: Virtual address of the src descriptor
 177  * @src_p: Physical address of the src descriptor
 178  * @dst_v: Virtual address of the dst descriptor
 179  * @dst_p: Physical address of the dst descriptor
 180  */
 181 struct zynqmp_dma_desc_sw {
 182         u64 src;
 183         u64 dst;
 184         u32 len;
 185         struct list_head node;
 186         struct list_head tx_list;
 187         struct dma_async_tx_descriptor async_tx;
 188         struct zynqmp_dma_desc_ll *src_v;
 189         dma_addr_t src_p;
 190         struct zynqmp_dma_desc_ll *dst_v;
 191         dma_addr_t dst_p;
 192 };
 193
 194 /**
 195  * struct zynqmp_dma_chan - Driver specific DMA channel structure
 196  * @zdev: Driver specific device structure
 197  * @regs: Control registers offset
 198  * @lock: Descriptor operation lock
 199  * @pending_list: Descriptors waiting
 200  * @free_list: Descriptors free
 201  * @active_list: Descriptors active
 202  * @sw_desc_pool: SW descriptor pool
 203  * @done_list: Complete descriptors
 204  * @common: DMA common channel
 205  * @desc_pool_v: Statically allocated descriptor base
 206  * @desc_pool_p: Physical allocated descriptor base
 207  * @desc_free_cnt: Descriptor available count
 208  * @dev: The dma device
 209  * @irq: Channel IRQ
 210  * @is_dmacoherent: Tells whether dma operations are coherent or not
 211  * @tasklet: Cleanup work after irq
 212  * @idle : Channel status;
 213  * @desc_size: Size of the low level descriptor
 214  * @err: Channel has errors
 215  * @bus_width: Bus width
 216  * @src_burst_len: Source burst length
 217  * @dst_burst_len: Dest burst length
 218  */
 219 struct zynqmp_dma_chan {
 220         struct zynqmp_dma_device *zdev;
 221         void __iomem *regs;
 222         spinlock_t lock;
 223         struct list_head pending_list;
 224         struct list_head free_list;
 225         struct list_head active_list;
 226         struct zynqmp_dma_desc_sw *sw_desc_pool;
 227         struct list_head done_list;
 228         struct dma_chan common;
 229         void *desc_pool_v;
 230         dma_addr_t desc_pool_p;
 231         u32 desc_free_cnt;
 232         struct device *dev;
 233         int irq;
 234         bool is_dmacoherent;
 235         struct tasklet_struct tasklet;
 236         bool idle;
 237         u32 desc_size;
 238         bool err;
 239         u32 bus_width;
 240         u32 src_burst_len;
 241         u32 dst_burst_len;
 242 };
 243
 244 /**
 245  * struct zynqmp_dma_device - DMA device structure
 246  * @dev: Device Structure
 247  * @common: DMA device structure
 248  * @chan: Driver specific DMA channel
 249  * @clk_main: Pointer to main clock
 250  * @clk_apb: Pointer to apb clock
 251  */
 252 struct zynqmp_dma_device {
 253         struct device *dev;
 254         struct dma_device common;
 255         struct zynqmp_dma_chan *chan;
 256         struct clk *clk_main;
 257         struct clk *clk_apb;
 258 };
 259
 260 static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg,
 261                                      u64 value)
 262 {
 263         lo_hi_writeq(value, chan->regs + reg);
 264 }
 265
 266 /**
 267  * zynqmp_dma_update_desc_to_ctrlr - Updates descriptor to the controller
 268  * @chan: ZynqMP DMA DMA channel pointer
 269  * @desc: Transaction descriptor pointer
 270  */
 271 static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan,
 272                                       struct zynqmp_dma_desc_sw *desc)
 273 {
 274         dma_addr_t addr;
 275
 276         addr = desc->src_p;
 277         zynqmp_dma_writeq(chan, ZYNQMP_DMA_SRC_START_LSB, addr);
 278         addr = desc->dst_p;
 279         zynqmp_dma_writeq(chan, ZYNQMP_DMA_DST_START_LSB, addr);
 280 }
 281
 282 /**
 283  * zynqmp_dma_desc_config_eod - Mark the descriptor as end descriptor
 284  * @chan: ZynqMP DMA channel pointer
 285  * @desc: Hw descriptor pointer
 286  */
 287 static void zynqmp_dma_desc_config_eod(struct zynqmp_dma_chan *chan,
 288                                        void *desc)
 289 {
 290         struct zynqmp_dma_desc_ll *hw = (struct zynqmp_dma_desc_ll *)desc;
 291
 292         hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_STOP;
 293         hw++;
 294         hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_COMP_INT | ZYNQMP_DMA_DESC_CTRL_STOP;
 295 }
 296
 297 /**
 298  * zynqmp_dma_config_sg_ll_desc - Configure the linked list descriptor
 299  * @chan: ZynqMP DMA channel pointer
 300  * @sdesc: Hw descriptor pointer
 301  * @src: Source buffer address
 302  * @dst: Destination buffer address
 303  * @len: Transfer length
 304  * @prev: Previous hw descriptor pointer
 305  */
 306 static void zynqmp_dma_config_sg_ll_desc(struct zynqmp_dma_chan *chan,
 307                                    struct zynqmp_dma_desc_ll *sdesc,
 308                                    dma_addr_t src, dma_addr_t dst, size_t len,
 309                                    struct zynqmp_dma_desc_ll *prev)
 310 {
 311         struct zynqmp_dma_desc_ll *ddesc = sdesc + 1;
 312
 313         sdesc->size = ddesc->size = len;
 314         sdesc->addr = src;
 315         ddesc->addr = dst;
 316
 317         sdesc->ctrl = ddesc->ctrl = ZYNQMP_DMA_DESC_CTRL_SIZE_256;
 318         if (chan->is_dmacoherent) {
 319                 sdesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
 320                 ddesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
 321         }
 322
 323         if (prev) {
 324                 dma_addr_t addr = chan->desc_pool_p +
 325                             ((uintptr_t)sdesc - (uintptr_t)chan->desc_pool_v);
 326                 ddesc = prev + 1;
 327                 prev->nxtdscraddr = addr;
 328                 ddesc->nxtdscraddr = addr + ZYNQMP_DMA_DESC_SIZE(chan);
 329         }
 330 }
 331
 332 /**
 333  * zynqmp_dma_init - Initialize the channel
 334  * @chan: ZynqMP DMA channel pointer
 335  */
 336 static void zynqmp_dma_init(struct zynqmp_dma_chan *chan)
 337 {
 338         u32 val;
 339
 340         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 341         val = readl(chan->regs + ZYNQMP_DMA_ISR);
 342         writel(val, chan->regs + ZYNQMP_DMA_ISR);
 343
 344         if (chan->is_dmacoherent) {
 345                 val = ZYNQMP_DMA_AXCOHRNT;
 346                 val = (val & ~ZYNQMP_DMA_AXCACHE) |
 347                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AXCACHE_OFST);
 348                 writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR);
 349         }
 350
 351         val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
 352         if (chan->is_dmacoherent) {
 353                 val = (val & ~ZYNQMP_DMA_ARCACHE) |
 354                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_ARCACHE_OFST);
 355                 val = (val & ~ZYNQMP_DMA_AWCACHE) |
 356                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AWCACHE_OFST);
 357         }
 358         writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
 359
 360         /* Clearing the interrupt account rgisters */
 361         val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
 362         val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 363
 364         chan->idle = true;
 365 }
 366
 367 /**
 368  * zynqmp_dma_tx_submit - Submit DMA transaction
 369  * @tx: Async transaction descriptor pointer
 370  *
 371  * Return: cookie value
 372  */
 373 static dma_cookie_t zynqmp_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 374 {
 375         struct zynqmp_dma_chan *chan = to_chan(tx->chan);
 376         struct zynqmp_dma_desc_sw *desc, *new;
 377         dma_cookie_t cookie;
 378         unsigned long irqflags;
 379
 380         new = tx_to_desc(tx);
 381         spin_lock_irqsave(&chan->lock, irqflags);
 382         cookie = dma_cookie_assign(tx);
 383
 384         if (!list_empty(&chan->pending_list)) {
 385                 desc = list_last_entry(&chan->pending_list,
 386                                      struct zynqmp_dma_desc_sw, node);
 387                 if (!list_empty(&desc->tx_list))
 388                         desc = list_last_entry(&desc->tx_list,
 389                                                struct zynqmp_dma_desc_sw, node);
 390                 desc->src_v->nxtdscraddr = new->src_p;
 391                 desc->src_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
 392                 desc->dst_v->nxtdscraddr = new->dst_p;
 393                 desc->dst_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
 394         }
 395
 396         list_add_tail(&new->node, &chan->pending_list);
 397         spin_unlock_irqrestore(&chan->lock, irqflags);
 398
 399         return cookie;
 400 }
 401
 402 /**
 403  * zynqmp_dma_get_descriptor - Get the sw descriptor from the pool
 404  * @chan: ZynqMP DMA channel pointer
 405  *
 406  * Return: The sw descriptor
 407  */
 408 static struct zynqmp_dma_desc_sw *
 409 zynqmp_dma_get_descriptor(struct zynqmp_dma_chan *chan)
 410 {
 411         struct zynqmp_dma_desc_sw *desc;
 412         unsigned long irqflags;
 413
 414         spin_lock_irqsave(&chan->lock, irqflags);
 415         desc = list_first_entry(&chan->free_list,
 416                                 struct zynqmp_dma_desc_sw, node);
 417         list_del(&desc->node);
 418         spin_unlock_irqrestore(&chan->lock, irqflags);
 419
 420         INIT_LIST_HEAD(&desc->tx_list);
 421         /* Clear the src and dst descriptor memory */
 422         memset((void *)desc->src_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
 423         memset((void *)desc->dst_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
 424
 425         return desc;
 426 }
 427
 428 /**
 429  * zynqmp_dma_free_descriptor - Issue pending transactions
 430  * @chan: ZynqMP DMA channel pointer
 431  * @sdesc: Transaction descriptor pointer
 432  */
 433 static void zynqmp_dma_free_descriptor(struct zynqmp_dma_chan *chan,
 434                                  struct zynqmp_dma_desc_sw *sdesc)
 435 {
 436         struct zynqmp_dma_desc_sw *child, *next;
 437
 438         chan->desc_free_cnt++;
 439         list_add_tail(&sdesc->node, &chan->free_list);
 440         list_for_each_entry_safe(child, next, &sdesc->tx_list, node) {
 441                 chan->desc_free_cnt++;
 442                 list_move_tail(&child->node, &chan->free_list);
 443         }
 444 }
 445
 446 /**
 447  * zynqmp_dma_free_desc_list - Free descriptors list
 448  * @chan: ZynqMP DMA channel pointer
 449  * @list: List to parse and delete the descriptor
 450  */
 451 static void zynqmp_dma_free_desc_list(struct zynqmp_dma_chan *chan,
 452                                       struct list_head *list)
 453 {
 454         struct zynqmp_dma_desc_sw *desc, *next;
 455
 456         list_for_each_entry_safe(desc, next, list, node)
 457                 zynqmp_dma_free_descriptor(chan, desc);
 458 }
 459
 460 /**
 461  * zynqmp_dma_alloc_chan_resources - Allocate channel resources
 462  * @dchan: DMA channel
 463  *
 464  * Return: Number of descriptors on success and failure value on error
 465  */
 466 static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan)
 467 {
 468         struct zynqmp_dma_chan *chan = to_chan(dchan);
 469         struct zynqmp_dma_desc_sw *desc;
 470         int i, ret;
 471
 472         ret = pm_runtime_get_sync(chan->dev);
 473         if (ret < 0)
 474                 return ret;
 475
 476         chan->sw_desc_pool = kcalloc(ZYNQMP_DMA_NUM_DESCS, sizeof(*desc),
 477                                      GFP_KERNEL);
 478         if (!chan->sw_desc_pool)
 479                 return -ENOMEM;
 480
 481         chan->idle = true;
 482         chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS;
 483
 484         INIT_LIST_HEAD(&chan->free_list);
 485
 486         for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
 487                 desc = chan->sw_desc_pool + i;
 488                 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
 489                 desc->async_tx.tx_submit = zynqmp_dma_tx_submit;
 490                 list_add_tail(&desc->node, &chan->free_list);
 491         }
 492
 493         chan->desc_pool_v = dma_alloc_coherent(chan->dev,
 494                                                (2 * chan->desc_size * ZYNQMP_DMA_NUM_DESCS),
 495                                                &chan->desc_pool_p, GFP_KERNEL);
 496         if (!chan->desc_pool_v)
 497                 return -ENOMEM;
 498
 499         for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
 500                 desc = chan->sw_desc_pool + i;
 501                 desc->src_v = (struct zynqmp_dma_desc_ll *) (chan->desc_pool_v +
 502                                         (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2));
 503                 desc->dst_v = (struct zynqmp_dma_desc_ll *) (desc->src_v + 1);
 504                 desc->src_p = chan->desc_pool_p +
 505                                 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2);
 506                 desc->dst_p = desc->src_p + ZYNQMP_DMA_DESC_SIZE(chan);
 507         }
 508
 509         return ZYNQMP_DMA_NUM_DESCS;
 510 }
 511
 512 /**
 513  * zynqmp_dma_start - Start DMA channel
 514  * @chan: ZynqMP DMA channel pointer
 515  */
 516 static void zynqmp_dma_start(struct zynqmp_dma_chan *chan)
 517 {
 518         writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER);
 519         writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
 520         chan->idle = false;
 521         writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2);
 522 }
 523
 524 /**
 525  * zynqmp_dma_handle_ovfl_int - Process the overflow interrupt
 526  * @chan: ZynqMP DMA channel pointer
 527  * @status: Interrupt status value
 528  */
 529 static void zynqmp_dma_handle_ovfl_int(struct zynqmp_dma_chan *chan, u32 status)
 530 {
 531         if (status & ZYNQMP_DMA_BYTE_CNT_OVRFL)
 532                 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
 533         if (status & ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
 534                 readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 535         if (status & ZYNQMP_DMA_IRQ_SRC_ACCT_ERR)
 536                 readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
 537 }
 538
 539 static void zynqmp_dma_config(struct zynqmp_dma_chan *chan)
 540 {
 541         u32 val;
 542
 543         val = readl(chan->regs + ZYNQMP_DMA_CTRL0);
 544         val |= ZYNQMP_DMA_POINT_TYPE_SG;
 545         writel(val, chan->regs + ZYNQMP_DMA_CTRL0);
 546
 547         val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
 548         val = (val & ~ZYNQMP_DMA_ARLEN) |
 549                 (chan->src_burst_len << ZYNQMP_DMA_ARLEN_OFST);
 550         val = (val & ~ZYNQMP_DMA_AWLEN) |
 551                 (chan->dst_burst_len << ZYNQMP_DMA_AWLEN_OFST);
 552         writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
 553 }
 554
 555 /**
 556  * zynqmp_dma_device_config - Zynqmp dma device configuration
 557  * @dchan: DMA channel
 558  * @config: DMA device config
 559  *
 560  * Return: 0 always
 561  */
 562 static int zynqmp_dma_device_config(struct dma_chan *dchan,
 563                                     struct dma_slave_config *config)
 564 {
 565         struct zynqmp_dma_chan *chan = to_chan(dchan);
 566
 567         chan->src_burst_len = config->src_maxburst;
 568         chan->dst_burst_len = config->dst_maxburst;
 569
 570         return 0;
 571 }
 572
 573 /**
 574  * zynqmp_dma_start_transfer - Initiate the new transfer
 575  * @chan: ZynqMP DMA channel pointer
 576  */
 577 static void zynqmp_dma_start_transfer(struct zynqmp_dma_chan *chan)
 578 {
 579         struct zynqmp_dma_desc_sw *desc;
 580
 581         if (!chan->idle)
 582                 return;
 583
 584         zynqmp_dma_config(chan);
 585
 586         desc = list_first_entry_or_null(&chan->pending_list,
 587                                         struct zynqmp_dma_desc_sw, node);
 588         if (!desc)
 589                 return;
 590
 591         list_splice_tail_init(&chan->pending_list, &chan->active_list);
 592         zynqmp_dma_update_desc_to_ctrlr(chan, desc);
 593         zynqmp_dma_start(chan);
 594 }
 595
 596
 597 /**
 598  * zynqmp_dma_chan_desc_cleanup - Cleanup the completed descriptors
 599  * @chan: ZynqMP DMA channel
 600  */
 601 static void zynqmp_dma_chan_desc_cleanup(struct zynqmp_dma_chan *chan)
 602 {
 603         struct zynqmp_dma_desc_sw *desc, *next;
 604
 605         list_for_each_entry_safe(desc, next, &chan->done_list, node) {
 606                 dma_async_tx_callback callback;
 607                 void *callback_param;
 608
 609                 list_del(&desc->node);
 610
 611                 callback = desc->async_tx.callback;
 612                 callback_param = desc->async_tx.callback_param;
 613                 if (callback) {
 614                         spin_unlock(&chan->lock);
 615                         callback(callback_param);
 616                         spin_lock(&chan->lock);
 617                 }
 618
 619                 /* Run any dependencies, then free the descriptor */
 620                 zynqmp_dma_free_descriptor(chan, desc);
 621         }
 622 }
 623
 624 /**
 625  * zynqmp_dma_complete_descriptor - Mark the active descriptor as complete
 626  * @chan: ZynqMP DMA channel pointer
 627  */
 628 static void zynqmp_dma_complete_descriptor(struct zynqmp_dma_chan *chan)
 629 {
 630         struct zynqmp_dma_desc_sw *desc;
 631
 632         desc = list_first_entry_or_null(&chan->active_list,
 633                                         struct zynqmp_dma_desc_sw, node);
 634         if (!desc)
 635                 return;
 636         list_del(&desc->node);
 637         dma_cookie_complete(&desc->async_tx);
 638         list_add_tail(&desc->node, &chan->done_list);
 639 }
 640
 641 /**
 642  * zynqmp_dma_issue_pending - Issue pending transactions
 643  * @dchan: DMA channel pointer
 644  */
 645 static void zynqmp_dma_issue_pending(struct dma_chan *dchan)
 646 {
 647         struct zynqmp_dma_chan *chan = to_chan(dchan);
 648         unsigned long irqflags;
 649
 650         spin_lock_irqsave(&chan->lock, irqflags);
 651         zynqmp_dma_start_transfer(chan);
 652         spin_unlock_irqrestore(&chan->lock, irqflags);
 653 }
 654
 655 /**
 656  * zynqmp_dma_free_descriptors - Free channel descriptors
 657  * @chan: ZynqMP DMA channel pointer
 658  */
 659 static void zynqmp_dma_free_descriptors(struct zynqmp_dma_chan *chan)
 660 {
 661         zynqmp_dma_free_desc_list(chan, &chan->active_list);
 662         zynqmp_dma_free_desc_list(chan, &chan->pending_list);
 663         zynqmp_dma_free_desc_list(chan, &chan->done_list);
 664 }
 665
 666 /**
 667  * zynqmp_dma_free_chan_resources - Free channel resources
 668  * @dchan: DMA channel pointer
 669  */
 670 static void zynqmp_dma_free_chan_resources(struct dma_chan *dchan)
 671 {
 672         struct zynqmp_dma_chan *chan = to_chan(dchan);
 673         unsigned long irqflags;
 674
 675         spin_lock_irqsave(&chan->lock, irqflags);
 676         zynqmp_dma_free_descriptors(chan);
 677         spin_unlock_irqrestore(&chan->lock, irqflags);
 678         dma_free_coherent(chan->dev,
 679                 (2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS),
 680                 chan->desc_pool_v, chan->desc_pool_p);
 681         kfree(chan->sw_desc_pool);
 682         pm_runtime_mark_last_busy(chan->dev);
 683         pm_runtime_put_autosuspend(chan->dev);
 684 }
 685
 686 /**
 687  * zynqmp_dma_reset - Reset the channel
 688  * @chan: ZynqMP DMA channel pointer
 689  */
 690 static void zynqmp_dma_reset(struct zynqmp_dma_chan *chan)
 691 {
 692         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 693
 694         zynqmp_dma_complete_descriptor(chan);
 695         zynqmp_dma_chan_desc_cleanup(chan);
 696         zynqmp_dma_free_descriptors(chan);
 697         zynqmp_dma_init(chan);
 698 }
 699
 700 /**
 701  * zynqmp_dma_irq_handler - ZynqMP DMA Interrupt handler
 702  * @irq: IRQ number
 703  * @data: Pointer to the ZynqMP DMA channel structure
 704  *
 705  * Return: IRQ_HANDLED/IRQ_NONE
 706  */
 707 static irqreturn_t zynqmp_dma_irq_handler(int irq, void *data)
 708 {
 709         struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
 710         u32 isr, imr, status;
 711         irqreturn_t ret = IRQ_NONE;
 712
 713         isr = readl(chan->regs + ZYNQMP_DMA_ISR);
 714         imr = readl(chan->regs + ZYNQMP_DMA_IMR);
 715         status = isr & ~imr;
 716
 717         writel(isr, chan->regs + ZYNQMP_DMA_ISR);
 718         if (status & ZYNQMP_DMA_INT_DONE) {
 719                 tasklet_schedule(&chan->tasklet);
 720                 ret = IRQ_HANDLED;
 721         }
 722
 723         if (status & ZYNQMP_DMA_DONE)
 724                 chan->idle = true;
 725
 726         if (status & ZYNQMP_DMA_INT_ERR) {
 727                 chan->err = true;
 728                 tasklet_schedule(&chan->tasklet);
 729                 dev_err(chan->dev, "Channel %p has errors\n", chan);
 730                 ret = IRQ_HANDLED;
 731         }
 732
 733         if (status & ZYNQMP_DMA_INT_OVRFL) {
 734                 zynqmp_dma_handle_ovfl_int(chan, status);
 735                 dev_dbg(chan->dev, "Channel %p overflow interrupt\n", chan);
 736                 ret = IRQ_HANDLED;
 737         }
 738
 739         return ret;
 740 }
 741
 742 /**
 743  * zynqmp_dma_do_tasklet - Schedule completion tasklet
 744  * @data: Pointer to the ZynqMP DMA channel structure
 745  */
 746 static void zynqmp_dma_do_tasklet(unsigned long data)
 747 {
 748         struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
 749         u32 count;
 750         unsigned long irqflags;
 751
 752         spin_lock_irqsave(&chan->lock, irqflags);
 753
 754         if (chan->err) {
 755                 zynqmp_dma_reset(chan);
 756                 chan->err = false;
 757                 goto unlock;
 758         }
 759
 760         count = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 761
 762         while (count) {
 763                 zynqmp_dma_complete_descriptor(chan);
 764                 zynqmp_dma_chan_desc_cleanup(chan);
 765                 count--;
 766         }
 767
 768         if (chan->idle)
 769                 zynqmp_dma_start_transfer(chan);
 770
 771 unlock:
 772         spin_unlock_irqrestore(&chan->lock, irqflags);
 773 }
 774
 775 /**
 776  * zynqmp_dma_device_terminate_all - Aborts all transfers on a channel
 777  * @dchan: DMA channel pointer
 778  *
 779  * Return: Always '0'
 780  */
 781 static int zynqmp_dma_device_terminate_all(struct dma_chan *dchan)
 782 {
 783         struct zynqmp_dma_chan *chan = to_chan(dchan);
 784         unsigned long irqflags;
 785
 786         spin_lock_irqsave(&chan->lock, irqflags);
 787         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 788         zynqmp_dma_free_descriptors(chan);
 789         spin_unlock_irqrestore(&chan->lock, irqflags);
 790
 791         return 0;
 792 }
 793
 794 /**
 795  * zynqmp_dma_prep_memcpy - prepare descriptors for memcpy transaction
 796  * @dchan: DMA channel
 797  * @dma_dst: Destination buffer address
 798  * @dma_src: Source buffer address
 799  * @len: Transfer length
 800  * @flags: transfer ack flags
 801  *
 802  * Return: Async transaction descriptor on success and NULL on failure
 803  */
 804 static struct dma_async_tx_descriptor *zynqmp_dma_prep_memcpy(
 805                                 struct dma_chan *dchan, dma_addr_t dma_dst,
 806                                 dma_addr_t dma_src, size_t len, ulong flags)
 807 {
 808         struct zynqmp_dma_chan *chan;
 809         struct zynqmp_dma_desc_sw *new, *first = NULL;
 810         void *desc = NULL, *prev = NULL;
 811         size_t copy;
 812         u32 desc_cnt;
 813         unsigned long irqflags;
 814
 815         chan = to_chan(dchan);
 816
 817         desc_cnt = DIV_ROUND_UP(len, ZYNQMP_DMA_MAX_TRANS_LEN);
 818
 819         spin_lock_irqsave(&chan->lock, irqflags);
 820         if (desc_cnt > chan->desc_free_cnt) {
 821                 spin_unlock_irqrestore(&chan->lock, irqflags);
 822                 dev_dbg(chan->dev, "chan %p descs are not available\n", chan);
 823                 return NULL;
 824         }
 825         chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt;
 826         spin_unlock_irqrestore(&chan->lock, irqflags);
 827
 828         do {
 829                 /* Allocate and populate the descriptor */
 830                 new = zynqmp_dma_get_descriptor(chan);
 831
 832                 copy = min_t(size_t, len, ZYNQMP_DMA_MAX_TRANS_LEN);
 833                 desc = (struct zynqmp_dma_desc_ll *)new->src_v;
 834                 zynqmp_dma_config_sg_ll_desc(chan, desc, dma_src,
 835                                              dma_dst, copy, prev);
 836                 prev = desc;
 837                 len -= copy;
 838                 dma_src += copy;
 839                 dma_dst += copy;
 840                 if (!first)
 841                         first = new;
 842                 else
 843                         list_add_tail(&new->node, &first->tx_list);
 844         } while (len);
 845
 846         zynqmp_dma_desc_config_eod(chan, desc);
 847         async_tx_ack(&first->async_tx);
 848         first->async_tx.flags = flags;
 849         return &first->async_tx;
 850 }
 851
 852 /**
 853  * zynqmp_dma_chan_remove - Channel remove function
 854  * @chan: ZynqMP DMA channel pointer
 855  */
 856 static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan)
 857 {
 858         if (!chan)
 859                 return;
 860
 861         if (chan->irq)
 862                 devm_free_irq(chan->zdev->dev, chan->irq, chan);
 863         tasklet_kill(&chan->tasklet);
 864         list_del(&chan->common.device_node);
 865 }
 866
 867 /**
 868  * zynqmp_dma_chan_probe - Per Channel Probing
 869  * @zdev: Driver specific device structure
 870  * @pdev: Pointer to the platform_device structure
 871  *
 872  * Return: '0' on success and failure value on error
 873  */
 874 static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev,
 875                            struct platform_device *pdev)
 876 {
 877         struct zynqmp_dma_chan *chan;
 878         struct resource *res;
 879         struct device_node *node = pdev->dev.of_node;
 880         int err;
 881
 882         chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
 883         if (!chan)
 884                 return -ENOMEM;
 885         chan->dev = zdev->dev;
 886         chan->zdev = zdev;
 887
 888         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 889         chan->regs = devm_ioremap_resource(&pdev->dev, res);
 890         if (IS_ERR(chan->regs))
 891                 return PTR_ERR(chan->regs);
 892
 893         chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
 894         chan->dst_burst_len = ZYNQMP_DMA_AWLEN_RST_VAL;
 895         chan->src_burst_len = ZYNQMP_DMA_ARLEN_RST_VAL;
 896         err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width);
 897         if (err < 0) {
 898                 dev_err(&pdev->dev, "missing xlnx,bus-width property\n");
 899                 return err;
 900         }
 901
 902         if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 &&
 903             chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) {
 904                 dev_err(zdev->dev, "invalid bus-width value");
 905                 return -EINVAL;
 906         }
 907
 908         chan->is_dmacoherent =  of_property_read_bool(node, "dma-coherent");
 909         zdev->chan = chan;
 910         tasklet_init(&chan->tasklet, zynqmp_dma_do_tasklet, (ulong)chan);
 911         spin_lock_init(&chan->lock);
 912         INIT_LIST_HEAD(&chan->active_list);
 913         INIT_LIST_HEAD(&chan->pending_list);
 914         INIT_LIST_HEAD(&chan->done_list);
 915         INIT_LIST_HEAD(&chan->free_list);
 916
 917         dma_cookie_init(&chan->common);
 918         chan->common.device = &zdev->common;
 919         list_add_tail(&chan->common.device_node, &zdev->common.channels);
 920
 921         zynqmp_dma_init(chan);
 922         chan->irq = platform_get_irq(pdev, 0);
 923         if (chan->irq < 0)
 924                 return -ENXIO;
 925         err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0,
 926                                "zynqmp-dma", chan);
 927         if (err)
 928                 return err;
 929
 930         chan->desc_size = sizeof(struct zynqmp_dma_desc_ll);
 931         chan->idle = true;
 932         return 0;
 933 }
 934
 935 /**
 936  * of_zynqmp_dma_xlate - Translation function
 937  * @dma_spec: Pointer to DMA specifier as found in the device tree
 938  * @ofdma: Pointer to DMA controller data
 939  *
 940  * Return: DMA channel pointer on success and NULL on error
 941  */
 942 static struct dma_chan *of_zynqmp_dma_xlate(struct of_phandle_args *dma_spec,
 943                                             struct of_dma *ofdma)
 944 {
 945         struct zynqmp_dma_device *zdev = ofdma->of_dma_data;
 946
 947         return dma_get_slave_channel(&zdev->chan->common);
 948 }
 949
 950 /**
 951  * zynqmp_dma_suspend - Suspend method for the driver
 952  * @dev:        Address of the device structure
 953  *
 954  * Put the driver into low power mode.
 955  * Return: 0 on success and failure value on error
 956  */
 957 static int __maybe_unused zynqmp_dma_suspend(struct device *dev)
 958 {
 959         if (!device_may_wakeup(dev))
 960                 return pm_runtime_force_suspend(dev);
 961
 962         return 0;
 963 }
 964
 965 /**
 966  * zynqmp_dma_resume - Resume from suspend
 967  * @dev:        Address of the device structure
 968  *
 969  * Resume operation after suspend.
 970  * Return: 0 on success and failure value on error
 971  */
 972 static int __maybe_unused zynqmp_dma_resume(struct device *dev)
 973 {
 974         if (!device_may_wakeup(dev))
 975                 return pm_runtime_force_resume(dev);
 976
 977         return 0;
 978 }
 979
 980 /**
 981  * zynqmp_dma_runtime_suspend - Runtime suspend method for the driver
 982  * @dev:        Address of the device structure
 983  *
 984  * Put the driver into low power mode.
 985  * Return: 0 always
 986  */
 987 static int __maybe_unused zynqmp_dma_runtime_suspend(struct device *dev)
 988 {
 989         struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
 990
 991         clk_disable_unprepare(zdev->clk_main);
 992         clk_disable_unprepare(zdev->clk_apb);
 993
 994         return 0;
 995 }
 996
 997 /**
 998  * zynqmp_dma_runtime_resume - Runtime suspend method for the driver
 999  * @dev:        Address of the device structure
1000  *
1001  * Put the driver into low power mode.
1002  * Return: 0 always
1003  */
1004 static int __maybe_unused zynqmp_dma_runtime_resume(struct device *dev)
1005 {
1006         struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
1007         int err;
1008
1009         err = clk_prepare_enable(zdev->clk_main);
1010         if (err) {
1011                 dev_err(dev, "Unable to enable main clock.\n");
1012                 return err;
1013         }
1014
1015         err = clk_prepare_enable(zdev->clk_apb);
1016         if (err) {
1017                 dev_err(dev, "Unable to enable apb clock.\n");
1018                 clk_disable_unprepare(zdev->clk_main);
1019                 return err;
1020         }
1021
1022         return 0;
1023 }
1024
1025 static const struct dev_pm_ops zynqmp_dma_dev_pm_ops = {
1026         SET_SYSTEM_SLEEP_PM_OPS(zynqmp_dma_suspend, zynqmp_dma_resume)
1027         SET_RUNTIME_PM_OPS(zynqmp_dma_runtime_suspend,
1028                            zynqmp_dma_runtime_resume, NULL)
1029 };
1030
1031 /**
1032  * zynqmp_dma_probe - Driver probe function
1033  * @pdev: Pointer to the platform_device structure
1034  *
1035  * Return: '0' on success and failure value on error
1036  */
1037 static int zynqmp_dma_probe(struct platform_device *pdev)
1038 {
1039         struct zynqmp_dma_device *zdev;
1040         struct dma_device *p;
1041         int ret;
1042
1043         zdev = devm_kzalloc(&pdev->dev, sizeof(*zdev), GFP_KERNEL);
1044         if (!zdev)
1045                 return -ENOMEM;
1046
1047         zdev->dev = &pdev->dev;
1048         INIT_LIST_HEAD(&zdev->common.channels);
1049
1050         dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1051         dma_cap_set(DMA_MEMCPY, zdev->common.cap_mask);
1052
1053         p = &zdev->common;
1054         p->device_prep_dma_memcpy = zynqmp_dma_prep_memcpy;
1055         p->device_terminate_all = zynqmp_dma_device_terminate_all;
1056         p->device_issue_pending = zynqmp_dma_issue_pending;
1057         p->device_alloc_chan_resources = zynqmp_dma_alloc_chan_resources;
1058         p->device_free_chan_resources = zynqmp_dma_free_chan_resources;
1059         p->device_tx_status = dma_cookie_status;
1060         p->device_config = zynqmp_dma_device_config;
1061         p->dev = &pdev->dev;
1062
1063         zdev->clk_main = devm_clk_get(&pdev->dev, "clk_main");
1064         if (IS_ERR(zdev->clk_main)) {
1065                 dev_err(&pdev->dev, "main clock not found.\n");
1066                 return PTR_ERR(zdev->clk_main);
1067         }
1068
1069         zdev->clk_apb = devm_clk_get(&pdev->dev, "clk_apb");
1070         if (IS_ERR(zdev->clk_apb)) {
1071                 dev_err(&pdev->dev, "apb clock not found.\n");
1072                 return PTR_ERR(zdev->clk_apb);
1073         }
1074
1075         platform_set_drvdata(pdev, zdev);
1076         pm_runtime_set_autosuspend_delay(zdev->dev, ZDMA_PM_TIMEOUT);
1077         pm_runtime_use_autosuspend(zdev->dev);
1078         pm_runtime_enable(zdev->dev);
1079         pm_runtime_get_sync(zdev->dev);
1080         if (!pm_runtime_enabled(zdev->dev)) {
1081                 ret = zynqmp_dma_runtime_resume(zdev->dev);
1082                 if (ret)
1083                         return ret;
1084         }
1085
1086         ret = zynqmp_dma_chan_probe(zdev, pdev);
1087         if (ret) {
1088                 dev_err(&pdev->dev, "Probing channel failed\n");
1089                 goto err_disable_pm;
1090         }
1091
1092         p->dst_addr_widths = BIT(zdev->chan->bus_width / 8);
1093         p->src_addr_widths = BIT(zdev->chan->bus_width / 8);
1094
1095         dma_async_device_register(&zdev->common);
1096
1097         ret = of_dma_controller_register(pdev->dev.of_node,
1098                                          of_zynqmp_dma_xlate, zdev);
1099         if (ret) {
1100                 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
1101                 dma_async_device_unregister(&zdev->common);
1102                 goto free_chan_resources;
1103         }
1104
1105         pm_runtime_mark_last_busy(zdev->dev);
1106         pm_runtime_put_sync_autosuspend(zdev->dev);
1107
1108         dev_info(&pdev->dev, "ZynqMP DMA driver Probe success\n");
1109
1110         return 0;
1111
1112 free_chan_resources:
1113         zynqmp_dma_chan_remove(zdev->chan);
1114 err_disable_pm:
1115         if (!pm_runtime_enabled(zdev->dev))
1116                 zynqmp_dma_runtime_suspend(zdev->dev);
1117         pm_runtime_disable(zdev->dev);
1118         return ret;
1119 }
1120
1121 /**
1122  * zynqmp_dma_remove - Driver remove function
1123  * @pdev: Pointer to the platform_device structure
1124  *
1125  * Return: Always '0'
1126  */
1127 static int zynqmp_dma_remove(struct platform_device *pdev)
1128 {
1129         struct zynqmp_dma_device *zdev = platform_get_drvdata(pdev);
1130
1131         of_dma_controller_free(pdev->dev.of_node);
1132         dma_async_device_unregister(&zdev->common);
1133
1134         zynqmp_dma_chan_remove(zdev->chan);
1135         pm_runtime_disable(zdev->dev);
1136         if (!pm_runtime_enabled(zdev->dev))
1137                 zynqmp_dma_runtime_suspend(zdev->dev);
1138
1139         return 0;
1140 }
1141
1142 static const struct of_device_id zynqmp_dma_of_match[] = {
1143         { .compatible = "xlnx,zynqmp-dma-1.0", },
1144         {}
1145 };
1146 MODULE_DEVICE_TABLE(of, zynqmp_dma_of_match);
1147
1148 static struct platform_driver zynqmp_dma_driver = {
1149         .driver = {
1150                 .name = "xilinx-zynqmp-dma",
1151                 .of_match_table = zynqmp_dma_of_match,
1152                 .pm = &zynqmp_dma_dev_pm_ops,
1153         },
1154         .probe = zynqmp_dma_probe,
1155         .remove = zynqmp_dma_remove,
1156 };
1157
1158 module_platform_driver(zynqmp_dma_driver);
1159
1160 MODULE_LICENSE("GPL");
1161 MODULE_AUTHOR("Xilinx, Inc.");
1162 MODULE_DESCRIPTION("Xilinx ZynqMP DMA driver");