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regulator: s2mps11: Adjust supported buck voltages to real values
[linux/fpc-iii.git] / drivers / video / fbdev / aty / atyfb_base.c
blobb6fe103df1453ef1417cf36f306932d5410593f3
1 /*
2 * ATI Frame Buffer Device Driver Core
3 *
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
8 *
9 * This driver supports the following ATI graphics chips:
10 * - ATI Mach64
11 *
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
15 *
16 * This driver is partly based on the PowerMac console driver:
17 *
18 * Copyright (C) 1996 Paul Mackerras
19 *
20 * and on the PowerMac ATI/mach64 display driver:
21 *
22 * Copyright (C) 1997 Michael AK Tesch
23 *
24 * with work by Jon Howell
25 * Harry AC Eaton
26 * Anthony Tong <atong@uiuc.edu>
27 *
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
30 *
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
33 * more details.
34 *
35 * Many thanks to Nitya from ATI devrel for support and patience !
36 */
37
38 /******************************************************************************
39
40 TODO:
41
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
46
47 (Anyone with Mac to help with this?)
48
49 ******************************************************************************/
50
51
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/kernel.h>
55 #include <linux/errno.h>
56 #include <linux/string.h>
57 #include <linux/mm.h>
58 #include <linux/slab.h>
59 #include <linux/vmalloc.h>
60 #include <linux/delay.h>
61 #include <linux/compiler.h>
62 #include <linux/console.h>
63 #include <linux/fb.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
69 #include <linux/backlight.h>
70 #include <linux/reboot.h>
71 #include <linux/dmi.h>
72
73 #include <asm/io.h>
74 #include <linux/uaccess.h>
75
76 #include <video/mach64.h>
77 #include "atyfb.h"
78 #include "ati_ids.h"
79
80 #ifdef __powerpc__
81 #include <asm/machdep.h>
82 #include <asm/prom.h>
83 #include "../macmodes.h"
84 #endif
85 #ifdef __sparc__
86 #include <asm/fbio.h>
87 #include <asm/oplib.h>
88 #include <asm/prom.h>
89 #endif
90
91 #ifdef CONFIG_ADB_PMU
92 #include <linux/adb.h>
93 #include <linux/pmu.h>
94 #endif
95 #ifdef CONFIG_BOOTX_TEXT
96 #include <asm/btext.h>
97 #endif
98 #ifdef CONFIG_PMAC_BACKLIGHT
99 #include <asm/backlight.h>
100 #endif
101
102 /*
103 * Debug flags.
104 */
105 #undef DEBUG
106 /*#define DEBUG*/
107
108 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
109 /* - must be large enough to catch all GUI-Regs */
110 /* - must be aligned to a PAGE boundary */
111 #define GUI_RESERVE (1 * PAGE_SIZE)
112
113 /* FIXME: remove the FAIL definition */
114 #define FAIL(msg) do { \
115 if (!(var->activate & FB_ACTIVATE_TEST)) \
116 printk(KERN_CRIT "atyfb: " msg "\n"); \
117 return -EINVAL; \
118 } while (0)
119 #define FAIL_MAX(msg, x, _max_) do { \
120 if (x > _max_) { \
121 if (!(var->activate & FB_ACTIVATE_TEST)) \
122 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
123 return -EINVAL; \
124 } \
125 } while (0)
126 #ifdef DEBUG
127 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
128 #else
129 #define DPRINTK(fmt, args...)
130 #endif
131
132 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
133 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
134
135 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
136 defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
137 static const u32 lt_lcd_regs[] = {
138 CNFG_PANEL_LG,
139 LCD_GEN_CNTL_LG,
140 DSTN_CONTROL_LG,
141 HFB_PITCH_ADDR_LG,
142 HORZ_STRETCHING_LG,
143 VERT_STRETCHING_LG,
144 0, /* EXT_VERT_STRETCH */
145 LT_GIO_LG,
146 POWER_MANAGEMENT_LG
147 };
148
149 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
150 {
151 if (M64_HAS(LT_LCD_REGS)) {
152 aty_st_le32(lt_lcd_regs[index], val, par);
153 } else {
154 unsigned long temp;
155
156 /* write addr byte */
157 temp = aty_ld_le32(LCD_INDEX, par);
158 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
159 /* write the register value */
160 aty_st_le32(LCD_DATA, val, par);
161 }
162 }
163
164 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
165 {
166 if (M64_HAS(LT_LCD_REGS)) {
167 return aty_ld_le32(lt_lcd_regs[index], par);
168 } else {
169 unsigned long temp;
170
171 /* write addr byte */
172 temp = aty_ld_le32(LCD_INDEX, par);
173 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
174 /* read the register value */
175 return aty_ld_le32(LCD_DATA, par);
176 }
177 }
178 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
179
180 #ifdef CONFIG_FB_ATY_GENERIC_LCD
181 /*
182 * ATIReduceRatio --
183 *
184 * Reduce a fraction by factoring out the largest common divider of the
185 * fraction's numerator and denominator.
186 */
187 static void ATIReduceRatio(int *Numerator, int *Denominator)
188 {
189 int Multiplier, Divider, Remainder;
190
191 Multiplier = *Numerator;
192 Divider = *Denominator;
193
194 while ((Remainder = Multiplier % Divider)) {
195 Multiplier = Divider;
196 Divider = Remainder;
197 }
198
199 *Numerator /= Divider;
200 *Denominator /= Divider;
201 }
202 #endif
203 /*
204 * The Hardware parameters for each card
205 */
206
207 struct pci_mmap_map {
208 unsigned long voff;
209 unsigned long poff;
210 unsigned long size;
211 unsigned long prot_flag;
212 unsigned long prot_mask;
213 };
214
215 static const struct fb_fix_screeninfo atyfb_fix = {
216 .id = "ATY Mach64",
217 .type = FB_TYPE_PACKED_PIXELS,
218 .visual = FB_VISUAL_PSEUDOCOLOR,
219 .xpanstep = 8,
220 .ypanstep = 1,
221 };
222
223 /*
224 * Frame buffer device API
225 */
226
227 static int atyfb_open(struct fb_info *info, int user);
228 static int atyfb_release(struct fb_info *info, int user);
229 static int atyfb_check_var(struct fb_var_screeninfo *var,
230 struct fb_info *info);
231 static int atyfb_set_par(struct fb_info *info);
232 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
233 u_int transp, struct fb_info *info);
234 static int atyfb_pan_display(struct fb_var_screeninfo *var,
235 struct fb_info *info);
236 static int atyfb_blank(int blank, struct fb_info *info);
237 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
238 #ifdef __sparc__
239 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
240 #endif
241 static int atyfb_sync(struct fb_info *info);
242
243 /*
244 * Internal routines
245 */
246
247 static int aty_init(struct fb_info *info);
248
249 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
250
251 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
252 static int aty_var_to_crtc(const struct fb_info *info,
253 const struct fb_var_screeninfo *var,
254 struct crtc *crtc);
255 static int aty_crtc_to_var(const struct crtc *crtc,
256 struct fb_var_screeninfo *var);
257 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
258 #ifdef CONFIG_PPC
259 static int read_aty_sense(const struct atyfb_par *par);
260 #endif
261
262 static DEFINE_MUTEX(reboot_lock);
263 static struct fb_info *reboot_info;
264
265 /*
266 * Interface used by the world
267 */
268
269 static struct fb_var_screeninfo default_var = {
270 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
271 640, 480, 640, 480, 0, 0, 8, 0,
272 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
273 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
274 0, FB_VMODE_NONINTERLACED
275 };
276
277 static const struct fb_videomode defmode = {
278 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
279 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
280 0, FB_VMODE_NONINTERLACED
281 };
282
283 static struct fb_ops atyfb_ops = {
284 .owner = THIS_MODULE,
285 .fb_open = atyfb_open,
286 .fb_release = atyfb_release,
287 .fb_check_var = atyfb_check_var,
288 .fb_set_par = atyfb_set_par,
289 .fb_setcolreg = atyfb_setcolreg,
290 .fb_pan_display = atyfb_pan_display,
291 .fb_blank = atyfb_blank,
292 .fb_ioctl = atyfb_ioctl,
293 .fb_fillrect = atyfb_fillrect,
294 .fb_copyarea = atyfb_copyarea,
295 .fb_imageblit = atyfb_imageblit,
296 #ifdef __sparc__
297 .fb_mmap = atyfb_mmap,
298 #endif
299 .fb_sync = atyfb_sync,
300 };
301
302 static bool noaccel;
303 static bool nomtrr;
304 static int vram;
305 static int pll;
306 static int mclk;
307 static int xclk;
308 static int comp_sync = -1;
309 static char *mode;
310
311 #ifdef CONFIG_PMAC_BACKLIGHT
312 static int backlight = 1;
313 #else
314 static int backlight = 0;
315 #endif
316
317 #ifdef CONFIG_PPC
318 static int default_vmode = VMODE_CHOOSE;
319 static int default_cmode = CMODE_CHOOSE;
320
321 module_param_named(vmode, default_vmode, int, 0);
322 MODULE_PARM_DESC(vmode, "int: video mode for mac");
323 module_param_named(cmode, default_cmode, int, 0);
324 MODULE_PARM_DESC(cmode, "int: color mode for mac");
325 #endif
326
327 #ifdef CONFIG_ATARI
328 static unsigned int mach64_count = 0;
329 static unsigned long phys_vmembase[FB_MAX] = { 0, };
330 static unsigned long phys_size[FB_MAX] = { 0, };
331 static unsigned long phys_guiregbase[FB_MAX] = { 0, };
332 #endif
333
334 /* top -> down is an evolution of mach64 chipset, any corrections? */
335 #define ATI_CHIP_88800GX (M64F_GX)
336 #define ATI_CHIP_88800CX (M64F_GX)
337
338 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
339 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
340
341 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
342 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
343
344 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
345 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
346 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
347
348 /* FIXME what is this chip? */
349 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
350
351 /* make sets shorter */
352 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
353
354 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
355 /*#define ATI_CHIP_264GTDVD ?*/
356 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
357
358 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
359 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
360 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
361
362 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_XL_MEM)
363 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_XL_MEM | M64F_MOBIL_BUS)
364
365 static struct {
366 u16 pci_id;
367 const char *name;
368 int pll, mclk, xclk, ecp_max;
369 u32 features;
370 } aty_chips[] = {
371 #ifdef CONFIG_FB_ATY_GX
372 /* Mach64 GX */
373 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
374 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
375 #endif /* CONFIG_FB_ATY_GX */
376
377 #ifdef CONFIG_FB_ATY_CT
378 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
379 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
380
381 /* FIXME what is this chip? */
382 { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
383
384 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
385 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
386
387 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
388 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
389
390 { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
391
392 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
393
394 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
395 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
396 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
397 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
398
399 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
400 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
401 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
402 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
403 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
404
405 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
406 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
407 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
408 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
409 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
410
411 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
412 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
413 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
414 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
415 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
416 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
417
418 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
419 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
420 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
421 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
422 #endif /* CONFIG_FB_ATY_CT */
423 };
424
425 /*
426 * Last page of 8 MB (4 MB on ISA) aperture is MMIO,
427 * unless the auxiliary register aperture is used.
428 */
429 static void aty_fudge_framebuffer_len(struct fb_info *info)
430 {
431 struct atyfb_par *par = (struct atyfb_par *) info->par;
432
433 if (!par->aux_start &&
434 (info->fix.smem_len == 0x800000 ||
435 (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
436 info->fix.smem_len -= GUI_RESERVE;
437 }
438
439 static int correct_chipset(struct atyfb_par *par)
440 {
441 u8 rev;
442 u16 type;
443 u32 chip_id;
444 const char *name;
445 int i;
446
447 for (i = (int)ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
448 if (par->pci_id == aty_chips[i].pci_id)
449 break;
450
451 if (i < 0)
452 return -ENODEV;
453
454 name = aty_chips[i].name;
455 par->pll_limits.pll_max = aty_chips[i].pll;
456 par->pll_limits.mclk = aty_chips[i].mclk;
457 par->pll_limits.xclk = aty_chips[i].xclk;
458 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
459 par->features = aty_chips[i].features;
460
461 chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
462 type = chip_id & CFG_CHIP_TYPE;
463 rev = (chip_id & CFG_CHIP_REV) >> 24;
464
465 switch (par->pci_id) {
466 #ifdef CONFIG_FB_ATY_GX
467 case PCI_CHIP_MACH64GX:
468 if (type != 0x00d7)
469 return -ENODEV;
470 break;
471 case PCI_CHIP_MACH64CX:
472 if (type != 0x0057)
473 return -ENODEV;
474 break;
475 #endif
476 #ifdef CONFIG_FB_ATY_CT
477 case PCI_CHIP_MACH64VT:
478 switch (rev & 0x07) {
479 case 0x00:
480 switch (rev & 0xc0) {
481 case 0x00:
482 name = "ATI264VT (A3) (Mach64 VT)";
483 par->pll_limits.pll_max = 170;
484 par->pll_limits.mclk = 67;
485 par->pll_limits.xclk = 67;
486 par->pll_limits.ecp_max = 80;
487 par->features = ATI_CHIP_264VT;
488 break;
489 case 0x40:
490 name = "ATI264VT2 (A4) (Mach64 VT)";
491 par->pll_limits.pll_max = 200;
492 par->pll_limits.mclk = 67;
493 par->pll_limits.xclk = 67;
494 par->pll_limits.ecp_max = 80;
495 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
496 break;
497 }
498 break;
499 case 0x01:
500 name = "ATI264VT3 (B1) (Mach64 VT)";
501 par->pll_limits.pll_max = 200;
502 par->pll_limits.mclk = 67;
503 par->pll_limits.xclk = 67;
504 par->pll_limits.ecp_max = 80;
505 par->features = ATI_CHIP_264VTB;
506 break;
507 case 0x02:
508 name = "ATI264VT3 (B2) (Mach64 VT)";
509 par->pll_limits.pll_max = 200;
510 par->pll_limits.mclk = 67;
511 par->pll_limits.xclk = 67;
512 par->pll_limits.ecp_max = 80;
513 par->features = ATI_CHIP_264VT3;
514 break;
515 }
516 break;
517 case PCI_CHIP_MACH64GT:
518 switch (rev & 0x07) {
519 case 0x01:
520 name = "3D RAGE II (Mach64 GT)";
521 par->pll_limits.pll_max = 170;
522 par->pll_limits.mclk = 67;
523 par->pll_limits.xclk = 67;
524 par->pll_limits.ecp_max = 80;
525 par->features = ATI_CHIP_264GTB;
526 break;
527 case 0x02:
528 name = "3D RAGE II+ (Mach64 GT)";
529 par->pll_limits.pll_max = 200;
530 par->pll_limits.mclk = 67;
531 par->pll_limits.xclk = 67;
532 par->pll_limits.ecp_max = 100;
533 par->features = ATI_CHIP_264GTB;
534 break;
535 }
536 break;
537 #endif
538 }
539
540 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
541 return 0;
542 }
543
544 static char ram_dram[] __maybe_unused = "DRAM";
545 static char ram_resv[] __maybe_unused = "RESV";
546 #ifdef CONFIG_FB_ATY_GX
547 static char ram_vram[] = "VRAM";
548 #endif /* CONFIG_FB_ATY_GX */
549 #ifdef CONFIG_FB_ATY_CT
550 static char ram_edo[] = "EDO";
551 static char ram_sdram[] = "SDRAM (1:1)";
552 static char ram_sgram[] = "SGRAM (1:1)";
553 static char ram_sdram32[] = "SDRAM (2:1) (32-bit)";
554 static char ram_wram[] = "WRAM";
555 static char ram_off[] = "OFF";
556 #endif /* CONFIG_FB_ATY_CT */
557
558
559 #ifdef CONFIG_FB_ATY_GX
560 static char *aty_gx_ram[8] = {
561 ram_dram, ram_vram, ram_vram, ram_dram,
562 ram_dram, ram_vram, ram_vram, ram_resv
563 };
564 #endif /* CONFIG_FB_ATY_GX */
565
566 #ifdef CONFIG_FB_ATY_CT
567 static char *aty_ct_ram[8] = {
568 ram_off, ram_dram, ram_edo, ram_edo,
569 ram_sdram, ram_sgram, ram_wram, ram_resv
570 };
571 static char *aty_xl_ram[8] = {
572 ram_off, ram_dram, ram_edo, ram_edo,
573 ram_sdram, ram_sgram, ram_sdram32, ram_resv
574 };
575 #endif /* CONFIG_FB_ATY_CT */
576
577 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var,
578 struct atyfb_par *par)
579 {
580 u32 pixclock = var->pixclock;
581 #ifdef CONFIG_FB_ATY_GENERIC_LCD
582 u32 lcd_on_off;
583 par->pll.ct.xres = 0;
584 if (par->lcd_table != 0) {
585 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
586 if (lcd_on_off & LCD_ON) {
587 par->pll.ct.xres = var->xres;
588 pixclock = par->lcd_pixclock;
589 }
590 }
591 #endif
592 return pixclock;
593 }
594
595 #if defined(CONFIG_PPC)
596
597 /*
598 * Apple monitor sense
599 */
600
601 static int read_aty_sense(const struct atyfb_par *par)
602 {
603 int sense, i;
604
605 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
606 __delay(200);
607 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
608 __delay(2000);
609 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
610 sense = ((i & 0x3000) >> 3) | (i & 0x100);
611
612 /* drive each sense line low in turn and collect the other 2 */
613 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
614 __delay(2000);
615 i = aty_ld_le32(GP_IO, par);
616 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
617 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
618 __delay(200);
619
620 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
621 __delay(2000);
622 i = aty_ld_le32(GP_IO, par);
623 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
624 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
625 __delay(200);
626
627 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
628 __delay(2000);
629 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
630 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
631 return sense;
632 }
633
634 #endif /* defined(CONFIG_PPC) */
635
636 /* ------------------------------------------------------------------------- */
637
638 /*
639 * CRTC programming
640 */
641
642 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
643 {
644 #ifdef CONFIG_FB_ATY_GENERIC_LCD
645 if (par->lcd_table != 0) {
646 if (!M64_HAS(LT_LCD_REGS)) {
647 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
648 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
649 }
650 crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par);
651 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
652
653
654 /* switch to non shadow registers */
655 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
656 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
657
658 /* save stretching */
659 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
660 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
661 if (!M64_HAS(LT_LCD_REGS))
662 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
663 }
664 #endif
665 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
666 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
667 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
668 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
669 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
670 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
671 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
672
673 #ifdef CONFIG_FB_ATY_GENERIC_LCD
674 if (par->lcd_table != 0) {
675 /* switch to shadow registers */
676 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
677 SHADOW_EN | SHADOW_RW_EN, par);
678
679 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
680 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
681 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
682 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
683
684 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
685 }
686 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
687 }
688
689 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
690 {
691 #ifdef CONFIG_FB_ATY_GENERIC_LCD
692 if (par->lcd_table != 0) {
693 /* stop CRTC */
694 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl &
695 ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
696
697 /* update non-shadow registers first */
698 aty_st_lcd(CNFG_PANEL, crtc->lcd_config_panel, par);
699 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
700 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
701
702 /* temporarily disable stretching */
703 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching &
704 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
705 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching &
706 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
707 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
708 }
709 #endif
710 /* turn off CRT */
711 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
712
713 DPRINTK("setting up CRTC\n");
714 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
715 ((((crtc->h_tot_disp >> 16) & 0xff) + 1) << 3),
716 (((crtc->v_tot_disp >> 16) & 0x7ff) + 1),
717 (crtc->h_sync_strt_wid & 0x200000) ? 'N' : 'P',
718 (crtc->v_sync_strt_wid & 0x200000) ? 'N' : 'P',
719 (crtc->gen_cntl & CRTC_CSYNC_EN) ? 'P' : 'N');
720
721 DPRINTK("CRTC_H_TOTAL_DISP: %x\n", crtc->h_tot_disp);
722 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n", crtc->h_sync_strt_wid);
723 DPRINTK("CRTC_V_TOTAL_DISP: %x\n", crtc->v_tot_disp);
724 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n", crtc->v_sync_strt_wid);
725 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
726 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
727 DPRINTK("CRTC_GEN_CNTL: %x\n", crtc->gen_cntl);
728
729 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
730 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
731 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
732 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
733 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
734 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
735
736 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
737 #if 0
738 FIXME
739 if (par->accel_flags & FB_ACCELF_TEXT)
740 aty_init_engine(par, info);
741 #endif
742 #ifdef CONFIG_FB_ATY_GENERIC_LCD
743 /* after setting the CRTC registers we should set the LCD registers. */
744 if (par->lcd_table != 0) {
745 /* switch to shadow registers */
746 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
747 SHADOW_EN | SHADOW_RW_EN, par);
748
749 DPRINTK("set shadow CRT to %ix%i %c%c\n",
750 ((((crtc->shadow_h_tot_disp >> 16) & 0xff) + 1) << 3),
751 (((crtc->shadow_v_tot_disp >> 16) & 0x7ff) + 1),
752 (crtc->shadow_h_sync_strt_wid & 0x200000) ? 'N' : 'P',
753 (crtc->shadow_v_sync_strt_wid & 0x200000) ? 'N' : 'P');
754
755 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n",
756 crtc->shadow_h_tot_disp);
757 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n",
758 crtc->shadow_h_sync_strt_wid);
759 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n",
760 crtc->shadow_v_tot_disp);
761 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n",
762 crtc->shadow_v_sync_strt_wid);
763
764 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
765 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
766 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
767 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
768
769 /* restore CRTC selection & shadow state and enable stretching */
770 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
771 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
772 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
773 if (!M64_HAS(LT_LCD_REGS))
774 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
775
776 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
777 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
778 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
779 if (!M64_HAS(LT_LCD_REGS)) {
780 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
781 aty_ld_le32(LCD_INDEX, par);
782 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
783 }
784 }
785 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
786 }
787
788 static u32 calc_line_length(struct atyfb_par *par, u32 vxres, u32 bpp)
789 {
790 u32 line_length = vxres * bpp / 8;
791
792 if (par->ram_type == SGRAM ||
793 (!M64_HAS(XL_MEM) && par->ram_type == WRAM))
794 line_length = (line_length + 63) & ~63;
795
796 return line_length;
797 }
798
799 static int aty_var_to_crtc(const struct fb_info *info,
800 const struct fb_var_screeninfo *var,
801 struct crtc *crtc)
802 {
803 struct atyfb_par *par = (struct atyfb_par *) info->par;
804 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
805 u32 sync, vmode;
806 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
807 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
808 u32 pix_width, dp_pix_width, dp_chain_mask;
809 u32 line_length;
810
811 /* input */
812 xres = (var->xres + 7) & ~7;
813 yres = var->yres;
814 vxres = (var->xres_virtual + 7) & ~7;
815 vyres = var->yres_virtual;
816 xoffset = (var->xoffset + 7) & ~7;
817 yoffset = var->yoffset;
818 bpp = var->bits_per_pixel;
819 if (bpp == 16)
820 bpp = (var->green.length == 5) ? 15 : 16;
821 sync = var->sync;
822 vmode = var->vmode;
823
824 /* convert (and round up) and validate */
825 if (vxres < xres + xoffset)
826 vxres = xres + xoffset;
827 h_disp = xres;
828
829 if (vyres < yres + yoffset)
830 vyres = yres + yoffset;
831 v_disp = yres;
832
833 if (bpp <= 8) {
834 bpp = 8;
835 pix_width = CRTC_PIX_WIDTH_8BPP;
836 dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP |
837 BYTE_ORDER_LSB_TO_MSB;
838 dp_chain_mask = DP_CHAIN_8BPP;
839 } else if (bpp <= 15) {
840 bpp = 16;
841 pix_width = CRTC_PIX_WIDTH_15BPP;
842 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
843 BYTE_ORDER_LSB_TO_MSB;
844 dp_chain_mask = DP_CHAIN_15BPP;
845 } else if (bpp <= 16) {
846 bpp = 16;
847 pix_width = CRTC_PIX_WIDTH_16BPP;
848 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
849 BYTE_ORDER_LSB_TO_MSB;
850 dp_chain_mask = DP_CHAIN_16BPP;
851 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
852 bpp = 24;
853 pix_width = CRTC_PIX_WIDTH_24BPP;
854 dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP |
855 BYTE_ORDER_LSB_TO_MSB;
856 dp_chain_mask = DP_CHAIN_24BPP;
857 } else if (bpp <= 32) {
858 bpp = 32;
859 pix_width = CRTC_PIX_WIDTH_32BPP;
860 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
861 BYTE_ORDER_LSB_TO_MSB;
862 dp_chain_mask = DP_CHAIN_32BPP;
863 } else
864 FAIL("invalid bpp");
865
866 line_length = calc_line_length(par, vxres, bpp);
867
868 if (vyres * line_length > info->fix.smem_len)
869 FAIL("not enough video RAM");
870
871 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
872 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
873
874 if ((xres > 1920) || (yres > 1200)) {
875 FAIL("MACH64 chips are designed for max 1920x1200\n"
876 "select another resolution.");
877 }
878 h_sync_strt = h_disp + var->right_margin;
879 h_sync_end = h_sync_strt + var->hsync_len;
880 h_sync_dly = var->right_margin & 7;
881 h_total = h_sync_end + h_sync_dly + var->left_margin;
882
883 v_sync_strt = v_disp + var->lower_margin;
884 v_sync_end = v_sync_strt + var->vsync_len;
885 v_total = v_sync_end + var->upper_margin;
886
887 #ifdef CONFIG_FB_ATY_GENERIC_LCD
888 if (par->lcd_table != 0) {
889 if (!M64_HAS(LT_LCD_REGS)) {
890 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
891 crtc->lcd_index = lcd_index &
892 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS |
893 LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
894 aty_st_le32(LCD_INDEX, lcd_index, par);
895 }
896
897 if (!M64_HAS(MOBIL_BUS))
898 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
899
900 crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par) | 0x4000;
901 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
902
903 crtc->lcd_gen_cntl &=
904 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
905 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
906 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
907 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
908
909 if ((crtc->lcd_gen_cntl & LCD_ON) &&
910 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
911 /*
912 * We cannot display the mode on the LCD. If the CRT is
913 * enabled we can turn off the LCD.
914 * If the CRT is off, it isn't a good idea to switch it
915 * on; we don't know if one is connected. So it's better
916 * to fail then.
917 */
918 if (crtc->lcd_gen_cntl & CRT_ON) {
919 if (!(var->activate & FB_ACTIVATE_TEST))
920 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
921 crtc->lcd_gen_cntl &= ~LCD_ON;
922 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
923 } else {
924 if (!(var->activate & FB_ACTIVATE_TEST))
925 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
926 return -EINVAL;
927 }
928 }
929 }
930
931 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
932 int VScan = 1;
933 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
934 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
935 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
936
937 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
938
939 /*
940 * This is horror! When we simulate, say 640x480 on an 800x600
941 * LCD monitor, the CRTC should be programmed 800x600 values for
942 * the non visible part, but 640x480 for the visible part.
943 * This code has been tested on a laptop with it's 1400x1050 LCD
944 * monitor and a conventional monitor both switched on.
945 * Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
946 * works with little glitches also with DOUBLESCAN modes
947 */
948 if (yres < par->lcd_height) {
949 VScan = par->lcd_height / yres;
950 if (VScan > 1) {
951 VScan = 2;
952 vmode |= FB_VMODE_DOUBLE;
953 }
954 }
955
956 h_sync_strt = h_disp + par->lcd_right_margin;
957 h_sync_end = h_sync_strt + par->lcd_hsync_len;
958 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
959 h_total = h_disp + par->lcd_hblank_len;
960
961 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
962 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
963 v_total = v_disp + par->lcd_vblank_len / VScan;
964 }
965 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
966
967 h_disp = (h_disp >> 3) - 1;
968 h_sync_strt = (h_sync_strt >> 3) - 1;
969 h_sync_end = (h_sync_end >> 3) - 1;
970 h_total = (h_total >> 3) - 1;
971 h_sync_wid = h_sync_end - h_sync_strt;
972
973 FAIL_MAX("h_disp too large", h_disp, 0xff);
974 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
975 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
976 if (h_sync_wid > 0x1f)
977 h_sync_wid = 0x1f;
978 FAIL_MAX("h_total too large", h_total, 0x1ff);
979
980 if (vmode & FB_VMODE_DOUBLE) {
981 v_disp <<= 1;
982 v_sync_strt <<= 1;
983 v_sync_end <<= 1;
984 v_total <<= 1;
985 }
986
987 v_disp--;
988 v_sync_strt--;
989 v_sync_end--;
990 v_total--;
991 v_sync_wid = v_sync_end - v_sync_strt;
992
993 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
994 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
995 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
996 if (v_sync_wid > 0x1f)
997 v_sync_wid = 0x1f;
998 FAIL_MAX("v_total too large", v_total, 0x7ff);
999
1000 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
1001
1002 /* output */
1003 crtc->vxres = vxres;
1004 crtc->vyres = vyres;
1005 crtc->xoffset = xoffset;
1006 crtc->yoffset = yoffset;
1007 crtc->bpp = bpp;
1008 crtc->off_pitch =
1009 ((yoffset * line_length + xoffset * bpp / 8) / 8) |
1010 ((line_length / bpp) << 22);
1011 crtc->vline_crnt_vline = 0;
1012
1013 crtc->h_tot_disp = h_total | (h_disp << 16);
1014 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly << 8) |
1015 ((h_sync_strt & 0x100) << 4) | (h_sync_wid << 16) |
1016 (h_sync_pol << 21);
1017 crtc->v_tot_disp = v_total | (v_disp << 16);
1018 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1019 (v_sync_pol << 21);
1020
1021 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
1022 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
1023 crtc->gen_cntl |= CRTC_VGA_LINEAR;
1024
1025 /* Enable doublescan mode if requested */
1026 if (vmode & FB_VMODE_DOUBLE)
1027 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
1028 /* Enable interlaced mode if requested */
1029 if (vmode & FB_VMODE_INTERLACED)
1030 crtc->gen_cntl |= CRTC_INTERLACE_EN;
1031 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1032 if (par->lcd_table != 0) {
1033 u32 vdisplay = yres;
1034 if (vmode & FB_VMODE_DOUBLE)
1035 vdisplay <<= 1;
1036 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
1037 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1038 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1039 USE_SHADOWED_VEND |
1040 USE_SHADOWED_ROWCUR |
1041 SHADOW_EN | SHADOW_RW_EN);
1042 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR/* | LOCK_8DOT*/;
1043
1044 /* MOBILITY M1 tested, FIXME: LT */
1045 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1046 if (!M64_HAS(LT_LCD_REGS))
1047 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1048 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1049
1050 crtc->horz_stretching &= ~(HORZ_STRETCH_RATIO |
1051 HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1052 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1053 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1054 do {
1055 /*
1056 * The horizontal blender misbehaves when
1057 * HDisplay is less than a certain threshold
1058 * (440 for a 1024-wide panel). It doesn't
1059 * stretch such modes enough. Use pixel
1060 * replication instead of blending to stretch
1061 * modes that can be made to exactly fit the
1062 * panel width. The undocumented "NoLCDBlend"
1063 * option allows the pixel-replicated mode to
1064 * be slightly wider or narrower than the
1065 * panel width. It also causes a mode that is
1066 * exactly half as wide as the panel to be
1067 * pixel-replicated, rather than blended.
1068 */
1069 int HDisplay = xres & ~7;
1070 int nStretch = par->lcd_width / HDisplay;
1071 int Remainder = par->lcd_width % HDisplay;
1072
1073 if ((!Remainder && ((nStretch > 2))) ||
1074 (((HDisplay * 16) / par->lcd_width) < 7)) {
1075 static const char StretchLoops[] = { 10, 12, 13, 15, 16 };
1076 int horz_stretch_loop = -1, BestRemainder;
1077 int Numerator = HDisplay, Denominator = par->lcd_width;
1078 int Index = 5;
1079 ATIReduceRatio(&Numerator, &Denominator);
1080
1081 BestRemainder = (Numerator * 16) / Denominator;
1082 while (--Index >= 0) {
1083 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1084 Denominator;
1085 if (Remainder < BestRemainder) {
1086 horz_stretch_loop = Index;
1087 if (!(BestRemainder = Remainder))
1088 break;
1089 }
1090 }
1091
1092 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1093 int horz_stretch_ratio = 0, Accumulator = 0;
1094 int reuse_previous = 1;
1095
1096 Index = StretchLoops[horz_stretch_loop];
1097
1098 while (--Index >= 0) {
1099 if (Accumulator > 0)
1100 horz_stretch_ratio |= reuse_previous;
1101 else
1102 Accumulator += Denominator;
1103 Accumulator -= Numerator;
1104 reuse_previous <<= 1;
1105 }
1106
1107 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1108 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1109 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1110 break; /* Out of the do { ... } while (0) */
1111 }
1112 }
1113
1114 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1115 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1116 } while (0);
1117 }
1118
1119 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1120 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1121 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1122
1123 if (!M64_HAS(LT_LCD_REGS) &&
1124 xres <= (M64_HAS(MOBIL_BUS) ? 1024 : 800))
1125 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1126 } else {
1127 /*
1128 * Don't use vertical blending if the mode is too wide
1129 * or not vertically stretched.
1130 */
1131 crtc->vert_stretching = 0;
1132 }
1133 /* copy to shadow crtc */
1134 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1135 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1136 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1137 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1138 }
1139 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1140
1141 if (M64_HAS(MAGIC_FIFO)) {
1142 /* FIXME: display FIFO low watermark values */
1143 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1144 }
1145 crtc->dp_pix_width = dp_pix_width;
1146 crtc->dp_chain_mask = dp_chain_mask;
1147
1148 return 0;
1149 }
1150
1151 static int aty_crtc_to_var(const struct crtc *crtc,
1152 struct fb_var_screeninfo *var)
1153 {
1154 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1155 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1156 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1157 u32 pix_width;
1158 u32 double_scan, interlace;
1159
1160 /* input */
1161 h_total = crtc->h_tot_disp & 0x1ff;
1162 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1163 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1164 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1165 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1166 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1167 v_total = crtc->v_tot_disp & 0x7ff;
1168 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1169 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1170 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1171 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1172 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1173 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1174 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1175 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1176
1177 /* convert */
1178 xres = (h_disp + 1) * 8;
1179 yres = v_disp + 1;
1180 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1181 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1182 hslen = h_sync_wid * 8;
1183 upper = v_total - v_sync_strt - v_sync_wid;
1184 lower = v_sync_strt - v_disp;
1185 vslen = v_sync_wid;
1186 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1187 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1188 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1189
1190 switch (pix_width) {
1191 #if 0
1192 case CRTC_PIX_WIDTH_4BPP:
1193 bpp = 4;
1194 var->red.offset = 0;
1195 var->red.length = 8;
1196 var->green.offset = 0;
1197 var->green.length = 8;
1198 var->blue.offset = 0;
1199 var->blue.length = 8;
1200 var->transp.offset = 0;
1201 var->transp.length = 0;
1202 break;
1203 #endif
1204 case CRTC_PIX_WIDTH_8BPP:
1205 bpp = 8;
1206 var->red.offset = 0;
1207 var->red.length = 8;
1208 var->green.offset = 0;
1209 var->green.length = 8;
1210 var->blue.offset = 0;
1211 var->blue.length = 8;
1212 var->transp.offset = 0;
1213 var->transp.length = 0;
1214 break;
1215 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1216 bpp = 16;
1217 var->red.offset = 10;
1218 var->red.length = 5;
1219 var->green.offset = 5;
1220 var->green.length = 5;
1221 var->blue.offset = 0;
1222 var->blue.length = 5;
1223 var->transp.offset = 0;
1224 var->transp.length = 0;
1225 break;
1226 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1227 bpp = 16;
1228 var->red.offset = 11;
1229 var->red.length = 5;
1230 var->green.offset = 5;
1231 var->green.length = 6;
1232 var->blue.offset = 0;
1233 var->blue.length = 5;
1234 var->transp.offset = 0;
1235 var->transp.length = 0;
1236 break;
1237 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1238 bpp = 24;
1239 var->red.offset = 16;
1240 var->red.length = 8;
1241 var->green.offset = 8;
1242 var->green.length = 8;
1243 var->blue.offset = 0;
1244 var->blue.length = 8;
1245 var->transp.offset = 0;
1246 var->transp.length = 0;
1247 break;
1248 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1249 bpp = 32;
1250 var->red.offset = 16;
1251 var->red.length = 8;
1252 var->green.offset = 8;
1253 var->green.length = 8;
1254 var->blue.offset = 0;
1255 var->blue.length = 8;
1256 var->transp.offset = 24;
1257 var->transp.length = 8;
1258 break;
1259 default:
1260 PRINTKE("Invalid pixel width\n");
1261 return -EINVAL;
1262 }
1263
1264 /* output */
1265 var->xres = xres;
1266 var->yres = yres;
1267 var->xres_virtual = crtc->vxres;
1268 var->yres_virtual = crtc->vyres;
1269 var->bits_per_pixel = bpp;
1270 var->left_margin = left;
1271 var->right_margin = right;
1272 var->upper_margin = upper;
1273 var->lower_margin = lower;
1274 var->hsync_len = hslen;
1275 var->vsync_len = vslen;
1276 var->sync = sync;
1277 var->vmode = FB_VMODE_NONINTERLACED;
1278 /*
1279 * In double scan mode, the vertical parameters are doubled,
1280 * so we need to halve them to get the right values.
1281 * In interlaced mode the values are already correct,
1282 * so no correction is necessary.
1283 */
1284 if (interlace)
1285 var->vmode = FB_VMODE_INTERLACED;
1286
1287 if (double_scan) {
1288 var->vmode = FB_VMODE_DOUBLE;
1289 var->yres >>= 1;
1290 var->upper_margin >>= 1;
1291 var->lower_margin >>= 1;
1292 var->vsync_len >>= 1;
1293 }
1294
1295 return 0;
1296 }
1297
1298 /* ------------------------------------------------------------------------- */
1299
1300 static int atyfb_set_par(struct fb_info *info)
1301 {
1302 struct atyfb_par *par = (struct atyfb_par *) info->par;
1303 struct fb_var_screeninfo *var = &info->var;
1304 u32 tmp, pixclock;
1305 int err;
1306 #ifdef DEBUG
1307 struct fb_var_screeninfo debug;
1308 u32 pixclock_in_ps;
1309 #endif
1310 if (par->asleep)
1311 return 0;
1312
1313 err = aty_var_to_crtc(info, var, &par->crtc);
1314 if (err)
1315 return err;
1316
1317 pixclock = atyfb_get_pixclock(var, par);
1318
1319 if (pixclock == 0) {
1320 PRINTKE("Invalid pixclock\n");
1321 return -EINVAL;
1322 } else {
1323 err = par->pll_ops->var_to_pll(info, pixclock,
1324 var->bits_per_pixel, &par->pll);
1325 if (err)
1326 return err;
1327 }
1328
1329 par->accel_flags = var->accel_flags; /* hack */
1330
1331 if (var->accel_flags) {
1332 info->fbops->fb_sync = atyfb_sync;
1333 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1334 } else {
1335 info->fbops->fb_sync = NULL;
1336 info->flags |= FBINFO_HWACCEL_DISABLED;
1337 }
1338
1339 if (par->blitter_may_be_busy)
1340 wait_for_idle(par);
1341
1342 aty_set_crtc(par, &par->crtc);
1343 par->dac_ops->set_dac(info, &par->pll,
1344 var->bits_per_pixel, par->accel_flags);
1345 par->pll_ops->set_pll(info, &par->pll);
1346
1347 #ifdef DEBUG
1348 if (par->pll_ops && par->pll_ops->pll_to_var)
1349 pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll);
1350 else
1351 pixclock_in_ps = 0;
1352
1353 if (0 == pixclock_in_ps) {
1354 PRINTKE("ALERT ops->pll_to_var get 0\n");
1355 pixclock_in_ps = pixclock;
1356 }
1357
1358 memset(&debug, 0, sizeof(debug));
1359 if (!aty_crtc_to_var(&par->crtc, &debug)) {
1360 u32 hSync, vRefresh;
1361 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1362 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1363
1364 h_disp = debug.xres;
1365 h_sync_strt = h_disp + debug.right_margin;
1366 h_sync_end = h_sync_strt + debug.hsync_len;
1367 h_total = h_sync_end + debug.left_margin;
1368 v_disp = debug.yres;
1369 v_sync_strt = v_disp + debug.lower_margin;
1370 v_sync_end = v_sync_strt + debug.vsync_len;
1371 v_total = v_sync_end + debug.upper_margin;
1372
1373 hSync = 1000000000 / (pixclock_in_ps * h_total);
1374 vRefresh = (hSync * 1000) / v_total;
1375 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1376 vRefresh *= 2;
1377 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1378 vRefresh /= 2;
1379
1380 DPRINTK("atyfb_set_par\n");
1381 DPRINTK(" Set Visible Mode to %ix%i-%i\n",
1382 var->xres, var->yres, var->bits_per_pixel);
1383 DPRINTK(" Virtual resolution %ix%i, "
1384 "pixclock_in_ps %i (calculated %i)\n",
1385 var->xres_virtual, var->yres_virtual,
1386 pixclock, pixclock_in_ps);
1387 DPRINTK(" Dot clock: %i MHz\n",
1388 1000000 / pixclock_in_ps);
1389 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1390 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1391 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1392 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1393 h_disp, h_sync_strt, h_sync_end, h_total,
1394 v_disp, v_sync_strt, v_sync_end, v_total);
1395 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1396 pixclock_in_ps,
1397 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1398 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1399 }
1400 #endif /* DEBUG */
1401
1402 if (!M64_HAS(INTEGRATED)) {
1403 /* Don't forget MEM_CNTL */
1404 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1405 switch (var->bits_per_pixel) {
1406 case 8:
1407 tmp |= 0x02000000;
1408 break;
1409 case 16:
1410 tmp |= 0x03000000;
1411 break;
1412 case 32:
1413 tmp |= 0x06000000;
1414 break;
1415 }
1416 aty_st_le32(MEM_CNTL, tmp, par);
1417 } else {
1418 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1419 if (!M64_HAS(MAGIC_POSTDIV))
1420 tmp |= par->mem_refresh_rate << 20;
1421 switch (var->bits_per_pixel) {
1422 case 8:
1423 case 24:
1424 tmp |= 0x00000000;
1425 break;
1426 case 16:
1427 tmp |= 0x04000000;
1428 break;
1429 case 32:
1430 tmp |= 0x08000000;
1431 break;
1432 }
1433 if (M64_HAS(CT_BUS)) {
1434 aty_st_le32(DAC_CNTL, 0x87010184, par);
1435 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1436 } else if (M64_HAS(VT_BUS)) {
1437 aty_st_le32(DAC_CNTL, 0x87010184, par);
1438 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1439 } else if (M64_HAS(MOBIL_BUS)) {
1440 aty_st_le32(DAC_CNTL, 0x80010102, par);
1441 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1442 } else {
1443 /* GT */
1444 aty_st_le32(DAC_CNTL, 0x86010102, par);
1445 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1446 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1447 }
1448 aty_st_le32(MEM_CNTL, tmp, par);
1449 }
1450 aty_st_8(DAC_MASK, 0xff, par);
1451
1452 info->fix.line_length = calc_line_length(par, var->xres_virtual,
1453 var->bits_per_pixel);
1454
1455 info->fix.visual = var->bits_per_pixel <= 8 ?
1456 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1457
1458 /* Initialize the graphics engine */
1459 if (par->accel_flags & FB_ACCELF_TEXT)
1460 aty_init_engine(par, info);
1461
1462 #ifdef CONFIG_BOOTX_TEXT
1463 btext_update_display(info->fix.smem_start,
1464 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1465 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1466 var->bits_per_pixel,
1467 par->crtc.vxres * var->bits_per_pixel / 8);
1468 #endif /* CONFIG_BOOTX_TEXT */
1469 #if 0
1470 /* switch to accelerator mode */
1471 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1472 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1473 #endif
1474 #ifdef DEBUG
1475 {
1476 /* dump non shadow CRTC, pll, LCD registers */
1477 int i; u32 base;
1478
1479 /* CRTC registers */
1480 base = 0x2000;
1481 printk("debug atyfb: Mach64 non-shadow register values:");
1482 for (i = 0; i < 256; i = i+4) {
1483 if (i % 16 == 0) {
1484 pr_cont("\n");
1485 printk("debug atyfb: 0x%04X: ", base + i);
1486 }
1487 pr_cont(" %08X", aty_ld_le32(i, par));
1488 }
1489 pr_cont("\n\n");
1490
1491 #ifdef CONFIG_FB_ATY_CT
1492 /* PLL registers */
1493 base = 0x00;
1494 printk("debug atyfb: Mach64 PLL register values:");
1495 for (i = 0; i < 64; i++) {
1496 if (i % 16 == 0) {
1497 pr_cont("\n");
1498 printk("debug atyfb: 0x%02X: ", base + i);
1499 }
1500 if (i % 4 == 0)
1501 pr_cont(" ");
1502 pr_cont("%02X", aty_ld_pll_ct(i, par));
1503 }
1504 pr_cont("\n\n");
1505 #endif /* CONFIG_FB_ATY_CT */
1506
1507 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1508 if (par->lcd_table != 0) {
1509 /* LCD registers */
1510 base = 0x00;
1511 printk("debug atyfb: LCD register values:");
1512 if (M64_HAS(LT_LCD_REGS)) {
1513 for (i = 0; i <= POWER_MANAGEMENT; i++) {
1514 if (i == EXT_VERT_STRETCH)
1515 continue;
1516 pr_cont("\ndebug atyfb: 0x%04X: ",
1517 lt_lcd_regs[i]);
1518 pr_cont(" %08X", aty_ld_lcd(i, par));
1519 }
1520 } else {
1521 for (i = 0; i < 64; i++) {
1522 if (i % 4 == 0)
1523 pr_cont("\ndebug atyfb: 0x%02X: ",
1524 base + i);
1525 pr_cont(" %08X", aty_ld_lcd(i, par));
1526 }
1527 }
1528 pr_cont("\n\n");
1529 }
1530 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1531 }
1532 #endif /* DEBUG */
1533 return 0;
1534 }
1535
1536 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1537 {
1538 struct atyfb_par *par = (struct atyfb_par *) info->par;
1539 int err;
1540 struct crtc crtc;
1541 union aty_pll pll;
1542 u32 pixclock;
1543
1544 memcpy(&pll, &par->pll, sizeof(pll));
1545
1546 err = aty_var_to_crtc(info, var, &crtc);
1547 if (err)
1548 return err;
1549
1550 pixclock = atyfb_get_pixclock(var, par);
1551
1552 if (pixclock == 0) {
1553 if (!(var->activate & FB_ACTIVATE_TEST))
1554 PRINTKE("Invalid pixclock\n");
1555 return -EINVAL;
1556 } else {
1557 err = par->pll_ops->var_to_pll(info, pixclock,
1558 var->bits_per_pixel, &pll);
1559 if (err)
1560 return err;
1561 }
1562
1563 if (var->accel_flags & FB_ACCELF_TEXT)
1564 info->var.accel_flags = FB_ACCELF_TEXT;
1565 else
1566 info->var.accel_flags = 0;
1567
1568 aty_crtc_to_var(&crtc, var);
1569 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1570 return 0;
1571 }
1572
1573 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1574 {
1575 u32 xoffset = info->var.xoffset;
1576 u32 yoffset = info->var.yoffset;
1577 u32 line_length = info->fix.line_length;
1578 u32 bpp = info->var.bits_per_pixel;
1579
1580 par->crtc.off_pitch =
1581 ((yoffset * line_length + xoffset * bpp / 8) / 8) |
1582 ((line_length / bpp) << 22);
1583 }
1584
1585
1586 /*
1587 * Open/Release the frame buffer device
1588 */
1589
1590 static int atyfb_open(struct fb_info *info, int user)
1591 {
1592 struct atyfb_par *par = (struct atyfb_par *) info->par;
1593
1594 if (user) {
1595 par->open++;
1596 #ifdef __sparc__
1597 par->mmaped = 0;
1598 #endif
1599 }
1600 return 0;
1601 }
1602
1603 static irqreturn_t aty_irq(int irq, void *dev_id)
1604 {
1605 struct atyfb_par *par = dev_id;
1606 int handled = 0;
1607 u32 int_cntl;
1608
1609 spin_lock(&par->int_lock);
1610
1611 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1612
1613 if (int_cntl & CRTC_VBLANK_INT) {
1614 /* clear interrupt */
1615 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) |
1616 CRTC_VBLANK_INT_AK, par);
1617 par->vblank.count++;
1618 if (par->vblank.pan_display) {
1619 par->vblank.pan_display = 0;
1620 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1621 }
1622 wake_up_interruptible(&par->vblank.wait);
1623 handled = 1;
1624 }
1625
1626 spin_unlock(&par->int_lock);
1627
1628 return IRQ_RETVAL(handled);
1629 }
1630
1631 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1632 {
1633 u32 int_cntl;
1634
1635 if (!test_and_set_bit(0, &par->irq_flags)) {
1636 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1637 clear_bit(0, &par->irq_flags);
1638 return -EINVAL;
1639 }
1640 spin_lock_irq(&par->int_lock);
1641 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1642 /* clear interrupt */
1643 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1644 /* enable interrupt */
1645 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1646 spin_unlock_irq(&par->int_lock);
1647 } else if (reenable) {
1648 spin_lock_irq(&par->int_lock);
1649 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1650 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1651 printk("atyfb: someone disabled IRQ [%08x]\n",
1652 int_cntl);
1653 /* re-enable interrupt */
1654 aty_st_le32(CRTC_INT_CNTL, int_cntl |
1655 CRTC_VBLANK_INT_EN, par);
1656 }
1657 spin_unlock_irq(&par->int_lock);
1658 }
1659
1660 return 0;
1661 }
1662
1663 static int aty_disable_irq(struct atyfb_par *par)
1664 {
1665 u32 int_cntl;
1666
1667 if (test_and_clear_bit(0, &par->irq_flags)) {
1668 if (par->vblank.pan_display) {
1669 par->vblank.pan_display = 0;
1670 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1671 }
1672 spin_lock_irq(&par->int_lock);
1673 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1674 /* disable interrupt */
1675 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par);
1676 spin_unlock_irq(&par->int_lock);
1677 free_irq(par->irq, par);
1678 }
1679
1680 return 0;
1681 }
1682
1683 static int atyfb_release(struct fb_info *info, int user)
1684 {
1685 struct atyfb_par *par = (struct atyfb_par *) info->par;
1686 #ifdef __sparc__
1687 int was_mmaped;
1688 #endif
1689
1690 if (!user)
1691 return 0;
1692
1693 par->open--;
1694 mdelay(1);
1695 wait_for_idle(par);
1696
1697 if (par->open)
1698 return 0;
1699
1700 #ifdef __sparc__
1701 was_mmaped = par->mmaped;
1702
1703 par->mmaped = 0;
1704
1705 if (was_mmaped) {
1706 struct fb_var_screeninfo var;
1707
1708 /*
1709 * Now reset the default display config, we have
1710 * no idea what the program(s) which mmap'd the
1711 * chip did to the configuration, nor whether it
1712 * restored it correctly.
1713 */
1714 var = default_var;
1715 if (noaccel)
1716 var.accel_flags &= ~FB_ACCELF_TEXT;
1717 else
1718 var.accel_flags |= FB_ACCELF_TEXT;
1719 if (var.yres == var.yres_virtual) {
1720 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1721 var.yres_virtual =
1722 ((videoram * 8) / var.bits_per_pixel) /
1723 var.xres_virtual;
1724 if (var.yres_virtual < var.yres)
1725 var.yres_virtual = var.yres;
1726 }
1727 }
1728 #endif
1729 aty_disable_irq(par);
1730
1731 return 0;
1732 }
1733
1734 /*
1735 * Pan or Wrap the Display
1736 *
1737 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1738 */
1739
1740 static int atyfb_pan_display(struct fb_var_screeninfo *var,
1741 struct fb_info *info)
1742 {
1743 struct atyfb_par *par = (struct atyfb_par *) info->par;
1744 u32 xres, yres, xoffset, yoffset;
1745
1746 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1747 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1748 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1749 yres >>= 1;
1750 xoffset = (var->xoffset + 7) & ~7;
1751 yoffset = var->yoffset;
1752 if (xoffset + xres > par->crtc.vxres ||
1753 yoffset + yres > par->crtc.vyres)
1754 return -EINVAL;
1755 info->var.xoffset = xoffset;
1756 info->var.yoffset = yoffset;
1757 if (par->asleep)
1758 return 0;
1759
1760 set_off_pitch(par, info);
1761 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1762 par->vblank.pan_display = 1;
1763 } else {
1764 par->vblank.pan_display = 0;
1765 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1766 }
1767
1768 return 0;
1769 }
1770
1771 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1772 {
1773 struct aty_interrupt *vbl;
1774 unsigned int count;
1775 int ret;
1776
1777 switch (crtc) {
1778 case 0:
1779 vbl = &par->vblank;
1780 break;
1781 default:
1782 return -ENODEV;
1783 }
1784
1785 ret = aty_enable_irq(par, 0);
1786 if (ret)
1787 return ret;
1788
1789 count = vbl->count;
1790 ret = wait_event_interruptible_timeout(vbl->wait,
1791 count != vbl->count, HZ/10);
1792 if (ret < 0)
1793 return ret;
1794 if (ret == 0) {
1795 aty_enable_irq(par, 1);
1796 return -ETIMEDOUT;
1797 }
1798
1799 return 0;
1800 }
1801
1802
1803 #ifdef DEBUG
1804 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1805 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1806
1807 struct atyclk {
1808 u32 ref_clk_per;
1809 u8 pll_ref_div;
1810 u8 mclk_fb_div;
1811 u8 mclk_post_div; /* 1,2,3,4,8 */
1812 u8 mclk_fb_mult; /* 2 or 4 */
1813 u8 xclk_post_div; /* 1,2,3,4,8 */
1814 u8 vclk_fb_div;
1815 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1816 u32 dsp_xclks_per_row; /* 0-16383 */
1817 u32 dsp_loop_latency; /* 0-15 */
1818 u32 dsp_precision; /* 0-7 */
1819 u32 dsp_on; /* 0-2047 */
1820 u32 dsp_off; /* 0-2047 */
1821 };
1822
1823 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1824 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1825 #endif
1826
1827 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1828 {
1829 struct atyfb_par *par = (struct atyfb_par *) info->par;
1830 #ifdef __sparc__
1831 struct fbtype fbtyp;
1832 #endif
1833
1834 switch (cmd) {
1835 #ifdef __sparc__
1836 case FBIOGTYPE:
1837 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1838 fbtyp.fb_width = par->crtc.vxres;
1839 fbtyp.fb_height = par->crtc.vyres;
1840 fbtyp.fb_depth = info->var.bits_per_pixel;
1841 fbtyp.fb_cmsize = info->cmap.len;
1842 fbtyp.fb_size = info->fix.smem_len;
1843 if (copy_to_user((struct fbtype __user *) arg, &fbtyp,
1844 sizeof(fbtyp)))
1845 return -EFAULT;
1846 break;
1847 #endif /* __sparc__ */
1848
1849 case FBIO_WAITFORVSYNC:
1850 {
1851 u32 crtc;
1852
1853 if (get_user(crtc, (__u32 __user *) arg))
1854 return -EFAULT;
1855
1856 return aty_waitforvblank(par, crtc);
1857 }
1858
1859 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1860 case ATYIO_CLKR:
1861 if (M64_HAS(INTEGRATED)) {
1862 struct atyclk clk = { 0 };
1863 union aty_pll *pll = &par->pll;
1864 u32 dsp_config = pll->ct.dsp_config;
1865 u32 dsp_on_off = pll->ct.dsp_on_off;
1866 clk.ref_clk_per = par->ref_clk_per;
1867 clk.pll_ref_div = pll->ct.pll_ref_div;
1868 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1869 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1870 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1871 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1872 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1873 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1874 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1875 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1876 clk.dsp_precision = (dsp_config >> 20) & 7;
1877 clk.dsp_off = dsp_on_off & 0x7ff;
1878 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1879 if (copy_to_user((struct atyclk __user *) arg, &clk,
1880 sizeof(clk)))
1881 return -EFAULT;
1882 } else
1883 return -EINVAL;
1884 break;
1885 case ATYIO_CLKW:
1886 if (M64_HAS(INTEGRATED)) {
1887 struct atyclk clk;
1888 union aty_pll *pll = &par->pll;
1889 if (copy_from_user(&clk, (struct atyclk __user *) arg,
1890 sizeof(clk)))
1891 return -EFAULT;
1892 par->ref_clk_per = clk.ref_clk_per;
1893 pll->ct.pll_ref_div = clk.pll_ref_div;
1894 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1895 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1896 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1897 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1898 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1899 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1900 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1901 ((clk.dsp_loop_latency & 0xf) << 16) |
1902 ((clk.dsp_precision & 7) << 20);
1903 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) |
1904 ((clk.dsp_on & 0x7ff) << 16);
1905 /*aty_calc_pll_ct(info, &pll->ct);*/
1906 aty_set_pll_ct(info, pll);
1907 } else
1908 return -EINVAL;
1909 break;
1910 case ATYIO_FEATR:
1911 if (get_user(par->features, (u32 __user *) arg))
1912 return -EFAULT;
1913 break;
1914 case ATYIO_FEATW:
1915 if (put_user(par->features, (u32 __user *) arg))
1916 return -EFAULT;
1917 break;
1918 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1919 default:
1920 return -EINVAL;
1921 }
1922 return 0;
1923 }
1924
1925 static int atyfb_sync(struct fb_info *info)
1926 {
1927 struct atyfb_par *par = (struct atyfb_par *) info->par;
1928
1929 if (par->blitter_may_be_busy)
1930 wait_for_idle(par);
1931 return 0;
1932 }
1933
1934 #ifdef __sparc__
1935 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1936 {
1937 struct atyfb_par *par = (struct atyfb_par *) info->par;
1938 unsigned int size, page, map_size = 0;
1939 unsigned long map_offset = 0;
1940 unsigned long off;
1941 int i;
1942
1943 if (!par->mmap_map)
1944 return -ENXIO;
1945
1946 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1947 return -EINVAL;
1948
1949 off = vma->vm_pgoff << PAGE_SHIFT;
1950 size = vma->vm_end - vma->vm_start;
1951
1952 /* VM_IO | VM_DONTEXPAND | VM_DONTDUMP are set by remap_pfn_range() */
1953
1954 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1955 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1956 off += 0x8000000000000000UL;
1957
1958 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1959
1960 /* Each page, see which map applies */
1961 for (page = 0; page < size;) {
1962 map_size = 0;
1963 for (i = 0; par->mmap_map[i].size; i++) {
1964 unsigned long start = par->mmap_map[i].voff;
1965 unsigned long end = start + par->mmap_map[i].size;
1966 unsigned long offset = off + page;
1967
1968 if (start > offset)
1969 continue;
1970 if (offset >= end)
1971 continue;
1972
1973 map_size = par->mmap_map[i].size - (offset - start);
1974 map_offset = par->mmap_map[i].poff + (offset - start);
1975 break;
1976 }
1977 if (!map_size) {
1978 page += PAGE_SIZE;
1979 continue;
1980 }
1981 if (page + map_size > size)
1982 map_size = size - page;
1983
1984 pgprot_val(vma->vm_page_prot) &= ~(par->mmap_map[i].prot_mask);
1985 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1986
1987 if (remap_pfn_range(vma, vma->vm_start + page,
1988 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1989 return -EAGAIN;
1990
1991 page += map_size;
1992 }
1993
1994 if (!map_size)
1995 return -EINVAL;
1996
1997 if (!par->mmaped)
1998 par->mmaped = 1;
1999 return 0;
2000 }
2001 #endif /* __sparc__ */
2002
2003
2004
2005 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
2006
2007 #ifdef CONFIG_PPC_PMAC
2008 /* Power management routines. Those are used for PowerBook sleep.
2009 */
2010 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
2011 {
2012 u32 pm;
2013 int timeout;
2014
2015 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2016 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
2017 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2018 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2019
2020 timeout = 2000;
2021 if (sleep) {
2022 /* Sleep */
2023 pm &= ~PWR_MGT_ON;
2024 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2025 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2026 udelay(10);
2027 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2028 pm |= SUSPEND_NOW;
2029 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2030 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2031 udelay(10);
2032 pm |= PWR_MGT_ON;
2033 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2034 do {
2035 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2036 mdelay(1);
2037 if ((--timeout) == 0)
2038 break;
2039 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2040 } else {
2041 /* Wakeup */
2042 pm &= ~PWR_MGT_ON;
2043 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2044 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2045 udelay(10);
2046 pm &= ~SUSPEND_NOW;
2047 pm |= (PWR_BLON | AUTO_PWR_UP);
2048 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2049 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2050 udelay(10);
2051 pm |= PWR_MGT_ON;
2052 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2053 do {
2054 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2055 mdelay(1);
2056 if ((--timeout) == 0)
2057 break;
2058 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2059 }
2060 mdelay(500);
2061
2062 return timeout ? 0 : -EIO;
2063 }
2064 #endif /* CONFIG_PPC_PMAC */
2065
2066 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2067 {
2068 struct fb_info *info = pci_get_drvdata(pdev);
2069 struct atyfb_par *par = (struct atyfb_par *) info->par;
2070
2071 if (state.event == pdev->dev.power.power_state.event)
2072 return 0;
2073
2074 console_lock();
2075
2076 fb_set_suspend(info, 1);
2077
2078 /* Idle & reset engine */
2079 wait_for_idle(par);
2080 aty_reset_engine(par);
2081
2082 /* Blank display and LCD */
2083 atyfb_blank(FB_BLANK_POWERDOWN, info);
2084
2085 par->asleep = 1;
2086 par->lock_blank = 1;
2087
2088 /*
2089 * Because we may change PCI D state ourselves, we need to
2090 * first save the config space content so the core can
2091 * restore it properly on resume.
2092 */
2093 pci_save_state(pdev);
2094
2095 #ifdef CONFIG_PPC_PMAC
2096 /* Set chip to "suspend" mode */
2097 if (machine_is(powermac) && aty_power_mgmt(1, par)) {
2098 par->asleep = 0;
2099 par->lock_blank = 0;
2100 atyfb_blank(FB_BLANK_UNBLANK, info);
2101 fb_set_suspend(info, 0);
2102 console_unlock();
2103 return -EIO;
2104 }
2105 #else
2106 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2107 #endif
2108
2109 console_unlock();
2110
2111 pdev->dev.power.power_state = state;
2112
2113 return 0;
2114 }
2115
2116 static void aty_resume_chip(struct fb_info *info)
2117 {
2118 struct atyfb_par *par = info->par;
2119
2120 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2121
2122 if (par->pll_ops->resume_pll)
2123 par->pll_ops->resume_pll(info, &par->pll);
2124
2125 if (par->aux_start)
2126 aty_st_le32(BUS_CNTL,
2127 aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2128 }
2129
2130 static int atyfb_pci_resume(struct pci_dev *pdev)
2131 {
2132 struct fb_info *info = pci_get_drvdata(pdev);
2133 struct atyfb_par *par = (struct atyfb_par *) info->par;
2134
2135 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2136 return 0;
2137
2138 console_lock();
2139
2140 /*
2141 * PCI state will have been restored by the core, so
2142 * we should be in D0 now with our config space fully
2143 * restored
2144 */
2145
2146 #ifdef CONFIG_PPC_PMAC
2147 if (machine_is(powermac) &&
2148 pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
2149 aty_power_mgmt(0, par);
2150 #endif
2151
2152 aty_resume_chip(info);
2153
2154 par->asleep = 0;
2155
2156 /* Restore display */
2157 atyfb_set_par(info);
2158
2159 /* Refresh */
2160 fb_set_suspend(info, 0);
2161
2162 /* Unblank */
2163 par->lock_blank = 0;
2164 atyfb_blank(FB_BLANK_UNBLANK, info);
2165
2166 console_unlock();
2167
2168 pdev->dev.power.power_state = PMSG_ON;
2169
2170 return 0;
2171 }
2172
2173 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2174
2175 /* Backlight */
2176 #ifdef CONFIG_FB_ATY_BACKLIGHT
2177 #define MAX_LEVEL 0xFF
2178
2179 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2180 {
2181 struct fb_info *info = pci_get_drvdata(par->pdev);
2182 int atylevel;
2183
2184 /* Get and convert the value */
2185 /* No locking of bl_curve since we read a single value */
2186 atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2187
2188 if (atylevel < 0)
2189 atylevel = 0;
2190 else if (atylevel > MAX_LEVEL)
2191 atylevel = MAX_LEVEL;
2192
2193 return atylevel;
2194 }
2195
2196 static int aty_bl_update_status(struct backlight_device *bd)
2197 {
2198 struct atyfb_par *par = bl_get_data(bd);
2199 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2200 int level;
2201
2202 if (bd->props.power != FB_BLANK_UNBLANK ||
2203 bd->props.fb_blank != FB_BLANK_UNBLANK)
2204 level = 0;
2205 else
2206 level = bd->props.brightness;
2207
2208 reg |= (BLMOD_EN | BIASMOD_EN);
2209 if (level > 0) {
2210 reg &= ~BIAS_MOD_LEVEL_MASK;
2211 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2212 } else {
2213 reg &= ~BIAS_MOD_LEVEL_MASK;
2214 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2215 }
2216 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2217
2218 return 0;
2219 }
2220
2221 static const struct backlight_ops aty_bl_data = {
2222 .update_status = aty_bl_update_status,
2223 };
2224
2225 static void aty_bl_init(struct atyfb_par *par)
2226 {
2227 struct backlight_properties props;
2228 struct fb_info *info = pci_get_drvdata(par->pdev);
2229 struct backlight_device *bd;
2230 char name[12];
2231
2232 #ifdef CONFIG_PMAC_BACKLIGHT
2233 if (!pmac_has_backlight_type("ati"))
2234 return;
2235 #endif
2236
2237 snprintf(name, sizeof(name), "atybl%d", info->node);
2238
2239 memset(&props, 0, sizeof(struct backlight_properties));
2240 props.type = BACKLIGHT_RAW;
2241 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
2242 bd = backlight_device_register(name, info->dev, par, &aty_bl_data,
2243 &props);
2244 if (IS_ERR(bd)) {
2245 info->bl_dev = NULL;
2246 printk(KERN_WARNING "aty: Backlight registration failed\n");
2247 goto error;
2248 }
2249
2250 info->bl_dev = bd;
2251 fb_bl_default_curve(info, 0,
2252 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2253 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2254
2255 bd->props.brightness = bd->props.max_brightness;
2256 bd->props.power = FB_BLANK_UNBLANK;
2257 backlight_update_status(bd);
2258
2259 printk("aty: Backlight initialized (%s)\n", name);
2260
2261 return;
2262
2263 error:
2264 return;
2265 }
2266
2267 #ifdef CONFIG_PCI
2268 static void aty_bl_exit(struct backlight_device *bd)
2269 {
2270 backlight_device_unregister(bd);
2271 printk("aty: Backlight unloaded\n");
2272 }
2273 #endif /* CONFIG_PCI */
2274
2275 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2276
2277 static void aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2278 {
2279 static const int ragepro_tbl[] = {
2280 44, 50, 55, 66, 75, 80, 100
2281 };
2282 static const int ragexl_tbl[] = {
2283 50, 66, 75, 83, 90, 95, 100, 105,
2284 110, 115, 120, 125, 133, 143, 166
2285 };
2286 const int *refresh_tbl;
2287 int i, size;
2288
2289 if (M64_HAS(XL_MEM)) {
2290 refresh_tbl = ragexl_tbl;
2291 size = ARRAY_SIZE(ragexl_tbl);
2292 } else {
2293 refresh_tbl = ragepro_tbl;
2294 size = ARRAY_SIZE(ragepro_tbl);
2295 }
2296
2297 for (i = 0; i < size; i++) {
2298 if (xclk < refresh_tbl[i])
2299 break;
2300 }
2301 par->mem_refresh_rate = i;
2302 }
2303
2304 /*
2305 * Initialisation
2306 */
2307
2308 static struct fb_info *fb_list = NULL;
2309
2310 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2311 static int atyfb_get_timings_from_lcd(struct atyfb_par *par,
2312 struct fb_var_screeninfo *var)
2313 {
2314 int ret = -EINVAL;
2315
2316 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2317 *var = default_var;
2318 var->xres = var->xres_virtual = par->lcd_hdisp;
2319 var->right_margin = par->lcd_right_margin;
2320 var->left_margin = par->lcd_hblank_len -
2321 (par->lcd_right_margin + par->lcd_hsync_dly +
2322 par->lcd_hsync_len);
2323 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2324 var->yres = var->yres_virtual = par->lcd_vdisp;
2325 var->lower_margin = par->lcd_lower_margin;
2326 var->upper_margin = par->lcd_vblank_len -
2327 (par->lcd_lower_margin + par->lcd_vsync_len);
2328 var->vsync_len = par->lcd_vsync_len;
2329 var->pixclock = par->lcd_pixclock;
2330 ret = 0;
2331 }
2332
2333 return ret;
2334 }
2335 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2336
2337 static int aty_init(struct fb_info *info)
2338 {
2339 struct atyfb_par *par = (struct atyfb_par *) info->par;
2340 const char *ramname = NULL, *xtal;
2341 int gtb_memsize, has_var = 0;
2342 struct fb_var_screeninfo var;
2343 int ret;
2344
2345 init_waitqueue_head(&par->vblank.wait);
2346 spin_lock_init(&par->int_lock);
2347
2348 #ifdef CONFIG_FB_ATY_GX
2349 if (!M64_HAS(INTEGRATED)) {
2350 u32 stat0;
2351 u8 dac_type, dac_subtype, clk_type;
2352 stat0 = aty_ld_le32(CNFG_STAT0, par);
2353 par->bus_type = (stat0 >> 0) & 0x07;
2354 par->ram_type = (stat0 >> 3) & 0x07;
2355 ramname = aty_gx_ram[par->ram_type];
2356 /* FIXME: clockchip/RAMDAC probing? */
2357 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2358 #ifdef CONFIG_ATARI
2359 clk_type = CLK_ATI18818_1;
2360 dac_type = (stat0 >> 9) & 0x07;
2361 if (dac_type == 0x07)
2362 dac_subtype = DAC_ATT20C408;
2363 else
2364 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2365 #else
2366 dac_type = DAC_IBMRGB514;
2367 dac_subtype = DAC_IBMRGB514;
2368 clk_type = CLK_IBMRGB514;
2369 #endif
2370 switch (dac_subtype) {
2371 case DAC_IBMRGB514:
2372 par->dac_ops = &aty_dac_ibm514;
2373 break;
2374 #ifdef CONFIG_ATARI
2375 case DAC_ATI68860_B:
2376 case DAC_ATI68860_C:
2377 par->dac_ops = &aty_dac_ati68860b;
2378 break;
2379 case DAC_ATT20C408:
2380 case DAC_ATT21C498:
2381 par->dac_ops = &aty_dac_att21c498;
2382 break;
2383 #endif
2384 default:
2385 PRINTKI("aty_init: DAC type not implemented yet!\n");
2386 par->dac_ops = &aty_dac_unsupported;
2387 break;
2388 }
2389 switch (clk_type) {
2390 #ifdef CONFIG_ATARI
2391 case CLK_ATI18818_1:
2392 par->pll_ops = &aty_pll_ati18818_1;
2393 break;
2394 #else
2395 case CLK_IBMRGB514:
2396 par->pll_ops = &aty_pll_ibm514;
2397 break;
2398 #endif
2399 #if 0 /* dead code */
2400 case CLK_STG1703:
2401 par->pll_ops = &aty_pll_stg1703;
2402 break;
2403 case CLK_CH8398:
2404 par->pll_ops = &aty_pll_ch8398;
2405 break;
2406 case CLK_ATT20C408:
2407 par->pll_ops = &aty_pll_att20c408;
2408 break;
2409 #endif
2410 default:
2411 PRINTKI("aty_init: CLK type not implemented yet!");
2412 par->pll_ops = &aty_pll_unsupported;
2413 break;
2414 }
2415 }
2416 #endif /* CONFIG_FB_ATY_GX */
2417 #ifdef CONFIG_FB_ATY_CT
2418 if (M64_HAS(INTEGRATED)) {
2419 par->dac_ops = &aty_dac_ct;
2420 par->pll_ops = &aty_pll_ct;
2421 par->bus_type = PCI;
2422 par->ram_type = (aty_ld_le32(CNFG_STAT0, par) & 0x07);
2423 if (M64_HAS(XL_MEM))
2424 ramname = aty_xl_ram[par->ram_type];
2425 else
2426 ramname = aty_ct_ram[par->ram_type];
2427 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2428 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2429 par->pll_limits.mclk = 63;
2430 /* Mobility + 32bit memory interface need halved XCLK. */
2431 if (M64_HAS(MOBIL_BUS) && par->ram_type == SDRAM32)
2432 par->pll_limits.xclk = (par->pll_limits.xclk + 1) >> 1;
2433 }
2434 #endif
2435 #ifdef CONFIG_PPC_PMAC
2436 /*
2437 * The Apple iBook1 uses non-standard memory frequencies.
2438 * We detect it and set the frequency manually.
2439 */
2440 if (of_machine_is_compatible("PowerBook2,1")) {
2441 par->pll_limits.mclk = 70;
2442 par->pll_limits.xclk = 53;
2443 }
2444 #endif
2445
2446 /* Allow command line to override clocks. */
2447 if (pll)
2448 par->pll_limits.pll_max = pll;
2449 if (mclk)
2450 par->pll_limits.mclk = mclk;
2451 if (xclk)
2452 par->pll_limits.xclk = xclk;
2453
2454 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2455 par->pll_per = 1000000/par->pll_limits.pll_max;
2456 par->mclk_per = 1000000/par->pll_limits.mclk;
2457 par->xclk_per = 1000000/par->pll_limits.xclk;
2458
2459 par->ref_clk_per = 1000000000000ULL / 14318180;
2460 xtal = "14.31818";
2461
2462 #ifdef CONFIG_FB_ATY_CT
2463 if (M64_HAS(GTB_DSP)) {
2464 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2465
2466 if (pll_ref_div) {
2467 int diff1, diff2;
2468 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2469 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2470 if (diff1 < 0)
2471 diff1 = -diff1;
2472 if (diff2 < 0)
2473 diff2 = -diff2;
2474 if (diff2 < diff1) {
2475 par->ref_clk_per = 1000000000000ULL / 29498928;
2476 xtal = "29.498928";
2477 }
2478 }
2479 }
2480 #endif /* CONFIG_FB_ATY_CT */
2481
2482 /* save previous video mode */
2483 aty_get_crtc(par, &par->saved_crtc);
2484 if (par->pll_ops->get_pll)
2485 par->pll_ops->get_pll(info, &par->saved_pll);
2486
2487 par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2488 gtb_memsize = M64_HAS(GTB_DSP);
2489 if (gtb_memsize)
2490 /* 0xF used instead of MEM_SIZE_ALIAS */
2491 switch (par->mem_cntl & 0xF) {
2492 case MEM_SIZE_512K:
2493 info->fix.smem_len = 0x80000;
2494 break;
2495 case MEM_SIZE_1M:
2496 info->fix.smem_len = 0x100000;
2497 break;
2498 case MEM_SIZE_2M_GTB:
2499 info->fix.smem_len = 0x200000;
2500 break;
2501 case MEM_SIZE_4M_GTB:
2502 info->fix.smem_len = 0x400000;
2503 break;
2504 case MEM_SIZE_6M_GTB:
2505 info->fix.smem_len = 0x600000;
2506 break;
2507 case MEM_SIZE_8M_GTB:
2508 info->fix.smem_len = 0x800000;
2509 break;
2510 default:
2511 info->fix.smem_len = 0x80000;
2512 } else
2513 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2514 case MEM_SIZE_512K:
2515 info->fix.smem_len = 0x80000;
2516 break;
2517 case MEM_SIZE_1M:
2518 info->fix.smem_len = 0x100000;
2519 break;
2520 case MEM_SIZE_2M:
2521 info->fix.smem_len = 0x200000;
2522 break;
2523 case MEM_SIZE_4M:
2524 info->fix.smem_len = 0x400000;
2525 break;
2526 case MEM_SIZE_6M:
2527 info->fix.smem_len = 0x600000;
2528 break;
2529 case MEM_SIZE_8M:
2530 info->fix.smem_len = 0x800000;
2531 break;
2532 default:
2533 info->fix.smem_len = 0x80000;
2534 }
2535
2536 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2537 if (aty_ld_le32(CNFG_STAT1, par) & 0x40000000)
2538 info->fix.smem_len += 0x400000;
2539 }
2540
2541 if (vram) {
2542 info->fix.smem_len = vram * 1024;
2543 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2544 if (info->fix.smem_len <= 0x80000)
2545 par->mem_cntl |= MEM_SIZE_512K;
2546 else if (info->fix.smem_len <= 0x100000)
2547 par->mem_cntl |= MEM_SIZE_1M;
2548 else if (info->fix.smem_len <= 0x200000)
2549 par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2550 else if (info->fix.smem_len <= 0x400000)
2551 par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2552 else if (info->fix.smem_len <= 0x600000)
2553 par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2554 else
2555 par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2556 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2557 }
2558
2559 /*
2560 * Reg Block 0 (CT-compatible block) is at mmio_start
2561 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2562 */
2563 if (M64_HAS(GX)) {
2564 info->fix.mmio_len = 0x400;
2565 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2566 } else if (M64_HAS(CT)) {
2567 info->fix.mmio_len = 0x400;
2568 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2569 } else if (M64_HAS(VT)) {
2570 info->fix.mmio_start -= 0x400;
2571 info->fix.mmio_len = 0x800;
2572 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2573 } else {/* GT */
2574 info->fix.mmio_start -= 0x400;
2575 info->fix.mmio_len = 0x800;
2576 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2577 }
2578
2579 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2580 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len>>20),
2581 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal,
2582 par->pll_limits.pll_max, par->pll_limits.mclk,
2583 par->pll_limits.xclk);
2584
2585 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
2586 if (M64_HAS(INTEGRATED)) {
2587 int i;
2588 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL "
2589 "EXT_MEM_CNTL CRTC_GEN_CNTL DSP_CONFIG "
2590 "DSP_ON_OFF CLOCK_CNTL\n"
2591 "debug atyfb: %08x %08x %08x "
2592 "%08x %08x %08x "
2593 "%08x %08x\n"
2594 "debug atyfb: PLL",
2595 aty_ld_le32(BUS_CNTL, par),
2596 aty_ld_le32(DAC_CNTL, par),
2597 aty_ld_le32(MEM_CNTL, par),
2598 aty_ld_le32(EXT_MEM_CNTL, par),
2599 aty_ld_le32(CRTC_GEN_CNTL, par),
2600 aty_ld_le32(DSP_CONFIG, par),
2601 aty_ld_le32(DSP_ON_OFF, par),
2602 aty_ld_le32(CLOCK_CNTL, par));
2603 for (i = 0; i < 40; i++)
2604 pr_cont(" %02x", aty_ld_pll_ct(i, par));
2605 pr_cont("\n");
2606 }
2607 #endif
2608 if (par->pll_ops->init_pll)
2609 par->pll_ops->init_pll(info, &par->pll);
2610 if (par->pll_ops->resume_pll)
2611 par->pll_ops->resume_pll(info, &par->pll);
2612
2613 aty_fudge_framebuffer_len(info);
2614
2615 /*
2616 * Disable register access through the linear aperture
2617 * if the auxiliary aperture is used so we can access
2618 * the full 8 MB of video RAM on 8 MB boards.
2619 */
2620 if (par->aux_start)
2621 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) |
2622 BUS_APER_REG_DIS, par);
2623
2624 if (!nomtrr)
2625 /*
2626 * Only the ioremap_wc()'d area will get WC here
2627 * since ioremap_uc() was used on the entire PCI BAR.
2628 */
2629 par->wc_cookie = arch_phys_wc_add(par->res_start,
2630 par->res_size);
2631
2632 info->fbops = &atyfb_ops;
2633 info->pseudo_palette = par->pseudo_palette;
2634 info->flags = FBINFO_DEFAULT |
2635 FBINFO_HWACCEL_IMAGEBLIT |
2636 FBINFO_HWACCEL_FILLRECT |
2637 FBINFO_HWACCEL_COPYAREA |
2638 FBINFO_HWACCEL_YPAN |
2639 FBINFO_READS_FAST;
2640
2641 #ifdef CONFIG_PMAC_BACKLIGHT
2642 if (M64_HAS(G3_PB_1_1) && of_machine_is_compatible("PowerBook1,1")) {
2643 /*
2644 * these bits let the 101 powerbook
2645 * wake up from sleep -- paulus
2646 */
2647 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par) |
2648 USE_F32KHZ | TRISTATE_MEM_EN, par);
2649 } else
2650 #endif
2651 if (M64_HAS(MOBIL_BUS) && backlight) {
2652 #ifdef CONFIG_FB_ATY_BACKLIGHT
2653 aty_bl_init(par);
2654 #endif
2655 }
2656
2657 memset(&var, 0, sizeof(var));
2658 #ifdef CONFIG_PPC
2659 if (machine_is(powermac)) {
2660 /*
2661 * FIXME: The NVRAM stuff should be put in a Mac-specific file,
2662 * as it applies to all Mac video cards
2663 */
2664 if (mode) {
2665 if (mac_find_mode(&var, info, mode, 8))
2666 has_var = 1;
2667 } else {
2668 if (default_vmode == VMODE_CHOOSE) {
2669 int sense;
2670 if (M64_HAS(G3_PB_1024x768))
2671 /* G3 PowerBook with 1024x768 LCD */
2672 default_vmode = VMODE_1024_768_60;
2673 else if (of_machine_is_compatible("iMac"))
2674 default_vmode = VMODE_1024_768_75;
2675 else if (of_machine_is_compatible("PowerBook2,1"))
2676 /* iBook with 800x600 LCD */
2677 default_vmode = VMODE_800_600_60;
2678 else
2679 default_vmode = VMODE_640_480_67;
2680 sense = read_aty_sense(par);
2681 PRINTKI("monitor sense=%x, mode %d\n",
2682 sense, mac_map_monitor_sense(sense));
2683 }
2684 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2685 default_vmode = VMODE_640_480_60;
2686 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2687 default_cmode = CMODE_8;
2688 if (!mac_vmode_to_var(default_vmode, default_cmode,
2689 &var))
2690 has_var = 1;
2691 }
2692 }
2693
2694 #endif /* !CONFIG_PPC */
2695
2696 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2697 if (!atyfb_get_timings_from_lcd(par, &var))
2698 has_var = 1;
2699 #endif
2700
2701 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2702 has_var = 1;
2703
2704 if (!has_var)
2705 var = default_var;
2706
2707 if (noaccel)
2708 var.accel_flags &= ~FB_ACCELF_TEXT;
2709 else
2710 var.accel_flags |= FB_ACCELF_TEXT;
2711
2712 if (comp_sync != -1) {
2713 if (!comp_sync)
2714 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2715 else
2716 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2717 }
2718
2719 if (var.yres == var.yres_virtual) {
2720 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2721 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2722 if (var.yres_virtual < var.yres)
2723 var.yres_virtual = var.yres;
2724 }
2725
2726 ret = atyfb_check_var(&var, info);
2727 if (ret) {
2728 PRINTKE("can't set default video mode\n");
2729 goto aty_init_exit;
2730 }
2731
2732 #ifdef CONFIG_FB_ATY_CT
2733 if (!noaccel && M64_HAS(INTEGRATED))
2734 aty_init_cursor(info);
2735 #endif /* CONFIG_FB_ATY_CT */
2736 info->var = var;
2737
2738 ret = fb_alloc_cmap(&info->cmap, 256, 0);
2739 if (ret < 0)
2740 goto aty_init_exit;
2741
2742 ret = register_framebuffer(info);
2743 if (ret < 0) {
2744 fb_dealloc_cmap(&info->cmap);
2745 goto aty_init_exit;
2746 }
2747
2748 fb_list = info;
2749
2750 PRINTKI("fb%d: %s frame buffer device on %s\n",
2751 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2752 return 0;
2753
2754 aty_init_exit:
2755 /* restore video mode */
2756 aty_set_crtc(par, &par->saved_crtc);
2757 par->pll_ops->set_pll(info, &par->saved_pll);
2758 arch_phys_wc_del(par->wc_cookie);
2759
2760 return ret;
2761 }
2762
2763 #if defined(CONFIG_ATARI) && !defined(MODULE)
2764 static int store_video_par(char *video_str, unsigned char m64_num)
2765 {
2766 char *p;
2767 unsigned long vmembase, size, guiregbase;
2768
2769 PRINTKI("store_video_par() '%s' \n", video_str);
2770
2771 if (!(p = strsep(&video_str, ";")) || !*p)
2772 goto mach64_invalid;
2773 vmembase = simple_strtoul(p, NULL, 0);
2774 if (!(p = strsep(&video_str, ";")) || !*p)
2775 goto mach64_invalid;
2776 size = simple_strtoul(p, NULL, 0);
2777 if (!(p = strsep(&video_str, ";")) || !*p)
2778 goto mach64_invalid;
2779 guiregbase = simple_strtoul(p, NULL, 0);
2780
2781 phys_vmembase[m64_num] = vmembase;
2782 phys_size[m64_num] = size;
2783 phys_guiregbase[m64_num] = guiregbase;
2784 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2785 guiregbase);
2786 return 0;
2787
2788 mach64_invalid:
2789 phys_vmembase[m64_num] = 0;
2790 return -1;
2791 }
2792 #endif /* CONFIG_ATARI && !MODULE */
2793
2794 /*
2795 * Blank the display.
2796 */
2797
2798 static int atyfb_blank(int blank, struct fb_info *info)
2799 {
2800 struct atyfb_par *par = (struct atyfb_par *) info->par;
2801 u32 gen_cntl;
2802
2803 if (par->lock_blank || par->asleep)
2804 return 0;
2805
2806 #ifdef CONFIG_FB_ATY_GENERIC_LCD
2807 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2808 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2809 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2810 pm &= ~PWR_BLON;
2811 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2812 }
2813 #endif
2814
2815 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2816 gen_cntl &= ~0x400004c;
2817 switch (blank) {
2818 case FB_BLANK_UNBLANK:
2819 break;
2820 case FB_BLANK_NORMAL:
2821 gen_cntl |= 0x4000040;
2822 break;
2823 case FB_BLANK_VSYNC_SUSPEND:
2824 gen_cntl |= 0x4000048;
2825 break;
2826 case FB_BLANK_HSYNC_SUSPEND:
2827 gen_cntl |= 0x4000044;
2828 break;
2829 case FB_BLANK_POWERDOWN:
2830 gen_cntl |= 0x400004c;
2831 break;
2832 }
2833 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2834
2835 #ifdef CONFIG_FB_ATY_GENERIC_LCD
2836 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2837 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2838 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2839 pm |= PWR_BLON;
2840 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2841 }
2842 #endif
2843
2844 return 0;
2845 }
2846
2847 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2848 const struct atyfb_par *par)
2849 {
2850 aty_st_8(DAC_W_INDEX, regno, par);
2851 aty_st_8(DAC_DATA, red, par);
2852 aty_st_8(DAC_DATA, green, par);
2853 aty_st_8(DAC_DATA, blue, par);
2854 }
2855
2856 /*
2857 * Set a single color register. The values supplied are already
2858 * rounded down to the hardware's capabilities (according to the
2859 * entries in the var structure). Return != 0 for invalid regno.
2860 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2861 */
2862
2863 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2864 u_int transp, struct fb_info *info)
2865 {
2866 struct atyfb_par *par = (struct atyfb_par *) info->par;
2867 int i, depth;
2868 u32 *pal = info->pseudo_palette;
2869
2870 depth = info->var.bits_per_pixel;
2871 if (depth == 16)
2872 depth = (info->var.green.length == 5) ? 15 : 16;
2873
2874 if (par->asleep)
2875 return 0;
2876
2877 if (regno > 255 ||
2878 (depth == 16 && regno > 63) ||
2879 (depth == 15 && regno > 31))
2880 return 1;
2881
2882 red >>= 8;
2883 green >>= 8;
2884 blue >>= 8;
2885
2886 par->palette[regno].red = red;
2887 par->palette[regno].green = green;
2888 par->palette[regno].blue = blue;
2889
2890 if (regno < 16) {
2891 switch (depth) {
2892 case 15:
2893 pal[regno] = (regno << 10) | (regno << 5) | regno;
2894 break;
2895 case 16:
2896 pal[regno] = (regno << 11) | (regno << 5) | regno;
2897 break;
2898 case 24:
2899 pal[regno] = (regno << 16) | (regno << 8) | regno;
2900 break;
2901 case 32:
2902 i = (regno << 8) | regno;
2903 pal[regno] = (i << 16) | i;
2904 break;
2905 }
2906 }
2907
2908 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2909 if (M64_HAS(EXTRA_BRIGHT))
2910 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2911 aty_st_8(DAC_CNTL, i, par);
2912 aty_st_8(DAC_MASK, 0xff, par);
2913
2914 if (M64_HAS(INTEGRATED)) {
2915 if (depth == 16) {
2916 if (regno < 32)
2917 aty_st_pal(regno << 3, red,
2918 par->palette[regno << 1].green,
2919 blue, par);
2920 red = par->palette[regno >> 1].red;
2921 blue = par->palette[regno >> 1].blue;
2922 regno <<= 2;
2923 } else if (depth == 15) {
2924 regno <<= 3;
2925 for (i = 0; i < 8; i++)
2926 aty_st_pal(regno + i, red, green, blue, par);
2927 }
2928 }
2929 aty_st_pal(regno, red, green, blue, par);
2930
2931 return 0;
2932 }
2933
2934 #ifdef CONFIG_PCI
2935
2936 #ifdef __sparc__
2937
2938 static int atyfb_setup_sparc(struct pci_dev *pdev, struct fb_info *info,
2939 unsigned long addr)
2940 {
2941 struct atyfb_par *par = info->par;
2942 struct device_node *dp;
2943 u32 mem, chip_id;
2944 int i, j, ret;
2945
2946 /*
2947 * Map memory-mapped registers.
2948 */
2949 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2950 info->fix.mmio_start = addr + 0x7ffc00UL;
2951
2952 /*
2953 * Map in big-endian aperture.
2954 */
2955 info->screen_base = (char *) (addr + 0x800000UL);
2956 info->fix.smem_start = addr + 0x800000UL;
2957
2958 /*
2959 * Figure mmap addresses from PCI config space.
2960 * Split Framebuffer in big- and little-endian halfs.
2961 */
2962 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2963 /* nothing */ ;
2964 j = i + 4;
2965
2966 par->mmap_map = kcalloc(j, sizeof(*par->mmap_map), GFP_ATOMIC);
2967 if (!par->mmap_map) {
2968 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2969 return -ENOMEM;
2970 }
2971
2972 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2973 struct resource *rp = &pdev->resource[i];
2974 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2975 unsigned long base;
2976 u32 size, pbase;
2977
2978 base = rp->start;
2979
2980 io = (rp->flags & IORESOURCE_IO);
2981
2982 size = rp->end - base + 1;
2983
2984 pci_read_config_dword(pdev, breg, &pbase);
2985
2986 if (io)
2987 size &= ~1;
2988
2989 /*
2990 * Map the framebuffer a second time, this time without
2991 * the braindead _PAGE_IE setting. This is used by the
2992 * fixed Xserver, but we need to maintain the old mapping
2993 * to stay compatible with older ones...
2994 */
2995 if (base == addr) {
2996 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2997 par->mmap_map[j].poff = base & PAGE_MASK;
2998 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2999 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3000 par->mmap_map[j].prot_flag = _PAGE_E;
3001 j++;
3002 }
3003
3004 /*
3005 * Here comes the old framebuffer mapping with _PAGE_IE
3006 * set for the big endian half of the framebuffer...
3007 */
3008 if (base == addr) {
3009 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3010 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3011 par->mmap_map[j].size = 0x800000;
3012 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3013 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3014 size -= 0x800000;
3015 j++;
3016 }
3017
3018 par->mmap_map[j].voff = pbase & PAGE_MASK;
3019 par->mmap_map[j].poff = base & PAGE_MASK;
3020 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3021 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3022 par->mmap_map[j].prot_flag = _PAGE_E;
3023 j++;
3024 }
3025
3026 ret = correct_chipset(par);
3027 if (ret)
3028 return ret;
3029
3030 if (IS_XL(pdev->device)) {
3031 /*
3032 * Fix PROMs idea of MEM_CNTL settings...
3033 */
3034 mem = aty_ld_le32(MEM_CNTL, par);
3035 chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
3036 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3037 switch (mem & 0x0f) {
3038 case 3:
3039 mem = (mem & ~(0x0f)) | 2;
3040 break;
3041 case 7:
3042 mem = (mem & ~(0x0f)) | 3;
3043 break;
3044 case 9:
3045 mem = (mem & ~(0x0f)) | 4;
3046 break;
3047 case 11:
3048 mem = (mem & ~(0x0f)) | 5;
3049 break;
3050 default:
3051 break;
3052 }
3053 if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
3054 mem &= ~(0x00700000);
3055 }
3056 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
3057 aty_st_le32(MEM_CNTL, mem, par);
3058 }
3059
3060 dp = pci_device_to_OF_node(pdev);
3061 if (dp == of_console_device) {
3062 struct fb_var_screeninfo *var = &default_var;
3063 unsigned int N, P, Q, M, T, R;
3064 u32 v_total, h_total;
3065 struct crtc crtc;
3066 u8 pll_regs[16];
3067 u8 clock_cntl;
3068
3069 crtc.vxres = of_getintprop_default(dp, "width", 1024);
3070 crtc.vyres = of_getintprop_default(dp, "height", 768);
3071 var->bits_per_pixel = of_getintprop_default(dp, "depth", 8);
3072 var->xoffset = var->yoffset = 0;
3073 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3074 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3075 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3076 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3077 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3078 aty_crtc_to_var(&crtc, var);
3079
3080 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3081 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3082
3083 /*
3084 * Read the PLL to figure actual Refresh Rate.
3085 */
3086 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3087 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3088 for (i = 0; i < 16; i++)
3089 pll_regs[i] = aty_ld_pll_ct(i, par);
3090
3091 /*
3092 * PLL Reference Divider M:
3093 */
3094 M = pll_regs[PLL_REF_DIV];
3095
3096 /*
3097 * PLL Feedback Divider N (Dependent on CLOCK_CNTL):
3098 */
3099 N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)];
3100
3101 /*
3102 * PLL Post Divider P (Dependent on CLOCK_CNTL):
3103 */
3104 P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) |
3105 ((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)];
3106
3107 /*
3108 * PLL Divider Q:
3109 */
3110 Q = N / P;
3111
3112 /*
3113 * Target Frequency:
3114 *
3115 * T * M
3116 * Q = -------
3117 * 2 * R
3118 *
3119 * where R is XTALIN (= 14318 or 29498 kHz).
3120 */
3121 if (IS_XL(pdev->device))
3122 R = 29498;
3123 else
3124 R = 14318;
3125
3126 T = 2 * Q * R / M;
3127
3128 default_var.pixclock = 1000000000 / T;
3129 }
3130
3131 return 0;
3132 }
3133
3134 #else /* __sparc__ */
3135
3136 #ifdef __i386__
3137 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3138 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3139 {
3140 u32 driv_inf_tab, sig;
3141 u16 lcd_ofs;
3142
3143 /*
3144 * To support an LCD panel, we should know it's dimensions and
3145 * it's desired pixel clock.
3146 * There are two ways to do it:
3147 * - Check the startup video mode and calculate the panel
3148 * size from it. This is unreliable.
3149 * - Read it from the driver information table in the video BIOS.
3150 */
3151 /* Address of driver information table is at offset 0x78. */
3152 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3153
3154 /* Check for the driver information table signature. */
3155 sig = *(u32 *)driv_inf_tab;
3156 if ((sig == 0x54504c24) || /* Rage LT pro */
3157 (sig == 0x544d5224) || /* Rage mobility */
3158 (sig == 0x54435824) || /* Rage XC */
3159 (sig == 0x544c5824)) { /* Rage XL */
3160 PRINTKI("BIOS contains driver information table.\n");
3161 lcd_ofs = *(u16 *)(driv_inf_tab + 10);
3162 par->lcd_table = 0;
3163 if (lcd_ofs != 0)
3164 par->lcd_table = bios_base + lcd_ofs;
3165 }
3166
3167 if (par->lcd_table != 0) {
3168 char model[24];
3169 char strbuf[16];
3170 char refresh_rates_buf[100];
3171 int id, tech, f, i, m, default_refresh_rate;
3172 char *txtcolour;
3173 char *txtmonitor;
3174 char *txtdual;
3175 char *txtformat;
3176 u16 width, height, panel_type, refresh_rates;
3177 u16 *lcdmodeptr;
3178 u32 format;
3179 u8 lcd_refresh_rates[16] = { 50, 56, 60, 67, 70, 72, 75, 76, 85,
3180 90, 100, 120, 140, 150, 160, 200 };
3181 /*
3182 * The most important information is the panel size at
3183 * offset 25 and 27, but there's some other nice information
3184 * which we print to the screen.
3185 */
3186 id = *(u8 *)par->lcd_table;
3187 strncpy(model, (char *)par->lcd_table+1, 24);
3188 model[23] = 0;
3189
3190 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3191 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3192 panel_type = *(u16 *)(par->lcd_table+29);
3193 if (panel_type & 1)
3194 txtcolour = "colour";
3195 else
3196 txtcolour = "monochrome";
3197 if (panel_type & 2)
3198 txtdual = "dual (split) ";
3199 else
3200 txtdual = "";
3201 tech = (panel_type >> 2) & 63;
3202 switch (tech) {
3203 case 0:
3204 txtmonitor = "passive matrix";
3205 break;
3206 case 1:
3207 txtmonitor = "active matrix";
3208 break;
3209 case 2:
3210 txtmonitor = "active addressed STN";
3211 break;
3212 case 3:
3213 txtmonitor = "EL";
3214 break;
3215 case 4:
3216 txtmonitor = "plasma";
3217 break;
3218 default:
3219 txtmonitor = "unknown";
3220 }
3221 format = *(u32 *)(par->lcd_table+57);
3222 if (tech == 0 || tech == 2) {
3223 switch (format & 7) {
3224 case 0:
3225 txtformat = "12 bit interface";
3226 break;
3227 case 1:
3228 txtformat = "16 bit interface";
3229 break;
3230 case 2:
3231 txtformat = "24 bit interface";
3232 break;
3233 default:
3234 txtformat = "unknown format";
3235 }
3236 } else {
3237 switch (format & 7) {
3238 case 0:
3239 txtformat = "8 colours";
3240 break;
3241 case 1:
3242 txtformat = "512 colours";
3243 break;
3244 case 2:
3245 txtformat = "4096 colours";
3246 break;
3247 case 4:
3248 txtformat = "262144 colours (LT mode)";
3249 break;
3250 case 5:
3251 txtformat = "16777216 colours";
3252 break;
3253 case 6:
3254 txtformat = "262144 colours (FDPI-2 mode)";
3255 break;
3256 default:
3257 txtformat = "unknown format";
3258 }
3259 }
3260 PRINTKI("%s%s %s monitor detected: %s\n",
3261 txtdual, txtcolour, txtmonitor, model);
3262 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3263 id, width, height, txtformat);
3264 refresh_rates_buf[0] = 0;
3265 refresh_rates = *(u16 *)(par->lcd_table+62);
3266 m = 1;
3267 f = 0;
3268 for (i = 0; i < 16; i++) {
3269 if (refresh_rates & m) {
3270 if (f == 0) {
3271 sprintf(strbuf, "%d",
3272 lcd_refresh_rates[i]);
3273 f++;
3274 } else {
3275 sprintf(strbuf, ",%d",
3276 lcd_refresh_rates[i]);
3277 }
3278 strcat(refresh_rates_buf, strbuf);
3279 }
3280 m = m << 1;
3281 }
3282 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3283 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3284 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3285 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3286 /*
3287 * We now need to determine the crtc parameters for the
3288 * LCD monitor. This is tricky, because they are not stored
3289 * individually in the BIOS. Instead, the BIOS contains a
3290 * table of display modes that work for this monitor.
3291 *
3292 * The idea is that we search for a mode of the same dimensions
3293 * as the dimensions of the LCD monitor. Say our LCD monitor
3294 * is 800x600 pixels, we search for a 800x600 monitor.
3295 * The CRTC parameters we find here are the ones that we need
3296 * to use to simulate other resolutions on the LCD screen.
3297 */
3298 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3299 while (*lcdmodeptr != 0) {
3300 u32 modeptr;
3301 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3302 modeptr = bios_base + *lcdmodeptr;
3303
3304 mwidth = *((u16 *)(modeptr+0));
3305 mheight = *((u16 *)(modeptr+2));
3306
3307 if (mwidth == width && mheight == height) {
3308 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3309 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3310 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3311 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3312 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3313 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3314
3315 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3316 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3317 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3318 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3319
3320 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3321 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3322 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3323 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3324
3325 par->lcd_vtotal++;
3326 par->lcd_vdisp++;
3327 lcd_vsync_start++;
3328
3329 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3330 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3331 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3332 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3333 break;
3334 }
3335
3336 lcdmodeptr++;
3337 }
3338 if (*lcdmodeptr == 0) {
3339 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3340 /* To do: Switch to CRT if possible. */
3341 } else {
3342 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3343 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3344 par->lcd_hdisp,
3345 par->lcd_hdisp + par->lcd_right_margin,
3346 par->lcd_hdisp + par->lcd_right_margin
3347 + par->lcd_hsync_dly + par->lcd_hsync_len,
3348 par->lcd_htotal,
3349 par->lcd_vdisp,
3350 par->lcd_vdisp + par->lcd_lower_margin,
3351 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3352 par->lcd_vtotal);
3353 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3354 par->lcd_pixclock,
3355 par->lcd_hblank_len - (par->lcd_right_margin +
3356 par->lcd_hsync_dly + par->lcd_hsync_len),
3357 par->lcd_hdisp,
3358 par->lcd_right_margin,
3359 par->lcd_hsync_len,
3360 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3361 par->lcd_vdisp,
3362 par->lcd_lower_margin,
3363 par->lcd_vsync_len);
3364 }
3365 }
3366 }
3367 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3368
3369 static int init_from_bios(struct atyfb_par *par)
3370 {
3371 u32 bios_base, rom_addr;
3372 int ret;
3373
3374 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3375 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3376
3377 /* The BIOS starts with 0xaa55. */
3378 if (*((u16 *)bios_base) == 0xaa55) {
3379
3380 u8 *bios_ptr;
3381 u16 rom_table_offset, freq_table_offset;
3382 PLL_BLOCK_MACH64 pll_block;
3383
3384 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3385
3386 /* check for frequncy table */
3387 bios_ptr = (u8*)bios_base;
3388 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3389 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3390 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3391
3392 PRINTKI("BIOS frequency table:\n");
3393 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3394 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3395 pll_block.ref_freq, pll_block.ref_divider);
3396 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3397 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3398 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3399
3400 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3401 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3402 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3403 par->pll_limits.ref_div = pll_block.ref_divider;
3404 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3405 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3406 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3407 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3408 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3409 aty_init_lcd(par, bios_base);
3410 #endif
3411 ret = 0;
3412 } else {
3413 PRINTKE("no BIOS frequency table found, use parameters\n");
3414 ret = -ENXIO;
3415 }
3416 iounmap((void __iomem *)bios_base);
3417
3418 return ret;
3419 }
3420 #endif /* __i386__ */
3421
3422 static int atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info,
3423 unsigned long addr)
3424 {
3425 struct atyfb_par *par = info->par;
3426 u16 tmp;
3427 unsigned long raddr;
3428 struct resource *rrp;
3429 int ret = 0;
3430
3431 raddr = addr + 0x7ff000UL;
3432 rrp = &pdev->resource[2];
3433 if ((rrp->flags & IORESOURCE_MEM) &&
3434 request_mem_region(rrp->start, resource_size(rrp), "atyfb")) {
3435 par->aux_start = rrp->start;
3436 par->aux_size = resource_size(rrp);
3437 raddr = rrp->start;
3438 PRINTKI("using auxiliary register aperture\n");
3439 }
3440
3441 info->fix.mmio_start = raddr;
3442 /*
3443 * By using strong UC we force the MTRR to never have an
3444 * effect on the MMIO region on both non-PAT and PAT systems.
3445 */
3446 par->ati_regbase = ioremap_uc(info->fix.mmio_start, 0x1000);
3447 if (par->ati_regbase == NULL)
3448 return -ENOMEM;
3449
3450 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3451 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3452
3453 /*
3454 * Enable memory-space accesses using config-space
3455 * command register.
3456 */
3457 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3458 if (!(tmp & PCI_COMMAND_MEMORY)) {
3459 tmp |= PCI_COMMAND_MEMORY;
3460 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3461 }
3462 #ifdef __BIG_ENDIAN
3463 /* Use the big-endian aperture */
3464 addr += 0x800000;
3465 #endif
3466
3467 /* Map in frame buffer */
3468 info->fix.smem_start = addr;
3469
3470 /*
3471 * The framebuffer is not always 8 MiB, that's just the size of the
3472 * PCI BAR. We temporarily abuse smem_len here to store the size
3473 * of the BAR. aty_init() will later correct it to match the actual
3474 * framebuffer size.
3475 *
3476 * On devices that don't have the auxiliary register aperture, the
3477 * registers are housed at the top end of the framebuffer PCI BAR.
3478 * aty_fudge_framebuffer_len() is used to reduce smem_len to not
3479 * overlap with the registers.
3480 */
3481 info->fix.smem_len = 0x800000;
3482
3483 aty_fudge_framebuffer_len(info);
3484
3485 info->screen_base = ioremap_wc(info->fix.smem_start,
3486 info->fix.smem_len);
3487 if (info->screen_base == NULL) {
3488 ret = -ENOMEM;
3489 goto atyfb_setup_generic_fail;
3490 }
3491
3492 ret = correct_chipset(par);
3493 if (ret)
3494 goto atyfb_setup_generic_fail;
3495 #ifdef __i386__
3496 ret = init_from_bios(par);
3497 if (ret)
3498 goto atyfb_setup_generic_fail;
3499 #endif
3500 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3501 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3502 else
3503 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3504
3505 /* according to ATI, we should use clock 3 for acelerated mode */
3506 par->clk_wr_offset = 3;
3507
3508 return 0;
3509
3510 atyfb_setup_generic_fail:
3511 iounmap(par->ati_regbase);
3512 par->ati_regbase = NULL;
3513 if (info->screen_base) {
3514 iounmap(info->screen_base);
3515 info->screen_base = NULL;
3516 }
3517 return ret;
3518 }
3519
3520 #endif /* !__sparc__ */
3521
3522 static int atyfb_pci_probe(struct pci_dev *pdev,
3523 const struct pci_device_id *ent)
3524 {
3525 unsigned long addr, res_start, res_size;
3526 struct fb_info *info;
3527 struct resource *rp;
3528 struct atyfb_par *par;
3529 int rc = -ENOMEM;
3530
3531 /* Enable device in PCI config */
3532 if (pci_enable_device(pdev)) {
3533 PRINTKE("Cannot enable PCI device\n");
3534 return -ENXIO;
3535 }
3536
3537 /* Find which resource to use */
3538 rp = &pdev->resource[0];
3539 if (rp->flags & IORESOURCE_IO)
3540 rp = &pdev->resource[1];
3541 addr = rp->start;
3542 if (!addr)
3543 return -ENXIO;
3544
3545 /* Reserve space */
3546 res_start = rp->start;
3547 res_size = resource_size(rp);
3548 if (!request_mem_region(res_start, res_size, "atyfb"))
3549 return -EBUSY;
3550
3551 /* Allocate framebuffer */
3552 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3553 if (!info) {
3554 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3555 return -ENOMEM;
3556 }
3557 par = info->par;
3558 par->bus_type = PCI;
3559 info->fix = atyfb_fix;
3560 info->device = &pdev->dev;
3561 par->pci_id = pdev->device;
3562 par->res_start = res_start;
3563 par->res_size = res_size;
3564 par->irq = pdev->irq;
3565 par->pdev = pdev;
3566
3567 /* Setup "info" structure */
3568 #ifdef __sparc__
3569 rc = atyfb_setup_sparc(pdev, info, addr);
3570 #else
3571 rc = atyfb_setup_generic(pdev, info, addr);
3572 #endif
3573 if (rc)
3574 goto err_release_mem;
3575
3576 pci_set_drvdata(pdev, info);
3577
3578 /* Init chip & register framebuffer */
3579 rc = aty_init(info);
3580 if (rc)
3581 goto err_release_io;
3582
3583 #ifdef __sparc__
3584 /*
3585 * Add /dev/fb mmap values.
3586 */
3587 par->mmap_map[0].voff = 0x8000000000000000UL;
3588 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3589 par->mmap_map[0].size = info->fix.smem_len;
3590 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3591 par->mmap_map[0].prot_flag = _PAGE_E;
3592 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3593 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3594 par->mmap_map[1].size = PAGE_SIZE;
3595 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3596 par->mmap_map[1].prot_flag = _PAGE_E;
3597 #endif /* __sparc__ */
3598
3599 mutex_lock(&reboot_lock);
3600 if (!reboot_info)
3601 reboot_info = info;
3602 mutex_unlock(&reboot_lock);
3603
3604 return 0;
3605
3606 err_release_io:
3607 #ifdef __sparc__
3608 kfree(par->mmap_map);
3609 #else
3610 if (par->ati_regbase)
3611 iounmap(par->ati_regbase);
3612 if (info->screen_base)
3613 iounmap(info->screen_base);
3614 #endif
3615 err_release_mem:
3616 if (par->aux_start)
3617 release_mem_region(par->aux_start, par->aux_size);
3618
3619 release_mem_region(par->res_start, par->res_size);
3620 framebuffer_release(info);
3621
3622 return rc;
3623 }
3624
3625 #endif /* CONFIG_PCI */
3626
3627 #ifdef CONFIG_ATARI
3628
3629 static int __init atyfb_atari_probe(void)
3630 {
3631 struct atyfb_par *par;
3632 struct fb_info *info;
3633 int m64_num;
3634 u32 clock_r;
3635 int num_found = 0;
3636
3637 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3638 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3639 !phys_guiregbase[m64_num]) {
3640 PRINTKI("phys_*[%d] parameters not set => "
3641 "returning early. \n", m64_num);
3642 continue;
3643 }
3644
3645 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3646 if (!info) {
3647 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3648 return -ENOMEM;
3649 }
3650 par = info->par;
3651
3652 info->fix = atyfb_fix;
3653
3654 par->irq = (unsigned int) -1; /* something invalid */
3655
3656 /*
3657 * Map the video memory (physical address given)
3658 * to somewhere in the kernel address space.
3659 */
3660 info->screen_base = ioremap_wc(phys_vmembase[m64_num],
3661 phys_size[m64_num]);
3662 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3663 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3664 0xFC00ul;
3665 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3666
3667 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3668 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3669
3670 switch (clock_r & 0x003F) {
3671 case 0x12:
3672 par->clk_wr_offset = 3; /* */
3673 break;
3674 case 0x34:
3675 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3676 break;
3677 case 0x16:
3678 par->clk_wr_offset = 1; /* */
3679 break;
3680 case 0x38:
3681 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3682 break;
3683 }
3684
3685 /* Fake pci_id for correct_chipset() */
3686 switch (aty_ld_le32(CNFG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3687 case 0x00d7:
3688 par->pci_id = PCI_CHIP_MACH64GX;
3689 break;
3690 case 0x0057:
3691 par->pci_id = PCI_CHIP_MACH64CX;
3692 break;
3693 default:
3694 break;
3695 }
3696
3697 if (correct_chipset(par) || aty_init(info)) {
3698 iounmap(info->screen_base);
3699 iounmap(par->ati_regbase);
3700 framebuffer_release(info);
3701 } else {
3702 num_found++;
3703 }
3704 }
3705
3706 return num_found ? 0 : -ENXIO;
3707 }
3708
3709 #endif /* CONFIG_ATARI */
3710
3711 #ifdef CONFIG_PCI
3712
3713 static void atyfb_remove(struct fb_info *info)
3714 {
3715 struct atyfb_par *par = (struct atyfb_par *) info->par;
3716
3717 /* restore video mode */
3718 aty_set_crtc(par, &par->saved_crtc);
3719 par->pll_ops->set_pll(info, &par->saved_pll);
3720
3721 unregister_framebuffer(info);
3722
3723 #ifdef CONFIG_FB_ATY_BACKLIGHT
3724 if (M64_HAS(MOBIL_BUS))
3725 aty_bl_exit(info->bl_dev);
3726 #endif
3727 arch_phys_wc_del(par->wc_cookie);
3728
3729 #ifndef __sparc__
3730 if (par->ati_regbase)
3731 iounmap(par->ati_regbase);
3732 if (info->screen_base)
3733 iounmap(info->screen_base);
3734 #ifdef __BIG_ENDIAN
3735 if (info->sprite.addr)
3736 iounmap(info->sprite.addr);
3737 #endif
3738 #endif
3739 #ifdef __sparc__
3740 kfree(par->mmap_map);
3741 #endif
3742 if (par->aux_start)
3743 release_mem_region(par->aux_start, par->aux_size);
3744
3745 if (par->res_start)
3746 release_mem_region(par->res_start, par->res_size);
3747
3748 framebuffer_release(info);
3749 }
3750
3751
3752 static void atyfb_pci_remove(struct pci_dev *pdev)
3753 {
3754 struct fb_info *info = pci_get_drvdata(pdev);
3755
3756 mutex_lock(&reboot_lock);
3757 if (reboot_info == info)
3758 reboot_info = NULL;
3759 mutex_unlock(&reboot_lock);
3760
3761 atyfb_remove(info);
3762 }
3763
3764 static const struct pci_device_id atyfb_pci_tbl[] = {
3765 #ifdef CONFIG_FB_ATY_GX
3766 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GX) },
3767 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64CX) },
3768 #endif /* CONFIG_FB_ATY_GX */
3769
3770 #ifdef CONFIG_FB_ATY_CT
3771 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64CT) },
3772 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64ET) },
3773
3774 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LT) },
3775
3776 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VT) },
3777 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GT) },
3778
3779 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VU) },
3780 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GU) },
3781
3782 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LG) },
3783
3784 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VV) },
3785
3786 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GV) },
3787 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GW) },
3788 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GY) },
3789 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GZ) },
3790
3791 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GB) },
3792 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GD) },
3793 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GI) },
3794 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GP) },
3795 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GQ) },
3796
3797 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LB) },
3798 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LD) },
3799 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LI) },
3800 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LP) },
3801 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LQ) },
3802
3803 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GM) },
3804 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GN) },
3805 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GO) },
3806 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GL) },
3807 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GR) },
3808 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GS) },
3809
3810 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LM) },
3811 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LN) },
3812 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LR) },
3813 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LS) },
3814 #endif /* CONFIG_FB_ATY_CT */
3815 { }
3816 };
3817
3818 MODULE_DEVICE_TABLE(pci, atyfb_pci_tbl);
3819
3820 static struct pci_driver atyfb_driver = {
3821 .name = "atyfb",
3822 .id_table = atyfb_pci_tbl,
3823 .probe = atyfb_pci_probe,
3824 .remove = atyfb_pci_remove,
3825 #ifdef CONFIG_PM
3826 .suspend = atyfb_pci_suspend,
3827 .resume = atyfb_pci_resume,
3828 #endif /* CONFIG_PM */
3829 };
3830
3831 #endif /* CONFIG_PCI */
3832
3833 #ifndef MODULE
3834 static int __init atyfb_setup(char *options)
3835 {
3836 char *this_opt;
3837
3838 if (!options || !*options)
3839 return 0;
3840
3841 while ((this_opt = strsep(&options, ",")) != NULL) {
3842 if (!strncmp(this_opt, "noaccel", 7)) {
3843 noaccel = 1;
3844 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3845 nomtrr = 1;
3846 } else if (!strncmp(this_opt, "vram:", 5))
3847 vram = simple_strtoul(this_opt + 5, NULL, 0);
3848 else if (!strncmp(this_opt, "pll:", 4))
3849 pll = simple_strtoul(this_opt + 4, NULL, 0);
3850 else if (!strncmp(this_opt, "mclk:", 5))
3851 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3852 else if (!strncmp(this_opt, "xclk:", 5))
3853 xclk = simple_strtoul(this_opt+5, NULL, 0);
3854 else if (!strncmp(this_opt, "comp_sync:", 10))
3855 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3856 else if (!strncmp(this_opt, "backlight:", 10))
3857 backlight = simple_strtoul(this_opt+10, NULL, 0);
3858 #ifdef CONFIG_PPC
3859 else if (!strncmp(this_opt, "vmode:", 6)) {
3860 unsigned int vmode =
3861 simple_strtoul(this_opt + 6, NULL, 0);
3862 if (vmode > 0 && vmode <= VMODE_MAX)
3863 default_vmode = vmode;
3864 } else if (!strncmp(this_opt, "cmode:", 6)) {
3865 unsigned int cmode =
3866 simple_strtoul(this_opt + 6, NULL, 0);
3867 switch (cmode) {
3868 case 0:
3869 case 8:
3870 default_cmode = CMODE_8;
3871 break;
3872 case 15:
3873 case 16:
3874 default_cmode = CMODE_16;
3875 break;
3876 case 24:
3877 case 32:
3878 default_cmode = CMODE_32;
3879 break;
3880 }
3881 }
3882 #endif
3883 #ifdef CONFIG_ATARI
3884 /*
3885 * Why do we need this silly Mach64 argument?
3886 * We are already here because of mach64= so its redundant.
3887 */
3888 else if (MACH_IS_ATARI
3889 && (!strncmp(this_opt, "Mach64:", 7))) {
3890 static unsigned char m64_num;
3891 static char mach64_str[80];
3892 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3893 if (!store_video_par(mach64_str, m64_num)) {
3894 m64_num++;
3895 mach64_count = m64_num;
3896 }
3897 }
3898 #endif
3899 else
3900 mode = this_opt;
3901 }
3902 return 0;
3903 }
3904 #endif /* MODULE */
3905
3906 static int atyfb_reboot_notify(struct notifier_block *nb,
3907 unsigned long code, void *unused)
3908 {
3909 struct atyfb_par *par;
3910
3911 if (code != SYS_RESTART)
3912 return NOTIFY_DONE;
3913
3914 mutex_lock(&reboot_lock);
3915
3916 if (!reboot_info)
3917 goto out;
3918
3919 if (!lock_fb_info(reboot_info))
3920 goto out;
3921
3922 par = reboot_info->par;
3923
3924 /*
3925 * HP OmniBook 500's BIOS doesn't like the state of the
3926 * hardware after atyfb has been used. Restore the hardware
3927 * to the original state to allow successful reboots.
3928 */
3929 aty_set_crtc(par, &par->saved_crtc);
3930 par->pll_ops->set_pll(reboot_info, &par->saved_pll);
3931
3932 unlock_fb_info(reboot_info);
3933 out:
3934 mutex_unlock(&reboot_lock);
3935
3936 return NOTIFY_DONE;
3937 }
3938
3939 static struct notifier_block atyfb_reboot_notifier = {
3940 .notifier_call = atyfb_reboot_notify,
3941 };
3942
3943 static const struct dmi_system_id atyfb_reboot_ids[] __initconst = {
3944 {
3945 .ident = "HP OmniBook 500",
3946 .matches = {
3947 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3948 DMI_MATCH(DMI_PRODUCT_NAME, "HP OmniBook PC"),
3949 DMI_MATCH(DMI_PRODUCT_VERSION, "HP OmniBook 500 FA"),
3950 },
3951 },
3952
3953 { }
3954 };
3955 static bool registered_notifier = false;
3956
3957 static int __init atyfb_init(void)
3958 {
3959 int err1 = 1, err2 = 1;
3960 #ifndef MODULE
3961 char *option = NULL;
3962
3963 if (fb_get_options("atyfb", &option))
3964 return -ENODEV;
3965 atyfb_setup(option);
3966 #endif
3967
3968 #ifdef CONFIG_PCI
3969 err1 = pci_register_driver(&atyfb_driver);
3970 #endif
3971 #ifdef CONFIG_ATARI
3972 err2 = atyfb_atari_probe();
3973 #endif
3974
3975 if (err1 && err2)
3976 return -ENODEV;
3977
3978 if (dmi_check_system(atyfb_reboot_ids)) {
3979 register_reboot_notifier(&atyfb_reboot_notifier);
3980 registered_notifier = true;
3981 }
3982
3983 return 0;
3984 }
3985
3986 static void __exit atyfb_exit(void)
3987 {
3988 if (registered_notifier)
3989 unregister_reboot_notifier(&atyfb_reboot_notifier);
3990
3991 #ifdef CONFIG_PCI
3992 pci_unregister_driver(&atyfb_driver);
3993 #endif
3994 }
3995
3996 module_init(atyfb_init);
3997 module_exit(atyfb_exit);
3998
3999 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
4000 MODULE_LICENSE("GPL");
4001 module_param(noaccel, bool, 0);
4002 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
4003 module_param(vram, int, 0);
4004 MODULE_PARM_DESC(vram, "int: override size of video ram");
4005 module_param(pll, int, 0);
4006 MODULE_PARM_DESC(pll, "int: override video clock");
4007 module_param(mclk, int, 0);
4008 MODULE_PARM_DESC(mclk, "int: override memory clock");
4009 module_param(xclk, int, 0);
4010 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
4011 module_param(comp_sync, int, 0);
4012 MODULE_PARM_DESC(comp_sync, "Set composite sync signal to low (0) or high (1)");
4013 module_param(mode, charp, 0);
4014 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
4015 module_param(nomtrr, bool, 0);
4016 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
Linux with added FPC-III support