| blob | 4710845dbac4fb663e35fcf0056499614a06e56b |
1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
5 By: David Howells <dhowells@redhat.com>
7 Contents:
9 (*) Abstract memory access model.
11 - Device operations.
12 - Guarantees.
14 (*) What are memory barriers?
16 - Varieties of memory barrier.
17 - What may not be assumed about memory barriers?
18 - Data dependency barriers.
19 - Control dependencies.
20 - SMP barrier pairing.
21 - Examples of memory barrier sequences.
22 - Read memory barriers vs load speculation.
24 (*) Explicit kernel barriers.
26 - Compiler barrier.
27 - The CPU memory barriers.
28 - MMIO write barrier.
30 (*) Implicit kernel memory barriers.
32 - Locking functions.
33 - Interrupt disabling functions.
34 - Miscellaneous functions.
36 (*) Inter-CPU locking barrier effects.
38 - Locks vs memory accesses.
39 - Locks vs I/O accesses.
41 (*) Where are memory barriers needed?
43 - Interprocessor interaction.
44 - Atomic operations.
45 - Accessing devices.
46 - Interrupts.
48 (*) Kernel I/O barrier effects.
50 (*) Assumed minimum execution ordering model.
52 (*) The effects of the cpu cache.
54 - Cache coherency.
55 - Cache coherency vs DMA.
56 - Cache coherency vs MMIO.
58 (*) The things CPUs get up to.
60 - And then there's the Alpha.
62 (*) References.
65 ============================
66 ABSTRACT MEMORY ACCESS MODEL
67 ============================
69 Consider the following abstract model of the system:
71 : :
72 : :
73 : :
74 +-------+ : +--------+ : +-------+
75 | | : | | : | |
76 | | : | | : | |
77 | CPU 1 |<----->| Memory |<----->| CPU 2 |
78 | | : | | : | |
79 | | : | | : | |
80 +-------+ : +--------+ : +-------+
81 ^ : ^ : ^
82 | : | : |
83 | : | : |
84 | : v : |
85 | : +--------+ : |
86 | : | | : |
87 | : | | : |
88 +---------->| Device |<----------+
89 : | | :
90 : | | :
91 : +--------+ :
92 : :
94 Each CPU executes a program that generates memory access operations. In the
95 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
96 perform the memory operations in any order it likes, provided program causality
97 appears to be maintained. Similarly, the compiler may also arrange the
98 instructions it emits in any order it likes, provided it doesn't affect the
99 apparent operation of the program.
101 So in the above diagram, the effects of the memory operations performed by a
102 CPU are perceived by the rest of the system as the operations cross the
103 interface between the CPU and rest of the system (the dotted lines).
106 For example, consider the following sequence of events:
108 CPU 1 CPU 2
109 =============== ===============
110 { A == 1; B == 2 }
111 A = 3; x = A;
112 B = 4; y = B;
114 The set of accesses as seen by the memory system in the middle can be arranged
115 in 24 different combinations:
117 STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
118 STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
119 STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
120 STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
121 STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
122 STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
123 STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
124 STORE B=4, ...
125 ...
127 and can thus result in four different combinations of values:
129 x == 1, y == 2
130 x == 1, y == 4
131 x == 3, y == 2
132 x == 3, y == 4
135 Furthermore, the stores committed by a CPU to the memory system may not be
136 perceived by the loads made by another CPU in the same order as the stores were
137 committed.
140 As a further example, consider this sequence of events:
142 CPU 1 CPU 2
143 =============== ===============
144 { A == 1, B == 2, C = 3, P == &A, Q == &C }
145 B = 4; Q = P;
146 P = &B D = *Q;
148 There is an obvious data dependency here, as the value loaded into D depends on
149 the address retrieved from P by CPU 2. At the end of the sequence, any of the
150 following results are possible:
152 (Q == &A) and (D == 1)
153 (Q == &B) and (D == 2)
154 (Q == &B) and (D == 4)
156 Note that CPU 2 will never try and load C into D because the CPU will load P
157 into Q before issuing the load of *Q.
160 DEVICE OPERATIONS
161 -----------------
163 Some devices present their control interfaces as collections of memory
164 locations, but the order in which the control registers are accessed is very
165 important. For instance, imagine an ethernet card with a set of internal
166 registers that are accessed through an address port register (A) and a data
167 port register (D). To read internal register 5, the following code might then
168 be used:
170 *A = 5;
171 x = *D;
173 but this might show up as either of the following two sequences:
175 STORE *A = 5, x = LOAD *D
176 x = LOAD *D, STORE *A = 5
178 the second of which will almost certainly result in a malfunction, since it set
179 the address _after_ attempting to read the register.
182 GUARANTEES
183 ----------
185 There are some minimal guarantees that may be expected of a CPU:
187 (*) On any given CPU, dependent memory accesses will be issued in order, with
188 respect to itself. This means that for:
190 Q = P; D = *Q;
192 the CPU will issue the following memory operations:
194 Q = LOAD P, D = LOAD *Q
196 and always in that order.
198 (*) Overlapping loads and stores within a particular CPU will appear to be
199 ordered within that CPU. This means that for:
201 a = *X; *X = b;
203 the CPU will only issue the following sequence of memory operations:
205 a = LOAD *X, STORE *X = b
207 And for:
209 *X = c; d = *X;
211 the CPU will only issue:
213 STORE *X = c, d = LOAD *X
215 (Loads and stores overlap if they are targetted at overlapping pieces of
216 memory).
218 And there are a number of things that _must_ or _must_not_ be assumed:
220 (*) It _must_not_ be assumed that independent loads and stores will be issued
221 in the order given. This means that for:
223 X = *A; Y = *B; *D = Z;
225 we may get any of the following sequences:
227 X = LOAD *A, Y = LOAD *B, STORE *D = Z
228 X = LOAD *A, STORE *D = Z, Y = LOAD *B
229 Y = LOAD *B, X = LOAD *A, STORE *D = Z
230 Y = LOAD *B, STORE *D = Z, X = LOAD *A
231 STORE *D = Z, X = LOAD *A, Y = LOAD *B
232 STORE *D = Z, Y = LOAD *B, X = LOAD *A
234 (*) It _must_ be assumed that overlapping memory accesses may be merged or
235 discarded. This means that for:
237 X = *A; Y = *(A + 4);
239 we may get any one of the following sequences:
241 X = LOAD *A; Y = LOAD *(A + 4);
242 Y = LOAD *(A + 4); X = LOAD *A;
243 {X, Y} = LOAD {*A, *(A + 4) };
245 And for:
247 *A = X; Y = *A;
249 we may get either of:
251 STORE *A = X; Y = LOAD *A;
252 STORE *A = Y = X;
255 =========================
256 WHAT ARE MEMORY BARRIERS?
257 =========================
259 As can be seen above, independent memory operations are effectively performed
260 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
261 What is required is some way of intervening to instruct the compiler and the
262 CPU to restrict the order.
264 Memory barriers are such interventions. They impose a perceived partial
265 ordering between the memory operations specified on either side of the barrier.
266 They request that the sequence of memory events generated appears to other
267 parts of the system as if the barrier is effective on that CPU.
270 VARIETIES OF MEMORY BARRIER
271 ---------------------------
273 Memory barriers come in four basic varieties:
275 (1) Write (or store) memory barriers.
277 A write memory barrier gives a guarantee that all the STORE operations
278 specified before the barrier will appear to happen before all the STORE
279 operations specified after the barrier with respect to the other
280 components of the system.
282 A write barrier is a partial ordering on stores only; it is not required
283 to have any effect on loads.
285 A CPU can be viewed as as commiting a sequence of store operations to the
286 memory system as time progresses. All stores before a write barrier will
287 occur in the sequence _before_ all the stores after the write barrier.
289 [!] Note that write barriers should normally be paired with read or data
290 dependency barriers; see the "SMP barrier pairing" subsection.
293 (2) Data dependency barriers.
295 A data dependency barrier is a weaker form of read barrier. In the case
296 where two loads are performed such that the second depends on the result
297 of the first (eg: the first load retrieves the address to which the second
298 load will be directed), a data dependency barrier would be required to
299 make sure that the target of the second load is updated before the address
300 obtained by the first load is accessed.
302 A data dependency barrier is a partial ordering on interdependent loads
303 only; it is not required to have any effect on stores, independent loads
304 or overlapping loads.
306 As mentioned in (1), the other CPUs in the system can be viewed as
307 committing sequences of stores to the memory system that the CPU being
308 considered can then perceive. A data dependency barrier issued by the CPU
309 under consideration guarantees that for any load preceding it, if that
310 load touches one of a sequence of stores from another CPU, then by the
311 time the barrier completes, the effects of all the stores prior to that
312 touched by the load will be perceptible to any loads issued after the data
313 dependency barrier.
315 See the "Examples of memory barrier sequences" subsection for diagrams
316 showing the ordering constraints.
318 [!] Note that the first load really has to have a _data_ dependency and
319 not a control dependency. If the address for the second load is dependent
320 on the first load, but the dependency is through a conditional rather than
321 actually loading the address itself, then it's a _control_ dependency and
322 a full read barrier or better is required. See the "Control dependencies"
323 subsection for more information.
325 [!] Note that data dependency barriers should normally be paired with
326 write barriers; see the "SMP barrier pairing" subsection.
329 (3) Read (or load) memory barriers.
331 A read barrier is a data dependency barrier plus a guarantee that all the
332 LOAD operations specified before the barrier will appear to happen before
333 all the LOAD operations specified after the barrier with respect to the
334 other components of the system.
336 A read barrier is a partial ordering on loads only; it is not required to
337 have any effect on stores.
339 Read memory barriers imply data dependency barriers, and so can substitute
340 for them.
342 [!] Note that read barriers should normally be paired with write barriers;
343 see the "SMP barrier pairing" subsection.
346 (4) General memory barriers.
348 A general memory barrier gives a guarantee that all the LOAD and STORE
349 operations specified before the barrier will appear to happen before all
350 the LOAD and STORE operations specified after the barrier with respect to
351 the other components of the system.
353 A general memory barrier is a partial ordering over both loads and stores.
355 General memory barriers imply both read and write memory barriers, and so
356 can substitute for either.
359 And a couple of implicit varieties:
361 (5) LOCK operations.
363 This acts as a one-way permeable barrier. It guarantees that all memory
364 operations after the LOCK operation will appear to happen after the LOCK
365 operation with respect to the other components of the system.
367 Memory operations that occur before a LOCK operation may appear to happen
368 after it completes.
370 A LOCK operation should almost always be paired with an UNLOCK operation.
373 (6) UNLOCK operations.
375 This also acts as a one-way permeable barrier. It guarantees that all
376 memory operations before the UNLOCK operation will appear to happen before
377 the UNLOCK operation with respect to the other components of the system.
379 Memory operations that occur after an UNLOCK operation may appear to
380 happen before it completes.
382 LOCK and UNLOCK operations are guaranteed to appear with respect to each
383 other strictly in the order specified.
385 The use of LOCK and UNLOCK operations generally precludes the need for
386 other sorts of memory barrier (but note the exceptions mentioned in the
387 subsection "MMIO write barrier").
390 Memory barriers are only required where there's a possibility of interaction
391 between two CPUs or between a CPU and a device. If it can be guaranteed that
392 there won't be any such interaction in any particular piece of code, then
393 memory barriers are unnecessary in that piece of code.
396 Note that these are the _minimum_ guarantees. Different architectures may give
397 more substantial guarantees, but they may _not_ be relied upon outside of arch
398 specific code.
401 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
402 ----------------------------------------------
404 There are certain things that the Linux kernel memory barriers do not guarantee:
406 (*) There is no guarantee that any of the memory accesses specified before a
407 memory barrier will be _complete_ by the completion of a memory barrier
408 instruction; the barrier can be considered to draw a line in that CPU's
409 access queue that accesses of the appropriate type may not cross.
411 (*) There is no guarantee that issuing a memory barrier on one CPU will have
412 any direct effect on another CPU or any other hardware in the system. The
413 indirect effect will be the order in which the second CPU sees the effects
414 of the first CPU's accesses occur, but see the next point:
416 (*) There is no guarantee that the a CPU will see the correct order of effects
417 from a second CPU's accesses, even _if_ the second CPU uses a memory
418 barrier, unless the first CPU _also_ uses a matching memory barrier (see
419 the subsection on "SMP Barrier Pairing").
421 (*) There is no guarantee that some intervening piece of off-the-CPU
422 hardware[*] will not reorder the memory accesses. CPU cache coherency
423 mechanisms should propagate the indirect effects of a memory barrier
424 between CPUs, but might not do so in order.
426 [*] For information on bus mastering DMA and coherency please read:
428 Documentation/pci.txt
429 Documentation/DMA-mapping.txt
430 Documentation/DMA-API.txt
433 DATA DEPENDENCY BARRIERS
434 ------------------------
436 The usage requirements of data dependency barriers are a little subtle, and
437 it's not always obvious that they're needed. To illustrate, consider the
438 following sequence of events:
440 CPU 1 CPU 2
441 =============== ===============
442 { A == 1, B == 2, C = 3, P == &A, Q == &C }
443 B = 4;
444 <write barrier>
445 P = &B
446 Q = P;
447 D = *Q;
449 There's a clear data dependency here, and it would seem that by the end of the
450 sequence, Q must be either &A or &B, and that:
452 (Q == &A) implies (D == 1)
453 (Q == &B) implies (D == 4)
455 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
456 leading to the following situation:
458 (Q == &B) and (D == 2) ????
460 Whilst this may seem like a failure of coherency or causality maintenance, it
461 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
462 Alpha).
464 To deal with this, a data dependency barrier must be inserted between the
465 address load and the data load:
467 CPU 1 CPU 2
468 =============== ===============
469 { A == 1, B == 2, C = 3, P == &A, Q == &C }
470 B = 4;
471 <write barrier>
472 P = &B
473 Q = P;
474 <data dependency barrier>
475 D = *Q;
477 This enforces the occurrence of one of the two implications, and prevents the
478 third possibility from arising.
480 [!] Note that this extremely counterintuitive situation arises most easily on
481 machines with split caches, so that, for example, one cache bank processes
482 even-numbered cache lines and the other bank processes odd-numbered cache
483 lines. The pointer P might be stored in an odd-numbered cache line, and the
484 variable B might be stored in an even-numbered cache line. Then, if the
485 even-numbered bank of the reading CPU's cache is extremely busy while the
486 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
487 but the old value of the variable B (1).
490 Another example of where data dependency barriers might by required is where a
491 number is read from memory and then used to calculate the index for an array
492 access:
494 CPU 1 CPU 2
495 =============== ===============
496 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
497 M[1] = 4;
498 <write barrier>
499 P = 1
500 Q = P;
501 <data dependency barrier>
502 D = M[Q];
505 The data dependency barrier is very important to the RCU system, for example.
506 See rcu_dereference() in include/linux/rcupdate.h. This permits the current
507 target of an RCU'd pointer to be replaced with a new modified target, without
508 the replacement target appearing to be incompletely initialised.
510 See also the subsection on "Cache Coherency" for a more thorough example.
513 CONTROL DEPENDENCIES
514 --------------------
516 A control dependency requires a full read memory barrier, not simply a data
517 dependency barrier to make it work correctly. Consider the following bit of
518 code:
520 q = &a;
521 if (p)
522 q = &b;
523 <data dependency barrier>
524 x = *q;
526 This will not have the desired effect because there is no actual data
527 dependency, but rather a control dependency that the CPU may short-circuit by
528 attempting to predict the outcome in advance. In such a case what's actually
529 required is:
531 q = &a;
532 if (p)
533 q = &b;
534 <read barrier>
535 x = *q;
538 SMP BARRIER PAIRING
539 -------------------
541 When dealing with CPU-CPU interactions, certain types of memory barrier should
542 always be paired. A lack of appropriate pairing is almost certainly an error.
544 A write barrier should always be paired with a data dependency barrier or read
545 barrier, though a general barrier would also be viable. Similarly a read
546 barrier or a data dependency barrier should always be paired with at least an
547 write barrier, though, again, a general barrier is viable:
549 CPU 1 CPU 2
550 =============== ===============
551 a = 1;
552 <write barrier>
553 b = 2; x = b;
554 <read barrier>
555 y = a;
557 Or:
559 CPU 1 CPU 2
560 =============== ===============================
561 a = 1;
562 <write barrier>
563 b = &a; x = b;
564 <data dependency barrier>
565 y = *x;
567 Basically, the read barrier always has to be there, even though it can be of
568 the "weaker" type.
570 [!] Note that the stores before the write barrier would normally be expected to
571 match the loads after the read barrier or data dependency barrier, and vice
572 versa:
574 CPU 1 CPU 2
575 =============== ===============
576 a = 1; }---- --->{ v = c
577 b = 2; } \ / { w = d
578 <write barrier> \ <read barrier>
579 c = 3; } / \ { x = a;
580 d = 4; }---- --->{ y = b;
583 EXAMPLES OF MEMORY BARRIER SEQUENCES
584 ------------------------------------
586 Firstly, write barriers act as a partial orderings on store operations.
587 Consider the following sequence of events:
589 CPU 1
590 =======================
591 STORE A = 1
592 STORE B = 2
593 STORE C = 3
594 <write barrier>
595 STORE D = 4
596 STORE E = 5
598 This sequence of events is committed to the memory coherence system in an order
599 that the rest of the system might perceive as the unordered set of { STORE A,
600 STORE B, STORE C } all occuring before the unordered set of { STORE D, STORE E
601 }:
603 +-------+ : :
604 | | +------+
605 | |------>| C=3 | } /\
606 | | : +------+ }----- \ -----> Events perceptible
607 | | : | A=1 | } \/ to rest of system
608 | | : +------+ }
609 | CPU 1 | : | B=2 | }
610 | | +------+ }
611 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
612 | | +------+ } requires all stores prior to the
613 | | : | E=5 | } barrier to be committed before
614 | | : +------+ } further stores may be take place.
615 | |------>| D=4 | }
616 | | +------+
617 +-------+ : :
618 |
619 | Sequence in which stores are committed to the
620 | memory system by CPU 1
621 V
624 Secondly, data dependency barriers act as a partial orderings on data-dependent
625 loads. Consider the following sequence of events:
627 CPU 1 CPU 2
628 ======================= =======================
629 { B = 7; X = 9; Y = 8; C = &Y }
630 STORE A = 1
631 STORE B = 2
632 <write barrier>
633 STORE C = &B LOAD X
634 STORE D = 4 LOAD C (gets &B)
635 LOAD *C (reads B)
637 Without intervention, CPU 2 may perceive the events on CPU 1 in some
638 effectively random order, despite the write barrier issued by CPU 1:
640 +-------+ : : : :
641 | | +------+ +-------+ | Sequence of update
642 | |------>| B=2 |----- --->| Y->8 | | of perception on
643 | | : +------+ \ +-------+ | CPU 2
644 | CPU 1 | : | A=1 | \ --->| C->&Y | V
645 | | +------+ | +-------+
646 | | wwwwwwwwwwwwwwww | : :
647 | | +------+ | : :
648 | | : | C=&B |--- | : : +-------+
649 | | : +------+ \ | +-------+ | |
650 | |------>| D=4 | ----------->| C->&B |------>| |
651 | | +------+ | +-------+ | |
652 +-------+ : : | : : | |
653 | : : | |
654 | : : | CPU 2 |
655 | +-------+ | |
656 Apparently incorrect ---> | | B->7 |------>| |
657 perception of B (!) | +-------+ | |
658 | : : | |
659 | +-------+ | |
660 The load of X holds ---> \ | X->9 |------>| |
661 up the maintenance \ +-------+ | |
662 of coherence of B ----->| B->2 | +-------+
663 +-------+
664 : :
667 In the above example, CPU 2 perceives that B is 7, despite the load of *C
668 (which would be B) coming after the the LOAD of C.
670 If, however, a data dependency barrier were to be placed between the load of C
671 and the load of *C (ie: B) on CPU 2:
673 CPU 1 CPU 2
674 ======================= =======================
675 { B = 7; X = 9; Y = 8; C = &Y }
676 STORE A = 1
677 STORE B = 2
678 <write barrier>
679 STORE C = &B LOAD X
680 STORE D = 4 LOAD C (gets &B)
681 <data dependency barrier>
682 LOAD *C (reads B)
684 then the following will occur:
686 +-------+ : : : :
687 | | +------+ +-------+
688 | |------>| B=2 |----- --->| Y->8 |
689 | | : +------+ \ +-------+
690 | CPU 1 | : | A=1 | \ --->| C->&Y |
691 | | +------+ | +-------+
692 | | wwwwwwwwwwwwwwww | : :
693 | | +------+ | : :
694 | | : | C=&B |--- | : : +-------+
695 | | : +------+ \ | +-------+ | |
696 | |------>| D=4 | ----------->| C->&B |------>| |
697 | | +------+ | +-------+ | |
698 +-------+ : : | : : | |
699 | : : | |
700 | : : | CPU 2 |
701 | +-------+ | |
702 | | X->9 |------>| |
703 | +-------+ | |
704 Makes sure all effects ---> \ ddddddddddddddddd | |
705 prior to the store of C \ +-------+ | |
706 are perceptible to ----->| B->2 |------>| |
707 subsequent loads +-------+ | |
708 : : +-------+
711 And thirdly, a read barrier acts as a partial order on loads. Consider the
712 following sequence of events:
714 CPU 1 CPU 2
715 ======================= =======================
716 { A = 0, B = 9 }
717 STORE A=1
718 <write barrier>
719 STORE B=2
720 LOAD B
721 LOAD A
723 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
724 some effectively random order, despite the write barrier issued by CPU 1:
726 +-------+ : : : :
727 | | +------+ +-------+
728 | |------>| A=1 |------ --->| A->0 |
729 | | +------+ \ +-------+
730 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
731 | | +------+ | +-------+
732 | |------>| B=2 |--- | : :
733 | | +------+ \ | : : +-------+
734 +-------+ : : \ | +-------+ | |
735 ---------->| B->2 |------>| |
736 | +-------+ | CPU 2 |
737 | | A->0 |------>| |
738 | +-------+ | |
739 | : : +-------+
740 \ : :
741 \ +-------+
742 ---->| A->1 |
743 +-------+
744 : :
747 If, however, a read barrier were to be placed between the load of E and the
748 load of A on CPU 2:
750 CPU 1 CPU 2
751 ======================= =======================
752 { A = 0, B = 9 }
753 STORE A=1
754 <write barrier>
755 STORE B=2
756 LOAD B
757 <read barrier>
758 LOAD A
760 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
761 2:
763 +-------+ : : : :
764 | | +------+ +-------+
765 | |------>| A=1 |------ --->| A->0 |
766 | | +------+ \ +-------+
767 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
768 | | +------+ | +-------+
769 | |------>| B=2 |--- | : :
770 | | +------+ \ | : : +-------+
771 +-------+ : : \ | +-------+ | |
772 ---------->| B->2 |------>| |
773 | +-------+ | CPU 2 |
774 | : : | |
775 | : : | |
776 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
777 barrier causes all effects \ +-------+ | |
778 prior to the storage of B ---->| A->1 |------>| |
779 to be perceptible to CPU 2 +-------+ | |
780 : : +-------+
783 To illustrate this more completely, consider what could happen if the code
784 contained a load of A either side of the read barrier:
786 CPU 1 CPU 2
787 ======================= =======================
788 { A = 0, B = 9 }
789 STORE A=1
790 <write barrier>
791 STORE B=2
792 LOAD B
793 LOAD A [first load of A]
794 <read barrier>
795 LOAD A [second load of A]
797 Even though the two loads of A both occur after the load of B, they may both
798 come up with different values:
800 +-------+ : : : :
801 | | +------+ +-------+
802 | |------>| A=1 |------ --->| A->0 |
803 | | +------+ \ +-------+
804 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
805 | | +------+ | +-------+
806 | |------>| B=2 |--- | : :
807 | | +------+ \ | : : +-------+
808 +-------+ : : \ | +-------+ | |
809 ---------->| B->2 |------>| |
810 | +-------+ | CPU 2 |
811 | : : | |
812 | : : | |
813 | +-------+ | |
814 | | A->0 |------>| 1st |
815 | +-------+ | |
816 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
817 barrier causes all effects \ +-------+ | |
818 prior to the storage of B ---->| A->1 |------>| 2nd |
819 to be perceptible to CPU 2 +-------+ | |
820 : : +-------+
823 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
824 before the read barrier completes anyway:
826 +-------+ : : : :
827 | | +------+ +-------+
828 | |------>| A=1 |------ --->| A->0 |
829 | | +------+ \ +-------+
830 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
831 | | +------+ | +-------+
832 | |------>| B=2 |--- | : :
833 | | +------+ \ | : : +-------+
834 +-------+ : : \ | +-------+ | |
835 ---------->| B->2 |------>| |
836 | +-------+ | CPU 2 |
837 | : : | |
838 \ : : | |
839 \ +-------+ | |
840 ---->| A->1 |------>| 1st |
841 +-------+ | |
842 rrrrrrrrrrrrrrrrr | |
843 +-------+ | |
844 | A->1 |------>| 2nd |
845 +-------+ | |
846 : : +-------+
849 The guarantee is that the second load will always come up with A == 1 if the
850 load of B came up with B == 2. No such guarantee exists for the first load of
851 A; that may come up with either A == 0 or A == 1.
854 READ MEMORY BARRIERS VS LOAD SPECULATION
855 ----------------------------------------
857 Many CPUs speculate with loads: that is they see that they will need to load an
858 item from memory, and they find a time where they're not using the bus for any
859 other loads, and so do the load in advance - even though they haven't actually
860 got to that point in the instruction execution flow yet. This permits the
861 actual load instruction to potentially complete immediately because the CPU
862 already has the value to hand.
864 It may turn out that the CPU didn't actually need the value - perhaps because a
865 branch circumvented the load - in which case it can discard the value or just
866 cache it for later use.
868 Consider:
870 CPU 1 CPU 2
871 ======================= =======================
872 LOAD B
873 DIVIDE } Divide instructions generally
874 DIVIDE } take a long time to perform
875 LOAD A
877 Which might appear as this:
879 : : +-------+
880 +-------+ | |
881 --->| B->2 |------>| |
882 +-------+ | CPU 2 |
883 : :DIVIDE | |
884 +-------+ | |
885 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
886 division speculates on the +-------+ ~ | |
887 LOAD of A : : ~ | |
888 : :DIVIDE | |
889 : : ~ | |
890 Once the divisions are complete --> : : ~-->| |
891 the CPU can then perform the : : | |
892 LOAD with immediate effect : : +-------+
895 Placing a read barrier or a data dependency barrier just before the second
896 load:
898 CPU 1 CPU 2
899 ======================= =======================
900 LOAD B
901 DIVIDE
902 DIVIDE
903 <read barrier>
904 LOAD A
906 will force any value speculatively obtained to be reconsidered to an extent
907 dependent on the type of barrier used. If there was no change made to the
908 speculated memory location, then the speculated value will just be used:
910 : : +-------+
911 +-------+ | |
912 --->| B->2 |------>| |
913 +-------+ | CPU 2 |
914 : :DIVIDE | |
915 +-------+ | |
916 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
917 division speculates on the +-------+ ~ | |
918 LOAD of A : : ~ | |
919 : :DIVIDE | |
920 : : ~ | |
921 : : ~ | |
922 rrrrrrrrrrrrrrrr~ | |
923 : : ~ | |
924 : : ~-->| |
925 : : | |
926 : : +-------+
929 but if there was an update or an invalidation from another CPU pending, then
930 the speculation will be cancelled and the value reloaded:
932 : : +-------+
933 +-------+ | |
934 --->| B->2 |------>| |
935 +-------+ | CPU 2 |
936 : :DIVIDE | |
937 +-------+ | |
938 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
939 division speculates on the +-------+ ~ | |
940 LOAD of A : : ~ | |
941 : :DIVIDE | |
942 : : ~ | |
943 : : ~ | |
944 rrrrrrrrrrrrrrrrr | |
945 +-------+ | |
946 The speculation is discarded ---> --->| A->1 |------>| |
947 and an updated value is +-------+ | |
948 retrieved : : +-------+
951 ========================
952 EXPLICIT KERNEL BARRIERS
953 ========================
955 The Linux kernel has a variety of different barriers that act at different
956 levels:
958 (*) Compiler barrier.
960 (*) CPU memory barriers.
962 (*) MMIO write barrier.
965 COMPILER BARRIER
966 ----------------
968 The Linux kernel has an explicit compiler barrier function that prevents the
969 compiler from moving the memory accesses either side of it to the other side:
971 barrier();
973 This a general barrier - lesser varieties of compiler barrier do not exist.
975 The compiler barrier has no direct effect on the CPU, which may then reorder
976 things however it wishes.
979 CPU MEMORY BARRIERS
980 -------------------
982 The Linux kernel has eight basic CPU memory barriers:
984 TYPE MANDATORY SMP CONDITIONAL
985 =============== ======================= ===========================
986 GENERAL mb() smp_mb()
987 WRITE wmb() smp_wmb()
988 READ rmb() smp_rmb()
989 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
992 All CPU memory barriers unconditionally imply compiler barriers.
994 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
995 systems because it is assumed that a CPU will be appear to be self-consistent,
996 and will order overlapping accesses correctly with respect to itself.
998 [!] Note that SMP memory barriers _must_ be used to control the ordering of
999 references to shared memory on SMP systems, though the use of locking instead
1000 is sufficient.
1002 Mandatory barriers should not be used to control SMP effects, since mandatory
1003 barriers unnecessarily impose overhead on UP systems. They may, however, be
1004 used to control MMIO effects on accesses through relaxed memory I/O windows.
1005 These are required even on non-SMP systems as they affect the order in which
1006 memory operations appear to a device by prohibiting both the compiler and the
1007 CPU from reordering them.
1010 There are some more advanced barrier functions:
1012 (*) set_mb(var, value)
1013 (*) set_wmb(var, value)
1015 These assign the value to the variable and then insert at least a write
1016 barrier after it, depending on the function. They aren't guaranteed to
1017 insert anything more than a compiler barrier in a UP compilation.
1020 (*) smp_mb__before_atomic_dec();
1021 (*) smp_mb__after_atomic_dec();
1022 (*) smp_mb__before_atomic_inc();
1023 (*) smp_mb__after_atomic_inc();
1025 These are for use with atomic add, subtract, increment and decrement
1026 functions that don't return a value, especially when used for reference
1027 counting. These functions do not imply memory barriers.
1029 As an example, consider a piece of code that marks an object as being dead
1030 and then decrements the object's reference count:
1032 obj->dead = 1;
1033 smp_mb__before_atomic_dec();
1034 atomic_dec(&obj->ref_count);
1036 This makes sure that the death mark on the object is perceived to be set
1037 *before* the reference counter is decremented.
1039 See Documentation/atomic_ops.txt for more information. See the "Atomic
1040 operations" subsection for information on where to use these.
1043 (*) smp_mb__before_clear_bit(void);
1044 (*) smp_mb__after_clear_bit(void);
1046 These are for use similar to the atomic inc/dec barriers. These are
1047 typically used for bitwise unlocking operations, so care must be taken as
1048 there are no implicit memory barriers here either.
1050 Consider implementing an unlock operation of some nature by clearing a
1051 locking bit. The clear_bit() would then need to be barriered like this:
1053 smp_mb__before_clear_bit();
1054 clear_bit( ... );
1056 This prevents memory operations before the clear leaking to after it. See
1057 the subsection on "Locking Functions" with reference to UNLOCK operation
1058 implications.
1060 See Documentation/atomic_ops.txt for more information. See the "Atomic
1061 operations" subsection for information on where to use these.
1064 MMIO WRITE BARRIER
1065 ------------------
1067 The Linux kernel also has a special barrier for use with memory-mapped I/O
1068 writes:
1070 mmiowb();
1072 This is a variation on the mandatory write barrier that causes writes to weakly
1073 ordered I/O regions to be partially ordered. Its effects may go beyond the
1074 CPU->Hardware interface and actually affect the hardware at some level.
1076 See the subsection "Locks vs I/O accesses" for more information.
1079 ===============================
1080 IMPLICIT KERNEL MEMORY BARRIERS
1081 ===============================
1083 Some of the other functions in the linux kernel imply memory barriers, amongst
1084 which are locking and scheduling functions.
1086 This specification is a _minimum_ guarantee; any particular architecture may
1087 provide more substantial guarantees, but these may not be relied upon outside
1088 of arch specific code.
1091 LOCKING FUNCTIONS
1092 -----------------
1094 The Linux kernel has a number of locking constructs:
1096 (*) spin locks
1097 (*) R/W spin locks
1098 (*) mutexes
1099 (*) semaphores
1100 (*) R/W semaphores
1101 (*) RCU
1103 In all cases there are variants on "LOCK" operations and "UNLOCK" operations
1104 for each construct. These operations all imply certain barriers:
1106 (1) LOCK operation implication:
1108 Memory operations issued after the LOCK will be completed after the LOCK
1109 operation has completed.
1111 Memory operations issued before the LOCK may be completed after the LOCK
1112 operation has completed.
1114 (2) UNLOCK operation implication:
1116 Memory operations issued before the UNLOCK will be completed before the
1117 UNLOCK operation has completed.
1119 Memory operations issued after the UNLOCK may be completed before the
1120 UNLOCK operation has completed.
1122 (3) LOCK vs LOCK implication:
1124 All LOCK operations issued before another LOCK operation will be completed
1125 before that LOCK operation.
1127 (4) LOCK vs UNLOCK implication:
1129 All LOCK operations issued before an UNLOCK operation will be completed
1130 before the UNLOCK operation.
1132 All UNLOCK operations issued before a LOCK operation will be completed
1133 before the LOCK operation.
1135 (5) Failed conditional LOCK implication:
1137 Certain variants of the LOCK operation may fail, either due to being
1138 unable to get the lock immediately, or due to receiving an unblocked
1139 signal whilst asleep waiting for the lock to become available. Failed
1140 locks do not imply any sort of barrier.
1142 Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is
1143 equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
1145 [!] Note: one of the consequence of LOCKs and UNLOCKs being only one-way
1146 barriers is that the effects instructions outside of a critical section may
1147 seep into the inside of the critical section.
1149 A LOCK followed by an UNLOCK may not be assumed to be full memory barrier
1150 because it is possible for an access preceding the LOCK to happen after the
1151 LOCK, and an access following the UNLOCK to happen before the UNLOCK, and the
1152 two accesses can themselves then cross:
1154 *A = a;
1155 LOCK
1156 UNLOCK
1157 *B = b;
1159 may occur as:
1161 LOCK, STORE *B, STORE *A, UNLOCK
1163 Locks and semaphores may not provide any guarantee of ordering on UP compiled
1164 systems, and so cannot be counted on in such a situation to actually achieve
1165 anything at all - especially with respect to I/O accesses - unless combined
1166 with interrupt disabling operations.
1168 See also the section on "Inter-CPU locking barrier effects".
1171 As an example, consider the following:
1173 *A = a;
1174 *B = b;
1175 LOCK
1176 *C = c;
1177 *D = d;
1178 UNLOCK
1179 *E = e;
1180 *F = f;
1182 The following sequence of events is acceptable:
1184 LOCK, {*F,*A}, *E, {*C,*D}, *B, UNLOCK
1186 [+] Note that {*F,*A} indicates a combined access.
1188 But none of the following are:
1190 {*F,*A}, *B, LOCK, *C, *D, UNLOCK, *E
1191 *A, *B, *C, LOCK, *D, UNLOCK, *E, *F
1192 *A, *B, LOCK, *C, UNLOCK, *D, *E, *F
1193 *B, LOCK, *C, *D, UNLOCK, {*F,*A}, *E
1197 INTERRUPT DISABLING FUNCTIONS
1198 -----------------------------
1200 Functions that disable interrupts (LOCK equivalent) and enable interrupts
1201 (UNLOCK equivalent) will act as compiler barriers only. So if memory or I/O
1202 barriers are required in such a situation, they must be provided from some
1203 other means.
1206 MISCELLANEOUS FUNCTIONS
1207 -----------------------
1209 Other functions that imply barriers:
1211 (*) schedule() and similar imply full memory barriers.
1214 =================================
1215 INTER-CPU LOCKING BARRIER EFFECTS
1216 =================================
1218 On SMP systems locking primitives give a more substantial form of barrier: one
1219 that does affect memory access ordering on other CPUs, within the context of
1220 conflict on any particular lock.
1223 LOCKS VS MEMORY ACCESSES
1224 ------------------------
1226 Consider the following: the system has a pair of spinlocks (M) and (Q), and
1227 three CPUs; then should the following sequence of events occur:
1229 CPU 1 CPU 2
1230 =============================== ===============================
1231 *A = a; *E = e;
1232 LOCK M LOCK Q
1233 *B = b; *F = f;
1234 *C = c; *G = g;
1235 UNLOCK M UNLOCK Q
1236 *D = d; *H = h;
1238 Then there is no guarantee as to what order CPU #3 will see the accesses to *A
1239 through *H occur in, other than the constraints imposed by the separate locks
1240 on the separate CPUs. It might, for example, see:
1242 *E, LOCK M, LOCK Q, *G, *C, *F, *A, *B, UNLOCK Q, *D, *H, UNLOCK M
1244 But it won't see any of:
1246 *B, *C or *D preceding LOCK M
1247 *A, *B or *C following UNLOCK M
1248 *F, *G or *H preceding LOCK Q
1249 *E, *F or *G following UNLOCK Q
1252 However, if the following occurs:
1254 CPU 1 CPU 2
1255 =============================== ===============================
1256 *A = a;
1257 LOCK M [1]
1258 *B = b;
1259 *C = c;
1260 UNLOCK M [1]
1261 *D = d; *E = e;
1262 LOCK M [2]
1263 *F = f;
1264 *G = g;
1265 UNLOCK M [2]
1266 *H = h;
1268 CPU #3 might see:
1270 *E, LOCK M [1], *C, *B, *A, UNLOCK M [1],
1271 LOCK M [2], *H, *F, *G, UNLOCK M [2], *D
1273 But assuming CPU #1 gets the lock first, it won't see any of:
1275 *B, *C, *D, *F, *G or *H preceding LOCK M [1]
1276 *A, *B or *C following UNLOCK M [1]
1277 *F, *G or *H preceding LOCK M [2]
1278 *A, *B, *C, *E, *F or *G following UNLOCK M [2]
1281 LOCKS VS I/O ACCESSES
1282 ---------------------
1284 Under certain circumstances (especially involving NUMA), I/O accesses within
1285 two spinlocked sections on two different CPUs may be seen as interleaved by the
1286 PCI bridge, because the PCI bridge does not necessarily participate in the
1287 cache-coherence protocol, and is therefore incapable of issuing the required
1288 read memory barriers.
1290 For example:
1292 CPU 1 CPU 2
1293 =============================== ===============================
1294 spin_lock(Q)
1295 writel(0, ADDR)
1296 writel(1, DATA);
1297 spin_unlock(Q);
1298 spin_lock(Q);
1299 writel(4, ADDR);
1300 writel(5, DATA);
1301 spin_unlock(Q);
1303 may be seen by the PCI bridge as follows:
1305 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
1307 which would probably cause the hardware to malfunction.
1310 What is necessary here is to intervene with an mmiowb() before dropping the
1311 spinlock, for example:
1313 CPU 1 CPU 2
1314 =============================== ===============================
1315 spin_lock(Q)
1316 writel(0, ADDR)
1317 writel(1, DATA);
1318 mmiowb();
1319 spin_unlock(Q);
1320 spin_lock(Q);
1321 writel(4, ADDR);
1322 writel(5, DATA);
1323 mmiowb();
1324 spin_unlock(Q);
1326 this will ensure that the two stores issued on CPU #1 appear at the PCI bridge
1327 before either of the stores issued on CPU #2.
1330 Furthermore, following a store by a load to the same device obviates the need
1331 for an mmiowb(), because the load forces the store to complete before the load
1332 is performed:
1334 CPU 1 CPU 2
1335 =============================== ===============================
1336 spin_lock(Q)
1337 writel(0, ADDR)
1338 a = readl(DATA);
1339 spin_unlock(Q);
1340 spin_lock(Q);
1341 writel(4, ADDR);
1342 b = readl(DATA);
1343 spin_unlock(Q);
1346 See Documentation/DocBook/deviceiobook.tmpl for more information.
1349 =================================
1350 WHERE ARE MEMORY BARRIERS NEEDED?
1351 =================================
1353 Under normal operation, memory operation reordering is generally not going to
1354 be a problem as a single-threaded linear piece of code will still appear to
1355 work correctly, even if it's in an SMP kernel. There are, however, three
1356 circumstances in which reordering definitely _could_ be a problem:
1358 (*) Interprocessor interaction.
1360 (*) Atomic operations.
1362 (*) Accessing devices (I/O).
1364 (*) Interrupts.
1367 INTERPROCESSOR INTERACTION
1368 --------------------------
1370 When there's a system with more than one processor, more than one CPU in the
1371 system may be working on the same data set at the same time. This can cause
1372 synchronisation problems, and the usual way of dealing with them is to use
1373 locks. Locks, however, are quite expensive, and so it may be preferable to
1374 operate without the use of a lock if at all possible. In such a case
1375 operations that affect both CPUs may have to be carefully ordered to prevent
1376 a malfunction.
1378 Consider, for example, the R/W semaphore slow path. Here a waiting process is
1379 queued on the semaphore, by virtue of it having a piece of its stack linked to
1380 the semaphore's list of waiting processes:
1382 struct rw_semaphore {
1383 ...
1384 spinlock_t lock;
1385 struct list_head waiters;
1386 };
1388 struct rwsem_waiter {
1389 struct list_head list;
1390 struct task_struct *task;
1391 };
1393 To wake up a particular waiter, the up_read() or up_write() functions have to:
1395 (1) read the next pointer from this waiter's record to know as to where the
1396 next waiter record is;
1398 (4) read the pointer to the waiter's task structure;
1400 (3) clear the task pointer to tell the waiter it has been given the semaphore;
1402 (4) call wake_up_process() on the task; and
1404 (5) release the reference held on the waiter's task struct.
1406 In otherwords, it has to perform this sequence of events:
1408 LOAD waiter->list.next;
1409 LOAD waiter->task;
1410 STORE waiter->task;
1411 CALL wakeup
1412 RELEASE task
1414 and if any of these steps occur out of order, then the whole thing may
1415 malfunction.
1417 Once it has queued itself and dropped the semaphore lock, the waiter does not
1418 get the lock again; it instead just waits for its task pointer to be cleared
1419 before proceeding. Since the record is on the waiter's stack, this means that
1420 if the task pointer is cleared _before_ the next pointer in the list is read,
1421 another CPU might start processing the waiter and might clobber the waiter's
1422 stack before the up*() function has a chance to read the next pointer.
1424 Consider then what might happen to the above sequence of events:
1426 CPU 1 CPU 2
1427 =============================== ===============================
1428 down_xxx()
1429 Queue waiter
1430 Sleep
1431 up_yyy()
1432 LOAD waiter->task;
1433 STORE waiter->task;
1434 Woken up by other event
1435 <preempt>
1436 Resume processing
1437 down_xxx() returns
1438 call foo()
1439 foo() clobbers *waiter
1440 </preempt>
1441 LOAD waiter->list.next;
1442 --- OOPS ---
1444 This could be dealt with using the semaphore lock, but then the down_xxx()
1445 function has to needlessly get the spinlock again after being woken up.
1447 The way to deal with this is to insert a general SMP memory barrier:
1449 LOAD waiter->list.next;
1450 LOAD waiter->task;
1451 smp_mb();
1452 STORE waiter->task;
1453 CALL wakeup
1454 RELEASE task
1456 In this case, the barrier makes a guarantee that all memory accesses before the
1457 barrier will appear to happen before all the memory accesses after the barrier
1458 with respect to the other CPUs on the system. It does _not_ guarantee that all
1459 the memory accesses before the barrier will be complete by the time the barrier
1460 instruction itself is complete.
1462 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
1463 compiler barrier, thus making sure the compiler emits the instructions in the
1464 right order without actually intervening in the CPU. Since there there's only
1465 one CPU, that CPU's dependency ordering logic will take care of everything
1466 else.
1469 ATOMIC OPERATIONS
1470 -----------------
1472 Whilst they are technically interprocessor interaction considerations, atomic
1473 operations are noted specially as some of them imply full memory barriers and
1474 some don't, but they're very heavily relied on as a group throughout the
1475 kernel.
1477 Any atomic operation that modifies some state in memory and returns information
1478 about the state (old or new) implies an SMP-conditional general memory barrier
1479 (smp_mb()) on each side of the actual operation. These include:
1481 xchg();
1482 cmpxchg();
1483 atomic_cmpxchg();
1484 atomic_inc_return();
1485 atomic_dec_return();
1486 atomic_add_return();
1487 atomic_sub_return();
1488 atomic_inc_and_test();
1489 atomic_dec_and_test();
1490 atomic_sub_and_test();
1491 atomic_add_negative();
1492 atomic_add_unless();
1493 test_and_set_bit();
1494 test_and_clear_bit();
1495 test_and_change_bit();
1497 These are used for such things as implementing LOCK-class and UNLOCK-class
1498 operations and adjusting reference counters towards object destruction, and as
1499 such the implicit memory barrier effects are necessary.
1502 The following operation are potential problems as they do _not_ imply memory
1503 barriers, but might be used for implementing such things as UNLOCK-class
1504 operations:
1506 atomic_set();
1507 set_bit();
1508 clear_bit();
1509 change_bit();
1511 With these the appropriate explicit memory barrier should be used if necessary
1512 (smp_mb__before_clear_bit() for instance).
1515 The following also do _not_ imply memory barriers, and so may require explicit
1516 memory barriers under some circumstances (smp_mb__before_atomic_dec() for
1517 instance)):
1519 atomic_add();
1520 atomic_sub();
1521 atomic_inc();
1522 atomic_dec();
1524 If they're used for statistics generation, then they probably don't need memory
1525 barriers, unless there's a coupling between statistical data.
1527 If they're used for reference counting on an object to control its lifetime,
1528 they probably don't need memory barriers because either the reference count
1529 will be adjusted inside a locked section, or the caller will already hold
1530 sufficient references to make the lock, and thus a memory barrier unnecessary.
1532 If they're used for constructing a lock of some description, then they probably
1533 do need memory barriers as a lock primitive generally has to do things in a
1534 specific order.
1537 Basically, each usage case has to be carefully considered as to whether memory
1538 barriers are needed or not.
1540 [!] Note that special memory barrier primitives are available for these
1541 situations because on some CPUs the atomic instructions used imply full memory
1542 barriers, and so barrier instructions are superfluous in conjunction with them,
1543 and in such cases the special barrier primitives will be no-ops.
1545 See Documentation/atomic_ops.txt for more information.
1548 ACCESSING DEVICES
1549 -----------------
1551 Many devices can be memory mapped, and so appear to the CPU as if they're just
1552 a set of memory locations. To control such a device, the driver usually has to
1553 make the right memory accesses in exactly the right order.
1555 However, having a clever CPU or a clever compiler creates a potential problem
1556 in that the carefully sequenced accesses in the driver code won't reach the
1557 device in the requisite order if the CPU or the compiler thinks it is more
1558 efficient to reorder, combine or merge accesses - something that would cause
1559 the device to malfunction.
1561 Inside of the Linux kernel, I/O should be done through the appropriate accessor
1562 routines - such as inb() or writel() - which know how to make such accesses
1563 appropriately sequential. Whilst this, for the most part, renders the explicit
1564 use of memory barriers unnecessary, there are a couple of situations where they
1565 might be needed:
1567 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
1568 so for _all_ general drivers locks should be used and mmiowb() must be
1569 issued prior to unlocking the critical section.
1571 (2) If the accessor functions are used to refer to an I/O memory window with
1572 relaxed memory access properties, then _mandatory_ memory barriers are
1573 required to enforce ordering.
1575 See Documentation/DocBook/deviceiobook.tmpl for more information.
1578 INTERRUPTS
1579 ----------
1581 A driver may be interrupted by its own interrupt service routine, and thus the
1582 two parts of the driver may interfere with each other's attempts to control or
1583 access the device.
1585 This may be alleviated - at least in part - by disabling local interrupts (a
1586 form of locking), such that the critical operations are all contained within
1587 the interrupt-disabled section in the driver. Whilst the driver's interrupt
1588 routine is executing, the driver's core may not run on the same CPU, and its
1589 interrupt is not permitted to happen again until the current interrupt has been
1590 handled, thus the interrupt handler does not need to lock against that.
1592 However, consider a driver that was talking to an ethernet card that sports an
1593 address register and a data register. If that driver's core talks to the card
1594 under interrupt-disablement and then the driver's interrupt handler is invoked:
1596 LOCAL IRQ DISABLE
1597 writew(ADDR, 3);
1598 writew(DATA, y);
1599 LOCAL IRQ ENABLE
1600 <interrupt>
1601 writew(ADDR, 4);
1602 q = readw(DATA);
1603 </interrupt>
1605 The store to the data register might happen after the second store to the
1606 address register if ordering rules are sufficiently relaxed:
1608 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
1611 If ordering rules are relaxed, it must be assumed that accesses done inside an
1612 interrupt disabled section may leak outside of it and may interleave with
1613 accesses performed in an interrupt - and vice versa - unless implicit or
1614 explicit barriers are used.
1616 Normally this won't be a problem because the I/O accesses done inside such
1617 sections will include synchronous load operations on strictly ordered I/O
1618 registers that form implicit I/O barriers. If this isn't sufficient then an
1619 mmiowb() may need to be used explicitly.
1622 A similar situation may occur between an interrupt routine and two routines
1623 running on separate CPUs that communicate with each other. If such a case is
1624 likely, then interrupt-disabling locks should be used to guarantee ordering.
1627 ==========================
1628 KERNEL I/O BARRIER EFFECTS
1629 ==========================
1631 When accessing I/O memory, drivers should use the appropriate accessor
1632 functions:
1634 (*) inX(), outX():
1636 These are intended to talk to I/O space rather than memory space, but
1637 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
1638 indeed have special I/O space access cycles and instructions, but many
1639 CPUs don't have such a concept.
1641 The PCI bus, amongst others, defines an I/O space concept - which on such
1642 CPUs as i386 and x86_64 cpus readily maps to the CPU's concept of I/O
1643 space. However, it may also mapped as a virtual I/O space in the CPU's
1644 memory map, particularly on those CPUs that don't support alternate
1645 I/O spaces.
1647 Accesses to this space may be fully synchronous (as on i386), but
1648 intermediary bridges (such as the PCI host bridge) may not fully honour
1649 that.
1651 They are guaranteed to be fully ordered with respect to each other.
1653 They are not guaranteed to be fully ordered with respect to other types of
1654 memory and I/O operation.
1656 (*) readX(), writeX():
1658 Whether these are guaranteed to be fully ordered and uncombined with
1659 respect to each other on the issuing CPU depends on the characteristics
1660 defined for the memory window through which they're accessing. On later
1661 i386 architecture machines, for example, this is controlled by way of the
1662 MTRR registers.
1664 Ordinarily, these will be guaranteed to be fully ordered and uncombined,,
1665 provided they're not accessing a prefetchable device.
1667 However, intermediary hardware (such as a PCI bridge) may indulge in
1668 deferral if it so wishes; to flush a store, a load from the same location
1669 is preferred[*], but a load from the same device or from configuration
1670 space should suffice for PCI.
1672 [*] NOTE! attempting to load from the same location as was written to may
1673 cause a malfunction - consider the 16550 Rx/Tx serial registers for
1674 example.
1676 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
1677 force stores to be ordered.
1679 Please refer to the PCI specification for more information on interactions
1680 between PCI transactions.
1682 (*) readX_relaxed()
1684 These are similar to readX(), but are not guaranteed to be ordered in any
1685 way. Be aware that there is no I/O read barrier available.
1687 (*) ioreadX(), iowriteX()
1689 These will perform as appropriate for the type of access they're actually
1690 doing, be it inX()/outX() or readX()/writeX().
1693 ========================================
1694 ASSUMED MINIMUM EXECUTION ORDERING MODEL
1695 ========================================
1697 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
1698 maintain the appearance of program causality with respect to itself. Some CPUs
1699 (such as i386 or x86_64) are more constrained than others (such as powerpc or
1700 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
1701 of arch-specific code.
1703 This means that it must be considered that the CPU will execute its instruction
1704 stream in any order it feels like - or even in parallel - provided that if an
1705 instruction in the stream depends on the an earlier instruction, then that
1706 earlier instruction must be sufficiently complete[*] before the later
1707 instruction may proceed; in other words: provided that the appearance of
1708 causality is maintained.
1710 [*] Some instructions have more than one effect - such as changing the
1711 condition codes, changing registers or changing memory - and different
1712 instructions may depend on different effects.
1714 A CPU may also discard any instruction sequence that winds up having no
1715 ultimate effect. For example, if two adjacent instructions both load an
1716 immediate value into the same register, the first may be discarded.
1719 Similarly, it has to be assumed that compiler might reorder the instruction
1720 stream in any way it sees fit, again provided the appearance of causality is
1721 maintained.
1724 ============================
1725 THE EFFECTS OF THE CPU CACHE
1726 ============================
1728 The way cached memory operations are perceived across the system is affected to
1729 a certain extent by the caches that lie between CPUs and memory, and by the
1730 memory coherence system that maintains the consistency of state in the system.
1732 As far as the way a CPU interacts with another part of the system through the
1733 caches goes, the memory system has to include the CPU's caches, and memory
1734 barriers for the most part act at the interface between the CPU and its cache
1735 (memory barriers logically act on the dotted line in the following diagram):
1737 <--- CPU ---> : <----------- Memory ----------->
1738 :
1739 +--------+ +--------+ : +--------+ +-----------+
1740 | | | | : | | | | +--------+
1741 | CPU | | Memory | : | CPU | | | | |
1742 | Core |--->| Access |----->| Cache |<-->| | | |
1743 | | | Queue | : | | | |--->| Memory |
1744 | | | | : | | | | | |
1745 +--------+ +--------+ : +--------+ | | | |
1746 : | Cache | +--------+
1747 : | Coherency |
1748 : | Mechanism | +--------+
1749 +--------+ +--------+ : +--------+ | | | |
1750 | | | | : | | | | | |
1751 | CPU | | Memory | : | CPU | | |--->| Device |
1752 | Core |--->| Access |----->| Cache |<-->| | | |
1753 | | | Queue | : | | | | | |
1754 | | | | : | | | | +--------+
1755 +--------+ +--------+ : +--------+ +-----------+
1756 :
1757 :
1759 Although any particular load or store may not actually appear outside of the
1760 CPU that issued it since it may have been satisfied within the CPU's own cache,
1761 it will still appear as if the full memory access had taken place as far as the
1762 other CPUs are concerned since the cache coherency mechanisms will migrate the
1763 cacheline over to the accessing CPU and propagate the effects upon conflict.
1765 The CPU core may execute instructions in any order it deems fit, provided the
1766 expected program causality appears to be maintained. Some of the instructions
1767 generate load and store operations which then go into the queue of memory
1768 accesses to be performed. The core may place these in the queue in any order
1769 it wishes, and continue execution until it is forced to wait for an instruction
1770 to complete.
1772 What memory barriers are concerned with is controlling the order in which
1773 accesses cross from the CPU side of things to the memory side of things, and
1774 the order in which the effects are perceived to happen by the other observers
1775 in the system.
1777 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
1778 their own loads and stores as if they had happened in program order.
1780 [!] MMIO or other device accesses may bypass the cache system. This depends on
1781 the properties of the memory window through which devices are accessed and/or
1782 the use of any special device communication instructions the CPU may have.
1785 CACHE COHERENCY
1786 ---------------
1788 Life isn't quite as simple as it may appear above, however: for while the
1789 caches are expected to be coherent, there's no guarantee that that coherency
1790 will be ordered. This means that whilst changes made on one CPU will
1791 eventually become visible on all CPUs, there's no guarantee that they will
1792 become apparent in the same order on those other CPUs.
1795 Consider dealing with a system that has pair of CPUs (1 & 2), each of which has
1796 a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
1798 :
1799 : +--------+
1800 : +---------+ | |
1801 +--------+ : +--->| Cache A |<------->| |
1802 | | : | +---------+ | |
1803 | CPU 1 |<---+ | |
1804 | | : | +---------+ | |
1805 +--------+ : +--->| Cache B |<------->| |
1806 : +---------+ | |
1807 : | Memory |
1808 : +---------+ | System |
1809 +--------+ : +--->| Cache C |<------->| |
1810 | | : | +---------+ | |
1811 | CPU 2 |<---+ | |
1812 | | : | +---------+ | |
1813 +--------+ : +--->| Cache D |<------->| |
1814 : +---------+ | |
1815 : +--------+
1816 :
1818 Imagine the system has the following properties:
1820 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
1821 resident in memory;
1823 (*) an even-numbered cache line may be in cache B, cache D or it may still be
1824 resident in memory;
1826 (*) whilst the CPU core is interrogating one cache, the other cache may be
1827 making use of the bus to access the rest of the system - perhaps to
1828 displace a dirty cacheline or to do a speculative load;
1830 (*) each cache has a queue of operations that need to be applied to that cache
1831 to maintain coherency with the rest of the system;
1833 (*) the coherency queue is not flushed by normal loads to lines already
1834 present in the cache, even though the contents of the queue may
1835 potentially effect those loads.
1837 Imagine, then, that two writes are made on the first CPU, with a write barrier
1838 between them to guarantee that they will appear to reach that CPU's caches in
1839 the requisite order:
1841 CPU 1 CPU 2 COMMENT
1842 =============== =============== =======================================
1843 u == 0, v == 1 and p == &u, q == &u
1844 v = 2;
1845 smp_wmb(); Make sure change to v visible before
1846 change to p
1847 <A:modify v=2> v is now in cache A exclusively
1848 p = &v;
1849 <B:modify p=&v> p is now in cache B exclusively
1851 The write memory barrier forces the other CPUs in the system to perceive that
1852 the local CPU's caches have apparently been updated in the correct order. But
1853 now imagine that the second CPU that wants to read those values:
1855 CPU 1 CPU 2 COMMENT
1856 =============== =============== =======================================
1857 ...
1858 q = p;
1859 x = *q;
1861 The above pair of reads may then fail to happen in expected order, as the
1862 cacheline holding p may get updated in one of the second CPU's caches whilst
1863 the update to the cacheline holding v is delayed in the other of the second
1864 CPU's caches by some other cache event:
1866 CPU 1 CPU 2 COMMENT
1867 =============== =============== =======================================
1868 u == 0, v == 1 and p == &u, q == &u
1869 v = 2;
1870 smp_wmb();
1871 <A:modify v=2> <C:busy>
1872 <C:queue v=2>
1873 p = &v; q = p;
1874 <D:request p>
1875 <B:modify p=&v> <D:commit p=&v>
1876 <D:read p>
1877 x = *q;
1878 <C:read *q> Reads from v before v updated in cache
1879 <C:unbusy>
1880 <C:commit v=2>
1882 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
1883 no guarantee that, without intervention, the order of update will be the same
1884 as that committed on CPU 1.
1887 To intervene, we need to interpolate a data dependency barrier or a read
1888 barrier between the loads. This will force the cache to commit its coherency
1889 queue before processing any further requests:
1891 CPU 1 CPU 2 COMMENT
1892 =============== =============== =======================================
1893 u == 0, v == 1 and p == &u, q == &u
1894 v = 2;
1895 smp_wmb();
1896 <A:modify v=2> <C:busy>
1897 <C:queue v=2>
1898 p = &b; q = p;
1899 <D:request p>
1900 <B:modify p=&v> <D:commit p=&v>
1901 <D:read p>
1902 smp_read_barrier_depends()
1903 <C:unbusy>
1904 <C:commit v=2>
1905 x = *q;
1906 <C:read *q> Reads from v after v updated in cache
1909 This sort of problem can be encountered on DEC Alpha processors as they have a
1910 split cache that improves performance by making better use of the data bus.
1911 Whilst most CPUs do imply a data dependency barrier on the read when a memory
1912 access depends on a read, not all do, so it may not be relied on.
1914 Other CPUs may also have split caches, but must coordinate between the various
1915 cachelets for normal memory accesss. The semantics of the Alpha removes the
1916 need for coordination in absence of memory barriers.
1919 CACHE COHERENCY VS DMA
1920 ----------------------
1922 Not all systems maintain cache coherency with respect to devices doing DMA. In
1923 such cases, a device attempting DMA may obtain stale data from RAM because
1924 dirty cache lines may be resident in the caches of various CPUs, and may not
1925 have been written back to RAM yet. To deal with this, the appropriate part of
1926 the kernel must flush the overlapping bits of cache on each CPU (and maybe
1927 invalidate them as well).
1929 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
1930 cache lines being written back to RAM from a CPU's cache after the device has
1931 installed its own data, or cache lines simply present in a CPUs cache may
1932 simply obscure the fact that RAM has been updated, until at such time as the
1933 cacheline is discarded from the CPU's cache and reloaded. To deal with this,
1934 the appropriate part of the kernel must invalidate the overlapping bits of the
1935 cache on each CPU.
1937 See Documentation/cachetlb.txt for more information on cache management.
1940 CACHE COHERENCY VS MMIO
1941 -----------------------
1943 Memory mapped I/O usually takes place through memory locations that are part of
1944 a window in the CPU's memory space that have different properties assigned than
1945 the usual RAM directed window.
1947 Amongst these properties is usually the fact that such accesses bypass the
1948 caching entirely and go directly to the device buses. This means MMIO accesses
1949 may, in effect, overtake accesses to cached memory that were emitted earlier.
1950 A memory barrier isn't sufficient in such a case, but rather the cache must be
1951 flushed between the cached memory write and the MMIO access if the two are in
1952 any way dependent.
1955 =========================
1956 THE THINGS CPUS GET UP TO
1957 =========================
1959 A programmer might take it for granted that the CPU will perform memory
1960 operations in exactly the order specified, so that if a CPU is, for example,
1961 given the following piece of code to execute:
1963 a = *A;
1964 *B = b;
1965 c = *C;
1966 d = *D;
1967 *E = e;
1969 They would then expect that the CPU will complete the memory operation for each
1970 instruction before moving on to the next one, leading to a definite sequence of
1971 operations as seen by external observers in the system:
1973 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
1976 Reality is, of course, much messier. With many CPUs and compilers, the above
1977 assumption doesn't hold because:
1979 (*) loads are more likely to need to be completed immediately to permit
1980 execution progress, whereas stores can often be deferred without a
1981 problem;
1983 (*) loads may be done speculatively, and the result discarded should it prove
1984 to have been unnecessary;
1986 (*) loads may be done speculatively, leading to the result having being
1987 fetched at the wrong time in the expected sequence of events;
1989 (*) the order of the memory accesses may be rearranged to promote better use
1990 of the CPU buses and caches;
1992 (*) loads and stores may be combined to improve performance when talking to
1993 memory or I/O hardware that can do batched accesses of adjacent locations,
1994 thus cutting down on transaction setup costs (memory and PCI devices may
1995 both be able to do this); and
1997 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
1998 mechanisms may alleviate this - once the store has actually hit the cache
1999 - there's no guarantee that the coherency management will be propagated in
2000 order to other CPUs.
2002 So what another CPU, say, might actually observe from the above piece of code
2003 is:
2005 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2007 (Where "LOAD {*C,*D}" is a combined load)
2010 However, it is guaranteed that a CPU will be self-consistent: it will see its
2011 _own_ accesses appear to be correctly ordered, without the need for a memory
2012 barrier. For instance with the following code:
2014 U = *A;
2015 *A = V;
2016 *A = W;
2017 X = *A;
2018 *A = Y;
2019 Z = *A;
2021 and assuming no intervention by an external influence, it can be assumed that
2022 the final result will appear to be:
2024 U == the original value of *A
2025 X == W
2026 Z == Y
2027 *A == Y
2029 The code above may cause the CPU to generate the full sequence of memory
2030 accesses:
2032 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2034 in that order, but, without intervention, the sequence may have almost any
2035 combination of elements combined or discarded, provided the program's view of
2036 the world remains consistent.
2038 The compiler may also combine, discard or defer elements of the sequence before
2039 the CPU even sees them.
2041 For instance:
2043 *A = V;
2044 *A = W;
2046 may be reduced to:
2048 *A = W;
2050 since, without a write barrier, it can be assumed that the effect of the
2051 storage of V to *A is lost. Similarly:
2053 *A = Y;
2054 Z = *A;
2056 may, without a memory barrier, be reduced to:
2058 *A = Y;
2059 Z = Y;
2061 and the LOAD operation never appear outside of the CPU.
2064 AND THEN THERE'S THE ALPHA
2065 --------------------------
2067 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2068 some versions of the Alpha CPU have a split data cache, permitting them to have
2069 two semantically related cache lines updating at separate times. This is where
2070 the data dependency barrier really becomes necessary as this synchronises both
2071 caches with the memory coherence system, thus making it seem like pointer
2072 changes vs new data occur in the right order.
2074 The Alpha defines the Linux's kernel's memory barrier model.
2076 See the subsection on "Cache Coherency" above.
2079 ==========
2080 REFERENCES
2081 ==========
2083 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2084 Digital Press)
2085 Chapter 5.2: Physical Address Space Characteristics
2086 Chapter 5.4: Caches and Write Buffers
2087 Chapter 5.5: Data Sharing
2088 Chapter 5.6: Read/Write Ordering
2090 AMD64 Architecture Programmer's Manual Volume 2: System Programming
2091 Chapter 7.1: Memory-Access Ordering
2092 Chapter 7.4: Buffering and Combining Memory Writes
2094 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2095 System Programming Guide
2096 Chapter 7.1: Locked Atomic Operations
2097 Chapter 7.2: Memory Ordering
2098 Chapter 7.4: Serializing Instructions
2100 The SPARC Architecture Manual, Version 9
2101 Chapter 8: Memory Models
2102 Appendix D: Formal Specification of the Memory Models
2103 Appendix J: Programming with the Memory Models
2105 UltraSPARC Programmer Reference Manual
2106 Chapter 5: Memory Accesses and Cacheability
2107 Chapter 15: Sparc-V9 Memory Models
2109 UltraSPARC III Cu User's Manual
2110 Chapter 9: Memory Models
2112 UltraSPARC IIIi Processor User's Manual
2113 Chapter 8: Memory Models
2115 UltraSPARC Architecture 2005
2116 Chapter 9: Memory
2117 Appendix D: Formal Specifications of the Memory Models
2119 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
2120 Chapter 8: Memory Models
2121 Appendix F: Caches and Cache Coherency
2123 Solaris Internals, Core Kernel Architecture, p63-68:
2124 Chapter 3.3: Hardware Considerations for Locks and
2125 Synchronization
2127 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
2128 for Kernel Programmers:
2129 Chapter 13: Other Memory Models
2131 Intel Itanium Architecture Software Developer's Manual: Volume 1:
2132 Section 2.6: Speculation
2133 Section 4.4: Memory Access