arch/mips/ddb5xxx/ddb5477/irq.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  *  arch/mips/ddb5xxx/ddb5477/irq.c
   6  *     The irq setup and misc routines for DDB5476.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/config.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/types.h>
  18 #include <linux/ptrace.h>
  19
  20 #include <asm/i8259.h>
  21 #include <asm/system.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/debug.h>
  24 #include <asm/addrspace.h>
  25 #include <asm/bootinfo.h>
  26
  27 #include <asm/ddb5xxx/ddb5xxx.h>
  28
  29
  30 /*
  31  * IRQ mapping
  32  *
  33  *  0-7: 8 CPU interrupts
  34  *      0 -     software interrupt 0
  35  *      1 -     software interrupt 1
  36  *      2 -     most Vrc5477 interrupts are routed to this pin
  37  *      3 -     (optional) some other interrupts routed to this pin for debugg
  38  *      4 -     not used
  39  *      5 -     not used
  40  *      6 -     not used
  41  *      7 -     cpu timer (used by default)
  42  *
  43  *  8-39: 32 Vrc5477 interrupt sources
  44  *      (refer to the Vrc5477 manual)
  45  */
  46
  47 #define PCI0                    DDB_INTPPES0
  48 #define PCI1                    DDB_INTPPES1
  49
  50 #define ACTIVE_LOW              1
  51 #define ACTIVE_HIGH             0
  52
  53 #define LEVEL_SENSE             2
  54 #define EDGE_TRIGGER            0
  55
  56 #define INTA                    0
  57 #define INTB                    1
  58 #define INTC                    2
  59 #define INTD                    3
  60 #define INTE                    4
  61
  62 static inline void
  63 set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
  64 {
  65         u32 reg_value;
  66         u32 reg_bitmask;
  67
  68         reg_value = ddb_in32(pci);
  69         reg_bitmask = 0x3 << (intn * 2);
  70
  71         reg_value &= ~reg_bitmask;
  72         reg_value |= (active | trigger) << (intn * 2);
  73         ddb_out32(pci, reg_value);
  74 }
  75
  76 extern void vrc5477_irq_init(u32 base);
  77 extern void mips_cpu_irq_init(u32 base);
  78 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
  79 static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
  80
  81 void __init arch_init_irq(void)
  82 {
  83         /* by default, we disable all interrupts and route all vrc5477
  84          * interrupts to pin 0 (irq 2) */
  85         ddb_out32(DDB_INTCTRL0, 0);
  86         ddb_out32(DDB_INTCTRL1, 0);
  87         ddb_out32(DDB_INTCTRL2, 0);
  88         ddb_out32(DDB_INTCTRL3, 0);
  89
  90         clear_c0_status(0xff00);
  91         set_c0_status(0x0400);
  92
  93         /* setup PCI interrupt attributes */
  94         set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
  95         set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
  96         if (mips_machtype == MACH_NEC_ROCKHOPPERII)
  97                 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
  98         else
  99                 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
 100         set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
 101         set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
 102
 103         set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
 104         set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
 105         set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
 106         set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
 107         set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
 108
 109         /*
 110          * for debugging purpose, we enable several error interrupts
 111          * and route them to pin 1. (IP3)
 112          */
 113         /* cpu parity check - 0 */
 114         ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
 115         /* cpu no-target decode - 1 */
 116         ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
 117         /* local bus read time-out - 7 */
 118         ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
 119         /* PCI SERR# - 14 */
 120         ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
 121         /* PCI internal error - 15 */
 122         ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
 123         /* IOPCI SERR# - 30 */
 124         ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
 125         /* IOPCI internal error - 31 */
 126         ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
 127
 128         /* init all controllers */
 129         init_i8259_irqs();
 130         mips_cpu_irq_init(CPU_IRQ_BASE);
 131         vrc5477_irq_init(VRC5477_IRQ_BASE);
 132
 133
 134         /* setup cascade interrupts */
 135         setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
 136         setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
 137 }
 138
 139 u8 i8259_interrupt_ack(void)
 140 {
 141         u8 irq;
 142         u32 reg;
 143
 144         /* Set window 0 for interrupt acknowledge */
 145         reg = ddb_in32(DDB_PCIINIT10);
 146
 147         ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
 148         irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
 149         ddb_out32(DDB_PCIINIT10, reg);
 150
 151         /* i8259.c set the base vector to be 0x0 */
 152         return irq + I8259_IRQ_BASE;
 153 }
 154 /*
 155  * the first level int-handler will jump here if it is a vrc5477 irq
 156  */
 157 #define NUM_5477_IRQS   32
 158 static void
 159 vrc5477_irq_dispatch(struct pt_regs *regs)
 160 {
 161         u32 intStatus;
 162         u32 bitmask;
 163         u32 i;
 164
 165         db_assert(ddb_in32(DDB_INT2STAT) == 0);
 166         db_assert(ddb_in32(DDB_INT3STAT) == 0);
 167         db_assert(ddb_in32(DDB_INT4STAT) == 0);
 168         db_assert(ddb_in32(DDB_NMISTAT) == 0);
 169
 170         if (ddb_in32(DDB_INT1STAT) != 0) {
 171 #if defined(CONFIG_RUNTIME_DEBUG)
 172                 vrc5477_show_int_regs();
 173 #endif
 174                 panic("error interrupt has happened.");
 175         }
 176
 177         intStatus = ddb_in32(DDB_INT0STAT);
 178
 179         if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
 180                 /* check for i8259 interrupts */
 181                 if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
 182                         int i8259_irq = i8259_interrupt_ack();
 183                         do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
 184                         return;
 185                 }
 186         }
 187
 188         for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
 189                 /* do we need to "and" with the int mask? */
 190                 if (intStatus & bitmask) {
 191                         do_IRQ(VRC5477_IRQ_BASE + i, regs);
 192                         return;
 193                 }
 194         }
 195 }
 196
 197 #define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
 198
 199 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 200 {
 201         unsigned int pending = read_c0_cause() & read_c0_status();
 202
 203         if (pending & STATUSF_IP7)
 204                 do_IRQ(CPU_IRQ_BASE + 7, regs);
 205         else if (pending & VR5477INTS)
 206                 vrc5477_irq_dispatch(regs);
 207         else if (pending & STATUSF_IP0)
 208                 do_IRQ(CPU_IRQ_BASE, regs);
 209         else if (pending & STATUSF_IP1)
 210                 do_IRQ(CPU_IRQ_BASE + 1, regs);
 211         else
 212                 spurious_interrupt(regs);
 213 }