arch/mips/kernel/traps.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
   7  * Copyright (C) 1995, 1996 Paul M. Antoine
   8  * Copyright (C) 1998 Ulf Carlsson
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 2000, 01 MIPS Technologies, Inc.
  12  * Copyright (C) 2002, 2003, 2004, 2005  Maciej W. Rozycki
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/mm.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/smp_lock.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/kallsyms.h>
  23 #include <linux/bootmem.h>
  24
  25 #include <asm/bootinfo.h>
  26 #include <asm/branch.h>
  27 #include <asm/break.h>
  28 #include <asm/cpu.h>
  29 #include <asm/dsp.h>
  30 #include <asm/fpu.h>
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/module.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/ptrace.h>
  36 #include <asm/sections.h>
  37 #include <asm/system.h>
  38 #include <asm/tlbdebug.h>
  39 #include <asm/traps.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/mmu_context.h>
  42 #include <asm/watch.h>
  43 #include <asm/types.h>
  44
  45 extern asmlinkage void handle_int(void);
  46 extern asmlinkage void handle_tlbm(void);
  47 extern asmlinkage void handle_tlbl(void);
  48 extern asmlinkage void handle_tlbs(void);
  49 extern asmlinkage void handle_adel(void);
  50 extern asmlinkage void handle_ades(void);
  51 extern asmlinkage void handle_ibe(void);
  52 extern asmlinkage void handle_dbe(void);
  53 extern asmlinkage void handle_sys(void);
  54 extern asmlinkage void handle_bp(void);
  55 extern asmlinkage void handle_ri(void);
  56 extern asmlinkage void handle_cpu(void);
  57 extern asmlinkage void handle_ov(void);
  58 extern asmlinkage void handle_tr(void);
  59 extern asmlinkage void handle_fpe(void);
  60 extern asmlinkage void handle_mdmx(void);
  61 extern asmlinkage void handle_watch(void);
  62 extern asmlinkage void handle_mt(void);
  63 extern asmlinkage void handle_dsp(void);
  64 extern asmlinkage void handle_mcheck(void);
  65 extern asmlinkage void handle_reserved(void);
  66
  67 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
  68         struct mips_fpu_soft_struct *ctx);
  69
  70 void (*board_be_init)(void);
  71 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  72 void (*board_nmi_handler_setup)(void);
  73 void (*board_ejtag_handler_setup)(void);
  74 void (*board_bind_eic_interrupt)(int irq, int regset);
  75
  76 /*
  77  * These constant is for searching for possible module text segments.
  78  * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
  79  */
  80 #define MODULE_RANGE (8*1024*1024)
  81
  82 /*
  83  * This routine abuses get_user()/put_user() to reference pointers
  84  * with at least a bit of error checking ...
  85  */
  86 void show_stack(struct task_struct *task, unsigned long *sp)
  87 {
  88         const int field = 2 * sizeof(unsigned long);
  89         long stackdata;
  90         int i;
  91
  92         if (!sp) {
  93                 if (task && task != current)
  94                         sp = (unsigned long *) task->thread.reg29;
  95                 else
  96                         sp = (unsigned long *) &sp;
  97         }
  98
  99         printk("Stack :");
 100         i = 0;
 101         while ((unsigned long) sp & (PAGE_SIZE - 1)) {
 102                 if (i && ((i % (64 / field)) == 0))
 103                         printk("\n       ");
 104                 if (i > 39) {
 105                         printk(" ...");
 106                         break;
 107                 }
 108
 109                 if (__get_user(stackdata, sp++)) {
 110                         printk(" (Bad stack address)");
 111                         break;
 112                 }
 113
 114                 printk(" %0*lx", field, stackdata);
 115                 i++;
 116         }
 117         printk("\n");
 118 }
 119
 120 void show_trace(struct task_struct *task, unsigned long *stack)
 121 {
 122         const int field = 2 * sizeof(unsigned long);
 123         unsigned long addr;
 124
 125         if (!stack) {
 126                 if (task && task != current)
 127                         stack = (unsigned long *) task->thread.reg29;
 128                 else
 129                         stack = (unsigned long *) &stack;
 130         }
 131
 132         printk("Call Trace:");
 133 #ifdef CONFIG_KALLSYMS
 134         printk("\n");
 135 #endif
 136         while (!kstack_end(stack)) {
 137                 addr = *stack++;
 138                 if (__kernel_text_address(addr)) {
 139                         printk(" [<%0*lx>] ", field, addr);
 140                         print_symbol("%s\n", addr);
 141                 }
 142         }
 143         printk("\n");
 144 }
 145
 146 /*
 147  * The architecture-independent dump_stack generator
 148  */
 149 void dump_stack(void)
 150 {
 151         unsigned long stack;
 152
 153         show_trace(current, &stack);
 154 }
 155
 156 EXPORT_SYMBOL(dump_stack);
 157
 158 void show_code(unsigned int *pc)
 159 {
 160         long i;
 161
 162         printk("\nCode:");
 163
 164         for(i = -3 ; i < 6 ; i++) {
 165                 unsigned int insn;
 166                 if (__get_user(insn, pc + i)) {
 167                         printk(" (Bad address in epc)\n");
 168                         break;
 169                 }
 170                 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
 171         }
 172 }
 173
 174 void show_regs(struct pt_regs *regs)
 175 {
 176         const int field = 2 * sizeof(unsigned long);
 177         unsigned int cause = regs->cp0_cause;
 178         int i;
 179
 180         printk("Cpu %d\n", smp_processor_id());
 181
 182         /*
 183          * Saved main processor registers
 184          */
 185         for (i = 0; i < 32; ) {
 186                 if ((i % 4) == 0)
 187                         printk("$%2d   :", i);
 188                 if (i == 0)
 189                         printk(" %0*lx", field, 0UL);
 190                 else if (i == 26 || i == 27)
 191                         printk(" %*s", field, "");
 192                 else
 193                         printk(" %0*lx", field, regs->regs[i]);
 194
 195                 i++;
 196                 if ((i % 4) == 0)
 197                         printk("\n");
 198         }
 199
 200         printk("Hi    : %0*lx\n", field, regs->hi);
 201         printk("Lo    : %0*lx\n", field, regs->lo);
 202
 203         /*
 204          * Saved cp0 registers
 205          */
 206         printk("epc   : %0*lx ", field, regs->cp0_epc);
 207         print_symbol("%s ", regs->cp0_epc);
 208         printk("    %s\n", print_tainted());
 209         printk("ra    : %0*lx ", field, regs->regs[31]);
 210         print_symbol("%s\n", regs->regs[31]);
 211
 212         printk("Status: %08x    ", (uint32_t) regs->cp0_status);
 213
 214         if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
 215                 if (regs->cp0_status & ST0_KUO)
 216                         printk("KUo ");
 217                 if (regs->cp0_status & ST0_IEO)
 218                         printk("IEo ");
 219                 if (regs->cp0_status & ST0_KUP)
 220                         printk("KUp ");
 221                 if (regs->cp0_status & ST0_IEP)
 222                         printk("IEp ");
 223                 if (regs->cp0_status & ST0_KUC)
 224                         printk("KUc ");
 225                 if (regs->cp0_status & ST0_IEC)
 226                         printk("IEc ");
 227         } else {
 228                 if (regs->cp0_status & ST0_KX)
 229                         printk("KX ");
 230                 if (regs->cp0_status & ST0_SX)
 231                         printk("SX ");
 232                 if (regs->cp0_status & ST0_UX)
 233                         printk("UX ");
 234                 switch (regs->cp0_status & ST0_KSU) {
 235                 case KSU_USER:
 236                         printk("USER ");
 237                         break;
 238                 case KSU_SUPERVISOR:
 239                         printk("SUPERVISOR ");
 240                         break;
 241                 case KSU_KERNEL:
 242                         printk("KERNEL ");
 243                         break;
 244                 default:
 245                         printk("BAD_MODE ");
 246                         break;
 247                 }
 248                 if (regs->cp0_status & ST0_ERL)
 249                         printk("ERL ");
 250                 if (regs->cp0_status & ST0_EXL)
 251                         printk("EXL ");
 252                 if (regs->cp0_status & ST0_IE)
 253                         printk("IE ");
 254         }
 255         printk("\n");
 256
 257         printk("Cause : %08x\n", cause);
 258
 259         cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 260         if (1 <= cause && cause <= 5)
 261                 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
 262
 263         printk("PrId  : %08x\n", read_c0_prid());
 264 }
 265
 266 void show_registers(struct pt_regs *regs)
 267 {
 268         show_regs(regs);
 269         print_modules();
 270         printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
 271                 current->comm, current->pid, current_thread_info(), current);
 272         show_stack(current, (long *) regs->regs[29]);
 273         show_trace(current, (long *) regs->regs[29]);
 274         show_code((unsigned int *) regs->cp0_epc);
 275         printk("\n");
 276 }
 277
 278 static DEFINE_SPINLOCK(die_lock);
 279
 280 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
 281 {
 282         static int die_counter;
 283 #ifdef CONFIG_MIPS_MT_SMTC
 284         unsigned long dvpret = dvpe();
 285 #endif /* CONFIG_MIPS_MT_SMTC */
 286
 287         console_verbose();
 288         spin_lock_irq(&die_lock);
 289         bust_spinlocks(1);
 290 #ifdef CONFIG_MIPS_MT_SMTC
 291         mips_mt_regdump(dvpret);
 292 #endif /* CONFIG_MIPS_MT_SMTC */
 293         printk("%s[#%d]:\n", str, ++die_counter);
 294         show_registers(regs);
 295         spin_unlock_irq(&die_lock);
 296         do_exit(SIGSEGV);
 297 }
 298
 299 extern const struct exception_table_entry __start___dbe_table[];
 300 extern const struct exception_table_entry __stop___dbe_table[];
 301
 302 void __declare_dbe_table(void)
 303 {
 304         __asm__ __volatile__(
 305         ".section\t__dbe_table,\"a\"\n\t"
 306         ".previous"
 307         );
 308 }
 309
 310 /* Given an address, look for it in the exception tables. */
 311 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
 312 {
 313         const struct exception_table_entry *e;
 314
 315         e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
 316         if (!e)
 317                 e = search_module_dbetables(addr);
 318         return e;
 319 }
 320
 321 asmlinkage void do_be(struct pt_regs *regs)
 322 {
 323         const int field = 2 * sizeof(unsigned long);
 324         const struct exception_table_entry *fixup = NULL;
 325         int data = regs->cp0_cause & 4;
 326         int action = MIPS_BE_FATAL;
 327
 328         /* XXX For now.  Fixme, this searches the wrong table ...  */
 329         if (data && !user_mode(regs))
 330                 fixup = search_dbe_tables(exception_epc(regs));
 331
 332         if (fixup)
 333                 action = MIPS_BE_FIXUP;
 334
 335         if (board_be_handler)
 336                 action = board_be_handler(regs, fixup != 0);
 337
 338         switch (action) {
 339         case MIPS_BE_DISCARD:
 340                 return;
 341         case MIPS_BE_FIXUP:
 342                 if (fixup) {
 343                         regs->cp0_epc = fixup->nextinsn;
 344                         return;
 345                 }
 346                 break;
 347         default:
 348                 break;
 349         }
 350
 351         /*
 352          * Assume it would be too dangerous to continue ...
 353          */
 354         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
 355                data ? "Data" : "Instruction",
 356                field, regs->cp0_epc, field, regs->regs[31]);
 357         die_if_kernel("Oops", regs);
 358         force_sig(SIGBUS, current);
 359 }
 360
 361 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
 362 {
 363         unsigned int __user *epc;
 364
 365         epc = (unsigned int __user *) regs->cp0_epc +
 366               ((regs->cp0_cause & CAUSEF_BD) != 0);
 367         if (!get_user(*opcode, epc))
 368                 return 0;
 369
 370         force_sig(SIGSEGV, current);
 371         return 1;
 372 }
 373
 374 /*
 375  * ll/sc emulation
 376  */
 377
 378 #define OPCODE 0xfc000000
 379 #define BASE   0x03e00000
 380 #define RT     0x001f0000
 381 #define OFFSET 0x0000ffff
 382 #define LL     0xc0000000
 383 #define SC     0xe0000000
 384 #define SPEC3  0x7c000000
 385 #define RD     0x0000f800
 386 #define FUNC   0x0000003f
 387 #define RDHWR  0x0000003b
 388
 389 /*
 390  * The ll_bit is cleared by r*_switch.S
 391  */
 392
 393 unsigned long ll_bit;
 394
 395 static struct task_struct *ll_task = NULL;
 396
 397 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
 398 {
 399         unsigned long value, __user *vaddr;
 400         long offset;
 401         int signal = 0;
 402
 403         /*
 404          * analyse the ll instruction that just caused a ri exception
 405          * and put the referenced address to addr.
 406          */
 407
 408         /* sign extend offset */
 409         offset = opcode & OFFSET;
 410         offset <<= 16;
 411         offset >>= 16;
 412
 413         vaddr = (unsigned long __user *)
 414                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 415
 416         if ((unsigned long)vaddr & 3) {
 417                 signal = SIGBUS;
 418                 goto sig;
 419         }
 420         if (get_user(value, vaddr)) {
 421                 signal = SIGSEGV;
 422                 goto sig;
 423         }
 424
 425         preempt_disable();
 426
 427         if (ll_task == NULL || ll_task == current) {
 428                 ll_bit = 1;
 429         } else {
 430                 ll_bit = 0;
 431         }
 432         ll_task = current;
 433
 434         preempt_enable();
 435
 436         compute_return_epc(regs);
 437
 438         regs->regs[(opcode & RT) >> 16] = value;
 439
 440         return;
 441
 442 sig:
 443         force_sig(signal, current);
 444 }
 445
 446 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
 447 {
 448         unsigned long __user *vaddr;
 449         unsigned long reg;
 450         long offset;
 451         int signal = 0;
 452
 453         /*
 454          * analyse the sc instruction that just caused a ri exception
 455          * and put the referenced address to addr.
 456          */
 457
 458         /* sign extend offset */
 459         offset = opcode & OFFSET;
 460         offset <<= 16;
 461         offset >>= 16;
 462
 463         vaddr = (unsigned long __user *)
 464                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 465         reg = (opcode & RT) >> 16;
 466
 467         if ((unsigned long)vaddr & 3) {
 468                 signal = SIGBUS;
 469                 goto sig;
 470         }
 471
 472         preempt_disable();
 473
 474         if (ll_bit == 0 || ll_task != current) {
 475                 compute_return_epc(regs);
 476                 regs->regs[reg] = 0;
 477                 preempt_enable();
 478                 return;
 479         }
 480
 481         preempt_enable();
 482
 483         if (put_user(regs->regs[reg], vaddr)) {
 484                 signal = SIGSEGV;
 485                 goto sig;
 486         }
 487
 488         compute_return_epc(regs);
 489         regs->regs[reg] = 1;
 490
 491         return;
 492
 493 sig:
 494         force_sig(signal, current);
 495 }
 496
 497 /*
 498  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
 499  * opcodes are supposed to result in coprocessor unusable exceptions if
 500  * executed on ll/sc-less processors.  That's the theory.  In practice a
 501  * few processors such as NEC's VR4100 throw reserved instruction exceptions
 502  * instead, so we're doing the emulation thing in both exception handlers.
 503  */
 504 static inline int simulate_llsc(struct pt_regs *regs)
 505 {
 506         unsigned int opcode;
 507
 508         if (unlikely(get_insn_opcode(regs, &opcode)))
 509                 return -EFAULT;
 510
 511         if ((opcode & OPCODE) == LL) {
 512                 simulate_ll(regs, opcode);
 513                 return 0;
 514         }
 515         if ((opcode & OPCODE) == SC) {
 516                 simulate_sc(regs, opcode);
 517                 return 0;
 518         }
 519
 520         return -EFAULT;                 /* Strange things going on ... */
 521 }
 522
 523 /*
 524  * Simulate trapping 'rdhwr' instructions to provide user accessible
 525  * registers not implemented in hardware.  The only current use of this
 526  * is the thread area pointer.
 527  */
 528 static inline int simulate_rdhwr(struct pt_regs *regs)
 529 {
 530         struct thread_info *ti = task_thread_info(current);
 531         unsigned int opcode;
 532
 533         if (unlikely(get_insn_opcode(regs, &opcode)))
 534                 return -EFAULT;
 535
 536         if (unlikely(compute_return_epc(regs)))
 537                 return -EFAULT;
 538
 539         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 540                 int rd = (opcode & RD) >> 11;
 541                 int rt = (opcode & RT) >> 16;
 542                 switch (rd) {
 543                         case 29:
 544                                 regs->regs[rt] = ti->tp_value;
 545                                 return 0;
 546                         default:
 547                                 return -EFAULT;
 548                 }
 549         }
 550
 551         /* Not ours.  */
 552         return -EFAULT;
 553 }
 554
 555 asmlinkage void do_ov(struct pt_regs *regs)
 556 {
 557         siginfo_t info;
 558
 559         die_if_kernel("Integer overflow", regs);
 560
 561         info.si_code = FPE_INTOVF;
 562         info.si_signo = SIGFPE;
 563         info.si_errno = 0;
 564         info.si_addr = (void __user *) regs->cp0_epc;
 565         force_sig_info(SIGFPE, &info, current);
 566 }
 567
 568 /*
 569  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
 570  */
 571 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 572 {
 573         if (fcr31 & FPU_CSR_UNI_X) {
 574                 int sig;
 575
 576                 preempt_disable();
 577
 578 #ifdef CONFIG_PREEMPT
 579                 if (!is_fpu_owner()) {
 580                         /* We might lose fpu before disabling preempt... */
 581                         own_fpu();
 582                         BUG_ON(!used_math());
 583                         restore_fp(current);
 584                 }
 585 #endif
 586                 /*
 587                  * Unimplemented operation exception.  If we've got the full
 588                  * software emulator on-board, let's use it...
 589                  *
 590                  * Force FPU to dump state into task/thread context.  We're
 591                  * moving a lot of data here for what is probably a single
 592                  * instruction, but the alternative is to pre-decode the FP
 593                  * register operands before invoking the emulator, which seems
 594                  * a bit extreme for what should be an infrequent event.
 595                  */
 596                 save_fp(current);
 597                 /* Ensure 'resume' not overwrite saved fp context again. */
 598                 lose_fpu();
 599
 600                 preempt_enable();
 601
 602                 /* Run the emulator */
 603                 sig = fpu_emulator_cop1Handler (regs,
 604                         &current->thread.fpu.soft);
 605
 606                 preempt_disable();
 607
 608                 own_fpu();      /* Using the FPU again.  */
 609                 /*
 610                  * We can't allow the emulated instruction to leave any of
 611                  * the cause bit set in $fcr31.
 612                  */
 613                 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
 614
 615                 /* Restore the hardware register state */
 616                 restore_fp(current);
 617
 618                 preempt_enable();
 619
 620                 /* If something went wrong, signal */
 621                 if (sig)
 622                         force_sig(sig, current);
 623
 624                 return;
 625         }
 626
 627         force_sig(SIGFPE, current);
 628 }
 629
 630 asmlinkage void do_bp(struct pt_regs *regs)
 631 {
 632         unsigned int opcode, bcode;
 633         siginfo_t info;
 634
 635         die_if_kernel("Break instruction in kernel code", regs);
 636
 637         if (get_insn_opcode(regs, &opcode))
 638                 return;
 639
 640         /*
 641          * There is the ancient bug in the MIPS assemblers that the break
 642          * code starts left to bit 16 instead to bit 6 in the opcode.
 643          * Gas is bug-compatible, but not always, grrr...
 644          * We handle both cases with a simple heuristics.  --macro
 645          */
 646         bcode = ((opcode >> 6) & ((1 << 20) - 1));
 647         if (bcode < (1 << 10))
 648                 bcode <<= 10;
 649
 650         /*
 651          * (A short test says that IRIX 5.3 sends SIGTRAP for all break
 652          * insns, even for break codes that indicate arithmetic failures.
 653          * Weird ...)
 654          * But should we continue the brokenness???  --macro
 655          */
 656         switch (bcode) {
 657         case BRK_OVERFLOW << 10:
 658         case BRK_DIVZERO << 10:
 659                 if (bcode == (BRK_DIVZERO << 10))
 660                         info.si_code = FPE_INTDIV;
 661                 else
 662                         info.si_code = FPE_INTOVF;
 663                 info.si_signo = SIGFPE;
 664                 info.si_errno = 0;
 665                 info.si_addr = (void __user *) regs->cp0_epc;
 666                 force_sig_info(SIGFPE, &info, current);
 667                 break;
 668         default:
 669                 force_sig(SIGTRAP, current);
 670         }
 671 }
 672
 673 asmlinkage void do_tr(struct pt_regs *regs)
 674 {
 675         unsigned int opcode, tcode = 0;
 676         siginfo_t info;
 677
 678         die_if_kernel("Trap instruction in kernel code", regs);
 679
 680         if (get_insn_opcode(regs, &opcode))
 681                 return;
 682
 683         /* Immediate versions don't provide a code.  */
 684         if (!(opcode & OPCODE))
 685                 tcode = ((opcode >> 6) & ((1 << 10) - 1));
 686
 687         /*
 688          * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
 689          * insns, even for trap codes that indicate arithmetic failures.
 690          * Weird ...)
 691          * But should we continue the brokenness???  --macro
 692          */
 693         switch (tcode) {
 694         case BRK_OVERFLOW:
 695         case BRK_DIVZERO:
 696                 if (tcode == BRK_DIVZERO)
 697                         info.si_code = FPE_INTDIV;
 698                 else
 699                         info.si_code = FPE_INTOVF;
 700                 info.si_signo = SIGFPE;
 701                 info.si_errno = 0;
 702                 info.si_addr = (void __user *) regs->cp0_epc;
 703                 force_sig_info(SIGFPE, &info, current);
 704                 break;
 705         default:
 706                 force_sig(SIGTRAP, current);
 707         }
 708 }
 709
 710 asmlinkage void do_ri(struct pt_regs *regs)
 711 {
 712         die_if_kernel("Reserved instruction in kernel code", regs);
 713
 714         if (!cpu_has_llsc)
 715                 if (!simulate_llsc(regs))
 716                         return;
 717
 718         if (!simulate_rdhwr(regs))
 719                 return;
 720
 721         force_sig(SIGILL, current);
 722 }
 723
 724 asmlinkage void do_cpu(struct pt_regs *regs)
 725 {
 726         unsigned int cpid;
 727
 728         die_if_kernel("do_cpu invoked from kernel context!", regs);
 729
 730         cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
 731
 732         switch (cpid) {
 733         case 0:
 734                 if (!cpu_has_llsc)
 735                         if (!simulate_llsc(regs))
 736                                 return;
 737
 738                 if (!simulate_rdhwr(regs))
 739                         return;
 740
 741                 break;
 742
 743         case 1:
 744                 preempt_disable();
 745
 746                 own_fpu();
 747                 if (used_math()) {      /* Using the FPU again.  */
 748                         restore_fp(current);
 749                 } else {                        /* First time FPU user.  */
 750                         init_fpu();
 751                         set_used_math();
 752                 }
 753
 754                 preempt_enable();
 755
 756                 if (!cpu_has_fpu) {
 757                         int sig = fpu_emulator_cop1Handler(regs,
 758                                                 &current->thread.fpu.soft);
 759                         if (sig)
 760                                 force_sig(sig, current);
 761 #ifdef CONFIG_MIPS_MT_FPAFF
 762                         else {
 763                         /*
 764                          * MIPS MT processors may have fewer FPU contexts
 765                          * than CPU threads. If we've emulated more than
 766                          * some threshold number of instructions, force
 767                          * migration to a "CPU" that has FP support.
 768                          */
 769                          if(mt_fpemul_threshold > 0
 770                          && ((current->thread.emulated_fp++
 771                             > mt_fpemul_threshold))) {
 772                           /*
 773                            * If there's no FPU present, or if the
 774                            * application has already restricted
 775                            * the allowed set to exclude any CPUs
 776                            * with FPUs, we'll skip the procedure.
 777                            */
 778                           if (cpus_intersects(current->cpus_allowed,
 779                                                 mt_fpu_cpumask)) {
 780                             cpumask_t tmask;
 781
 782                             cpus_and(tmask,
 783                                         current->thread.user_cpus_allowed,
 784                                         mt_fpu_cpumask);
 785                             set_cpus_allowed(current, tmask);
 786                             current->thread.mflags |= MF_FPUBOUND;
 787                           }
 788                          }
 789                         }
 790 #endif /* CONFIG_MIPS_MT_FPAFF */
 791                 }
 792
 793                 return;
 794
 795         case 2:
 796         case 3:
 797                 die_if_kernel("do_cpu invoked from kernel context!", regs);
 798                 break;
 799         }
 800
 801         force_sig(SIGILL, current);
 802 }
 803
 804 asmlinkage void do_mdmx(struct pt_regs *regs)
 805 {
 806         force_sig(SIGILL, current);
 807 }
 808
 809 asmlinkage void do_watch(struct pt_regs *regs)
 810 {
 811         /*
 812          * We use the watch exception where available to detect stack
 813          * overflows.
 814          */
 815         dump_tlb_all();
 816         show_regs(regs);
 817         panic("Caught WATCH exception - probably caused by stack overflow.");
 818 }
 819
 820 asmlinkage void do_mcheck(struct pt_regs *regs)
 821 {
 822         const int field = 2 * sizeof(unsigned long);
 823         int multi_match = regs->cp0_status & ST0_TS;
 824
 825         show_regs(regs);
 826
 827         if (multi_match) {
 828                 printk("Index   : %0x\n", read_c0_index());
 829                 printk("Pagemask: %0x\n", read_c0_pagemask());
 830                 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
 831                 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
 832                 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
 833                 printk("\n");
 834                 dump_tlb_all();
 835         }
 836
 837         show_code((unsigned int *) regs->cp0_epc);
 838
 839         /*
 840          * Some chips may have other causes of machine check (e.g. SB1
 841          * graduation timer)
 842          */
 843         panic("Caught Machine Check exception - %scaused by multiple "
 844               "matching entries in the TLB.",
 845               (multi_match) ? "" : "not ");
 846 }
 847
 848 asmlinkage void do_mt(struct pt_regs *regs)
 849 {
 850         int subcode;
 851
 852         die_if_kernel("MIPS MT Thread exception in kernel", regs);
 853
 854         subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
 855                         >> VPECONTROL_EXCPT_SHIFT;
 856         switch (subcode) {
 857         case 0:
 858                 printk(KERN_ERR "Thread Underflow\n");
 859                 break;
 860         case 1:
 861                 printk(KERN_ERR "Thread Overflow\n");
 862                 break;
 863         case 2:
 864                 printk(KERN_ERR "Invalid YIELD Qualifier\n");
 865                 break;
 866         case 3:
 867                 printk(KERN_ERR "Gating Storage Exception\n");
 868                 break;
 869         case 4:
 870                 printk(KERN_ERR "YIELD Scheduler Exception\n");
 871                 break;
 872         case 5:
 873                 printk(KERN_ERR "Gating Storage Schedulier Exception\n");
 874                 break;
 875         default:
 876                 printk(KERN_ERR "*** UNKNOWN THREAD EXCEPTION %d ***\n",
 877                         subcode);
 878                 break;
 879         }
 880         die_if_kernel("MIPS MT Thread exception in kernel", regs);
 881
 882         force_sig(SIGILL, current);
 883 }
 884
 885
 886 asmlinkage void do_dsp(struct pt_regs *regs)
 887 {
 888         if (cpu_has_dsp)
 889                 panic("Unexpected DSP exception\n");
 890
 891         force_sig(SIGILL, current);
 892 }
 893
 894 asmlinkage void do_reserved(struct pt_regs *regs)
 895 {
 896         /*
 897          * Game over - no way to handle this if it ever occurs.  Most probably
 898          * caused by a new unknown cpu type or after another deadly
 899          * hard/software error.
 900          */
 901         show_regs(regs);
 902         panic("Caught reserved exception %ld - should not happen.",
 903               (regs->cp0_cause & 0x7f) >> 2);
 904 }
 905
 906 asmlinkage void do_default_vi(struct pt_regs *regs)
 907 {
 908         show_regs(regs);
 909         panic("Caught unexpected vectored interrupt.");
 910 }
 911
 912 /*
 913  * Some MIPS CPUs can enable/disable for cache parity detection, but do
 914  * it different ways.
 915  */
 916 static inline void parity_protection_init(void)
 917 {
 918         switch (current_cpu_data.cputype) {
 919         case CPU_24K:
 920         case CPU_34K:
 921         case CPU_5KC:
 922                 write_c0_ecc(0x80000000);
 923                 back_to_back_c0_hazard();
 924                 /* Set the PE bit (bit 31) in the c0_errctl register. */
 925                 printk(KERN_INFO "Cache parity protection %sabled\n",
 926                        (read_c0_ecc() & 0x80000000) ? "en" : "dis");
 927                 break;
 928         case CPU_20KC:
 929         case CPU_25KF:
 930                 /* Clear the DE bit (bit 16) in the c0_status register. */
 931                 printk(KERN_INFO "Enable cache parity protection for "
 932                        "MIPS 20KC/25KF CPUs.\n");
 933                 clear_c0_status(ST0_DE);
 934                 break;
 935         default:
 936                 break;
 937         }
 938 }
 939
 940 asmlinkage void cache_parity_error(void)
 941 {
 942         const int field = 2 * sizeof(unsigned long);
 943         unsigned int reg_val;
 944
 945         /* For the moment, report the problem and hang. */
 946         printk("Cache error exception:\n");
 947         printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
 948         reg_val = read_c0_cacheerr();
 949         printk("c0_cacheerr == %08x\n", reg_val);
 950
 951         printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
 952                reg_val & (1<<30) ? "secondary" : "primary",
 953                reg_val & (1<<31) ? "data" : "insn");
 954         printk("Error bits: %s%s%s%s%s%s%s\n",
 955                reg_val & (1<<29) ? "ED " : "",
 956                reg_val & (1<<28) ? "ET " : "",
 957                reg_val & (1<<26) ? "EE " : "",
 958                reg_val & (1<<25) ? "EB " : "",
 959                reg_val & (1<<24) ? "EI " : "",
 960                reg_val & (1<<23) ? "E1 " : "",
 961                reg_val & (1<<22) ? "E0 " : "");
 962         printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
 963
 964 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
 965         if (reg_val & (1<<22))
 966                 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
 967
 968         if (reg_val & (1<<23))
 969                 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
 970 #endif
 971
 972         panic("Can't handle the cache error!");
 973 }
 974
 975 /*
 976  * SDBBP EJTAG debug exception handler.
 977  * We skip the instruction and return to the next instruction.
 978  */
 979 void ejtag_exception_handler(struct pt_regs *regs)
 980 {
 981         const int field = 2 * sizeof(unsigned long);
 982         unsigned long depc, old_epc;
 983         unsigned int debug;
 984
 985         printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
 986         depc = read_c0_depc();
 987         debug = read_c0_debug();
 988         printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
 989         if (debug & 0x80000000) {
 990                 /*
 991                  * In branch delay slot.
 992                  * We cheat a little bit here and use EPC to calculate the
 993                  * debug return address (DEPC). EPC is restored after the
 994                  * calculation.
 995                  */
 996                 old_epc = regs->cp0_epc;
 997                 regs->cp0_epc = depc;
 998                 __compute_return_epc(regs);
 999                 depc = regs->cp0_epc;
1000                 regs->cp0_epc = old_epc;
1001         } else
1002                 depc += 4;
1003         write_c0_depc(depc);
1004
1005 #if 0
1006         printk("\n\n----- Enable EJTAG single stepping ----\n\n");
1007         write_c0_debug(debug | 0x100);
1008 #endif
1009 }
1010
1011 /*
1012  * NMI exception handler.
1013  */
1014 void nmi_exception_handler(struct pt_regs *regs)
1015 {
1016 #ifdef CONFIG_MIPS_MT_SMTC
1017         unsigned long dvpret = dvpe();
1018         bust_spinlocks(1);
1019         printk("NMI taken!!!!\n");
1020         mips_mt_regdump(dvpret);
1021 #else
1022         bust_spinlocks(1);
1023         printk("NMI taken!!!!\n");
1024 #endif /* CONFIG_MIPS_MT_SMTC */
1025         die("NMI", regs);
1026         while(1) ;
1027 }
1028
1029 #define VECTORSPACING 0x100     /* for EI/VI mode */
1030
1031 unsigned long ebase;
1032 unsigned long exception_handlers[32];
1033 unsigned long vi_handlers[64];
1034
1035 /*
1036  * As a side effect of the way this is implemented we're limited
1037  * to interrupt handlers in the address range from
1038  * KSEG0 <= x < KSEG0 + 256mb on the Nevada.  Oh well ...
1039  */
1040 void *set_except_vector(int n, void *addr)
1041 {
1042         unsigned long handler = (unsigned long) addr;
1043         unsigned long old_handler = exception_handlers[n];
1044
1045         exception_handlers[n] = handler;
1046         if (n == 0 && cpu_has_divec) {
1047                 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1048                                                  (0x03ffffff & (handler >> 2));
1049                 flush_icache_range(ebase + 0x200, ebase + 0x204);
1050         }
1051         return (void *)old_handler;
1052 }
1053
1054 #ifdef CONFIG_CPU_MIPSR2
1055 /*
1056  * MIPSR2 shadow register set allocation
1057  * FIXME: SMP...
1058  */
1059
1060 static struct shadow_registers {
1061         /*
1062          * Number of shadow register sets supported
1063          */
1064         unsigned long sr_supported;
1065         /*
1066          * Bitmap of allocated shadow registers
1067          */
1068         unsigned long sr_allocated;
1069 } shadow_registers;
1070
1071 static void mips_srs_init(void)
1072 {
1073 #ifdef CONFIG_CPU_MIPSR2_SRS
1074         shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1075         printk(KERN_INFO "%d MIPSR2 register sets available\n",
1076                shadow_registers.sr_supported);
1077 #endif
1078         shadow_registers.sr_allocated = 1;      /* Set 0 used by kernel */
1079 }
1080
1081 int mips_srs_max(void)
1082 {
1083         return shadow_registers.sr_supported;
1084 }
1085
1086 int mips_srs_alloc(void)
1087 {
1088         struct shadow_registers *sr = &shadow_registers;
1089         int set;
1090
1091 again:
1092         set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1093         if (set >= sr->sr_supported)
1094                 return -1;
1095
1096         if (test_and_set_bit(set, &sr->sr_allocated))
1097                 goto again;
1098
1099         return set;
1100 }
1101
1102 void mips_srs_free(int set)
1103 {
1104         struct shadow_registers *sr = &shadow_registers;
1105
1106         clear_bit(set, &sr->sr_allocated);
1107 }
1108
1109 static void *set_vi_srs_handler(int n, void *addr, int srs)
1110 {
1111         unsigned long handler;
1112         unsigned long old_handler = vi_handlers[n];
1113         u32 *w;
1114         unsigned char *b;
1115
1116         if (!cpu_has_veic && !cpu_has_vint)
1117                 BUG();
1118
1119         if (addr == NULL) {
1120                 handler = (unsigned long) do_default_vi;
1121                 srs = 0;
1122         } else
1123                 handler = (unsigned long) addr;
1124         vi_handlers[n] = (unsigned long) addr;
1125
1126         b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1127
1128         if (srs >= mips_srs_max())
1129                 panic("Shadow register set %d not supported", srs);
1130
1131         if (cpu_has_veic) {
1132                 if (board_bind_eic_interrupt)
1133                         board_bind_eic_interrupt (n, srs);
1134         } else if (cpu_has_vint) {
1135                 /* SRSMap is only defined if shadow sets are implemented */
1136                 if (mips_srs_max() > 1)
1137                         change_c0_srsmap (0xf << n*4, srs << n*4);
1138         }
1139
1140         if (srs == 0) {
1141                 /*
1142                  * If no shadow set is selected then use the default handler
1143                  * that does normal register saving and a standard interrupt exit
1144                  */
1145
1146                 extern char except_vec_vi, except_vec_vi_lui;
1147                 extern char except_vec_vi_ori, except_vec_vi_end;
1148 #ifdef CONFIG_MIPS_MT_SMTC
1149                 /*
1150                  * We need to provide the SMTC vectored interrupt handler
1151                  * not only with the address of the handler, but with the
1152                  * Status.IM bit to be masked before going there.
1153                  */
1154                 extern char except_vec_vi_mori;
1155                 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1156 #endif /* CONFIG_MIPS_MT_SMTC */
1157                 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1158                 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1159                 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1160
1161                 if (handler_len > VECTORSPACING) {
1162                         /*
1163                          * Sigh... panicing won't help as the console
1164                          * is probably not configured :(
1165                          */
1166                         panic ("VECTORSPACING too small");
1167                 }
1168
1169                 memcpy (b, &except_vec_vi, handler_len);
1170 #ifdef CONFIG_MIPS_MT_SMTC
1171                 if (n > 7)
1172                         printk("Vector index %d exceeds SMTC maximum\n", n);
1173                 w = (u32 *)(b + mori_offset);
1174                 *w = (*w & 0xffff0000) | (0x100 << n);
1175 #endif /* CONFIG_MIPS_MT_SMTC */
1176                 w = (u32 *)(b + lui_offset);
1177                 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1178                 w = (u32 *)(b + ori_offset);
1179                 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1180                 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1181         }
1182         else {
1183                 /*
1184                  * In other cases jump directly to the interrupt handler
1185                  *
1186                  * It is the handlers responsibility to save registers if required
1187                  * (eg hi/lo) and return from the exception using "eret"
1188                  */
1189                 w = (u32 *)b;
1190                 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1191                 *w = 0;
1192                 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1193         }
1194
1195         return (void *)old_handler;
1196 }
1197
1198 void *set_vi_handler(int n, void *addr)
1199 {
1200         return set_vi_srs_handler(n, addr, 0);
1201 }
1202 #endif
1203
1204 /*
1205  * This is used by native signal handling
1206  */
1207 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1208 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1209
1210 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1211 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1212
1213 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1214 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1215
1216 #ifdef CONFIG_SMP
1217 static int smp_save_fp_context(struct sigcontext *sc)
1218 {
1219         return cpu_has_fpu
1220                ? _save_fp_context(sc)
1221                : fpu_emulator_save_context(sc);
1222 }
1223
1224 static int smp_restore_fp_context(struct sigcontext *sc)
1225 {
1226         return cpu_has_fpu
1227                ? _restore_fp_context(sc)
1228                : fpu_emulator_restore_context(sc);
1229 }
1230 #endif
1231
1232 static inline void signal_init(void)
1233 {
1234 #ifdef CONFIG_SMP
1235         /* For now just do the cpu_has_fpu check when the functions are invoked */
1236         save_fp_context = smp_save_fp_context;
1237         restore_fp_context = smp_restore_fp_context;
1238 #else
1239         if (cpu_has_fpu) {
1240                 save_fp_context = _save_fp_context;
1241                 restore_fp_context = _restore_fp_context;
1242         } else {
1243                 save_fp_context = fpu_emulator_save_context;
1244                 restore_fp_context = fpu_emulator_restore_context;
1245         }
1246 #endif
1247 }
1248
1249 #ifdef CONFIG_MIPS32_COMPAT
1250
1251 /*
1252  * This is used by 32-bit signal stuff on the 64-bit kernel
1253  */
1254 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1255 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1256
1257 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1258 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1259
1260 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1261 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1262
1263 static inline void signal32_init(void)
1264 {
1265         if (cpu_has_fpu) {
1266                 save_fp_context32 = _save_fp_context32;
1267                 restore_fp_context32 = _restore_fp_context32;
1268         } else {
1269                 save_fp_context32 = fpu_emulator_save_context32;
1270                 restore_fp_context32 = fpu_emulator_restore_context32;
1271         }
1272 }
1273 #endif
1274
1275 extern void cpu_cache_init(void);
1276 extern void tlb_init(void);
1277 extern void flush_tlb_handlers(void);
1278
1279 void __init per_cpu_trap_init(void)
1280 {
1281         unsigned int cpu = smp_processor_id();
1282         unsigned int status_set = ST0_CU0;
1283 #ifdef CONFIG_MIPS_MT_SMTC
1284         int secondaryTC = 0;
1285         int bootTC = (cpu == 0);
1286
1287         /*
1288          * Only do per_cpu_trap_init() for first TC of Each VPE.
1289          * Note that this hack assumes that the SMTC init code
1290          * assigns TCs consecutively and in ascending order.
1291          */
1292
1293         if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1294             ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1295                 secondaryTC = 1;
1296 #endif /* CONFIG_MIPS_MT_SMTC */
1297
1298         /*
1299          * Disable coprocessors and select 32-bit or 64-bit addressing
1300          * and the 16/32 or 32/32 FPR register model.  Reset the BEV
1301          * flag that some firmware may have left set and the TS bit (for
1302          * IP27).  Set XX for ISA IV code to work.
1303          */
1304 #ifdef CONFIG_64BIT
1305         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1306 #endif
1307         if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1308                 status_set |= ST0_XX;
1309         change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1310                          status_set);
1311
1312         if (cpu_has_dsp)
1313                 set_c0_status(ST0_MX);
1314
1315 #ifdef CONFIG_CPU_MIPSR2
1316         write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1317 #endif
1318
1319 #ifdef CONFIG_MIPS_MT_SMTC
1320         if (!secondaryTC) {
1321 #endif /* CONFIG_MIPS_MT_SMTC */
1322
1323         /*
1324          * Interrupt handling.
1325          */
1326         if (cpu_has_veic || cpu_has_vint) {
1327                 write_c0_ebase (ebase);
1328                 /* Setting vector spacing enables EI/VI mode  */
1329                 change_c0_intctl (0x3e0, VECTORSPACING);
1330         }
1331         if (cpu_has_divec) {
1332                 if (cpu_has_mipsmt) {
1333                         unsigned int vpflags = dvpe();
1334                         set_c0_cause(CAUSEF_IV);
1335                         evpe(vpflags);
1336                 } else
1337                         set_c0_cause(CAUSEF_IV);
1338         }
1339 #ifdef CONFIG_MIPS_MT_SMTC
1340         }
1341 #endif /* CONFIG_MIPS_MT_SMTC */
1342
1343         cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1344         TLBMISS_HANDLER_SETUP();
1345
1346         atomic_inc(&init_mm.mm_count);
1347         current->active_mm = &init_mm;
1348         BUG_ON(current->mm);
1349         enter_lazy_tlb(&init_mm, current);
1350
1351 #ifdef CONFIG_MIPS_MT_SMTC
1352         if (bootTC) {
1353 #endif /* CONFIG_MIPS_MT_SMTC */
1354                 cpu_cache_init();
1355                 tlb_init();
1356 #ifdef CONFIG_MIPS_MT_SMTC
1357         }
1358 #endif /* CONFIG_MIPS_MT_SMTC */
1359 }
1360
1361 /* Install CPU exception handler */
1362 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1363 {
1364         memcpy((void *)(ebase + offset), addr, size);
1365         flush_icache_range(ebase + offset, ebase + offset + size);
1366 }
1367
1368 /* Install uncached CPU exception handler */
1369 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1370 {
1371 #ifdef CONFIG_32BIT
1372         unsigned long uncached_ebase = KSEG1ADDR(ebase);
1373 #endif
1374 #ifdef CONFIG_64BIT
1375         unsigned long uncached_ebase = TO_UNCAC(ebase);
1376 #endif
1377
1378         memcpy((void *)(uncached_ebase + offset), addr, size);
1379 }
1380
1381 void __init trap_init(void)
1382 {
1383         extern char except_vec3_generic, except_vec3_r4000;
1384         extern char except_vec4;
1385         unsigned long i;
1386
1387         if (cpu_has_veic || cpu_has_vint)
1388                 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1389         else
1390                 ebase = CAC_BASE;
1391
1392 #ifdef CONFIG_CPU_MIPSR2
1393         mips_srs_init();
1394 #endif
1395
1396         per_cpu_trap_init();
1397
1398         /*
1399          * Copy the generic exception handlers to their final destination.
1400          * This will be overriden later as suitable for a particular
1401          * configuration.
1402          */
1403         set_handler(0x180, &except_vec3_generic, 0x80);
1404
1405         /*
1406          * Setup default vectors
1407          */
1408         for (i = 0; i <= 31; i++)
1409                 set_except_vector(i, handle_reserved);
1410
1411         /*
1412          * Copy the EJTAG debug exception vector handler code to it's final
1413          * destination.
1414          */
1415         if (cpu_has_ejtag && board_ejtag_handler_setup)
1416                 board_ejtag_handler_setup ();
1417
1418         /*
1419          * Only some CPUs have the watch exceptions.
1420          */
1421         if (cpu_has_watch)
1422                 set_except_vector(23, handle_watch);
1423
1424         /*
1425          * Initialise interrupt handlers
1426          */
1427         if (cpu_has_veic || cpu_has_vint) {
1428                 int nvec = cpu_has_veic ? 64 : 8;
1429                 for (i = 0; i < nvec; i++)
1430                         set_vi_handler(i, NULL);
1431         }
1432         else if (cpu_has_divec)
1433                 set_handler(0x200, &except_vec4, 0x8);
1434
1435         /*
1436          * Some CPUs can enable/disable for cache parity detection, but does
1437          * it different ways.
1438          */
1439         parity_protection_init();
1440
1441         /*
1442          * The Data Bus Errors / Instruction Bus Errors are signaled
1443          * by external hardware.  Therefore these two exceptions
1444          * may have board specific handlers.
1445          */
1446         if (board_be_init)
1447                 board_be_init();
1448
1449         set_except_vector(0, handle_int);
1450         set_except_vector(1, handle_tlbm);
1451         set_except_vector(2, handle_tlbl);
1452         set_except_vector(3, handle_tlbs);
1453
1454         set_except_vector(4, handle_adel);
1455         set_except_vector(5, handle_ades);
1456
1457         set_except_vector(6, handle_ibe);
1458         set_except_vector(7, handle_dbe);
1459
1460         set_except_vector(8, handle_sys);
1461         set_except_vector(9, handle_bp);
1462         set_except_vector(10, handle_ri);
1463         set_except_vector(11, handle_cpu);
1464         set_except_vector(12, handle_ov);
1465         set_except_vector(13, handle_tr);
1466
1467         if (current_cpu_data.cputype == CPU_R6000 ||
1468             current_cpu_data.cputype == CPU_R6000A) {
1469                 /*
1470                  * The R6000 is the only R-series CPU that features a machine
1471                  * check exception (similar to the R4000 cache error) and
1472                  * unaligned ldc1/sdc1 exception.  The handlers have not been
1473                  * written yet.  Well, anyway there is no R6000 machine on the
1474                  * current list of targets for Linux/MIPS.
1475                  * (Duh, crap, there is someone with a triple R6k machine)
1476                  */
1477                 //set_except_vector(14, handle_mc);
1478                 //set_except_vector(15, handle_ndc);
1479         }
1480
1481
1482         if (board_nmi_handler_setup)
1483                 board_nmi_handler_setup();
1484
1485         if (cpu_has_fpu && !cpu_has_nofpuex)
1486                 set_except_vector(15, handle_fpe);
1487
1488         set_except_vector(22, handle_mdmx);
1489
1490         if (cpu_has_mcheck)
1491                 set_except_vector(24, handle_mcheck);
1492
1493         if (cpu_has_mipsmt)
1494                 set_except_vector(25, handle_mt);
1495
1496         if (cpu_has_dsp)
1497                 set_except_vector(26, handle_dsp);
1498
1499         if (cpu_has_vce)
1500                 /* Special exception: R4[04]00 uses also the divec space. */
1501                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1502         else if (cpu_has_4kex)
1503                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1504         else
1505                 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1506
1507         signal_init();
1508 #ifdef CONFIG_MIPS32_COMPAT
1509         signal32_init();
1510 #endif
1511
1512         flush_icache_range(ebase, ebase + 0x400);
1513         flush_tlb_handlers();
1514 }