arch/mips/mips-boards/sim/sim_smp.c

   1 /*
   2  * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
   3  *
   4  *  This program is free software; you can distribute it and/or modify it
   5  *  under the terms of the GNU General Public License (Version 2) as
   6  *  published by the Free Software Foundation.
   7  *
   8  *  This program is distributed in the hope it will be useful, but WITHOUT
   9  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  11  *  for more details.
  12  *
  13  *  You should have received a copy of the GNU General Public License along
  14  *  with this program; if not, write to the Free Software Foundation, Inc.,
  15  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  16  *
  17  */
  18 /*
  19  * Simulator Platform-specific hooks for SMP operation
  20  */
  21 #include <linux/config.h>
  22 #include <linux/kernel.h>
  23 #include <linux/sched.h>
  24 #include <linux/cpumask.h>
  25 #include <linux/interrupt.h>
  26 #include <asm/atomic.h>
  27 #include <asm/cpu.h>
  28 #include <asm/processor.h>
  29 #include <asm/system.h>
  30 #include <asm/hardirq.h>
  31 #include <asm/mmu_context.h>
  32 #include <asm/smp.h>
  33 #ifdef CONFIG_MIPS_MT_SMTC
  34 #include <asm/smtc_ipi.h>
  35 #endif /* CONFIG_MIPS_MT_SMTC */
  36
  37 /* VPE/SMP Prototype implements platform interfaces directly */
  38 #if !defined(CONFIG_MIPS_MT_SMP)
  39
  40 /*
  41  * Cause the specified action to be performed on a targeted "CPU"
  42  */
  43
  44 void core_send_ipi(int cpu, unsigned int action)
  45 {
  46 #ifdef CONFIG_MIPS_MT_SMTC
  47         smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
  48 #endif /* CONFIG_MIPS_MT_SMTC */
  49 /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
  50
  51 }
  52
  53 /*
  54  * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
  55  */
  56
  57 void __init prom_build_cpu_map(void)
  58 {
  59 #ifdef CONFIG_MIPS_MT_SMTC
  60         int nextslot;
  61
  62         /*
  63          * As of November, 2004, MIPSsim only simulates one core
  64          * at a time.  However, that core may be a MIPS MT core
  65          * with multiple virtual processors and thread contexts.
  66          */
  67
  68         if (read_c0_config3() & (1<<2)) {
  69                 nextslot = mipsmt_build_cpu_map(1);
  70         }
  71 #endif /* CONFIG_MIPS_MT_SMTC */
  72 }
  73
  74 /*
  75  * Platform "CPU" startup hook
  76  */
  77
  78 void prom_boot_secondary(int cpu, struct task_struct *idle)
  79 {
  80 #ifdef CONFIG_MIPS_MT_SMTC
  81         smtc_boot_secondary(cpu, idle);
  82 #endif /* CONFIG_MIPS_MT_SMTC */
  83 }
  84
  85 /*
  86  * Post-config but pre-boot cleanup entry point
  87  */
  88
  89 void prom_init_secondary(void)
  90 {
  91 #ifdef CONFIG_MIPS_MT_SMTC
  92         void smtc_init_secondary(void);
  93
  94         smtc_init_secondary();
  95 #endif /* CONFIG_MIPS_MT_SMTC */
  96 }
  97
  98 /*
  99  * Platform SMP pre-initialization
 100  */
 101
 102 void prom_prepare_cpus(unsigned int max_cpus)
 103 {
 104 #ifdef CONFIG_MIPS_MT_SMTC
 105         /*
 106          * As noted above, we can assume a single CPU for now
 107          * but it may be multithreaded.
 108          */
 109
 110         if (read_c0_config3() & (1<<2)) {
 111                 mipsmt_prepare_cpus(max_cpus);
 112         }
 113 #endif /* CONFIG_MIPS_MT_SMTC */
 114 }
 115
 116 /*
 117  * SMP initialization finalization entry point
 118  */
 119
 120 void prom_smp_finish(void)
 121 {
 122 #ifdef CONFIG_MIPS_MT_SMTC
 123         smtc_smp_finish();
 124 #endif /* CONFIG_MIPS_MT_SMTC */
 125 }
 126
 127 /*
 128  * Hook for after all CPUs are online
 129  */
 130
 131 void prom_cpus_done(void)
 132 {
 133 #ifdef CONFIG_MIPS_MT_SMTC
 134
 135 #endif /* CONFIG_MIPS_MT_SMTC */
 136 }
 137 #endif /* CONFIG_MIPS32R2_MT_SMP */