arch/mips/pci/pci-bcm1480ht.c

   1 /*
   2  * Copyright (C) 2001,2002,2005 Broadcom Corporation
   3  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  18  */
  19
  20 /*
  21  * BCM1480/1455-specific HT support (looking like PCI)
  22  *
  23  * This module provides the glue between Linux's PCI subsystem
  24  * and the hardware.  We basically provide glue for accessing
  25  * configuration space, and set up the translation for I/O
  26  * space accesses.
  27  *
  28  * To access configuration space, we use ioremap.  In the 32-bit
  29  * kernel, this consumes either 4 or 8 page table pages, and 16MB of
  30  * kernel mapped memory.  Hopefully neither of these should be a huge
  31  * problem.
  32  *
  33  */
  34 #include <linux/config.h>
  35 #include <linux/types.h>
  36 #include <linux/pci.h>
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/mm.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42
  43 #include <asm/sibyte/bcm1480_regs.h>
  44 #include <asm/sibyte/bcm1480_scd.h>
  45 #include <asm/sibyte/board.h>
  46 #include <asm/io.h>
  47
  48 /*
  49  * Macros for calculating offsets into config space given a device
  50  * structure or dev/fun/reg
  51  */
  52 #define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
  53 #define CFGADDR(bus,devfn,where)   CFGOFFSET((bus)->number,(devfn),where)
  54
  55 static void *ht_cfg_space;
  56
  57 #define PCI_BUS_ENABLED 1
  58 #define PCI_DEVICE_MODE 2
  59
  60 static int bcm1480ht_bus_status = 0;
  61
  62 #define PCI_BRIDGE_DEVICE  0
  63 #define HT_BRIDGE_DEVICE   1
  64
  65 /*
  66  * HT's level-sensitive interrupts require EOI, which is generated
  67  * through a 4MB memory-mapped region
  68  */
  69 unsigned long ht_eoi_space;
  70
  71 /*
  72  * Read/write 32-bit values in config space.
  73  */
  74 static inline u32 READCFG32(u32 addr)
  75 {
  76         return *(u32 *)(ht_cfg_space + (addr&~3));
  77 }
  78
  79 static inline void WRITECFG32(u32 addr, u32 data)
  80 {
  81         *(u32 *)(ht_cfg_space + (addr & ~3)) = data;
  82 }
  83
  84 /*
  85  * Some checks before doing config cycles:
  86  * In PCI Device Mode, hide everything on bus 0 except the LDT host
  87  * bridge.  Otherwise, access is controlled by bridge MasterEn bits.
  88  */
  89 static int bcm1480ht_can_access(struct pci_bus *bus, int devfn)
  90 {
  91         u32 devno;
  92
  93         if (!(bcm1480ht_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
  94                 return 0;
  95
  96         if (bus->number == 0) {
  97                 devno = PCI_SLOT(devfn);
  98                 if (bcm1480ht_bus_status & PCI_DEVICE_MODE)
  99                         return 0;
 100         }
 101         return 1;
 102 }
 103
 104 /*
 105  * Read/write access functions for various sizes of values
 106  * in config space.  Return all 1's for disallowed accesses
 107  * for a kludgy but adequate simulation of master aborts.
 108  */
 109
 110 static int bcm1480ht_pcibios_read(struct pci_bus *bus, unsigned int devfn,
 111                                   int where, int size, u32 * val)
 112 {
 113         u32 data = 0;
 114
 115         if ((size == 2) && (where & 1))
 116                 return PCIBIOS_BAD_REGISTER_NUMBER;
 117         else if ((size == 4) && (where & 3))
 118                 return PCIBIOS_BAD_REGISTER_NUMBER;
 119
 120         if (bcm1480ht_can_access(bus, devfn))
 121                 data = READCFG32(CFGADDR(bus, devfn, where));
 122         else
 123                 data = 0xFFFFFFFF;
 124
 125         if (size == 1)
 126                 *val = (data >> ((where & 3) << 3)) & 0xff;
 127         else if (size == 2)
 128                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 129         else
 130                 *val = data;
 131
 132         return PCIBIOS_SUCCESSFUL;
 133 }
 134
 135 static int bcm1480ht_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 136                                    int where, int size, u32 val)
 137 {
 138         u32 cfgaddr = CFGADDR(bus, devfn, where);
 139         u32 data = 0;
 140
 141         if ((size == 2) && (where & 1))
 142                 return PCIBIOS_BAD_REGISTER_NUMBER;
 143         else if ((size == 4) && (where & 3))
 144                 return PCIBIOS_BAD_REGISTER_NUMBER;
 145
 146         if (!bcm1480ht_can_access(bus, devfn))
 147                 return PCIBIOS_BAD_REGISTER_NUMBER;
 148
 149         data = READCFG32(cfgaddr);
 150
 151         if (size == 1)
 152                 data = (data & ~(0xff << ((where & 3) << 3))) |
 153                     (val << ((where & 3) << 3));
 154         else if (size == 2)
 155                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 156                     (val << ((where & 3) << 3));
 157         else
 158                 data = val;
 159
 160         WRITECFG32(cfgaddr, data);
 161
 162         return PCIBIOS_SUCCESSFUL;
 163 }
 164
 165 static int bcm1480ht_pcibios_get_busno(void)
 166 {
 167         return 0;
 168 }
 169
 170 struct pci_ops bcm1480ht_pci_ops = {
 171         .read   = bcm1480ht_pcibios_read,
 172         .write  = bcm1480ht_pcibios_write,
 173 };
 174
 175 static struct resource bcm1480ht_mem_resource = {
 176         .name   = "BCM1480 HT MEM",
 177         .start  = 0x40000000UL,
 178         .end    = 0x5fffffffUL,
 179         .flags  = IORESOURCE_MEM,
 180 };
 181
 182 static struct resource bcm1480ht_io_resource = {
 183         .name   = "BCM1480 HT I/O",
 184         .start  = 0x00000000UL,
 185         .end    = 0x01ffffffUL,
 186         .flags  = IORESOURCE_IO,
 187 };
 188
 189 struct pci_controller bcm1480ht_controller = {
 190         .pci_ops        = &bcm1480ht_pci_ops,
 191         .mem_resource   = &bcm1480ht_mem_resource,
 192         .io_resource    = &bcm1480ht_io_resource,
 193         .index          = 1,
 194         .get_busno      = bcm1480ht_pcibios_get_busno,
 195 };
 196
 197 static int __init bcm1480ht_pcibios_init(void)
 198 {
 199         uint32_t cmdreg;
 200
 201         ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
 202
 203         /*
 204          * See if the PCI bus has been configured by the firmware.
 205          */
 206         cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
 207                                      PCI_COMMAND));
 208         if (!(cmdreg & PCI_COMMAND_MASTER)) {
 209                 printk("HT: Skipping HT probe. Bus is not initialized.\n");
 210                 iounmap(ht_cfg_space);
 211                 return 1; /* XXX */
 212         }
 213         bcm1480ht_bus_status |= PCI_BUS_ENABLED;
 214
 215         ht_eoi_space = (unsigned long)
 216                 ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
 217                         4 * 1024 * 1024);
 218
 219         register_pci_controller(&bcm1480ht_controller);
 220
 221         return 0;
 222 }
 223
 224 arch_initcall(bcm1480ht_pcibios_init);