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Linux 2.6.17.7
[linux/fpc-iii.git] / arch / mips / tx4938 / toshiba_rbtx4938 / setup.c
blob9166cd4557eb01f1b5e7db4777d882ac4a97416c
1 /*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
3 *
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/ioport.h>
18 #include <linux/proc_fs.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/console.h>
22 #include <linux/pci.h>
23 #include <linux/pm.h>
24
25 #include <asm/wbflush.h>
26 #include <asm/reboot.h>
27 #include <asm/irq.h>
28 #include <asm/time.h>
29 #include <asm/uaccess.h>
30 #include <asm/io.h>
31 #include <asm/bootinfo.h>
32 #include <asm/tx4938/rbtx4938.h>
33 #ifdef CONFIG_SERIAL_TXX9
34 #include <linux/tty.h>
35 #include <linux/serial.h>
36 #include <linux/serial_core.h>
37 #endif
38
39 extern void rbtx4938_time_init(void) __init;
40 extern char * __init prom_getcmdline(void);
41 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
42
43 /* These functions are used for rebooting or halting the machine*/
44 extern void rbtx4938_machine_restart(char *command);
45 extern void rbtx4938_machine_halt(void);
46 extern void rbtx4938_machine_power_off(void);
47
48 /* clocks */
49 unsigned int txx9_master_clock;
50 unsigned int txx9_cpu_clock;
51 unsigned int txx9_gbus_clock;
52
53 unsigned long rbtx4938_ce_base[8];
54 unsigned long rbtx4938_ce_size[8];
55 int txboard_pci66_mode;
56 static int tx4938_pcic_trdyto; /* default: disabled */
57 static int tx4938_pcic_retryto; /* default: disabled */
58 static int tx4938_ccfg_toeon = 1;
59
60 struct tx4938_pcic_reg *pcicptrs[4] = {
61 tx4938_pcicptr /* default setting for TX4938 */
62 };
63
64 static struct {
65 unsigned long base;
66 unsigned long size;
67 } phys_regions[16] __initdata;
68 static int num_phys_regions __initdata;
69
70 #define PHYS_REGION_MINSIZE 0x10000
71
72 void rbtx4938_machine_halt(void)
73 {
74 printk(KERN_NOTICE "System Halted\n");
75 local_irq_disable();
76
77 while (1)
78 __asm__(".set\tmips3\n\t"
79 "wait\n\t"
80 ".set\tmips0");
81 }
82
83 void rbtx4938_machine_power_off(void)
84 {
85 rbtx4938_machine_halt();
86 /* no return */
87 }
88
89 void rbtx4938_machine_restart(char *command)
90 {
91 local_irq_disable();
92
93 printk("Rebooting...");
94 *rbtx4938_softresetlock_ptr = 1;
95 *rbtx4938_sfvol_ptr = 1;
96 *rbtx4938_softreset_ptr = 1;
97 wbflush();
98
99 while(1);
100 }
101
102 void __init
103 txboard_add_phys_region(unsigned long base, unsigned long size)
104 {
105 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
106 printk("phys_region overflow\n");
107 return;
108 }
109 phys_regions[num_phys_regions].base = base;
110 phys_regions[num_phys_regions].size = size;
111 num_phys_regions++;
112 }
113 unsigned long __init
114 txboard_find_free_phys_region(unsigned long begin, unsigned long end,
115 unsigned long size)
116 {
117 unsigned long base;
118 int i;
119
120 for (base = begin / size * size; base < end; base += size) {
121 for (i = 0; i < num_phys_regions; i++) {
122 if (phys_regions[i].size &&
123 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
124 base + (size - 1) >= phys_regions[i].base)
125 break;
126 }
127 if (i == num_phys_regions)
128 return base;
129 }
130 return 0;
131 }
132 unsigned long __init
133 txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
134 unsigned long *size)
135 {
136 unsigned long sz, base;
137 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
138 base = txboard_find_free_phys_region(begin, end, sz);
139 if (base) {
140 *size = sz;
141 return base;
142 }
143 }
144 return 0;
145 }
146 unsigned long __init
147 txboard_request_phys_region_range(unsigned long begin, unsigned long end,
148 unsigned long size)
149 {
150 unsigned long base;
151 base = txboard_find_free_phys_region(begin, end, size);
152 if (base)
153 txboard_add_phys_region(base, size);
154 return base;
155 }
156 unsigned long __init
157 txboard_request_phys_region(unsigned long size)
158 {
159 unsigned long base;
160 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
161 base = txboard_find_free_phys_region(begin, end, size);
162 if (base)
163 txboard_add_phys_region(base, size);
164 return base;
165 }
166 unsigned long __init
167 txboard_request_phys_region_shrink(unsigned long *size)
168 {
169 unsigned long base;
170 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
171 base = txboard_find_free_phys_region_shrink(begin, end, size);
172 if (base)
173 txboard_add_phys_region(base, *size);
174 return base;
175 }
176
177 #ifdef CONFIG_PCI
178 void __init
179 tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
180 struct pci_controller *channel,
181 unsigned long pci_io_base,
182 int extarb)
183 {
184 int i;
185
186 /* Disable All Initiator Space */
187 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
188 TX4938_PCIC_PCICCFG_G2PMEN(1)|
189 TX4938_PCIC_PCICCFG_G2PMEN(2)|
190 TX4938_PCIC_PCICCFG_G2PIOEN);
191
192 /* GB->PCI mappings */
193 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
194 pcicptr->g2piogbase = pci_io_base |
195 #ifdef __BIG_ENDIAN
196 TX4938_PCIC_G2PIOGBASE_ECHG
197 #else
198 TX4938_PCIC_G2PIOGBASE_BSDIS
199 #endif
200 ;
201 pcicptr->g2piopbase = 0;
202 for (i = 0; i < 3; i++) {
203 pcicptr->g2pmmask[i] = 0;
204 pcicptr->g2pmgbase[i] = 0;
205 pcicptr->g2pmpbase[i] = 0;
206 }
207 if (channel->mem_resource->end) {
208 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
209 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
210 #ifdef __BIG_ENDIAN
211 TX4938_PCIC_G2PMnGBASE_ECHG
212 #else
213 TX4938_PCIC_G2PMnGBASE_BSDIS
214 #endif
215 ;
216 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
217 }
218 /* PCI->GB mappings (I/O 256B) */
219 pcicptr->p2giopbase = 0; /* 256B */
220 pcicptr->p2giogbase = 0;
221 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
222 pcicptr->p2gm0plbase = 0;
223 pcicptr->p2gm0pubase = 0;
224 pcicptr->p2gmgbase[0] = 0 |
225 TX4938_PCIC_P2GMnGBASE_TMEMEN |
226 #ifdef __BIG_ENDIAN
227 TX4938_PCIC_P2GMnGBASE_TECHG
228 #else
229 TX4938_PCIC_P2GMnGBASE_TBSDIS
230 #endif
231 ;
232 /* PCI->GB mappings (MEM 16MB) */
233 pcicptr->p2gm1plbase = 0xffffffff;
234 pcicptr->p2gm1pubase = 0xffffffff;
235 pcicptr->p2gmgbase[1] = 0;
236 /* PCI->GB mappings (MEM 1MB) */
237 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
238 pcicptr->p2gmgbase[2] = 0;
239
240 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
241 /* Enable Initiator Memory Space */
242 if (channel->mem_resource->end)
243 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
244 /* Enable Initiator I/O Space */
245 if (channel->io_resource->end)
246 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
247 /* Enable Initiator Config */
248 pcicptr->pciccfg |=
249 TX4938_PCIC_PCICCFG_ICAEN |
250 TX4938_PCIC_PCICCFG_TCAR;
251
252 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
253 pcicptr->pcicfg1 = 0;
254
255 pcicptr->g2ptocnt &= ~0xffff;
256
257 if (tx4938_pcic_trdyto >= 0) {
258 pcicptr->g2ptocnt &= ~0xff;
259 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
260 }
261
262 if (tx4938_pcic_retryto >= 0) {
263 pcicptr->g2ptocnt &= ~0xff00;
264 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
265 }
266
267 /* Clear All Local Bus Status */
268 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
269 /* Enable All Local Bus Interrupts */
270 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
271 /* Clear All Initiator Status */
272 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
273 /* Enable All Initiator Interrupts */
274 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
275 /* Clear All PCI Status Error */
276 pcicptr->pcistatus =
277 (pcicptr->pcistatus & 0x0000ffff) |
278 (TX4938_PCIC_PCISTATUS_ALL << 16);
279 /* Enable All PCI Status Error Interrupts */
280 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
281
282 if (!extarb) {
283 /* Reset Bus Arbiter */
284 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
285 pcicptr->pbabm = 0;
286 /* Enable Bus Arbiter */
287 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
288 }
289
290 /* PCIC Int => IRC IRQ16 */
291 pcicptr->pcicfg2 =
292 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
293
294 pcicptr->pcistatus = PCI_COMMAND_MASTER |
295 PCI_COMMAND_MEMORY |
296 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
297 }
298
299 int __init
300 tx4938_report_pciclk(void)
301 {
302 unsigned long pcode = TX4938_REV_PCODE();
303 int pciclk = 0;
304 printk("TX%lx PCIC --%s PCICLK:",
305 pcode,
306 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
307 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
308
309 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
310 case TX4938_CCFG_PCIDIVMODE_4:
311 pciclk = txx9_cpu_clock / 4; break;
312 case TX4938_CCFG_PCIDIVMODE_4_5:
313 pciclk = txx9_cpu_clock * 2 / 9; break;
314 case TX4938_CCFG_PCIDIVMODE_5:
315 pciclk = txx9_cpu_clock / 5; break;
316 case TX4938_CCFG_PCIDIVMODE_5_5:
317 pciclk = txx9_cpu_clock * 2 / 11; break;
318 case TX4938_CCFG_PCIDIVMODE_8:
319 pciclk = txx9_cpu_clock / 8; break;
320 case TX4938_CCFG_PCIDIVMODE_9:
321 pciclk = txx9_cpu_clock / 9; break;
322 case TX4938_CCFG_PCIDIVMODE_10:
323 pciclk = txx9_cpu_clock / 10; break;
324 case TX4938_CCFG_PCIDIVMODE_11:
325 pciclk = txx9_cpu_clock / 11; break;
326 }
327 printk("Internal(%dMHz)", pciclk / 1000000);
328 } else {
329 printk("External");
330 pciclk = -1;
331 }
332 printk("\n");
333 return pciclk;
334 }
335
336 void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
337 {
338 pcicptrs[ch] = pcicptr;
339 }
340
341 struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
342 {
343 return pcicptrs[ch];
344 }
345
346 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
347 int top_bus, int busnr, int devfn)
348 {
349 static struct pci_dev dev;
350 static struct pci_bus bus;
351
352 dev.sysdata = (void *)hose;
353 dev.devfn = devfn;
354 bus.number = busnr;
355 bus.ops = hose->pci_ops;
356 bus.parent = NULL;
357 dev.bus = &bus;
358
359 return &dev;
360 }
361
362 #define EARLY_PCI_OP(rw, size, type) \
363 static int early_##rw##_config_##size(struct pci_controller *hose, \
364 int top_bus, int bus, int devfn, int offset, type value) \
365 { \
366 return pci_##rw##_config_##size( \
367 fake_pci_dev(hose, top_bus, bus, devfn), \
368 offset, value); \
369 }
370
371 EARLY_PCI_OP(read, word, u16 *)
372
373 int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
374 {
375 u32 pci_devfn;
376 unsigned short vid;
377 int devfn_start = 0;
378 int devfn_stop = 0xff;
379 int cap66 = -1;
380 u16 stat;
381
382 printk("PCI: Checking 66MHz capabilities...\n");
383
384 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
385 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
386 PCI_VENDOR_ID, &vid);
387
388 if (vid == 0xffff) continue;
389
390 /* check 66MHz capability */
391 if (cap66 < 0)
392 cap66 = 1;
393 if (cap66) {
394 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
395 PCI_STATUS, &stat);
396 if (!(stat & PCI_STATUS_66MHZ)) {
397 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
398 current_bus, pci_devfn);
399 cap66 = 0;
400 break;
401 }
402 }
403 }
404 return cap66 > 0;
405 }
406
407 int __init
408 tx4938_pciclk66_setup(void)
409 {
410 int pciclk;
411
412 /* Assert M66EN */
413 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
414 /* Double PCICLK (if possible) */
415 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
416 unsigned int pcidivmode =
417 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
418 switch (pcidivmode) {
419 case TX4938_CCFG_PCIDIVMODE_8:
420 case TX4938_CCFG_PCIDIVMODE_4:
421 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
422 pciclk = txx9_cpu_clock / 4;
423 break;
424 case TX4938_CCFG_PCIDIVMODE_9:
425 case TX4938_CCFG_PCIDIVMODE_4_5:
426 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
427 pciclk = txx9_cpu_clock * 2 / 9;
428 break;
429 case TX4938_CCFG_PCIDIVMODE_10:
430 case TX4938_CCFG_PCIDIVMODE_5:
431 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
432 pciclk = txx9_cpu_clock / 5;
433 break;
434 case TX4938_CCFG_PCIDIVMODE_11:
435 case TX4938_CCFG_PCIDIVMODE_5_5:
436 default:
437 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
438 pciclk = txx9_cpu_clock * 2 / 11;
439 break;
440 }
441 tx4938_ccfgptr->ccfg =
442 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
443 | pcidivmode;
444 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
445 (unsigned long)tx4938_ccfgptr->ccfg);
446 } else {
447 pciclk = -1;
448 }
449 return pciclk;
450 }
451
452 extern struct pci_controller tx4938_pci_controller[];
453 static int __init tx4938_pcibios_init(void)
454 {
455 unsigned long mem_base[2];
456 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
457 unsigned long io_base[2];
458 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
459 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
460 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
461
462 PCIBIOS_MIN_IO = 0x00001000UL;
463 PCIBIOS_MIN_MEM = 0x01000000UL;
464
465 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
466 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
467
468 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
469 (unsigned short)(tx4938_pcicptr->pciid >> 16),
470 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
471 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
472 extarb ? "External" : "Internal");
473
474 /* setup PCI area */
475 tx4938_pci_controller[0].io_resource->start = io_base[0];
476 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
477 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
478 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
479
480 set_tx4938_pcicptr(0, tx4938_pcicptr);
481
482 register_pci_controller(&tx4938_pci_controller[0]);
483
484 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
485 printk("TX4938_CCFG_PCI66 already configured\n");
486 txboard_pci66_mode = -1; /* already configured */
487 }
488
489 /* Reset PCI Bus */
490 *rbtx4938_pcireset_ptr = 0;
491 /* Reset PCIC */
492 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
493 if (txboard_pci66_mode > 0)
494 tx4938_pciclk66_setup();
495 mdelay(10);
496 /* clear PCIC reset */
497 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
498 *rbtx4938_pcireset_ptr = 1;
499 wbflush();
500 tx4938_report_pcic_status1(tx4938_pcicptr);
501
502 tx4938_report_pciclk();
503 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
504 if (txboard_pci66_mode == 0 &&
505 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
506 /* Reset PCI Bus */
507 *rbtx4938_pcireset_ptr = 0;
508 /* Reset PCIC */
509 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
510 tx4938_pciclk66_setup();
511 mdelay(10);
512 /* clear PCIC reset */
513 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
514 *rbtx4938_pcireset_ptr = 1;
515 wbflush();
516 /* Reinitialize PCIC */
517 tx4938_report_pciclk();
518 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
519 }
520
521 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
522 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
523 /* Reset PCIC1 */
524 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
525 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
526 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
527 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
528 else
529 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
530 mdelay(10);
531 /* clear PCIC1 reset */
532 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
533 tx4938_report_pcic_status1(tx4938_pcic1ptr);
534
535 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
536 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
537 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
538 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
539 printk("%s PCICLK:%dMHz\n",
540 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
541 txx9_gbus_clock /
542 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
543 1000000);
544
545 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
546 tx4938_pci_controller[1].io_resource->start =
547 io_base[1] - io_base[0];
548 tx4938_pci_controller[1].io_resource->end =
549 io_base[1] - io_base[0] + io_size[1] - 1;
550 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
551 tx4938_pci_controller[1].mem_resource->end =
552 mem_base[1] + mem_size[1] - 1;
553 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
554
555 register_pci_controller(&tx4938_pci_controller[1]);
556
557 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
558
559 /* map ioport 0 to PCI I/O space address 0 */
560 set_io_port_base(KSEG1 + io_base[0]);
561
562 return 0;
563 }
564
565 arch_initcall(tx4938_pcibios_init);
566
567 #endif /* CONFIG_PCI */
568
569 /* SPI support */
570
571 /* chip select for SPI devices */
572 #define SEEPROM1_CS 7 /* PIO7 */
573 #define SEEPROM2_CS 0 /* IOC */
574 #define SEEPROM3_CS 1 /* IOC */
575 #define SRTC_CS 2 /* IOC */
576
577 static int rbtx4938_spi_cs_func(int chipid, int on)
578 {
579 unsigned char bit;
580 switch (chipid) {
581 case RBTX4938_SEEPROM1_CHIPID:
582 if (on)
583 tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS);
584 else
585 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
586 return 0;
587 break;
588 case RBTX4938_SEEPROM2_CHIPID:
589 bit = (1 << SEEPROM2_CS);
590 break;
591 case RBTX4938_SEEPROM3_CHIPID:
592 bit = (1 << SEEPROM3_CS);
593 break;
594 case RBTX4938_SRTC_CHIPID:
595 bit = (1 << SRTC_CS);
596 break;
597 default:
598 return -ENODEV;
599 }
600 /* bit1,2,4 are low active, bit3 is high active */
601 *rbtx4938_spics_ptr =
602 (*rbtx4938_spics_ptr & ~bit) |
603 ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit);
604 return 0;
605 }
606
607 #ifdef CONFIG_PCI
608 extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
609
610 int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
611 {
612 struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata;
613 static unsigned char dat[17];
614 static int read_dat = 0;
615 int ch = 0;
616
617 if (channel != &tx4938_pci_controller[1])
618 return -ENODEV;
619 /* TX4938 PCIC1 */
620 switch (PCI_SLOT(dev->devfn)) {
621 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
622 ch = 0;
623 break;
624 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
625 ch = 1;
626 break;
627 default:
628 return -ENODEV;
629 }
630 if (!read_dat) {
631 unsigned char sum;
632 int i;
633 read_dat = 1;
634 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
635 if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID,
636 0, dat, sizeof(dat))) {
637 printk(KERN_ERR "seeprom: read error.\n");
638 } else {
639 if (strcmp(dat, "MAC") != 0)
640 printk(KERN_WARNING "seeprom: bad signature.\n");
641 for (i = 0, sum = 0; i < sizeof(dat); i++)
642 sum += dat[i];
643 if (sum)
644 printk(KERN_WARNING "seeprom: bad checksum.\n");
645 }
646 }
647 memcpy(addr, &dat[4 + 6 * ch], 6);
648 return 0;
649 }
650 #endif /* CONFIG_PCI */
651
652 extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on));
653 static void __init rbtx4938_spi_setup(void)
654 {
655 /* set SPI_SEL */
656 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
657 /* chip selects for SPI devices */
658 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
659 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
660 txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func);
661 }
662
663 static struct resource rbtx4938_fpga_resource;
664
665 static char pcode_str[8];
666 static struct resource tx4938_reg_resource = {
667 pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM
668 };
669
670 void __init tx4938_board_setup(void)
671 {
672 int i;
673 unsigned long divmode;
674 int cpuclk = 0;
675 unsigned long pcode = TX4938_REV_PCODE();
676
677 ioport_resource.start = 0x1000;
678 ioport_resource.end = 0xffffffff;
679 iomem_resource.start = 0x1000;
680 iomem_resource.end = 0xffffffff; /* expand to 4GB */
681
682 sprintf(pcode_str, "TX%lx", pcode);
683 /* SDRAMC,EBUSC are configured by PROM */
684 for (i = 0; i < 8; i++) {
685 if (!(tx4938_ebuscptr->cr[i] & 0x8))
686 continue; /* disabled */
687 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
688 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
689 }
690
691 /* clocks */
692 if (txx9_master_clock) {
693 /* calculate gbus_clock and cpu_clock from master_clock */
694 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
695 switch (divmode) {
696 case TX4938_CCFG_DIVMODE_8:
697 case TX4938_CCFG_DIVMODE_10:
698 case TX4938_CCFG_DIVMODE_12:
699 case TX4938_CCFG_DIVMODE_16:
700 case TX4938_CCFG_DIVMODE_18:
701 txx9_gbus_clock = txx9_master_clock * 4; break;
702 default:
703 txx9_gbus_clock = txx9_master_clock;
704 }
705 switch (divmode) {
706 case TX4938_CCFG_DIVMODE_2:
707 case TX4938_CCFG_DIVMODE_8:
708 cpuclk = txx9_gbus_clock * 2; break;
709 case TX4938_CCFG_DIVMODE_2_5:
710 case TX4938_CCFG_DIVMODE_10:
711 cpuclk = txx9_gbus_clock * 5 / 2; break;
712 case TX4938_CCFG_DIVMODE_3:
713 case TX4938_CCFG_DIVMODE_12:
714 cpuclk = txx9_gbus_clock * 3; break;
715 case TX4938_CCFG_DIVMODE_4:
716 case TX4938_CCFG_DIVMODE_16:
717 cpuclk = txx9_gbus_clock * 4; break;
718 case TX4938_CCFG_DIVMODE_4_5:
719 case TX4938_CCFG_DIVMODE_18:
720 cpuclk = txx9_gbus_clock * 9 / 2; break;
721 }
722 txx9_cpu_clock = cpuclk;
723 } else {
724 if (txx9_cpu_clock == 0) {
725 txx9_cpu_clock = 300000000; /* 300MHz */
726 }
727 /* calculate gbus_clock and master_clock from cpu_clock */
728 cpuclk = txx9_cpu_clock;
729 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
730 switch (divmode) {
731 case TX4938_CCFG_DIVMODE_2:
732 case TX4938_CCFG_DIVMODE_8:
733 txx9_gbus_clock = cpuclk / 2; break;
734 case TX4938_CCFG_DIVMODE_2_5:
735 case TX4938_CCFG_DIVMODE_10:
736 txx9_gbus_clock = cpuclk * 2 / 5; break;
737 case TX4938_CCFG_DIVMODE_3:
738 case TX4938_CCFG_DIVMODE_12:
739 txx9_gbus_clock = cpuclk / 3; break;
740 case TX4938_CCFG_DIVMODE_4:
741 case TX4938_CCFG_DIVMODE_16:
742 txx9_gbus_clock = cpuclk / 4; break;
743 case TX4938_CCFG_DIVMODE_4_5:
744 case TX4938_CCFG_DIVMODE_18:
745 txx9_gbus_clock = cpuclk * 2 / 9; break;
746 }
747 switch (divmode) {
748 case TX4938_CCFG_DIVMODE_8:
749 case TX4938_CCFG_DIVMODE_10:
750 case TX4938_CCFG_DIVMODE_12:
751 case TX4938_CCFG_DIVMODE_16:
752 case TX4938_CCFG_DIVMODE_18:
753 txx9_master_clock = txx9_gbus_clock / 4; break;
754 default:
755 txx9_master_clock = txx9_gbus_clock;
756 }
757 }
758 /* change default value to udelay/mdelay take reasonable time */
759 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
760
761 /* CCFG */
762 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
763 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
764 /* clear PCIC1 reset */
765 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
766 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
767
768 /* enable Timeout BusError */
769 if (tx4938_ccfg_toeon)
770 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
771
772 /* DMA selection */
773 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
774
775 /* Use external clock for external arbiter */
776 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
777 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
778
779 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
780 pcode_str,
781 cpuclk / 1000000, txx9_master_clock / 1000000,
782 (unsigned long)tx4938_ccfgptr->crir,
783 tx4938_ccfgptr->ccfg,
784 tx4938_ccfgptr->pcfg);
785
786 printk("%s SDRAMC --", pcode_str);
787 for (i = 0; i < 4; i++) {
788 unsigned long long cr = tx4938_sdramcptr->cr[i];
789 unsigned long ram_base, ram_size;
790 if (!((unsigned long)cr & 0x00000400))
791 continue; /* disabled */
792 ram_base = (unsigned long)(cr >> 49) << 21;
793 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
794 if (ram_base >= 0x20000000)
795 continue; /* high memory (ignore) */
796 printk(" CR%d:%016Lx", i, cr);
797 txboard_add_phys_region(ram_base, ram_size);
798 }
799 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
800
801 /* SRAM */
802 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
803 unsigned int size = 0x800;
804 unsigned long base =
805 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
806 txboard_add_phys_region(base, size);
807 }
808
809 /* IRC */
810 /* disable interrupt control */
811 tx4938_ircptr->cer = 0;
812
813 /* TMR */
814 /* disable all timers */
815 for (i = 0; i < TX4938_NR_TMR; i++) {
816 tx4938_tmrptr(i)->tcr = 0x00000020;
817 tx4938_tmrptr(i)->tisr = 0;
818 tx4938_tmrptr(i)->cpra = 0xffffffff;
819 tx4938_tmrptr(i)->itmr = 0;
820 tx4938_tmrptr(i)->ccdr = 0;
821 tx4938_tmrptr(i)->pgmr = 0;
822 }
823
824 /* enable DMA */
825 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
826 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
827
828 /* PIO */
829 tx4938_pioptr->maskcpu = 0;
830 tx4938_pioptr->maskext = 0;
831
832 /* TX4938 internal registers */
833 if (request_resource(&iomem_resource, &tx4938_reg_resource))
834 printk("request resource for internal registers failed\n");
835 }
836
837 #ifdef CONFIG_PCI
838 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
839 {
840 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
841 unsigned long g2pstatus = pcicptr->g2pstatus;
842 unsigned long pcicstatus = pcicptr->pcicstatus;
843 static struct {
844 unsigned long flag;
845 const char *str;
846 } pcistat_tbl[] = {
847 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
848 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
849 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
850 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
851 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
852 { PCI_STATUS_PARITY, "MasterParityError" },
853 }, g2pstat_tbl[] = {
854 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
855 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
856 }, pcicstat_tbl[] = {
857 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
858 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
859 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
860 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
861 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
862 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
863 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
864 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
865 };
866 int i;
867
868 printk("pcistat:%04x(", pcistatus);
869 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
870 if (pcistatus & pcistat_tbl[i].flag)
871 printk("%s ", pcistat_tbl[i].str);
872 printk("), g2pstatus:%08lx(", g2pstatus);
873 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
874 if (g2pstatus & g2pstat_tbl[i].flag)
875 printk("%s ", g2pstat_tbl[i].str);
876 printk("), pcicstatus:%08lx(", pcicstatus);
877 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
878 if (pcicstatus & pcicstat_tbl[i].flag)
879 printk("%s ", pcicstat_tbl[i].str);
880 printk(")\n");
881 }
882
883 void tx4938_report_pcic_status(void)
884 {
885 int i;
886 struct tx4938_pcic_reg *pcicptr;
887 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
888 tx4938_report_pcic_status1(pcicptr);
889 }
890
891 #endif /* CONFIG_PCI */
892
893 /* We use onchip r4k counter or TMR timer as our system wide timer
894 * interrupt running at 100HZ. */
895
896 extern void __init rtc_rx5c348_init(int chipid);
897 void __init rbtx4938_time_init(void)
898 {
899 rtc_rx5c348_init(RBTX4938_SRTC_CHIPID);
900 mips_hpt_frequency = txx9_cpu_clock / 2;
901 }
902
903 void __init toshiba_rbtx4938_setup(void)
904 {
905 unsigned long long pcfg;
906 char *argptr;
907
908 iomem_resource.end = 0xffffffff; /* 4GB */
909
910 if (txx9_master_clock == 0)
911 txx9_master_clock = 25000000; /* 25MHz */
912 tx4938_board_setup();
913 /* setup irq stuff */
914 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */
915 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */
916 /* setup serial stuff */
917 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
918 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
919
920 #ifndef CONFIG_PCI
921 set_io_port_base(RBTX4938_ETHER_BASE);
922 #endif
923
924 #ifdef CONFIG_SERIAL_TXX9
925 {
926 extern int early_serial_txx9_setup(struct uart_port *port);
927 int i;
928 struct uart_port req;
929 for(i = 0; i < 2; i++) {
930 memset(&req, 0, sizeof(req));
931 req.line = i;
932 req.iotype = UPIO_MEM;
933 req.membase = (char *)(0xff1ff300 + i * 0x100);
934 req.mapbase = 0xff1ff300 + i * 0x100;
935 req.irq = 32 + i;
936 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
937 req.uartclk = 50000000;
938 early_serial_txx9_setup(&req);
939 }
940 }
941 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
942 argptr = prom_getcmdline();
943 if (strstr(argptr, "console=") == NULL) {
944 strcat(argptr, " console=ttyS0,38400");
945 }
946 #endif
947 #endif
948
949 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
950 printk("PIOSEL: disabling both ata and nand selection\n");
951 local_irq_disable();
952 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
953 #endif
954
955 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
956 printk("PIOSEL: enabling nand selection\n");
957 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
958 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
959 #endif
960
961 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
962 printk("PIOSEL: enabling ata selection\n");
963 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
964 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
965 #endif
966
967 #ifdef CONFIG_IP_PNP
968 argptr = prom_getcmdline();
969 if (strstr(argptr, "ip=") == NULL) {
970 strcat(argptr, " ip=any");
971 }
972 #endif
973
974
975 #ifdef CONFIG_FB
976 {
977 conswitchp = &dummy_con;
978 }
979 #endif
980
981 rbtx4938_spi_setup();
982 pcfg = tx4938_ccfgptr->pcfg; /* updated */
983 /* fixup piosel */
984 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
985 TX4938_PCFG_ATA_SEL) {
986 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
987 }
988 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
989 TX4938_PCFG_NDF_SEL) {
990 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
991 }
992 else {
993 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
994 }
995
996 rbtx4938_fpga_resource.name = "FPGA Registers";
997 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
998 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
999 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
1000 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
1001 printk("request resource for fpga failed\n");
1002
1003 /* disable all OnBoard I/O interrupts */
1004 *rbtx4938_imask_ptr = 0;
1005
1006 _machine_restart = rbtx4938_machine_restart;
1007 _machine_halt = rbtx4938_machine_halt;
1008 pm_power_off = rbtx4938_machine_power_off;
1009
1010 *rbtx4938_led_ptr = 0xff;
1011 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
1012 printk(" DIPSW:%02x,%02x\n",
1013 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
1014 }
1015
1016 #ifdef CONFIG_PROC_FS
1017 extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid);
1018 static int __init tx4938_spi_proc_setup(void)
1019 {
1020 struct proc_dir_entry *tx4938_spi_eeprom_dir;
1021
1022 tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0);
1023
1024 if (!tx4938_spi_eeprom_dir)
1025 return -ENOMEM;
1026
1027 /* don't allow user access to RBTX4938_SEEPROM1_CHIPID
1028 * as it contains eth0 and eth1 MAC addresses
1029 */
1030 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID);
1031 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID);
1032
1033 return 0;
1034 }
1035
1036 __initcall(tx4938_spi_proc_setup);
1037 #endif
Linux with added FPC-III support