| blob | ea469eefa14603b82070efc9a7cf2cf18e52f96a |
1 /*
2 * $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $
3 *
4 * PowerPC version
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
12 *
13 * This file contains low-level assembler routines for managing
14 * the PowerPC MMU hash table. (PPC 8xx processors don't use a
15 * hash table, so this file is not used on them.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
24 #include <linux/config.h>
25 #include <asm/reg.h>
26 #include <asm/page.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
33 #ifdef CONFIG_SMP
34 .comm mmu_hash_lock,4
35 #endif /* CONFIG_SMP */
37 /*
38 * Sync CPUs with hash_page taking & releasing the hash
39 * table lock
40 */
41 #ifdef CONFIG_SMP
42 .text
43 _GLOBAL(hash_page_sync)
44 lis r8,mmu_hash_lock@h
45 ori r8,r8,mmu_hash_lock@l
46 lis r0,0x0fff
47 b 10f
48 11: lwz r6,0(r8)
49 cmpwi 0,r6,0
50 bne 11b
51 10: lwarx r6,0,r8
52 cmpwi 0,r6,0
53 bne- 11b
54 stwcx. r0,0,r8
55 bne- 10b
56 isync
57 eieio
58 li r0,0
59 stw r0,0(r8)
60 blr
61 #endif
63 /*
64 * Load a PTE into the hash table, if possible.
65 * The address is in r4, and r3 contains an access flag:
66 * _PAGE_RW (0x400) if a write.
67 * r9 contains the SRR1 value, from which we use the MSR_PR bit.
68 * SPRG3 contains the physical address of the current task's thread.
69 *
70 * Returns to the caller if the access is illegal or there is no
71 * mapping for the address. Otherwise it places an appropriate PTE
72 * in the hash table and returns from the exception.
73 * Uses r0, r3 - r8, ctr, lr.
74 */
75 .text
76 _GLOBAL(hash_page)
77 #ifdef CONFIG_PPC64BRIDGE
78 mfmsr r0
79 clrldi r0,r0,1 /* make sure it's in 32-bit mode */
80 MTMSRD(r0)
81 isync
82 #endif
83 tophys(r7,0) /* gets -KERNELBASE into r7 */
84 #ifdef CONFIG_SMP
85 addis r8,r7,mmu_hash_lock@h
86 ori r8,r8,mmu_hash_lock@l
87 lis r0,0x0fff
88 b 10f
89 11: lwz r6,0(r8)
90 cmpwi 0,r6,0
91 bne 11b
92 10: lwarx r6,0,r8
93 cmpwi 0,r6,0
94 bne- 11b
95 stwcx. r0,0,r8
96 bne- 10b
97 isync
98 #endif
99 /* Get PTE (linux-style) and check access */
100 lis r0,KERNELBASE@h /* check if kernel address */
101 cmplw 0,r4,r0
102 mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */
103 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
104 lwz r5,PGDIR(r8) /* virt page-table root */
105 blt+ 112f /* assume user more likely */
106 lis r5,swapper_pg_dir@ha /* if kernel address, use */
107 addi r5,r5,swapper_pg_dir@l /* kernel page table */
108 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
109 112: add r5,r5,r7 /* convert to phys addr */
110 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
111 lwz r8,0(r5) /* get pmd entry */
112 rlwinm. r8,r8,0,0,19 /* extract address of pte page */
113 #ifdef CONFIG_SMP
114 beq- hash_page_out /* return if no mapping */
115 #else
116 /* XXX it seems like the 601 will give a machine fault on the
117 rfi if its alignment is wrong (bottom 4 bits of address are
118 8 or 0xc) and we have had a not-taken conditional branch
119 to the address following the rfi. */
120 beqlr-
121 #endif
122 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
123 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
124 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
126 /*
127 * Update the linux PTE atomically. We do the lwarx up-front
128 * because almost always, there won't be a permission violation
129 * and there won't already be an HPTE, and thus we will have
130 * to update the PTE to set _PAGE_HASHPTE. -- paulus.
131 */
132 retry:
133 lwarx r6,0,r8 /* get linux-style pte */
134 andc. r5,r3,r6 /* check access & ~permission */
135 #ifdef CONFIG_SMP
136 bne- hash_page_out /* return if access not permitted */
137 #else
138 bnelr-
139 #endif
140 or r5,r0,r6 /* set accessed/dirty bits */
141 stwcx. r5,0,r8 /* attempt to update PTE */
142 bne- retry /* retry if someone got there first */
144 mfsrin r3,r4 /* get segment reg for segment */
145 mfctr r0
146 stw r0,_CTR(r11)
147 bl create_hpte /* add the hash table entry */
149 #ifdef CONFIG_SMP
150 eieio
151 addis r8,r7,mmu_hash_lock@ha
152 li r0,0
153 stw r0,mmu_hash_lock@l(r8)
154 #endif
156 /* Return from the exception */
157 lwz r5,_CTR(r11)
158 mtctr r5
159 lwz r0,GPR0(r11)
160 lwz r7,GPR7(r11)
161 lwz r8,GPR8(r11)
162 b fast_exception_return
164 #ifdef CONFIG_SMP
165 hash_page_out:
166 eieio
167 addis r8,r7,mmu_hash_lock@ha
168 li r0,0
169 stw r0,mmu_hash_lock@l(r8)
170 blr
171 #endif /* CONFIG_SMP */
173 /*
174 * Add an entry for a particular page to the hash table.
175 *
176 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
177 *
178 * We assume any necessary modifications to the pte (e.g. setting
179 * the accessed bit) have already been done and that there is actually
180 * a hash table in use (i.e. we're not on a 603).
181 */
182 _GLOBAL(add_hash_page)
183 mflr r0
184 stw r0,4(r1)
186 /* Convert context and va to VSID */
187 mulli r3,r3,897*16 /* multiply context by context skew */
188 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
189 mulli r0,r0,0x111 /* multiply by ESID skew */
190 add r3,r3,r0 /* note create_hpte trims to 24 bits */
192 #ifdef CONFIG_SMP
193 rlwinm r8,r1,0,0,18 /* use cpu number to make tag */
194 lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */
195 oris r8,r8,12
196 #endif /* CONFIG_SMP */
198 /*
199 * We disable interrupts here, even on UP, because we don't
200 * want to race with hash_page, and because we want the
201 * _PAGE_HASHPTE bit to be a reliable indication of whether
202 * the HPTE exists (or at least whether one did once).
203 * We also turn off the MMU for data accesses so that we
204 * we can't take a hash table miss (assuming the code is
205 * covered by a BAT). -- paulus
206 */
207 mfmsr r10
208 SYNC
209 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
210 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
211 mtmsr r0
212 SYNC_601
213 isync
215 tophys(r7,0)
217 #ifdef CONFIG_SMP
218 addis r9,r7,mmu_hash_lock@ha
219 addi r9,r9,mmu_hash_lock@l
220 10: lwarx r0,0,r9 /* take the mmu_hash_lock */
221 cmpi 0,r0,0
222 bne- 11f
223 stwcx. r8,0,r9
224 beq+ 12f
225 11: lwz r0,0(r9)
226 cmpi 0,r0,0
227 beq 10b
228 b 11b
229 12: isync
230 #endif
232 /*
233 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
234 * If _PAGE_HASHPTE was already set, we don't replace the existing
235 * HPTE, so we just unlock and return.
236 */
237 mr r8,r5
238 rlwimi r8,r4,22,20,29
239 1: lwarx r6,0,r8
240 andi. r0,r6,_PAGE_HASHPTE
241 bne 9f /* if HASHPTE already set, done */
242 ori r5,r6,_PAGE_HASHPTE
243 stwcx. r5,0,r8
244 bne- 1b
246 bl create_hpte
248 9:
249 #ifdef CONFIG_SMP
250 eieio
251 li r0,0
252 stw r0,0(r9) /* clear mmu_hash_lock */
253 #endif
255 /* reenable interrupts and DR */
256 mtmsr r10
257 SYNC_601
258 isync
260 lwz r0,4(r1)
261 mtlr r0
262 blr
264 /*
265 * This routine adds a hardware PTE to the hash table.
266 * It is designed to be called with the MMU either on or off.
267 * r3 contains the VSID, r4 contains the virtual address,
268 * r5 contains the linux PTE, r6 contains the old value of the
269 * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
270 * offset to be added to addresses (0 if the MMU is on,
271 * -KERNELBASE if it is off).
272 * On SMP, the caller should have the mmu_hash_lock held.
273 * We assume that the caller has (or will) set the _PAGE_HASHPTE
274 * bit in the linux PTE in memory. The value passed in r6 should
275 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
276 * this routine will skip the search for an existing HPTE.
277 * This procedure modifies r0, r3 - r6, r8, cr0.
278 * -- paulus.
279 *
280 * For speed, 4 of the instructions get patched once the size and
281 * physical address of the hash table are known. These definitions
282 * of Hash_base and Hash_bits below are just an example.
283 */
284 Hash_base = 0xc0180000
285 Hash_bits = 12 /* e.g. 256kB hash table */
286 Hash_msk = (((1 << Hash_bits) - 1) * 64)
288 #ifndef CONFIG_PPC64BRIDGE
289 /* defines for the PTE format for 32-bit PPCs */
290 #define PTE_SIZE 8
291 #define PTEG_SIZE 64
292 #define LG_PTEG_SIZE 6
293 #define LDPTEu lwzu
294 #define STPTE stw
295 #define CMPPTE cmpw
296 #define PTE_H 0x40
297 #define PTE_V 0x80000000
298 #define TST_V(r) rlwinm. r,r,0,0,0
299 #define SET_V(r) oris r,r,PTE_V@h
300 #define CLR_V(r,t) rlwinm r,r,0,1,31
302 #else
303 /* defines for the PTE format for 64-bit PPCs */
304 #define PTE_SIZE 16
305 #define PTEG_SIZE 128
306 #define LG_PTEG_SIZE 7
307 #define LDPTEu ldu
308 #define STPTE std
309 #define CMPPTE cmpd
310 #define PTE_H 2
311 #define PTE_V 1
312 #define TST_V(r) andi. r,r,PTE_V
313 #define SET_V(r) ori r,r,PTE_V
314 #define CLR_V(r,t) li t,PTE_V; andc r,r,t
315 #endif /* CONFIG_PPC64BRIDGE */
317 #define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
318 #define HASH_RIGHT 31-LG_PTEG_SIZE
320 _GLOBAL(create_hpte)
321 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
322 rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */
323 rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
324 and r8,r8,r0 /* writable if _RW & _DIRTY */
325 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
326 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
327 ori r8,r8,0xe14 /* clear out reserved bits and M */
328 andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
329 BEGIN_FTR_SECTION
330 ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */
331 END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
333 /* Construct the high word of the PPC-style PTE (r5) */
334 #ifndef CONFIG_PPC64BRIDGE
335 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
336 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
337 #else /* CONFIG_PPC64BRIDGE */
338 clrlwi r3,r3,8 /* reduce vsid to 24 bits */
339 sldi r5,r3,12 /* shift vsid into position */
340 rlwimi r5,r4,16,20,24 /* put in API (abbrev page index) */
341 #endif /* CONFIG_PPC64BRIDGE */
342 SET_V(r5) /* set V (valid) bit */
344 /* Get the address of the primary PTE group in the hash table (r3) */
345 _GLOBAL(hash_page_patch_A)
346 addis r0,r7,Hash_base@h /* base address of hash table */
347 rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
348 rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
349 xor r3,r3,r0 /* make primary hash */
350 li r0,8 /* PTEs/group */
352 /*
353 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
354 * if it is clear, meaning that the HPTE isn't there already...
355 */
356 andi. r6,r6,_PAGE_HASHPTE
357 beq+ 10f /* no PTE: go look for an empty slot */
358 tlbie r4
360 addis r4,r7,htab_hash_searches@ha
361 lwz r6,htab_hash_searches@l(r4)
362 addi r6,r6,1 /* count how many searches we do */
363 stw r6,htab_hash_searches@l(r4)
365 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
366 mtctr r0
367 addi r4,r3,-PTE_SIZE
368 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
369 CMPPTE 0,r6,r5
370 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
371 beq+ found_slot
373 /* Search the secondary PTEG for a matching PTE */
374 ori r5,r5,PTE_H /* set H (secondary hash) bit */
375 _GLOBAL(hash_page_patch_B)
376 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
377 xori r4,r4,(-PTEG_SIZE & 0xffff)
378 addi r4,r4,-PTE_SIZE
379 mtctr r0
380 2: LDPTEu r6,PTE_SIZE(r4)
381 CMPPTE 0,r6,r5
382 bdnzf 2,2b
383 beq+ found_slot
384 xori r5,r5,PTE_H /* clear H bit again */
386 /* Search the primary PTEG for an empty slot */
387 10: mtctr r0
388 addi r4,r3,-PTE_SIZE /* search primary PTEG */
389 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
390 TST_V(r6) /* test valid bit */
391 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
392 beq+ found_empty
394 /* update counter of times that the primary PTEG is full */
395 addis r4,r7,primary_pteg_full@ha
396 lwz r6,primary_pteg_full@l(r4)
397 addi r6,r6,1
398 stw r6,primary_pteg_full@l(r4)
400 /* Search the secondary PTEG for an empty slot */
401 ori r5,r5,PTE_H /* set H (secondary hash) bit */
402 _GLOBAL(hash_page_patch_C)
403 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
404 xori r4,r4,(-PTEG_SIZE & 0xffff)
405 addi r4,r4,-PTE_SIZE
406 mtctr r0
407 2: LDPTEu r6,PTE_SIZE(r4)
408 TST_V(r6)
409 bdnzf 2,2b
410 beq+ found_empty
411 xori r5,r5,PTE_H /* clear H bit again */
413 /*
414 * Choose an arbitrary slot in the primary PTEG to overwrite.
415 * Since both the primary and secondary PTEGs are full, and we
416 * have no information that the PTEs in the primary PTEG are
417 * more important or useful than those in the secondary PTEG,
418 * and we know there is a definite (although small) speed
419 * advantage to putting the PTE in the primary PTEG, we always
420 * put the PTE in the primary PTEG.
421 */
422 addis r4,r7,next_slot@ha
423 lwz r6,next_slot@l(r4)
424 addi r6,r6,PTE_SIZE
425 andi. r6,r6,7*PTE_SIZE
426 stw r6,next_slot@l(r4)
427 add r4,r3,r6
429 #ifndef CONFIG_SMP
430 /* Store PTE in PTEG */
431 found_empty:
432 STPTE r5,0(r4)
433 found_slot:
434 STPTE r8,PTE_SIZE/2(r4)
436 #else /* CONFIG_SMP */
437 /*
438 * Between the tlbie above and updating the hash table entry below,
439 * another CPU could read the hash table entry and put it in its TLB.
440 * There are 3 cases:
441 * 1. using an empty slot
442 * 2. updating an earlier entry to change permissions (i.e. enable write)
443 * 3. taking over the PTE for an unrelated address
444 *
445 * In each case it doesn't really matter if the other CPUs have the old
446 * PTE in their TLB. So we don't need to bother with another tlbie here,
447 * which is convenient as we've overwritten the register that had the
448 * address. :-) The tlbie above is mainly to make sure that this CPU comes
449 * and gets the new PTE from the hash table.
450 *
451 * We do however have to make sure that the PTE is never in an invalid
452 * state with the V bit set.
453 */
454 found_empty:
455 found_slot:
456 CLR_V(r5,r0) /* clear V (valid) bit in PTE */
457 STPTE r5,0(r4)
458 sync
459 TLBSYNC
460 STPTE r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
461 sync
462 SET_V(r5)
463 STPTE r5,0(r4) /* finally set V bit in PTE */
464 #endif /* CONFIG_SMP */
466 sync /* make sure pte updates get to memory */
467 blr
469 .comm next_slot,4
470 .comm primary_pteg_full,4
471 .comm htab_hash_searches,4
473 /*
474 * Flush the entry for a particular page from the hash table.
475 *
476 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
477 * int count)
478 *
479 * We assume that there is a hash table in use (Hash != 0).
480 */
481 _GLOBAL(flush_hash_pages)
482 tophys(r7,0)
484 /*
485 * We disable interrupts here, even on UP, because we want
486 * the _PAGE_HASHPTE bit to be a reliable indication of
487 * whether the HPTE exists (or at least whether one did once).
488 * We also turn off the MMU for data accesses so that we
489 * we can't take a hash table miss (assuming the code is
490 * covered by a BAT). -- paulus
491 */
492 mfmsr r10
493 SYNC
494 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
495 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
496 mtmsr r0
497 SYNC_601
498 isync
500 /* First find a PTE in the range that has _PAGE_HASHPTE set */
501 rlwimi r5,r4,22,20,29
502 1: lwz r0,0(r5)
503 cmpwi cr1,r6,1
504 andi. r0,r0,_PAGE_HASHPTE
505 bne 2f
506 ble cr1,19f
507 addi r4,r4,0x1000
508 addi r5,r5,4
509 addi r6,r6,-1
510 b 1b
512 /* Convert context and va to VSID */
513 2: mulli r3,r3,897*16 /* multiply context by context skew */
514 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
515 mulli r0,r0,0x111 /* multiply by ESID skew */
516 add r3,r3,r0 /* note code below trims to 24 bits */
518 /* Construct the high word of the PPC-style PTE (r11) */
519 #ifndef CONFIG_PPC64BRIDGE
520 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
521 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
522 #else /* CONFIG_PPC64BRIDGE */
523 clrlwi r3,r3,8 /* reduce vsid to 24 bits */
524 sldi r11,r3,12 /* shift vsid into position */
525 rlwimi r11,r4,16,20,24 /* put in API (abbrev page index) */
526 #endif /* CONFIG_PPC64BRIDGE */
527 SET_V(r11) /* set V (valid) bit */
529 #ifdef CONFIG_SMP
530 addis r9,r7,mmu_hash_lock@ha
531 addi r9,r9,mmu_hash_lock@l
532 rlwinm r8,r1,0,0,18
533 add r8,r8,r7
534 lwz r8,TI_CPU(r8)
535 oris r8,r8,9
536 10: lwarx r0,0,r9
537 cmpi 0,r0,0
538 bne- 11f
539 stwcx. r8,0,r9
540 beq+ 12f
541 11: lwz r0,0(r9)
542 cmpi 0,r0,0
543 beq 10b
544 b 11b
545 12: isync
546 #endif
548 /*
549 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is
550 * already clear, we're done (for this pte). If not,
551 * clear it (atomically) and proceed. -- paulus.
552 */
553 33: lwarx r8,0,r5 /* fetch the pte */
554 andi. r0,r8,_PAGE_HASHPTE
555 beq 8f /* done if HASHPTE is already clear */
556 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
557 stwcx. r8,0,r5 /* update the pte */
558 bne- 33b
560 /* Get the address of the primary PTE group in the hash table (r3) */
561 _GLOBAL(flush_hash_patch_A)
562 addis r8,r7,Hash_base@h /* base address of hash table */
563 rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
564 rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
565 xor r8,r0,r8 /* make primary hash */
567 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
568 li r0,8 /* PTEs/group */
569 mtctr r0
570 addi r12,r8,-PTE_SIZE
571 1: LDPTEu r0,PTE_SIZE(r12) /* get next PTE */
572 CMPPTE 0,r0,r11
573 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
574 beq+ 3f
576 /* Search the secondary PTEG for a matching PTE */
577 ori r11,r11,PTE_H /* set H (secondary hash) bit */
578 li r0,8 /* PTEs/group */
579 _GLOBAL(flush_hash_patch_B)
580 xoris r12,r8,Hash_msk>>16 /* compute secondary hash */
581 xori r12,r12,(-PTEG_SIZE & 0xffff)
582 addi r12,r12,-PTE_SIZE
583 mtctr r0
584 2: LDPTEu r0,PTE_SIZE(r12)
585 CMPPTE 0,r0,r11
586 bdnzf 2,2b
587 xori r11,r11,PTE_H /* clear H again */
588 bne- 4f /* should rarely fail to find it */
590 3: li r0,0
591 STPTE r0,0(r12) /* invalidate entry */
592 4: sync
593 tlbie r4 /* in hw tlb too */
594 sync
596 8: ble cr1,9f /* if all ptes checked */
597 81: addi r6,r6,-1
598 addi r5,r5,4 /* advance to next pte */
599 addi r4,r4,0x1000
600 lwz r0,0(r5) /* check next pte */
601 cmpwi cr1,r6,1
602 andi. r0,r0,_PAGE_HASHPTE
603 bne 33b
604 bgt cr1,81b
606 9:
607 #ifdef CONFIG_SMP
608 TLBSYNC
609 li r0,0
610 stw r0,0(r9) /* clear mmu_hash_lock */
611 #endif
613 19: mtmsr r10
614 SYNC_601
615 isync
616 blr