| blob | 31d0a924317c7d94a6f7c87a6d23225e5b79205f |
1 /*
2 * $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $
3 *
4 * PowerPC version
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
12 *
13 * This file contains low-level assembler routines for managing
14 * the PowerPC MMU hash table. (PPC 8xx processors don't use a
15 * hash table, so this file is not used on them.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
24 #include <linux/config.h>
25 #include <asm/processor.h>
26 #include <asm/page.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
33 #ifdef CONFIG_SMP
34 .comm mmu_hash_lock,4
35 #endif /* CONFIG_SMP */
37 /*
38 * Sync CPUs with hash_page taking & releasing the hash
39 * table lock
40 */
41 #ifdef CONFIG_SMP
42 .text
43 _GLOBAL(hash_page_sync)
44 lis r8,mmu_hash_lock@h
45 ori r8,r8,mmu_hash_lock@l
46 lis r0,0x0fff
47 b 10f
48 11: lwz r6,0(r8)
49 cmpwi 0,r6,0
50 bne 11b
51 10: lwarx r6,0,r8
52 cmpwi 0,r6,0
53 bne- 11b
54 stwcx. r0,0,r8
55 bne- 10b
56 isync
57 eieio
58 li r0,0
59 stw r0,0(r8)
60 blr
61 #endif
63 /*
64 * Load a PTE into the hash table, if possible.
65 * The address is in r4, and r3 contains an access flag:
66 * _PAGE_RW (0x400) if a write.
67 * r9 contains the SRR1 value, from which we use the MSR_PR bit.
68 * SPRG3 contains the physical address of the current task's thread.
69 *
70 * Returns to the caller if the access is illegal or there is no
71 * mapping for the address. Otherwise it places an appropriate PTE
72 * in the hash table and returns from the exception.
73 * Uses r0, r3 - r8, ctr, lr.
74 */
75 .text
76 _GLOBAL(hash_page)
77 tophys(r7,0) /* gets -KERNELBASE into r7 */
78 #ifdef CONFIG_SMP
79 addis r8,r7,mmu_hash_lock@h
80 ori r8,r8,mmu_hash_lock@l
81 lis r0,0x0fff
82 b 10f
83 11: lwz r6,0(r8)
84 cmpwi 0,r6,0
85 bne 11b
86 10: lwarx r6,0,r8
87 cmpwi 0,r6,0
88 bne- 11b
89 stwcx. r0,0,r8
90 bne- 10b
91 isync
92 #endif
93 /* Get PTE (linux-style) and check access */
94 lis r0,KERNELBASE@h /* check if kernel address */
95 cmplw 0,r4,r0
96 mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */
97 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
98 lwz r5,PGDIR(r8) /* virt page-table root */
99 blt+ 112f /* assume user more likely */
100 lis r5,swapper_pg_dir@ha /* if kernel address, use */
101 addi r5,r5,swapper_pg_dir@l /* kernel page table */
102 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
103 112: add r5,r5,r7 /* convert to phys addr */
104 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
105 lwz r8,0(r5) /* get pmd entry */
106 rlwinm. r8,r8,0,0,19 /* extract address of pte page */
107 #ifdef CONFIG_SMP
108 beq- hash_page_out /* return if no mapping */
109 #else
110 /* XXX it seems like the 601 will give a machine fault on the
111 rfi if its alignment is wrong (bottom 4 bits of address are
112 8 or 0xc) and we have had a not-taken conditional branch
113 to the address following the rfi. */
114 beqlr-
115 #endif
116 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
117 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
118 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
120 /*
121 * Update the linux PTE atomically. We do the lwarx up-front
122 * because almost always, there won't be a permission violation
123 * and there won't already be an HPTE, and thus we will have
124 * to update the PTE to set _PAGE_HASHPTE. -- paulus.
125 */
126 retry:
127 lwarx r6,0,r8 /* get linux-style pte */
128 andc. r5,r3,r6 /* check access & ~permission */
129 #ifdef CONFIG_SMP
130 bne- hash_page_out /* return if access not permitted */
131 #else
132 bnelr-
133 #endif
134 or r5,r0,r6 /* set accessed/dirty bits */
135 stwcx. r5,0,r8 /* attempt to update PTE */
136 bne- retry /* retry if someone got there first */
138 mfsrin r3,r4 /* get segment reg for segment */
139 mfctr r0
140 stw r0,_CTR(r11)
141 bl create_hpte /* add the hash table entry */
143 /*
144 * htab_reloads counts the number of times we have to fault an
145 * HPTE into the hash table. This should only happen after a
146 * fork (because fork does a flush_tlb_mm) or a vmalloc or ioremap.
147 * Where a page is faulted into a process's address space,
148 * update_mmu_cache gets called to put the HPTE into the hash table
149 * and those are counted as preloads rather than reloads.
150 */
151 addis r8,r7,htab_reloads@ha
152 lwz r3,htab_reloads@l(r8)
153 addi r3,r3,1
154 stw r3,htab_reloads@l(r8)
156 #ifdef CONFIG_SMP
157 eieio
158 addis r8,r7,mmu_hash_lock@ha
159 li r0,0
160 stw r0,mmu_hash_lock@l(r8)
161 #endif
163 /* Return from the exception */
164 lwz r5,_CTR(r11)
165 mtctr r5
166 lwz r0,GPR0(r11)
167 lwz r7,GPR7(r11)
168 lwz r8,GPR8(r11)
169 b fast_exception_return
171 #ifdef CONFIG_SMP
172 hash_page_out:
173 eieio
174 addis r8,r7,mmu_hash_lock@ha
175 li r0,0
176 stw r0,mmu_hash_lock@l(r8)
177 blr
178 #endif /* CONFIG_SMP */
180 /*
181 * Add an entry for a particular page to the hash table.
182 *
183 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
184 *
185 * We assume any necessary modifications to the pte (e.g. setting
186 * the accessed bit) have already been done and that there is actually
187 * a hash table in use (i.e. we're not on a 603).
188 */
189 _GLOBAL(add_hash_page)
190 mflr r0
191 stw r0,4(r1)
193 /* Convert context and va to VSID */
194 mulli r3,r3,897*16 /* multiply context by context skew */
195 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
196 mulli r0,r0,0x111 /* multiply by ESID skew */
197 add r3,r3,r0 /* note create_hpte trims to 24 bits */
199 #ifdef CONFIG_SMP
200 rlwinm r8,r1,0,0,18 /* use cpu number to make tag */
201 lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */
202 oris r8,r8,12
203 #endif /* CONFIG_SMP */
205 /*
206 * We disable interrupts here, even on UP, because we don't
207 * want to race with hash_page, and because we want the
208 * _PAGE_HASHPTE bit to be a reliable indication of whether
209 * the HPTE exists (or at least whether one did once).
210 * We also turn off the MMU for data accesses so that we
211 * we can't take a hash table miss (assuming the code is
212 * covered by a BAT). -- paulus
213 */
214 mfmsr r10
215 SYNC
216 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
217 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
218 mtmsr r0
219 SYNC_601
220 isync
222 tophys(r7,0)
224 #ifdef CONFIG_SMP
225 addis r9,r7,mmu_hash_lock@ha
226 addi r9,r9,mmu_hash_lock@l
227 10: lwarx r0,0,r9 /* take the mmu_hash_lock */
228 cmpi 0,r0,0
229 bne- 11f
230 stwcx. r8,0,r9
231 beq+ 12f
232 11: lwz r0,0(r9)
233 cmpi 0,r0,0
234 beq 10b
235 b 11b
236 12: isync
237 #endif
239 /*
240 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
241 * If _PAGE_HASHPTE was already set, we don't replace the existing
242 * HPTE, so we just unlock and return.
243 */
244 mr r8,r5
245 rlwimi r8,r4,22,20,29
246 1: lwarx r6,0,r8
247 andi. r0,r6,_PAGE_HASHPTE
248 bne 9f /* if HASHPTE already set, done */
249 ori r5,r6,_PAGE_HASHPTE
250 stwcx. r5,0,r8
251 bne- 1b
253 bl create_hpte
255 addis r8,r7,htab_preloads@ha
256 lwz r3,htab_preloads@l(r8)
257 addi r3,r3,1
258 stw r3,htab_preloads@l(r8)
260 9:
261 #ifdef CONFIG_SMP
262 eieio
263 li r0,0
264 stw r0,0(r9) /* clear mmu_hash_lock */
265 #endif
267 /* reenable interrupts and DR */
268 mtmsr r10
269 SYNC_601
270 isync
272 lwz r0,4(r1)
273 mtlr r0
274 blr
276 /*
277 * This routine adds a hardware PTE to the hash table.
278 * It is designed to be called with the MMU either on or off.
279 * r3 contains the VSID, r4 contains the virtual address,
280 * r5 contains the linux PTE, r6 contains the old value of the
281 * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
282 * offset to be added to addresses (0 if the MMU is on,
283 * -KERNELBASE if it is off).
284 * On SMP, the caller should have the mmu_hash_lock held.
285 * We assume that the caller has (or will) set the _PAGE_HASHPTE
286 * bit in the linux PTE in memory. The value passed in r6 should
287 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
288 * this routine will skip the search for an existing HPTE.
289 * This procedure modifies r0, r3 - r6, r8, cr0.
290 * -- paulus.
291 *
292 * For speed, 4 of the instructions get patched once the size and
293 * physical address of the hash table are known. These definitions
294 * of Hash_base and Hash_bits below are just an example.
295 */
296 Hash_base = 0xc0180000
297 Hash_bits = 12 /* e.g. 256kB hash table */
298 Hash_msk = (((1 << Hash_bits) - 1) * 64)
300 /* defines for the PTE format for 32-bit PPCs */
301 #define PTE_SIZE 8
302 #define PTEG_SIZE 64
303 #define LG_PTEG_SIZE 6
304 #define LDPTEu lwzu
305 #define STPTE stw
306 #define CMPPTE cmpw
307 #define PTE_H 0x40
308 #define PTE_V 0x80000000
309 #define TST_V(r) rlwinm. r,r,0,0,0
310 #define SET_V(r) oris r,r,PTE_V@h
311 #define CLR_V(r,t) rlwinm r,r,0,1,31
313 #define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
314 #define HASH_RIGHT 31-LG_PTEG_SIZE
316 _GLOBAL(create_hpte)
317 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
318 rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */
319 rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
320 and r8,r8,r0 /* writable if _RW & _DIRTY */
321 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
322 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
323 ori r8,r8,0xe14 /* clear out reserved bits and M */
324 andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
325 BEGIN_FTR_SECTION
326 ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */
327 END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
329 /* Construct the high word of the PPC-style PTE (r5) */
330 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
331 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
332 SET_V(r5) /* set V (valid) bit */
334 /* Get the address of the primary PTE group in the hash table (r3) */
335 _GLOBAL(hash_page_patch_A)
336 addis r0,r7,Hash_base@h /* base address of hash table */
337 rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
338 rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
339 xor r3,r3,r0 /* make primary hash */
340 li r0,8 /* PTEs/group */
342 /*
343 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
344 * if it is clear, meaning that the HPTE isn't there already...
345 */
346 andi. r6,r6,_PAGE_HASHPTE
347 beq+ 10f /* no PTE: go look for an empty slot */
348 tlbie r4
350 addis r4,r7,htab_hash_searches@ha
351 lwz r6,htab_hash_searches@l(r4)
352 addi r6,r6,1 /* count how many searches we do */
353 stw r6,htab_hash_searches@l(r4)
355 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
356 mtctr r0
357 addi r4,r3,-PTE_SIZE
358 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
359 CMPPTE 0,r6,r5
360 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
361 beq+ found_slot
363 /* Search the secondary PTEG for a matching PTE */
364 ori r5,r5,PTE_H /* set H (secondary hash) bit */
365 _GLOBAL(hash_page_patch_B)
366 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
367 xori r4,r4,(-PTEG_SIZE & 0xffff)
368 addi r4,r4,-PTE_SIZE
369 mtctr r0
370 2: LDPTEu r6,PTE_SIZE(r4)
371 CMPPTE 0,r6,r5
372 bdnzf 2,2b
373 beq+ found_slot
374 xori r5,r5,PTE_H /* clear H bit again */
376 /* Search the primary PTEG for an empty slot */
377 10: mtctr r0
378 addi r4,r3,-PTE_SIZE /* search primary PTEG */
379 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
380 TST_V(r6) /* test valid bit */
381 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
382 beq+ found_empty
384 /* update counter of times that the primary PTEG is full */
385 addis r4,r7,primary_pteg_full@ha
386 lwz r6,primary_pteg_full@l(r4)
387 addi r6,r6,1
388 stw r6,primary_pteg_full@l(r4)
390 /* Search the secondary PTEG for an empty slot */
391 ori r5,r5,PTE_H /* set H (secondary hash) bit */
392 _GLOBAL(hash_page_patch_C)
393 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
394 xori r4,r4,(-PTEG_SIZE & 0xffff)
395 addi r4,r4,-PTE_SIZE
396 mtctr r0
397 2: LDPTEu r6,PTE_SIZE(r4)
398 TST_V(r6)
399 bdnzf 2,2b
400 beq+ found_empty
401 xori r5,r5,PTE_H /* clear H bit again */
403 /*
404 * Choose an arbitrary slot in the primary PTEG to overwrite.
405 * Since both the primary and secondary PTEGs are full, and we
406 * have no information that the PTEs in the primary PTEG are
407 * more important or useful than those in the secondary PTEG,
408 * and we know there is a definite (although small) speed
409 * advantage to putting the PTE in the primary PTEG, we always
410 * put the PTE in the primary PTEG.
411 */
412 addis r4,r7,next_slot@ha
413 lwz r6,next_slot@l(r4)
414 addi r6,r6,PTE_SIZE
415 andi. r6,r6,7*PTE_SIZE
416 stw r6,next_slot@l(r4)
417 add r4,r3,r6
419 /* update counter of evicted pages */
420 addis r6,r7,htab_evicts@ha
421 lwz r3,htab_evicts@l(r6)
422 addi r3,r3,1
423 stw r3,htab_evicts@l(r6)
425 #ifndef CONFIG_SMP
426 /* Store PTE in PTEG */
427 found_empty:
428 STPTE r5,0(r4)
429 found_slot:
430 STPTE r8,PTE_SIZE/2(r4)
432 #else /* CONFIG_SMP */
433 /*
434 * Between the tlbie above and updating the hash table entry below,
435 * another CPU could read the hash table entry and put it in its TLB.
436 * There are 3 cases:
437 * 1. using an empty slot
438 * 2. updating an earlier entry to change permissions (i.e. enable write)
439 * 3. taking over the PTE for an unrelated address
440 *
441 * In each case it doesn't really matter if the other CPUs have the old
442 * PTE in their TLB. So we don't need to bother with another tlbie here,
443 * which is convenient as we've overwritten the register that had the
444 * address. :-) The tlbie above is mainly to make sure that this CPU comes
445 * and gets the new PTE from the hash table.
446 *
447 * We do however have to make sure that the PTE is never in an invalid
448 * state with the V bit set.
449 */
450 found_empty:
451 found_slot:
452 CLR_V(r5,r0) /* clear V (valid) bit in PTE */
453 STPTE r5,0(r4)
454 sync
455 TLBSYNC
456 STPTE r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
457 sync
458 SET_V(r5)
459 STPTE r5,0(r4) /* finally set V bit in PTE */
460 #endif /* CONFIG_SMP */
462 sync /* make sure pte updates get to memory */
463 blr
465 .comm next_slot,4
466 .comm primary_pteg_full,4
467 .comm htab_hash_searches,4
469 /*
470 * Flush the entry for a particular page from the hash table.
471 *
472 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
473 * int count)
474 *
475 * We assume that there is a hash table in use (Hash != 0).
476 */
477 _GLOBAL(flush_hash_pages)
478 tophys(r7,0)
480 /*
481 * We disable interrupts here, even on UP, because we want
482 * the _PAGE_HASHPTE bit to be a reliable indication of
483 * whether the HPTE exists (or at least whether one did once).
484 * We also turn off the MMU for data accesses so that we
485 * we can't take a hash table miss (assuming the code is
486 * covered by a BAT). -- paulus
487 */
488 mfmsr r10
489 SYNC
490 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
491 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
492 mtmsr r0
493 SYNC_601
494 isync
496 /* First find a PTE in the range that has _PAGE_HASHPTE set */
497 rlwimi r5,r4,22,20,29
498 1: lwz r0,0(r5)
499 cmpwi cr1,r6,1
500 andi. r0,r0,_PAGE_HASHPTE
501 bne 2f
502 ble cr1,19f
503 addi r4,r4,0x1000
504 addi r5,r5,4
505 addi r6,r6,-1
506 b 1b
508 /* Convert context and va to VSID */
509 2: mulli r3,r3,897*16 /* multiply context by context skew */
510 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
511 mulli r0,r0,0x111 /* multiply by ESID skew */
512 add r3,r3,r0 /* note code below trims to 24 bits */
514 /* Construct the high word of the PPC-style PTE (r11) */
515 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
516 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
517 SET_V(r11) /* set V (valid) bit */
519 #ifdef CONFIG_SMP
520 addis r9,r7,mmu_hash_lock@ha
521 addi r9,r9,mmu_hash_lock@l
522 rlwinm r8,r1,0,0,18
523 add r8,r8,r7
524 lwz r8,TI_CPU(r8)
525 oris r8,r8,9
526 10: lwarx r0,0,r9
527 cmpi 0,r0,0
528 bne- 11f
529 stwcx. r8,0,r9
530 beq+ 12f
531 11: lwz r0,0(r9)
532 cmpi 0,r0,0
533 beq 10b
534 b 11b
535 12: isync
536 #endif
538 /*
539 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is
540 * already clear, we're done (for this pte). If not,
541 * clear it (atomically) and proceed. -- paulus.
542 */
543 33: lwarx r8,0,r5 /* fetch the pte */
544 andi. r0,r8,_PAGE_HASHPTE
545 beq 8f /* done if HASHPTE is already clear */
546 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
547 stwcx. r8,0,r5 /* update the pte */
548 bne- 33b
550 /* Get the address of the primary PTE group in the hash table (r3) */
551 _GLOBAL(flush_hash_patch_A)
552 addis r8,r7,Hash_base@h /* base address of hash table */
553 rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
554 rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
555 xor r8,r0,r8 /* make primary hash */
557 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
558 li r0,8 /* PTEs/group */
559 mtctr r0
560 addi r12,r8,-PTE_SIZE
561 1: LDPTEu r0,PTE_SIZE(r12) /* get next PTE */
562 CMPPTE 0,r0,r11
563 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
564 beq+ 3f
566 /* Search the secondary PTEG for a matching PTE */
567 ori r11,r11,PTE_H /* set H (secondary hash) bit */
568 li r0,8 /* PTEs/group */
569 _GLOBAL(flush_hash_patch_B)
570 xoris r12,r8,Hash_msk>>16 /* compute secondary hash */
571 xori r12,r12,(-PTEG_SIZE & 0xffff)
572 addi r12,r12,-PTE_SIZE
573 mtctr r0
574 2: LDPTEu r0,PTE_SIZE(r12)
575 CMPPTE 0,r0,r11
576 bdnzf 2,2b
577 xori r11,r11,PTE_H /* clear H again */
578 bne- 4f /* should rarely fail to find it */
580 3: li r0,0
581 STPTE r0,0(r12) /* invalidate entry */
582 4: sync
583 tlbie r4 /* in hw tlb too */
584 sync
586 8: ble cr1,9f /* if all ptes checked */
587 81: addi r6,r6,-1
588 addi r5,r5,4 /* advance to next pte */
589 addi r4,r4,0x1000
590 lwz r0,0(r5) /* check next pte */
591 cmpwi cr1,r6,1
592 andi. r0,r0,_PAGE_HASHPTE
593 bne 33b
594 bgt cr1,81b
596 9:
597 #ifdef CONFIG_SMP
598 TLBSYNC
599 li r0,0
600 stw r0,0(r9) /* clear mmu_hash_lock */
601 #endif
603 19: mtmsr r10
604 SYNC_601
605 isync
606 blr