arch/ppc/mm/ppc_mmu.c

   1 /*
   2  * This file contains the routines for handling the MMU on those
   3  * PowerPC implementations where the MMU substantially follows the
   4  * architecture specification.  This includes the 6xx, 7xx, 7xxx,
   5  * 8260, and 83xx implementations but excludes the 8xx and 4xx.
   6  *  -- paulus
   7  *
   8  *  Derived from arch/ppc/mm/init.c:
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  12  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  13  *    Copyright (C) 1996 Paul Mackerras
  14  *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  15  *
  16  *  Derived from "arch/i386/mm/init.c"
  17  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  *
  24  */
  25
  26 #include <linux/config.h>
  27 #include <linux/kernel.h>
  28 #include <linux/mm.h>
  29 #include <linux/init.h>
  30 #include <linux/highmem.h>
  31
  32 #include <asm/prom.h>
  33 #include <asm/mmu.h>
  34 #include <asm/machdep.h>
  35
  36 #include "mmu_decl.h"
  37 #include "mem_pieces.h"
  38
  39 PTE *Hash, *Hash_end;
  40 unsigned long Hash_size, Hash_mask;
  41 unsigned long _SDR1;
  42
  43 union ubat {                    /* BAT register values to be loaded */
  44         BAT     bat;
  45         u32     word[2];
  46 } BATS[4][2];                   /* 4 pairs of IBAT, DBAT */
  47
  48 struct batrange {               /* stores address ranges mapped by BATs */
  49         unsigned long start;
  50         unsigned long limit;
  51         unsigned long phys;
  52 } bat_addrs[4];
  53
  54 /*
  55  * Return PA for this VA if it is mapped by a BAT, or 0
  56  */
  57 unsigned long v_mapped_by_bats(unsigned long va)
  58 {
  59         int b;
  60         for (b = 0; b < 4; ++b)
  61                 if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
  62                         return bat_addrs[b].phys + (va - bat_addrs[b].start);
  63         return 0;
  64 }
  65
  66 /*
  67  * Return VA for a given PA or 0 if not mapped
  68  */
  69 unsigned long p_mapped_by_bats(unsigned long pa)
  70 {
  71         int b;
  72         for (b = 0; b < 4; ++b)
  73                 if (pa >= bat_addrs[b].phys
  74                     && pa < (bat_addrs[b].limit-bat_addrs[b].start)
  75                               +bat_addrs[b].phys)
  76                         return bat_addrs[b].start+(pa-bat_addrs[b].phys);
  77         return 0;
  78 }
  79
  80 unsigned long __init mmu_mapin_ram(void)
  81 {
  82         unsigned long tot, bl, done;
  83         unsigned long max_size = (256<<20);
  84         unsigned long align;
  85
  86         if (__map_without_bats)
  87                 return 0;
  88
  89         /* Set up BAT2 and if necessary BAT3 to cover RAM. */
  90
  91         /* Make sure we don't map a block larger than the
  92            smallest alignment of the physical address. */
  93         /* alignment of PPC_MEMSTART */
  94         align = ~(PPC_MEMSTART-1) & PPC_MEMSTART;
  95         /* set BAT block size to MIN(max_size, align) */
  96         if (align && align < max_size)
  97                 max_size = align;
  98
  99         tot = total_lowmem;
 100         for (bl = 128<<10; bl < max_size; bl <<= 1) {
 101                 if (bl * 2 > tot)
 102                         break;
 103         }
 104
 105         setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
 106         done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1;
 107         if ((done < tot) && !bat_addrs[3].limit) {
 108                 /* use BAT3 to cover a bit more */
 109                 tot -= done;
 110                 for (bl = 128<<10; bl < max_size; bl <<= 1)
 111                         if (bl * 2 > tot)
 112                                 break;
 113                 setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
 114                 done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1;
 115         }
 116
 117         return done;
 118 }
 119
 120 /*
 121  * Set up one of the I/D BAT (block address translation) register pairs.
 122  * The parameters are not checked; in particular size must be a power
 123  * of 2 between 128k and 256M.
 124  */
 125 void __init setbat(int index, unsigned long virt, unsigned long phys,
 126                    unsigned int size, int flags)
 127 {
 128         unsigned int bl;
 129         int wimgxpp;
 130         union ubat *bat = BATS[index];
 131
 132         if (((flags & _PAGE_NO_CACHE) == 0) &&
 133             cpu_has_feature(CPU_FTR_NEED_COHERENT))
 134                 flags |= _PAGE_COHERENT;
 135
 136         bl = (size >> 17) - 1;
 137         if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
 138                 /* 603, 604, etc. */
 139                 /* Do DBAT first */
 140                 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 141                                    | _PAGE_COHERENT | _PAGE_GUARDED);
 142                 wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
 143                 bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
 144                 bat[1].word[1] = phys | wimgxpp;
 145 #ifndef CONFIG_KGDB /* want user access for breakpoints */
 146                 if (flags & _PAGE_USER)
 147 #endif
 148                         bat[1].bat.batu.vp = 1;
 149                 if (flags & _PAGE_GUARDED) {
 150                         /* G bit must be zero in IBATs */
 151                         bat[0].word[0] = bat[0].word[1] = 0;
 152                 } else {
 153                         /* make IBAT same as DBAT */
 154                         bat[0] = bat[1];
 155                 }
 156         } else {
 157                 /* 601 cpu */
 158                 if (bl > BL_8M)
 159                         bl = BL_8M;
 160                 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 161                                    | _PAGE_COHERENT);
 162                 wimgxpp |= (flags & _PAGE_RW)?
 163                         ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
 164                 bat->word[0] = virt | wimgxpp | 4;      /* Ks=0, Ku=1 */
 165                 bat->word[1] = phys | bl | 0x40;        /* V=1 */
 166         }
 167
 168         bat_addrs[index].start = virt;
 169         bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
 170         bat_addrs[index].phys = phys;
 171 }
 172
 173 /*
 174  * Initialize the hash table and patch the instructions in hashtable.S.
 175  */
 176 void __init MMU_init_hw(void)
 177 {
 178         unsigned int hmask, mb, mb2;
 179         unsigned int n_hpteg, lg_n_hpteg;
 180
 181         extern unsigned int hash_page_patch_A[];
 182         extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
 183         extern unsigned int hash_page[];
 184         extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];
 185
 186         if (!cpu_has_feature(CPU_FTR_HPTE_TABLE)) {
 187                 /*
 188                  * Put a blr (procedure return) instruction at the
 189                  * start of hash_page, since we can still get DSI
 190                  * exceptions on a 603.
 191                  */
 192                 hash_page[0] = 0x4e800020;
 193                 flush_icache_range((unsigned long) &hash_page[0],
 194                                    (unsigned long) &hash_page[1]);
 195                 return;
 196         }
 197
 198         if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
 199
 200 #define LG_HPTEG_SIZE   6               /* 64 bytes per HPTEG */
 201 #define SDR1_LOW_BITS   ((n_hpteg - 1) >> 10)
 202 #define MIN_N_HPTEG     1024            /* min 64kB hash table */
 203
 204         /*
 205          * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
 206          * This is less than the recommended amount, but then
 207          * Linux ain't AIX.
 208          */
 209         n_hpteg = total_memory / (PAGE_SIZE * 8);
 210         if (n_hpteg < MIN_N_HPTEG)
 211                 n_hpteg = MIN_N_HPTEG;
 212         lg_n_hpteg = __ilog2(n_hpteg);
 213         if (n_hpteg & (n_hpteg - 1)) {
 214                 ++lg_n_hpteg;           /* round up if not power of 2 */
 215                 n_hpteg = 1 << lg_n_hpteg;
 216         }
 217         Hash_size = n_hpteg << LG_HPTEG_SIZE;
 218
 219         /*
 220          * Find some memory for the hash table.
 221          */
 222         if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
 223         Hash = mem_pieces_find(Hash_size, Hash_size);
 224         cacheable_memzero(Hash, Hash_size);
 225         _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
 226
 227         Hash_end = (PTE *) ((unsigned long)Hash + Hash_size);
 228
 229         printk("Total memory = %ldMB; using %ldkB for hash table (at %p)\n",
 230                total_memory >> 20, Hash_size >> 10, Hash);
 231
 232
 233         /*
 234          * Patch up the instructions in hashtable.S:create_hpte
 235          */
 236         if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
 237         Hash_mask = n_hpteg - 1;
 238         hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
 239         mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
 240         if (lg_n_hpteg > 16)
 241                 mb2 = 16 - LG_HPTEG_SIZE;
 242
 243         hash_page_patch_A[0] = (hash_page_patch_A[0] & ~0xffff)
 244                 | ((unsigned int)(Hash) >> 16);
 245         hash_page_patch_A[1] = (hash_page_patch_A[1] & ~0x7c0) | (mb << 6);
 246         hash_page_patch_A[2] = (hash_page_patch_A[2] & ~0x7c0) | (mb2 << 6);
 247         hash_page_patch_B[0] = (hash_page_patch_B[0] & ~0xffff) | hmask;
 248         hash_page_patch_C[0] = (hash_page_patch_C[0] & ~0xffff) | hmask;
 249
 250         /*
 251          * Ensure that the locations we've patched have been written
 252          * out from the data cache and invalidated in the instruction
 253          * cache, on those machines with split caches.
 254          */
 255         flush_icache_range((unsigned long) &hash_page_patch_A[0],
 256                            (unsigned long) &hash_page_patch_C[1]);
 257
 258         /*
 259          * Patch up the instructions in hashtable.S:flush_hash_page
 260          */
 261         flush_hash_patch_A[0] = (flush_hash_patch_A[0] & ~0xffff)
 262                 | ((unsigned int)(Hash) >> 16);
 263         flush_hash_patch_A[1] = (flush_hash_patch_A[1] & ~0x7c0) | (mb << 6);
 264         flush_hash_patch_A[2] = (flush_hash_patch_A[2] & ~0x7c0) | (mb2 << 6);
 265         flush_hash_patch_B[0] = (flush_hash_patch_B[0] & ~0xffff) | hmask;
 266         flush_icache_range((unsigned long) &flush_hash_patch_A[0],
 267                            (unsigned long) &flush_hash_patch_B[1]);
 268
 269         if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
 270 }