drivers/ide/pci/piix.c

   1 /*
   2  *  linux/drivers/ide/pci/piix.c        Version 0.44    March 20, 2003
   3  *
   4  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
   5  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   6  *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
   7  *
   8  *  May be copied or modified under the terms of the GNU General Public License
   9  *
  10  *  PIO mode setting function for Intel chipsets.
  11  *  For use instead of BIOS settings.
  12  *
  13  * 40-41
  14  * 42-43
  15  *
  16  *                 41
  17  *                 43
  18  *
  19  * | PIO 0       | c0 | 80 | 0 |        piix_tune_drive(drive, 0);
  20  * | PIO 2 | SW2 | d0 | 90 | 4 |        piix_tune_drive(drive, 2);
  21  * | PIO 3 | MW1 | e1 | a1 | 9 |        piix_tune_drive(drive, 3);
  22  * | PIO 4 | MW2 | e3 | a3 | b |        piix_tune_drive(drive, 4);
  23  *
  24  * sitre = word40 & 0x4000; primary
  25  * sitre = word42 & 0x4000; secondary
  26  *
  27  * 44 8421|8421    hdd|hdb
  28  *
  29  * 48 8421         hdd|hdc|hdb|hda udma enabled
  30  *
  31  *    0001         hda
  32  *    0010         hdb
  33  *    0100         hdc
  34  *    1000         hdd
  35  *
  36  * 4a 84|21        hdb|hda
  37  * 4b 84|21        hdd|hdc
  38  *
  39  *    ata-33/82371AB
  40  *    ata-33/82371EB
  41  *    ata-33/82801AB            ata-66/82801AA
  42  *    00|00 udma 0              00|00 reserved
  43  *    01|01 udma 1              01|01 udma 3
  44  *    10|10 udma 2              10|10 udma 4
  45  *    11|11 reserved            11|11 reserved
  46  *
  47  * 54 8421|8421    ata66 drive|ata66 enable
  48  *
  49  * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
  50  * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
  51  * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
  52  * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
  53  * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
  54  * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
  55  *
  56  * Documentation
  57  *      Publically available from Intel web site. Errata documentation
  58  * is also publically available. As an aide to anyone hacking on this
  59  * driver the list of errata that are relevant is below.going back to
  60  * PIIX4. Older device documentation is now a bit tricky to find.
  61  *
  62  * Errata of note:
  63  *
  64  * Unfixable
  65  *      PIIX4    errata #9      - Only on ultra obscure hw
  66  *      ICH3     errata #13     - Not observed to affect real hw
  67  *                                by Intel
  68  *
  69  * Things we must deal with
  70  *      PIIX4   errata #10      - BM IDE hang with non UDMA
  71  *                                (must stop/start dma to recover)
  72  *      440MX   errata #15      - As PIIX4 errata #10
  73  *      PIIX4   errata #15      - Must not read control registers
  74  *                                during a PIO transfer
  75  *      440MX   errata #13      - As PIIX4 errata #15
  76  *      ICH2    errata #21      - DMA mode 0 doesn't work right
  77  *      ICH0/1  errata #55      - As ICH2 errata #21
  78  *      ICH2    spec c #9       - Extra operations needed to handle
  79  *                                drive hotswap [NOT YET SUPPORTED]
  80  *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  81  *                                and must be dword aligned
  82  *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  83  *
  84  * Should have been BIOS fixed:
  85  *      450NX:  errata #19      - DMA hangs on old 450NX
  86  *      450NX:  errata #20      - DMA hangs on old 450NX
  87  *      450NX:  errata #25      - Corruption with DMA on old 450NX
  88  *      ICH3    errata #15      - IDE deadlock under high load
  89  *                                (BIOS must set dev 31 fn 0 bit 23)
  90  *      ICH3    errata #18      - Don't use native mode
  91  */
  92
  93 #include <linux/config.h>
  94 #include <linux/types.h>
  95 #include <linux/module.h>
  96 #include <linux/kernel.h>
  97 #include <linux/ioport.h>
  98 #include <linux/pci.h>
  99 #include <linux/hdreg.h>
 100 #include <linux/ide.h>
 101 #include <linux/delay.h>
 102 #include <linux/init.h>
 103
 104 #include <asm/io.h>
 105
 106 static int no_piix_dma;
 107
 108 /**
 109  *      piix_ratemask           -       compute rate mask for PIIX IDE
 110  *      @drive: IDE drive to compute for
 111  *
 112  *      Returns the available modes for the PIIX IDE controller.
 113  */
 114
 115 static u8 piix_ratemask (ide_drive_t *drive)
 116 {
 117         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 118         u8 mode;
 119
 120         switch(dev->device) {
 121                 case PCI_DEVICE_ID_INTEL_82801EB_1:
 122                         mode = 3;
 123                         break;
 124                 /* UDMA 100 capable */
 125                 case PCI_DEVICE_ID_INTEL_82801BA_8:
 126                 case PCI_DEVICE_ID_INTEL_82801BA_9:
 127                 case PCI_DEVICE_ID_INTEL_82801CA_10:
 128                 case PCI_DEVICE_ID_INTEL_82801CA_11:
 129                 case PCI_DEVICE_ID_INTEL_82801E_11:
 130                 case PCI_DEVICE_ID_INTEL_82801DB_1:
 131                 case PCI_DEVICE_ID_INTEL_82801DB_10:
 132                 case PCI_DEVICE_ID_INTEL_82801DB_11:
 133                 case PCI_DEVICE_ID_INTEL_82801EB_11:
 134                 case PCI_DEVICE_ID_INTEL_ESB_2:
 135                 case PCI_DEVICE_ID_INTEL_ICH6_19:
 136                 case PCI_DEVICE_ID_INTEL_ICH7_21:
 137                 case PCI_DEVICE_ID_INTEL_ESB2_18:
 138                 case PCI_DEVICE_ID_INTEL_ICH8_6:
 139                         mode = 3;
 140                         break;
 141                 /* UDMA 66 capable */
 142                 case PCI_DEVICE_ID_INTEL_82801AA_1:
 143                 case PCI_DEVICE_ID_INTEL_82372FB_1:
 144                         mode = 2;
 145                         break;
 146                 /* UDMA 33 capable */
 147                 case PCI_DEVICE_ID_INTEL_82371AB:
 148                 case PCI_DEVICE_ID_INTEL_82443MX_1:
 149                 case PCI_DEVICE_ID_INTEL_82451NX:
 150                 case PCI_DEVICE_ID_INTEL_82801AB_1:
 151                         return 1;
 152                 /* Non UDMA capable (MWDMA2) */
 153                 case PCI_DEVICE_ID_INTEL_82371SB_1:
 154                 case PCI_DEVICE_ID_INTEL_82371FB_1:
 155                 case PCI_DEVICE_ID_INTEL_82371FB_0:
 156                 case PCI_DEVICE_ID_INTEL_82371MX:
 157                 default:
 158                         return 0;
 159         }
 160
 161         /*
 162          *      If we are UDMA66 capable fall back to UDMA33
 163          *      if the drive cannot see an 80pin cable.
 164          */
 165         if (!eighty_ninty_three(drive))
 166                 mode = min(mode, (u8)1);
 167         return mode;
 168 }
 169
 170 /**
 171  *      piix_dma_2_pio          -       return the PIO mode matching DMA
 172  *      @xfer_rate: transfer speed
 173  *
 174  *      Returns the nearest equivalent PIO timing for the PIO or DMA
 175  *      mode requested by the controller.
 176  */
 177
 178 static u8 piix_dma_2_pio (u8 xfer_rate) {
 179         switch(xfer_rate) {
 180                 case XFER_UDMA_6:
 181                 case XFER_UDMA_5:
 182                 case XFER_UDMA_4:
 183                 case XFER_UDMA_3:
 184                 case XFER_UDMA_2:
 185                 case XFER_UDMA_1:
 186                 case XFER_UDMA_0:
 187                 case XFER_MW_DMA_2:
 188                 case XFER_PIO_4:
 189                         return 4;
 190                 case XFER_MW_DMA_1:
 191                 case XFER_PIO_3:
 192                         return 3;
 193                 case XFER_SW_DMA_2:
 194                 case XFER_PIO_2:
 195                         return 2;
 196                 case XFER_MW_DMA_0:
 197                 case XFER_SW_DMA_1:
 198                 case XFER_SW_DMA_0:
 199                 case XFER_PIO_1:
 200                 case XFER_PIO_0:
 201                 case XFER_PIO_SLOW:
 202                 default:
 203                         return 0;
 204         }
 205 }
 206
 207 /**
 208  *      piix_tune_drive         -       tune a drive attached to a PIIX
 209  *      @drive: drive to tune
 210  *      @pio: desired PIO mode
 211  *
 212  *      Set the interface PIO mode based upon  the settings done by AMI BIOS
 213  *      (might be useful if drive is not registered in CMOS for any reason).
 214  */
 215 static void piix_tune_drive (ide_drive_t *drive, u8 pio)
 216 {
 217         ide_hwif_t *hwif        = HWIF(drive);
 218         struct pci_dev *dev     = hwif->pci_dev;
 219         int is_slave            = (&hwif->drives[1] == drive);
 220         int master_port         = hwif->channel ? 0x42 : 0x40;
 221         int slave_port          = 0x44;
 222         unsigned long flags;
 223         u16 master_data;
 224         u8 slave_data;
 225                                  /* ISP  RTC */
 226         u8 timings[][2] = { { 0, 0 },
 227                             { 0, 0 },
 228                             { 1, 0 },
 229                             { 2, 1 },
 230                             { 2, 3 }, };
 231
 232         pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
 233         spin_lock_irqsave(&ide_lock, flags);
 234         pci_read_config_word(dev, master_port, &master_data);
 235         if (is_slave) {
 236                 master_data = master_data | 0x4000;
 237                 if (pio > 1)
 238                         /* enable PPE, IE and TIME */
 239                         master_data = master_data | 0x0070;
 240                 pci_read_config_byte(dev, slave_port, &slave_data);
 241                 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
 242                 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
 243         } else {
 244                 master_data = master_data & 0xccf8;
 245                 if (pio > 1)
 246                         /* enable PPE, IE and TIME */
 247                         master_data = master_data | 0x0007;
 248                 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
 249         }
 250         pci_write_config_word(dev, master_port, master_data);
 251         if (is_slave)
 252                 pci_write_config_byte(dev, slave_port, slave_data);
 253         spin_unlock_irqrestore(&ide_lock, flags);
 254 }
 255
 256 /**
 257  *      piix_tune_chipset       -       tune a PIIX interface
 258  *      @drive: IDE drive to tune
 259  *      @xferspeed: speed to configure
 260  *
 261  *      Set a PIIX interface channel to the desired speeds. This involves
 262  *      requires the right timing data into the PIIX configuration space
 263  *      then setting the drive parameters appropriately
 264  */
 265
 266 static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 267 {
 268         ide_hwif_t *hwif        = HWIF(drive);
 269         struct pci_dev *dev     = hwif->pci_dev;
 270         u8 maslave              = hwif->channel ? 0x42 : 0x40;
 271         u8 speed                = ide_rate_filter(piix_ratemask(drive), xferspeed);
 272         int a_speed             = 3 << (drive->dn * 4);
 273         int u_flag              = 1 << drive->dn;
 274         int v_flag              = 0x01 << drive->dn;
 275         int w_flag              = 0x10 << drive->dn;
 276         int u_speed             = 0;
 277         int                     sitre;
 278         u16                     reg4042, reg4a;
 279         u8                      reg48, reg54, reg55;
 280
 281         pci_read_config_word(dev, maslave, &reg4042);
 282         sitre = (reg4042 & 0x4000) ? 1 : 0;
 283         pci_read_config_byte(dev, 0x48, &reg48);
 284         pci_read_config_word(dev, 0x4a, &reg4a);
 285         pci_read_config_byte(dev, 0x54, &reg54);
 286         pci_read_config_byte(dev, 0x55, &reg55);
 287
 288         switch(speed) {
 289                 case XFER_UDMA_4:
 290                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
 291                 case XFER_UDMA_5:
 292                 case XFER_UDMA_3:
 293                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
 294                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
 295                 case XFER_MW_DMA_2:
 296                 case XFER_MW_DMA_1:
 297                 case XFER_SW_DMA_2:     break;
 298                 case XFER_PIO_4:
 299                 case XFER_PIO_3:
 300                 case XFER_PIO_2:
 301                 case XFER_PIO_0:        break;
 302                 default:                return -1;
 303         }
 304
 305         if (speed >= XFER_UDMA_0) {
 306                 if (!(reg48 & u_flag))
 307                         pci_write_config_byte(dev, 0x48, reg48 | u_flag);
 308                 if (speed == XFER_UDMA_5) {
 309                         pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
 310                 } else {
 311                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 312                 }
 313                 if ((reg4a & a_speed) != u_speed)
 314                         pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
 315                 if (speed > XFER_UDMA_2) {
 316                         if (!(reg54 & v_flag))
 317                                 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
 318                 } else
 319                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 320         } else {
 321                 if (reg48 & u_flag)
 322                         pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
 323                 if (reg4a & a_speed)
 324                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 325                 if (reg54 & v_flag)
 326                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 327                 if (reg55 & w_flag)
 328                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 329         }
 330
 331         piix_tune_drive(drive, piix_dma_2_pio(speed));
 332         return (ide_config_drive_speed(drive, speed));
 333 }
 334
 335 /**
 336  *      piix_faulty_dma0                -       check for DMA0 errata
 337  *      @hwif: IDE interface to check
 338  *
 339  *      If an ICH/ICH0/ICH2 interface is is operating in multi-word
 340  *      DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
 341  *      inadvertently provide an extra piece of secondary data to the primary
 342  *      device resulting in data corruption.
 343  *
 344  *      With such a device this test function returns true. This allows
 345  *      our tuning code to follow Intel recommendations and use PIO on
 346  *      such devices.
 347  */
 348
 349 static int piix_faulty_dma0(ide_hwif_t *hwif)
 350 {
 351         switch(hwif->pci_dev->device)
 352         {
 353                 case PCI_DEVICE_ID_INTEL_82801AA_1:     /* ICH */
 354                 case PCI_DEVICE_ID_INTEL_82801AB_1:     /* ICH0 */
 355                 case PCI_DEVICE_ID_INTEL_82801BA_8:     /* ICH2 */
 356                 case PCI_DEVICE_ID_INTEL_82801BA_9:     /* ICH2 */
 357                         return 1;
 358         }
 359         return 0;
 360 }
 361
 362 /**
 363  *      piix_config_drive_for_dma       -       configure drive for DMA
 364  *      @drive: IDE drive to configure
 365  *
 366  *      Set up a PIIX interface channel for the best available speed.
 367  *      We prefer UDMA if it is available and then MWDMA. If DMA is
 368  *      not available we switch to PIO and return 0.
 369  */
 370
 371 static int piix_config_drive_for_dma (ide_drive_t *drive)
 372 {
 373         u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
 374
 375         /* Some ICH devices cannot support DMA mode 0 */
 376         if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
 377                 speed = 0;
 378
 379         /* If no DMA speed was available or the chipset has DMA bugs
 380            then disable DMA and use PIO */
 381
 382         if (!speed || no_piix_dma) {
 383                 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
 384                 speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
 385         }
 386
 387         (void) piix_tune_chipset(drive, speed);
 388         return ide_dma_enable(drive);
 389 }
 390
 391 /**
 392  *      piix_config_drive_xfer_rate     -       set up an IDE device
 393  *      @drive: IDE drive to configure
 394  *
 395  *      Set up the PIIX interface for the best available speed on this
 396  *      interface, preferring DMA to PIO.
 397  */
 398
 399 static int piix_config_drive_xfer_rate (ide_drive_t *drive)
 400 {
 401         ide_hwif_t *hwif        = HWIF(drive);
 402         struct hd_driveid *id   = drive->id;
 403
 404         drive->init_speed = 0;
 405
 406         if ((id->capability & 1) && drive->autodma) {
 407
 408                 if (ide_use_dma(drive)) {
 409                         if (piix_config_drive_for_dma(drive))
 410                                 return hwif->ide_dma_on(drive);
 411                 }
 412
 413                 goto fast_ata_pio;
 414
 415         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 416 fast_ata_pio:
 417                 /* Find best PIO mode. */
 418                 hwif->tuneproc(drive, 255);
 419                 return hwif->ide_dma_off_quietly(drive);
 420         }
 421         /* IORDY not supported */
 422         return 0;
 423 }
 424
 425 /**
 426  *      init_chipset_piix       -       set up the PIIX chipset
 427  *      @dev: PCI device to set up
 428  *      @name: Name of the device
 429  *
 430  *      Initialize the PCI device as required. For the PIIX this turns
 431  *      out to be nice and simple
 432  */
 433
 434 static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
 435 {
 436         switch(dev->device) {
 437                 case PCI_DEVICE_ID_INTEL_82801EB_1:
 438                 case PCI_DEVICE_ID_INTEL_82801AA_1:
 439                 case PCI_DEVICE_ID_INTEL_82801AB_1:
 440                 case PCI_DEVICE_ID_INTEL_82801BA_8:
 441                 case PCI_DEVICE_ID_INTEL_82801BA_9:
 442                 case PCI_DEVICE_ID_INTEL_82801CA_10:
 443                 case PCI_DEVICE_ID_INTEL_82801CA_11:
 444                 case PCI_DEVICE_ID_INTEL_82801DB_1:
 445                 case PCI_DEVICE_ID_INTEL_82801DB_10:
 446                 case PCI_DEVICE_ID_INTEL_82801DB_11:
 447                 case PCI_DEVICE_ID_INTEL_82801EB_11:
 448                 case PCI_DEVICE_ID_INTEL_82801E_11:
 449                 case PCI_DEVICE_ID_INTEL_ESB_2:
 450                 case PCI_DEVICE_ID_INTEL_ICH6_19:
 451                 case PCI_DEVICE_ID_INTEL_ICH7_21:
 452                 case PCI_DEVICE_ID_INTEL_ESB2_18:
 453                 case PCI_DEVICE_ID_INTEL_ICH8_6:
 454                 {
 455                         unsigned int extra = 0;
 456                         pci_read_config_dword(dev, 0x54, &extra);
 457                         pci_write_config_dword(dev, 0x54, extra|0x400);
 458                 }
 459                 default:
 460                         break;
 461         }
 462
 463         return 0;
 464 }
 465
 466 /**
 467  *      init_hwif_piix          -       fill in the hwif for the PIIX
 468  *      @hwif: IDE interface
 469  *
 470  *      Set up the ide_hwif_t for the PIIX interface according to the
 471  *      capabilities of the hardware.
 472  */
 473
 474 static void __devinit init_hwif_piix(ide_hwif_t *hwif)
 475 {
 476         u8 reg54h = 0, reg55h = 0, ata66 = 0;
 477         u8 mask = hwif->channel ? 0xc0 : 0x30;
 478
 479 #ifndef CONFIG_IA64
 480         if (!hwif->irq)
 481                 hwif->irq = hwif->channel ? 15 : 14;
 482 #endif /* CONFIG_IA64 */
 483
 484         if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
 485                 /* This is a painful system best to let it self tune for now */
 486                 return;
 487         }
 488
 489         hwif->autodma = 0;
 490         hwif->tuneproc = &piix_tune_drive;
 491         hwif->speedproc = &piix_tune_chipset;
 492         hwif->drives[0].autotune = 1;
 493         hwif->drives[1].autotune = 1;
 494
 495         if (!hwif->dma_base)
 496                 return;
 497
 498         hwif->atapi_dma = 1;
 499         hwif->ultra_mask = 0x3f;
 500         hwif->mwdma_mask = 0x06;
 501         hwif->swdma_mask = 0x04;
 502
 503         switch(hwif->pci_dev->device) {
 504                 case PCI_DEVICE_ID_INTEL_82371MX:
 505                         hwif->mwdma_mask = 0x80;
 506                         hwif->swdma_mask = 0x80;
 507                 case PCI_DEVICE_ID_INTEL_82371FB_0:
 508                 case PCI_DEVICE_ID_INTEL_82371FB_1:
 509                 case PCI_DEVICE_ID_INTEL_82371SB_1:
 510                         hwif->ultra_mask = 0x80;
 511                         break;
 512                 case PCI_DEVICE_ID_INTEL_82371AB:
 513                 case PCI_DEVICE_ID_INTEL_82443MX_1:
 514                 case PCI_DEVICE_ID_INTEL_82451NX:
 515                 case PCI_DEVICE_ID_INTEL_82801AB_1:
 516                         hwif->ultra_mask = 0x07;
 517                         break;
 518                 default:
 519                         pci_read_config_byte(hwif->pci_dev, 0x54, &reg54h);
 520                         pci_read_config_byte(hwif->pci_dev, 0x55, &reg55h);
 521                         ata66 = (reg54h & mask) ? 1 : 0;
 522                         break;
 523         }
 524
 525         if (!(hwif->udma_four))
 526                 hwif->udma_four = ata66;
 527         hwif->ide_dma_check = &piix_config_drive_xfer_rate;
 528         if (!noautodma)
 529                 hwif->autodma = 1;
 530
 531         hwif->drives[1].autodma = hwif->autodma;
 532         hwif->drives[0].autodma = hwif->autodma;
 533 }
 534
 535 #define DECLARE_PIIX_DEV(name_str) \
 536         {                                               \
 537                 .name           = name_str,             \
 538                 .init_chipset   = init_chipset_piix,    \
 539                 .init_hwif      = init_hwif_piix,       \
 540                 .channels       = 2,                    \
 541                 .autodma        = AUTODMA,              \
 542                 .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 543                 .bootable       = ON_BOARD,             \
 544         }
 545
 546 static ide_pci_device_t piix_pci_info[] __devinitdata = {
 547         /*  0 */ DECLARE_PIIX_DEV("PIIXa"),
 548         /*  1 */ DECLARE_PIIX_DEV("PIIXb"),
 549
 550         {       /* 2 */
 551                 .name           = "MPIIX",
 552                 .init_hwif      = init_hwif_piix,
 553                 .channels       = 2,
 554                 .autodma        = NODMA,
 555                 .enablebits     = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}},
 556                 .bootable       = ON_BOARD,
 557         },
 558
 559         /*  3 */ DECLARE_PIIX_DEV("PIIX3"),
 560         /*  4 */ DECLARE_PIIX_DEV("PIIX4"),
 561         /*  5 */ DECLARE_PIIX_DEV("ICH0"),
 562         /*  6 */ DECLARE_PIIX_DEV("PIIX4"),
 563         /*  7 */ DECLARE_PIIX_DEV("ICH"),
 564         /*  8 */ DECLARE_PIIX_DEV("PIIX4"),
 565         /*  9 */ DECLARE_PIIX_DEV("PIIX4"),
 566         /* 10 */ DECLARE_PIIX_DEV("ICH2"),
 567         /* 11 */ DECLARE_PIIX_DEV("ICH2M"),
 568         /* 12 */ DECLARE_PIIX_DEV("ICH3M"),
 569         /* 13 */ DECLARE_PIIX_DEV("ICH3"),
 570         /* 14 */ DECLARE_PIIX_DEV("ICH4"),
 571         /* 15 */ DECLARE_PIIX_DEV("ICH5"),
 572         /* 16 */ DECLARE_PIIX_DEV("C-ICH"),
 573         /* 17 */ DECLARE_PIIX_DEV("ICH4"),
 574         /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"),
 575         /* 19 */ DECLARE_PIIX_DEV("ICH5"),
 576         /* 20 */ DECLARE_PIIX_DEV("ICH6"),
 577         /* 21 */ DECLARE_PIIX_DEV("ICH7"),
 578         /* 22 */ DECLARE_PIIX_DEV("ICH4"),
 579         /* 23 */ DECLARE_PIIX_DEV("ESB2"),
 580         /* 24 */ DECLARE_PIIX_DEV("ICH8M"),
 581 };
 582
 583 /**
 584  *      piix_init_one   -       called when a PIIX is found
 585  *      @dev: the piix device
 586  *      @id: the matching pci id
 587  *
 588  *      Called when the PCI registration layer (or the IDE initialization)
 589  *      finds a device matching our IDE device tables.
 590  */
 591
 592 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 593 {
 594         ide_pci_device_t *d = &piix_pci_info[id->driver_data];
 595
 596         return ide_setup_pci_device(dev, d);
 597 }
 598
 599 /**
 600  *      piix_check_450nx        -       Check for problem 450NX setup
 601  *
 602  *      Check for the present of 450NX errata #19 and errata #25. If
 603  *      they are found, disable use of DMA IDE
 604  */
 605
 606 static void __devinit piix_check_450nx(void)
 607 {
 608         struct pci_dev *pdev = NULL;
 609         u16 cfg;
 610         u8 rev;
 611         while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
 612         {
 613                 /* Look for 450NX PXB. Check for problem configurations
 614                    A PCI quirk checks bit 6 already */
 615                 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
 616                 pci_read_config_word(pdev, 0x41, &cfg);
 617                 /* Only on the original revision: IDE DMA can hang */
 618                 if(rev == 0x00)
 619                         no_piix_dma = 1;
 620                 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
 621                 else if(cfg & (1<<14) && rev < 5)
 622                         no_piix_dma = 2;
 623         }
 624         if(no_piix_dma)
 625                 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
 626         if(no_piix_dma == 2)
 627                 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
 628 }
 629
 630 static struct pci_device_id piix_pci_tbl[] = {
 631         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 632         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 633         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 634         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 635         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 636         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
 637         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
 638         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
 639         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
 640         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
 641         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
 642         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
 643         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
 644         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
 645         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
 646         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
 647         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
 648         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
 649 #ifdef CONFIG_BLK_DEV_IDE_SATA
 650         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
 651 #endif
 652         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
 653         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
 654         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
 655         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
 656         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23},
 657         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24},
 658         { 0, },
 659 };
 660 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 661
 662 static struct pci_driver driver = {
 663         .name           = "PIIX_IDE",
 664         .id_table       = piix_pci_tbl,
 665         .probe          = piix_init_one,
 666 };
 667
 668 static int __init piix_ide_init(void)
 669 {
 670         piix_check_450nx();
 671         return ide_pci_register_driver(&driver);
 672 }
 673
 674 module_init(piix_ide_init);
 675
 676 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
 677 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
 678 MODULE_LICENSE("GPL");