| blob | fac0a2b74de2e3d08d054322157b773bc5b79967 |
1 /*
2 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
33 /*
34 * This file contains all of the code that is specific to the InfiniPath
35 * HT-400 chip.
36 */
38 #include <linux/pci.h>
39 #include <linux/delay.h>
44 /*
45 * This lists the InfiniPath HT400 registers, in the actual chip layout.
46 * This structure should never be directly accessed.
47 *
48 * The names are in InterCap form because they're taken straight from
49 * the chip specification. Since they're only used in this file, they
50 * don't pollute the rest of the source.
51 */
143 };
145 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
146 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
147 #define IPATH_CREG_OFFSET(field) (offsetof( \
148 struct infinipath_counters, field) / sizeof(u64))
208 /*
209 * These should not be used directly via ipath_read_kreg64(),
210 * use them with ipath_read_kreg64_port(),
211 */
214 };
229 /* calc from Reg_CounterRegBase + offset */
251 };
253 /* kr_intstatus, kr_intclear, kr_intmask bits */
254 #define INFINIPATH_I_RCVURG_MASK 0x1FF
255 #define INFINIPATH_I_RCVAVAIL_MASK 0x1FF
257 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
258 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
259 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
260 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR 0x0000000000800000ULL
261 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR 0x0000000001000000ULL
262 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR 0x0000000002000000ULL
263 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR 0x0000000004000000ULL
264 #define INFINIPATH_HWE_HTCMISCERR4 0x0000000008000000ULL
265 #define INFINIPATH_HWE_HTCMISCERR5 0x0000000010000000ULL
266 #define INFINIPATH_HWE_HTCMISCERR6 0x0000000020000000ULL
267 #define INFINIPATH_HWE_HTCMISCERR7 0x0000000040000000ULL
268 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR 0x0000000080000000ULL
269 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
270 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR 0x0000000200000000ULL
271 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
272 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
273 #define INFINIPATH_HWE_HTBPLL_FBSLIP 0x0200000000000000ULL
274 #define INFINIPATH_HWE_HTBPLL_RFSLIP 0x0400000000000000ULL
275 #define INFINIPATH_HWE_HTAPLL_FBSLIP 0x0800000000000000ULL
276 #define INFINIPATH_HWE_HTAPLL_RFSLIP 0x1000000000000000ULL
277 #define INFINIPATH_HWE_SERDESPLLFAILED 0x2000000000000000ULL
279 /* kr_extstatus bits */
280 #define INFINIPATH_EXTS_FREQSEL 0x2
281 #define INFINIPATH_EXTS_SERDESSEL 0x4
282 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
283 #define INFINIPATH_EXTS_MEMBIST_CORRECT 0x0000000000008000
285 /*
286 * masks and bits that are different in different chips, or present only
287 * in one
288 */
290 INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
292 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
295 INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
297 INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
299 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
301 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
303 #define _IPATH_GPIO_SDA_NUM 1
304 #define _IPATH_GPIO_SCL_NUM 0
306 #define IPATH_GPIO_SDA \
307 (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
308 #define IPATH_GPIO_SCL \
309 (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
311 /* keep the code below somewhat more readonable; not used elsewhere */
312 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
313 infinipath_hwe_htclnkabyte1crcerr)
314 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr | \
315 infinipath_hwe_htclnkbbyte1crcerr)
316 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
317 infinipath_hwe_htclnkbbyte0crcerr)
318 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr | \
319 infinipath_hwe_htclnkbbyte1crcerr)
323 {
327 /* don't check if 8bit HT */
330 /* don't check if 8bit HT */
333 /*
334 * we'll want to ignore link errors on link that is
335 * not in use, if any. For now, complain about both
336 */
349 /*
350 * print extra info for debugging. slave/primary
351 * config word 4, 8 (link control 0, 1)
352 */
358 "linkctrl0 of slave/primary "
361 /* not if EOC bit set */
370 "linkctrl1 of slave/primary "
373 /* not if EOC bit set */
379 /* disable until driver reloaded */
388 _IPATH_HTLINK1_CRCBITS)));
389 }
391 /**
392 * ipath_ht_handle_hwerrors - display hardware errors
393 * @dd: the infinipath device
394 * @msg: the output buffer
395 * @msgl: the size of the output buffer
396 *
397 * Use same msg buffer as regular errors to avoid
398 * excessive stack use. Most hardware errors are catastrophic, but for
399 * right now, we'll print them and continue.
400 * We reuse the same message buffer as ipath_handle_errors() to avoid
401 * excessive stack usage.
402 */
405 {
406 ipath_err_t hwerrs;
415 /*
416 * better than printing cofusing messages
417 * This seems to be related to clearing the crc error, or
418 * the pll error during init.
419 */
425 }
428 /* Always clear the error status register, except MEMBISTFAIL,
429 * regardless of whether we continue or stop using the chip.
430 * We want that set so we know it failed, even across driver reload.
431 * We'll still ignore it in the hwerrmask. We do this partly for
432 * diagnostics, but also for support */
438 /*
439 * make sure we get this much out, unless told to be quiet,
440 * or it's occurred within the last 5 seconds
441 */
456 /*
457 * if any set that we aren't ignoring; only
458 * make the complaint once, in case it's stuck
459 * or recurring, and we get here multiple
460 * times.
461 */
466 }
468 /* mark as having had error */
470 /*
471 * mark as not usable, at a minimum until driver
472 * is reloaded, probably until reboot, since no
473 * other reset is possible.
474 */
481 ctrl);
482 }
483 }
487 /*
488 * may someday want to decode into which bits are which
489 * functional area for parity errors, etc.
490 */
494 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
495 INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
497 bits);
499 }
503 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) &
504 INFINIPATH_HWE_RXEMEMPARITYERR_MASK);
506 bits);
508 }
512 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
513 INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
515 bits);
517 }
540 msgl);
541 /* ignore from now on, so disable until driver reloaded */
545 }
546 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
547 INFINIPATH_HWE_COREPLL_RFSLIP | \
548 INFINIPATH_HWE_HTBPLL_FBSLIP | \
549 INFINIPATH_HWE_HTBPLL_RFSLIP | \
550 INFINIPATH_HWE_HTAPLL_FBSLIP | \
551 INFINIPATH_HWE_HTAPLL_RFSLIP)
558 /* ignore from now on, so disable until driver reloaded */
562 }
565 /*
566 * If it occurs, it is left masked since the eternal
567 * interface is unused
568 */
572 }
581 /*
582 * for status file; if no trailing brace is copied,
583 * we'll know it was truncated.
584 */
588 bail:;
589 }
591 /**
592 * ipath_ht_boardname - fill in the board name
593 * @dd: the infinipath device
594 * @name: the output buffer
595 * @namelen: the size of the output buffer
596 *
597 * fill in the board name, based on the board revision register
598 */
601 {
611 /*
612 * HT-460 original production board; two production levels, with
613 * different serial number ranges. See ipath_ht_early_init() for
614 * case where we enable IPATH_GPIO_INTR for later serial # range.
615 */
622 /* HT-460 small form factor production board */
644 boardrev);
646 }
651 /*
652 * This version of the driver only supports the HT-400
653 * Rev 3.2
654 */
660 }
661 /*
662 * pkt/word counters are 32 bit, and therefore wrap fast enough
663 * that we snapshot them from a timer, and maintain 64 bit shadow
664 * copies
665 */
674 else
677 u64 val;
680 /*
681 * hardware disabled
682 *
683 * This means that the chip is hardware disabled,
684 * and will not be able to bring up the link,
685 * in any case. We special case this and abort
686 * early, to avoid later messages. We also set
687 * the DISABLED status bit
688 */
692 /* this value is handled differently */
695 }
696 }
699 bail:
701 }
704 {
712 i);
716 /*
717 * writing the linkerr bits that are set should
718 * clear them
719 */
721 linkerr))
727 "Couldn't reread linkerror%d of "
731 "HT linkerror%d bits 0x%x "
734 }
735 }
736 }
739 {
742 }
748 /*
749 * Bits 13-15 of command==0 is slave/primary block. Clear any HT CRC
750 * errors. We only bother to do this at load time, because it's OK if
751 * it happened before we were loaded (first time after boot/reset),
752 * but any time after that, it's fatal anyway. Also need to not check
753 * for for upper byte errors if we are in 8 bit mode, so figure out
754 * our width. For now, at least, also complain if it's 8 bit.
755 */
758 {
764 /* command word, master_host bit */
765 /* master host || slave */
768 else
776 /*
777 * check both link control registers; clear both HT CRC sets if
778 * necessary.
779 */
788 /*
789 * now write them back to clear the error.
790 */
793 }
794 }
796 /*
797 * As with HT CRC bits, same for protocol errors that might occur
798 * during boot.
799 */
808 /*
809 * writing the linkerr bits that are set will clear
810 * them
811 */
818 "linkerror%d of HT slave/primary "
824 }
825 }
827 /*
828 * this is just for our link to the host, not devices connected
829 * through tunnel.
830 */
836 u32 width;
854 }
864 }
865 }
866 }
868 /*
869 * this is just for our link to the host, not devices connected
870 * through tunnel.
871 */
876 u32 speed;
897 /*
898 * assume reserved and vendor-specific are 200...
899 */
903 }
905 }
906 }
910 {
911 u32 int_handler_addr_lower;
912 u32 int_handler_addr_upper;
913 u64 ihandler;
914 u32 intvec;
916 /* use indirection register to get the intr handler */
925 /*
926 * kernels with CONFIG_PCI_MSI set the vector in the irq field of
927 * struct pci_device, so we use that to program the HT-400 internal
928 * interrupt register (not config space) with that value. The BIOS
929 * must still have done the basic MSI setup.
930 */
932 /*
933 * clear any vector bits there; normally not set but we'll overload
934 * this for some debug purposes (setting the HTC debug register
935 * value from software, rather than GPIOs), so it might be set on a
936 * driver reload.
937 */
939 /* x86 vector goes in intrinfo[23:16] */
946 /* can't program yet, so save for interrupt setup */
948 /* keep going, so we find link control stuff also */
951 }
953 /**
954 * ipath_setup_ht_config - setup the interruptconfig register
955 * @dd: the infinipath device
956 * @pdev: the PCI device
957 *
958 * setup the interruptconfig register from the HT config info.
959 * Also clear CRC errors in HT linkcontrol, if necessary.
960 * This is done only for the real hardware. It is done before
961 * chip address space is initted, so can't touch infinipath registers
962 */
965 {
969 /*
970 * Read the capability info to find the interrupt info, and also
971 * handle clearing CRC errors in linkctrl register if necessary. We
972 * do this early, before we ever enable errors or hardware errors,
973 * mostly to avoid causing the chip to enter freeze mode.
974 */
981 }
983 u8 cap_type;
985 /* the HT capability type byte is 3 bytes after the
986 * capability byte.
987 */
992 }
998 HT_CAPABILITY_ID)));
1004 }
1006 bail:
1008 }
1010 /**
1011 * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1012 * @dd: the infinipath device
1013 *
1014 * Called during driver unload.
1015 * This is currently a nop for the HT-400, not for all chips
1016 */
1018 {
1019 }
1021 /**
1022 * ipath_setup_ht_setextled - set the state of the two external LEDs
1023 * @dd: the infinipath device
1024 * @lst: the L state
1025 * @ltst: the LT state
1026 *
1027 * Set the state of the two external LEDs, to indicate physical and
1028 * logical state of IB link. For this chip (at least with recommended
1029 * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1030 * (logical state)
1031 *
1032 * Note: We try to match the Mellanox HCA LED behavior as best
1033 * we can. Green indicates physical link state is OK (something is
1034 * plugged in, and we can train).
1035 * Amber indicates the link is logically up (ACTIVE).
1036 * Mellanox further blinks the amber LED to indicate data packet
1037 * activity, but we have no hardware support for that, so it would
1038 * require waking up every 10-20 msecs and checking the counters
1039 * on the chip, and then turning the LED off if appropriate. That's
1040 * visible overhead, so not something we will do.
1041 *
1042 */
1045 {
1046 u64 extctl;
1048 /* the diags use the LED to indicate diag info, so we leave
1049 * the external LED alone when the diags are running */
1053 /*
1054 * start by setting both LED control bits to off, then turn
1055 * on the appropriate bit(s).
1056 */
1058 /*
1059 * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1060 * is inverted, because it is normally used to indicate
1061 * a hardware fault at reset, if there were errors
1062 */
1069 }
1073 INFINIPATH_EXTC_LED2PRIPORT_ON);
1078 }
1081 }
1084 {
1090 infinipath_i_bitsextant =
1093 INFINIPATH_I_RCVAVAIL_SHIFT) |
1097 infinipath_e_bitsextant =
1113 INFINIPATH_E_HARDWARE;
1115 infinipath_hwe_bitsextant =
1117 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1119 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1121 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1122 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1123 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1124 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1125 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1126 INFINIPATH_HWE_HTCMISCERR4 |
1128 INFINIPATH_HWE_HTCMISCERR7 |
1129 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1130 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1131 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1132 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1133 INFINIPATH_HWE_MEMBISTFAILED |
1134 INFINIPATH_HWE_COREPLL_FBSLIP |
1135 INFINIPATH_HWE_COREPLL_RFSLIP |
1136 INFINIPATH_HWE_HTBPLL_FBSLIP |
1137 INFINIPATH_HWE_HTBPLL_RFSLIP |
1138 INFINIPATH_HWE_HTAPLL_FBSLIP |
1139 INFINIPATH_HWE_HTAPLL_RFSLIP |
1140 INFINIPATH_HWE_SERDESPLLFAILED |
1141 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1142 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1146 }
1148 /**
1149 * ipath_ht_init_hwerrors - enable hardware errors
1150 * @dd: the infinipath device
1151 *
1152 * now that we have finished initializing everything that might reasonably
1153 * cause a hardware error, and cleared those errors bits as they occur,
1154 * we can enable hardware errors in the mask (potentially enabling
1155 * freeze mode), and enable hardware errors as errors (along with
1156 * everything else) in errormask
1157 */
1159 {
1160 ipath_err_t val;
1161 u64 extsval;
1170 /* barring bugs, all hwerrors become interrupts, which can */
1172 /* don't look at crc lane1 if 8 bit */
1175 /* don't look at crc lane1 if 8 bit */
1179 /*
1180 * disable RXDSYNCMEMPARITY because external serdes is unused,
1181 * and therefore the logic will never be used or initialized,
1182 * and uninitialized state will normally result in this error
1183 * being asserted. Similarly for the external serdess pll
1184 * lock signal.
1185 */
1187 INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1189 /*
1190 * Disable MISCERR4 because of an inversion in the HT core
1191 * logic checking for errors that cause this bit to be set.
1192 * The errata can also cause the protocol error bit to be set
1193 * in the HT config space linkerror register(s).
1194 */
1197 /*
1198 * PLL ignored because MDIO interface has a logic problem
1199 * for reads, on Comstock and Ponderosa. BRINGUP
1200 */
1204 }
1206 /**
1207 * ipath_ht_bringup_serdes - bring up the serdes
1208 * @dd: the infinipath device
1209 */
1211 {
1218 INFINIPATH_HWE_SERDESPLLFAILED)
1219 {
1223 INFINIPATH_HWE_SERDESPLLFAILED);
1224 }
1237 /* force reset on */
1238 val |= INFINIPATH_SERDC0_RESET_PLL
1239 /* | INFINIPATH_SERDC0_RESET_MASK */
1240 ;
1246 /* set lane resets, and tx idle, during pll reset */
1248 INFINIPATH_SERDC0_TXIDLE;
1252 val2);
1253 /*
1254 * be sure chip saw it
1255 */
1257 /*
1258 * need pll reset clear at least 11 usec before lane
1259 * resets cleared; give it a few more
1260 */
1263 }
1266 INFINIPATH_SERDC0_RESET_MASK |
1267 INFINIPATH_SERDC0_TXIDLE)) {
1269 INFINIPATH_SERDC0_RESET_MASK |
1270 INFINIPATH_SERDC0_TXIDLE);
1271 /* clear them */
1273 val);
1274 }
1280 INFINIPATH_XGXS_MDIOADDR_SHIFT);
1281 /*
1282 * we use address 3
1283 */
1286 }
1288 /* normally true after boot */
1291 }
1297 /* clear current and de-emphasis bits */
1299 /* set current to 20ma */
1301 /* set de-emphasis to -5.68dB */
1316 IPATH_MDIO_CTRL_XGXS_REG_8,
1322 else
1329 }
1331 /**
1332 * ipath_ht_quiet_serdes - set serdes to txidle
1333 * @dd: the infinipath device
1334 * driver is being unloaded
1335 */
1337 {
1344 }
1347 {
1355 }
1361 bail:
1363 }
1365 /**
1366 * ipath_pe_put_tid - write a TID in chip
1367 * @dd: the infinipath device
1368 * @tidptr: pointer to the expected TID (in chip) to udpate
1369 * @tidtype: 0 for eager, 1 for expected
1370 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1371 *
1372 * This exists as a separate routine to allow for special locking etc.
1373 * It's used for both the full cleanup on exit, as well as the normal
1374 * setup and teardown.
1375 */
1379 {
1383 "physaddr %lx has more than "
1386 }
1390 /* in words (fixed, full page). */
1394 }
1395 }
1398 }
1400 /**
1401 * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1402 * @dd: the infinipath device
1403 * @port: the port
1404 *
1405 * Used from ipath_close(), and at chip initialization.
1406 */
1408 {
1417 /*
1418 * need to invalidate all of the expected TID entries for this
1419 * port, so we don't have valid entries that might somehow get
1420 * used (early in next use of this port, or through some bug)
1421 */
1436 }
1438 /**
1439 * ipath_ht_tidtemplate - setup constants for TID updates
1440 * @dd: the infinipath device
1441 *
1442 * We setup stuff that we use a lot, to avoid calculating each time
1443 */
1445 {
1450 /*
1451 * work around chip errata bug 7358, by marking invalid tids
1452 * as having max length
1453 */
1455 INFINIPATH_RT_BUFSIZE_SHIFT;
1456 }
1459 {
1464 /*
1465 * one cache line; long IB headers will spill over into received
1466 * buffer
1467 */
1471 /*
1472 * For HT-400, we allocate a somewhat overly large eager buffer,
1473 * such that we can guarantee that we can receive the largest
1474 * packet that we can send out. To truly support a 4KB MTU,
1475 * we need to bump this to a large value. To date, other than
1476 * testing, we have never encountered an HCA that can really
1477 * send 4KB MTU packets, so we do not handle that (we'll get
1478 * errors interrupts if we ever see one).
1479 */
1483 /*
1484 * the min() check here is currently a nop, but it may not
1485 * always be, depending on just how we do ipath_rcvegrbufsize
1486 */
1492 /*
1493 * zero all the TID entries at startup. We do this for sanity,
1494 * in case of a previous driver crash of some kind, and also
1495 * because the chip powers up with these memories in an unknown
1496 * state. Use portcnt, not cfgports, since this is for the
1497 * full chip, not for current (possibly different) configuration
1498 * value.
1499 * Chip Errata bug 6447
1500 */
1504 /*
1505 * write the pbc of each buffer, to be sure it's initialized, then
1506 * cancel all the buffers, and also abort any packets that might
1507 * have been in flight for some reason (the latter is for driver
1508 * unload/reload, but isn't a bad idea at first init). PIO send
1509 * isn't enabled at this point, so there is no danger of sending
1510 * these out on the wire.
1511 * Chip Errata bug 6610
1512 */
1517 /*
1518 * reasonable word count, just to init pbc
1519 */
1522 }
1523 /*
1524 * self-clearing
1525 */
1527 INFINIPATH_S_ABORT);
1532 /*
1533 * Later production HT-460 has same changes as HT-465, so
1534 * can use GPIO interrupts. They have serial #'s starting
1535 * with 128, rather than 112.
1536 */
1539 }
1541 }
1543 /**
1544 * ipath_init_ht_get_base_info - set chip-specific flags for user code
1545 * @dd: the infinipath device
1546 * @kbase: ipath_base_info pointer
1547 *
1548 * We set the PCIE flag because the lower bandwidth on PCIe vs
1549 * HyperTransport can affect some user packet algorithims.
1550 */
1552 {
1556 IPATH_RUNTIME_RCVHDR_COPY;
1559 }
1561 /**
1562 * ipath_init_ht400_funcs - set up the chip-specific function pointers
1563 * @dd: the infinipath device
1564 *
1565 * This is global, and is called directly at init to set up the
1566 * chip-specific function pointers for later use.
1567 */
1569 {
1586 /*
1587 * initialize chip-specific variables
1588 */
1591 /*
1592 * setup the register offsets, since they are different for each
1593 * chip
1594 */
1598 /*
1599 * do very early init that is needed before ipath_f_bus is
1600 * called
1601 */
1603 }