2 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * This file contains all of the code that is specific to the
34 * InfiniPath PE-800 chip.
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/delay.h>
42 #include "ipath_kernel.h"
43 #include "ipath_registers.h"
46 * This file contains all the chip-specific register information and
47 * access functions for the PathScale PE800, the PCI-Express chip.
49 * This lists the InfiniPath PE800 registers, in the actual chip layout.
50 * This structure should never be directly accessed.
52 struct _infinipath_do_not_use_kernel_regs
{
53 unsigned long long Revision
;
54 unsigned long long Control
;
55 unsigned long long PageAlign
;
56 unsigned long long PortCnt
;
57 unsigned long long DebugPortSelect
;
58 unsigned long long Reserved0
;
59 unsigned long long SendRegBase
;
60 unsigned long long UserRegBase
;
61 unsigned long long CounterRegBase
;
62 unsigned long long Scratch
;
63 unsigned long long Reserved1
;
64 unsigned long long Reserved2
;
65 unsigned long long IntBlocked
;
66 unsigned long long IntMask
;
67 unsigned long long IntStatus
;
68 unsigned long long IntClear
;
69 unsigned long long ErrorMask
;
70 unsigned long long ErrorStatus
;
71 unsigned long long ErrorClear
;
72 unsigned long long HwErrMask
;
73 unsigned long long HwErrStatus
;
74 unsigned long long HwErrClear
;
75 unsigned long long HwDiagCtrl
;
76 unsigned long long MDIO
;
77 unsigned long long IBCStatus
;
78 unsigned long long IBCCtrl
;
79 unsigned long long ExtStatus
;
80 unsigned long long ExtCtrl
;
81 unsigned long long GPIOOut
;
82 unsigned long long GPIOMask
;
83 unsigned long long GPIOStatus
;
84 unsigned long long GPIOClear
;
85 unsigned long long RcvCtrl
;
86 unsigned long long RcvBTHQP
;
87 unsigned long long RcvHdrSize
;
88 unsigned long long RcvHdrCnt
;
89 unsigned long long RcvHdrEntSize
;
90 unsigned long long RcvTIDBase
;
91 unsigned long long RcvTIDCnt
;
92 unsigned long long RcvEgrBase
;
93 unsigned long long RcvEgrCnt
;
94 unsigned long long RcvBufBase
;
95 unsigned long long RcvBufSize
;
96 unsigned long long RxIntMemBase
;
97 unsigned long long RxIntMemSize
;
98 unsigned long long RcvPartitionKey
;
99 unsigned long long Reserved3
;
100 unsigned long long RcvPktLEDCnt
;
101 unsigned long long Reserved4
[8];
102 unsigned long long SendCtrl
;
103 unsigned long long SendPIOBufBase
;
104 unsigned long long SendPIOSize
;
105 unsigned long long SendPIOBufCnt
;
106 unsigned long long SendPIOAvailAddr
;
107 unsigned long long TxIntMemBase
;
108 unsigned long long TxIntMemSize
;
109 unsigned long long Reserved5
;
110 unsigned long long PCIeRBufTestReg0
;
111 unsigned long long PCIeRBufTestReg1
;
112 unsigned long long Reserved51
[6];
113 unsigned long long SendBufferError
;
114 unsigned long long SendBufferErrorCONT1
;
115 unsigned long long Reserved6SBE
[6];
116 unsigned long long RcvHdrAddr0
;
117 unsigned long long RcvHdrAddr1
;
118 unsigned long long RcvHdrAddr2
;
119 unsigned long long RcvHdrAddr3
;
120 unsigned long long RcvHdrAddr4
;
121 unsigned long long Reserved7RHA
[11];
122 unsigned long long RcvHdrTailAddr0
;
123 unsigned long long RcvHdrTailAddr1
;
124 unsigned long long RcvHdrTailAddr2
;
125 unsigned long long RcvHdrTailAddr3
;
126 unsigned long long RcvHdrTailAddr4
;
127 unsigned long long Reserved8RHTA
[11];
128 unsigned long long Reserved9SW
[8];
129 unsigned long long SerdesConfig0
;
130 unsigned long long SerdesConfig1
;
131 unsigned long long SerdesStatus
;
132 unsigned long long XGXSConfig
;
133 unsigned long long IBPLLCfg
;
134 unsigned long long Reserved10SW2
[3];
135 unsigned long long PCIEQ0SerdesConfig0
;
136 unsigned long long PCIEQ0SerdesConfig1
;
137 unsigned long long PCIEQ0SerdesStatus
;
138 unsigned long long Reserved11
;
139 unsigned long long PCIEQ1SerdesConfig0
;
140 unsigned long long PCIEQ1SerdesConfig1
;
141 unsigned long long PCIEQ1SerdesStatus
;
142 unsigned long long Reserved12
;
145 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
146 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
147 #define IPATH_CREG_OFFSET(field) (offsetof( \
148 struct infinipath_counters, field) / sizeof(u64))
150 static const struct ipath_kregs ipath_pe_kregs
= {
151 .kr_control
= IPATH_KREG_OFFSET(Control
),
152 .kr_counterregbase
= IPATH_KREG_OFFSET(CounterRegBase
),
153 .kr_debugportselect
= IPATH_KREG_OFFSET(DebugPortSelect
),
154 .kr_errorclear
= IPATH_KREG_OFFSET(ErrorClear
),
155 .kr_errormask
= IPATH_KREG_OFFSET(ErrorMask
),
156 .kr_errorstatus
= IPATH_KREG_OFFSET(ErrorStatus
),
157 .kr_extctrl
= IPATH_KREG_OFFSET(ExtCtrl
),
158 .kr_extstatus
= IPATH_KREG_OFFSET(ExtStatus
),
159 .kr_gpio_clear
= IPATH_KREG_OFFSET(GPIOClear
),
160 .kr_gpio_mask
= IPATH_KREG_OFFSET(GPIOMask
),
161 .kr_gpio_out
= IPATH_KREG_OFFSET(GPIOOut
),
162 .kr_gpio_status
= IPATH_KREG_OFFSET(GPIOStatus
),
163 .kr_hwdiagctrl
= IPATH_KREG_OFFSET(HwDiagCtrl
),
164 .kr_hwerrclear
= IPATH_KREG_OFFSET(HwErrClear
),
165 .kr_hwerrmask
= IPATH_KREG_OFFSET(HwErrMask
),
166 .kr_hwerrstatus
= IPATH_KREG_OFFSET(HwErrStatus
),
167 .kr_ibcctrl
= IPATH_KREG_OFFSET(IBCCtrl
),
168 .kr_ibcstatus
= IPATH_KREG_OFFSET(IBCStatus
),
169 .kr_intblocked
= IPATH_KREG_OFFSET(IntBlocked
),
170 .kr_intclear
= IPATH_KREG_OFFSET(IntClear
),
171 .kr_intmask
= IPATH_KREG_OFFSET(IntMask
),
172 .kr_intstatus
= IPATH_KREG_OFFSET(IntStatus
),
173 .kr_mdio
= IPATH_KREG_OFFSET(MDIO
),
174 .kr_pagealign
= IPATH_KREG_OFFSET(PageAlign
),
175 .kr_partitionkey
= IPATH_KREG_OFFSET(RcvPartitionKey
),
176 .kr_portcnt
= IPATH_KREG_OFFSET(PortCnt
),
177 .kr_rcvbthqp
= IPATH_KREG_OFFSET(RcvBTHQP
),
178 .kr_rcvbufbase
= IPATH_KREG_OFFSET(RcvBufBase
),
179 .kr_rcvbufsize
= IPATH_KREG_OFFSET(RcvBufSize
),
180 .kr_rcvctrl
= IPATH_KREG_OFFSET(RcvCtrl
),
181 .kr_rcvegrbase
= IPATH_KREG_OFFSET(RcvEgrBase
),
182 .kr_rcvegrcnt
= IPATH_KREG_OFFSET(RcvEgrCnt
),
183 .kr_rcvhdrcnt
= IPATH_KREG_OFFSET(RcvHdrCnt
),
184 .kr_rcvhdrentsize
= IPATH_KREG_OFFSET(RcvHdrEntSize
),
185 .kr_rcvhdrsize
= IPATH_KREG_OFFSET(RcvHdrSize
),
186 .kr_rcvintmembase
= IPATH_KREG_OFFSET(RxIntMemBase
),
187 .kr_rcvintmemsize
= IPATH_KREG_OFFSET(RxIntMemSize
),
188 .kr_rcvtidbase
= IPATH_KREG_OFFSET(RcvTIDBase
),
189 .kr_rcvtidcnt
= IPATH_KREG_OFFSET(RcvTIDCnt
),
190 .kr_revision
= IPATH_KREG_OFFSET(Revision
),
191 .kr_scratch
= IPATH_KREG_OFFSET(Scratch
),
192 .kr_sendbuffererror
= IPATH_KREG_OFFSET(SendBufferError
),
193 .kr_sendctrl
= IPATH_KREG_OFFSET(SendCtrl
),
194 .kr_sendpioavailaddr
= IPATH_KREG_OFFSET(SendPIOAvailAddr
),
195 .kr_sendpiobufbase
= IPATH_KREG_OFFSET(SendPIOBufBase
),
196 .kr_sendpiobufcnt
= IPATH_KREG_OFFSET(SendPIOBufCnt
),
197 .kr_sendpiosize
= IPATH_KREG_OFFSET(SendPIOSize
),
198 .kr_sendregbase
= IPATH_KREG_OFFSET(SendRegBase
),
199 .kr_txintmembase
= IPATH_KREG_OFFSET(TxIntMemBase
),
200 .kr_txintmemsize
= IPATH_KREG_OFFSET(TxIntMemSize
),
201 .kr_userregbase
= IPATH_KREG_OFFSET(UserRegBase
),
202 .kr_serdesconfig0
= IPATH_KREG_OFFSET(SerdesConfig0
),
203 .kr_serdesconfig1
= IPATH_KREG_OFFSET(SerdesConfig1
),
204 .kr_serdesstatus
= IPATH_KREG_OFFSET(SerdesStatus
),
205 .kr_xgxsconfig
= IPATH_KREG_OFFSET(XGXSConfig
),
206 .kr_ibpllcfg
= IPATH_KREG_OFFSET(IBPLLCfg
),
209 * These should not be used directly via ipath_read_kreg64(),
210 * use them with ipath_read_kreg64_port()
212 .kr_rcvhdraddr
= IPATH_KREG_OFFSET(RcvHdrAddr0
),
213 .kr_rcvhdrtailaddr
= IPATH_KREG_OFFSET(RcvHdrTailAddr0
),
215 /* This group is pe-800-specific; and used only in this file */
216 /* The rcvpktled register controls one of the debug port signals, so
217 * a packet activity LED can be connected to it. */
218 .kr_rcvpktledcnt
= IPATH_KREG_OFFSET(RcvPktLEDCnt
),
219 .kr_pcierbuftestreg0
= IPATH_KREG_OFFSET(PCIeRBufTestReg0
),
220 .kr_pcierbuftestreg1
= IPATH_KREG_OFFSET(PCIeRBufTestReg1
),
221 .kr_pcieq0serdesconfig0
= IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0
),
222 .kr_pcieq0serdesconfig1
= IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1
),
223 .kr_pcieq0serdesstatus
= IPATH_KREG_OFFSET(PCIEQ0SerdesStatus
),
224 .kr_pcieq1serdesconfig0
= IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0
),
225 .kr_pcieq1serdesconfig1
= IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1
),
226 .kr_pcieq1serdesstatus
= IPATH_KREG_OFFSET(PCIEQ1SerdesStatus
)
229 static const struct ipath_cregs ipath_pe_cregs
= {
230 .cr_badformatcnt
= IPATH_CREG_OFFSET(RxBadFormatCnt
),
231 .cr_erricrccnt
= IPATH_CREG_OFFSET(RxICRCErrCnt
),
232 .cr_errlinkcnt
= IPATH_CREG_OFFSET(RxLinkProblemCnt
),
233 .cr_errlpcrccnt
= IPATH_CREG_OFFSET(RxLPCRCErrCnt
),
234 .cr_errpkey
= IPATH_CREG_OFFSET(RxPKeyMismatchCnt
),
235 .cr_errrcvflowctrlcnt
= IPATH_CREG_OFFSET(RxFlowCtrlErrCnt
),
236 .cr_err_rlencnt
= IPATH_CREG_OFFSET(RxLenErrCnt
),
237 .cr_errslencnt
= IPATH_CREG_OFFSET(TxLenErrCnt
),
238 .cr_errtidfull
= IPATH_CREG_OFFSET(RxTIDFullErrCnt
),
239 .cr_errtidvalid
= IPATH_CREG_OFFSET(RxTIDValidErrCnt
),
240 .cr_errvcrccnt
= IPATH_CREG_OFFSET(RxVCRCErrCnt
),
241 .cr_ibstatuschange
= IPATH_CREG_OFFSET(IBStatusChangeCnt
),
242 .cr_intcnt
= IPATH_CREG_OFFSET(LBIntCnt
),
243 .cr_invalidrlencnt
= IPATH_CREG_OFFSET(RxMaxMinLenErrCnt
),
244 .cr_invalidslencnt
= IPATH_CREG_OFFSET(TxMaxMinLenErrCnt
),
245 .cr_lbflowstallcnt
= IPATH_CREG_OFFSET(LBFlowStallCnt
),
246 .cr_pktrcvcnt
= IPATH_CREG_OFFSET(RxDataPktCnt
),
247 .cr_pktrcvflowctrlcnt
= IPATH_CREG_OFFSET(RxFlowPktCnt
),
248 .cr_pktsendcnt
= IPATH_CREG_OFFSET(TxDataPktCnt
),
249 .cr_pktsendflowcnt
= IPATH_CREG_OFFSET(TxFlowPktCnt
),
250 .cr_portovflcnt
= IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt
),
251 .cr_rcvebpcnt
= IPATH_CREG_OFFSET(RxEBPCnt
),
252 .cr_rcvovflcnt
= IPATH_CREG_OFFSET(RxBufOvflCnt
),
253 .cr_senddropped
= IPATH_CREG_OFFSET(TxDroppedPktCnt
),
254 .cr_sendstallcnt
= IPATH_CREG_OFFSET(TxFlowStallCnt
),
255 .cr_sendunderruncnt
= IPATH_CREG_OFFSET(TxUnderrunCnt
),
256 .cr_wordrcvcnt
= IPATH_CREG_OFFSET(RxDwordCnt
),
257 .cr_wordsendcnt
= IPATH_CREG_OFFSET(TxDwordCnt
),
258 .cr_unsupvlcnt
= IPATH_CREG_OFFSET(TxUnsupVLErrCnt
),
259 .cr_rxdroppktcnt
= IPATH_CREG_OFFSET(RxDroppedPktCnt
),
260 .cr_iblinkerrrecovcnt
= IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt
),
261 .cr_iblinkdowncnt
= IPATH_CREG_OFFSET(IBLinkDownedCnt
),
262 .cr_ibsymbolerrcnt
= IPATH_CREG_OFFSET(IBSymbolErrCnt
)
265 /* kr_intstatus, kr_intclear, kr_intmask bits */
266 #define INFINIPATH_I_RCVURG_MASK 0x1F
267 #define INFINIPATH_I_RCVAVAIL_MASK 0x1F
269 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
270 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
271 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
272 #define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
273 #define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
274 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
275 #define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
276 #define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
277 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
278 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
279 #define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
280 #define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
281 #define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
283 /* kr_extstatus bits */
284 #define INFINIPATH_EXTS_FREQSEL 0x2
285 #define INFINIPATH_EXTS_SERDESSEL 0x4
286 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
287 #define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
289 #define _IPATH_GPIO_SDA_NUM 1
290 #define _IPATH_GPIO_SCL_NUM 0
292 #define IPATH_GPIO_SDA (1ULL << \
293 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
294 #define IPATH_GPIO_SCL (1ULL << \
295 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
298 * ipath_pe_handle_hwerrors - display hardware errors.
299 * @dd: the infinipath device
300 * @msg: the output buffer
301 * @msgl: the size of the output buffer
303 * Use same msg buffer as regular errors to avoid excessive stack
304 * use. Most hardware errors are catastrophic, but for right now,
305 * we'll print them and continue. We reuse the same message buffer as
306 * ipath_handle_errors() to avoid excessive stack usage.
308 static void ipath_pe_handle_hwerrors(struct ipath_devdata
*dd
, char *msg
,
316 hwerrs
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_hwerrstatus
);
319 * better than printing cofusing messages
320 * This seems to be related to clearing the crc error, or
321 * the pll error during init.
323 ipath_cdbg(VERBOSE
, "Called but no hardware errors set\n");
325 } else if (hwerrs
== ~0ULL) {
326 ipath_dev_err(dd
, "Read of hardware error status failed "
327 "(all bits set); ignoring\n");
330 ipath_stats
.sps_hwerrs
++;
332 /* Always clear the error status register, except MEMBISTFAIL,
333 * regardless of whether we continue or stop using the chip.
334 * We want that set so we know it failed, even across driver reload.
335 * We'll still ignore it in the hwerrmask. We do this partly for
336 * diagnostics, but also for support */
337 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrclear
,
338 hwerrs
&~INFINIPATH_HWE_MEMBISTFAILED
);
340 hwerrs
&= dd
->ipath_hwerrmask
;
343 * make sure we get this much out, unless told to be quiet,
344 * or it's occurred within the last 5 seconds
346 if ((hwerrs
& ~dd
->ipath_lasthwerror
) ||
347 (ipath_debug
& __IPATH_VERBDBG
))
348 dev_info(&dd
->pcidev
->dev
, "Hardware error: hwerr=0x%llx "
349 "(cleared)\n", (unsigned long long) hwerrs
);
350 dd
->ipath_lasthwerror
|= hwerrs
;
352 if (hwerrs
& ~infinipath_hwe_bitsextant
)
353 ipath_dev_err(dd
, "hwerror interrupt with unknown errors "
354 "%llx set\n", (unsigned long long)
355 (hwerrs
& ~infinipath_hwe_bitsextant
));
357 ctrl
= ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_control
);
358 if (ctrl
& INFINIPATH_C_FREEZEMODE
) {
361 * if any set that we aren't ignoring only make the
362 * complaint once, in case it's stuck or recurring,
363 * and we get here multiple times
365 if (dd
->ipath_flags
& IPATH_INITTED
) {
366 ipath_dev_err(dd
, "Fatal Error (freeze "
367 "mode), no longer usable\n");
371 * Mark as having had an error for driver, and also
372 * for /sys and status word mapped to user programs.
373 * This marks unit as not usable, until reset
375 *dd
->ipath_statusp
&= ~IPATH_STATUS_IB_READY
;
376 *dd
->ipath_statusp
|= IPATH_STATUS_HWERROR
;
377 dd
->ipath_flags
&= ~IPATH_INITTED
;
379 ipath_dbg("Clearing freezemode on ignored hardware "
381 ctrl
&= ~INFINIPATH_C_FREEZEMODE
;
382 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_control
,
389 if (hwerrs
& INFINIPATH_HWE_MEMBISTFAILED
) {
390 strlcat(msg
, "[Memory BIST test failed, PE-800 unusable]",
392 /* ignore from now on, so disable until driver reloaded */
393 *dd
->ipath_statusp
|= IPATH_STATUS_HWERROR
;
394 dd
->ipath_hwerrmask
&= ~INFINIPATH_HWE_MEMBISTFAILED
;
395 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrmask
,
396 dd
->ipath_hwerrmask
);
398 if (hwerrs
& (INFINIPATH_HWE_RXEMEMPARITYERR_MASK
399 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT
)) {
400 bits
= (u32
) ((hwerrs
>>
401 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT
) &
402 INFINIPATH_HWE_RXEMEMPARITYERR_MASK
);
403 snprintf(bitsmsg
, sizeof bitsmsg
, "[RXE Parity Errs %x] ",
405 strlcat(msg
, bitsmsg
, msgl
);
407 if (hwerrs
& (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
408 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT
)) {
409 bits
= (u32
) ((hwerrs
>>
410 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT
) &
411 INFINIPATH_HWE_TXEMEMPARITYERR_MASK
);
412 snprintf(bitsmsg
, sizeof bitsmsg
, "[TXE Parity Errs %x] ",
414 strlcat(msg
, bitsmsg
, msgl
);
416 if (hwerrs
& (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
417 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT
)) {
418 bits
= (u32
) ((hwerrs
>>
419 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT
) &
420 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
);
421 snprintf(bitsmsg
, sizeof bitsmsg
,
422 "[PCIe Mem Parity Errs %x] ", bits
);
423 strlcat(msg
, bitsmsg
, msgl
);
425 if (hwerrs
& INFINIPATH_HWE_IBCBUSTOSPCPARITYERR
)
426 strlcat(msg
, "[IB2IPATH Parity]", msgl
);
427 if (hwerrs
& INFINIPATH_HWE_IBCBUSFRSPCPARITYERR
)
428 strlcat(msg
, "[IPATH2IB Parity]", msgl
);
430 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
431 INFINIPATH_HWE_COREPLL_RFSLIP )
433 if (hwerrs
& _IPATH_PLL_FAIL
) {
434 snprintf(bitsmsg
, sizeof bitsmsg
,
435 "[PLL failed (%llx), PE-800 unusable]",
436 (unsigned long long) hwerrs
& _IPATH_PLL_FAIL
);
437 strlcat(msg
, bitsmsg
, msgl
);
438 /* ignore from now on, so disable until driver reloaded */
439 dd
->ipath_hwerrmask
&= ~(hwerrs
& _IPATH_PLL_FAIL
);
440 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrmask
,
441 dd
->ipath_hwerrmask
);
444 if (hwerrs
& INFINIPATH_HWE_SERDESPLLFAILED
) {
446 * If it occurs, it is left masked since the eternal
447 * interface is unused
449 dd
->ipath_hwerrmask
&= ~INFINIPATH_HWE_SERDESPLLFAILED
;
450 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrmask
,
451 dd
->ipath_hwerrmask
);
454 if (hwerrs
& INFINIPATH_HWE_PCIEPOISONEDTLP
)
455 strlcat(msg
, "[PCIe Poisoned TLP]", msgl
);
456 if (hwerrs
& INFINIPATH_HWE_PCIECPLTIMEOUT
)
457 strlcat(msg
, "[PCIe completion timeout]", msgl
);
460 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
461 * parity or memory parity error failures, because most likely we
462 * won't be able to talk to the core of the chip. Nonetheless, we
463 * might see them, if they are in parts of the PCIe core that aren't
466 if (hwerrs
& INFINIPATH_HWE_PCIE1PLLFAILED
)
467 strlcat(msg
, "[PCIePLL1]", msgl
);
468 if (hwerrs
& INFINIPATH_HWE_PCIE0PLLFAILED
)
469 strlcat(msg
, "[PCIePLL0]", msgl
);
470 if (hwerrs
& INFINIPATH_HWE_PCIEBUSPARITYXTLH
)
471 strlcat(msg
, "[PCIe XTLH core parity]", msgl
);
472 if (hwerrs
& INFINIPATH_HWE_PCIEBUSPARITYXADM
)
473 strlcat(msg
, "[PCIe ADM TX core parity]", msgl
);
474 if (hwerrs
& INFINIPATH_HWE_PCIEBUSPARITYRADM
)
475 strlcat(msg
, "[PCIe ADM RX core parity]", msgl
);
477 if (hwerrs
& INFINIPATH_HWE_RXDSYNCMEMPARITYERR
)
478 strlcat(msg
, "[Rx Dsync]", msgl
);
479 if (hwerrs
& INFINIPATH_HWE_SERDESPLLFAILED
)
480 strlcat(msg
, "[SerDes PLL]", msgl
);
482 ipath_dev_err(dd
, "%s hardware error\n", msg
);
483 if (isfatal
&& !ipath_diag_inuse
&& dd
->ipath_freezemsg
) {
485 * for /sys status file ; if no trailing } is copied, we'll
486 * know it was truncated.
488 snprintf(dd
->ipath_freezemsg
, dd
->ipath_freezelen
,
494 * ipath_pe_boardname - fill in the board name
495 * @dd: the infinipath device
496 * @name: the output buffer
497 * @namelen: the size of the output buffer
499 * info is based on the board revision register
501 static int ipath_pe_boardname(struct ipath_devdata
*dd
, char *name
,
505 u8 boardrev
= dd
->ipath_boardrev
;
510 n
= "InfiniPath_Emulation";
513 n
= "InfiniPath_PE-800-Bringup";
516 n
= "InfiniPath_PE-880";
519 n
= "InfiniPath_PE-850";
522 n
= "InfiniPath_PE-860";
526 "Don't yet know about board with ID %u\n",
528 snprintf(name
, namelen
, "Unknown_InfiniPath_PE-8xx_%u",
533 snprintf(name
, namelen
, "%s", n
);
535 if (dd
->ipath_majrev
!= 4 || dd
->ipath_minrev
!= 1) {
536 ipath_dev_err(dd
, "Unsupported PE-800 revision %u.%u!\n",
537 dd
->ipath_majrev
, dd
->ipath_minrev
);
546 * ipath_pe_init_hwerrors - enable hardware errors
547 * @dd: the infinipath device
549 * now that we have finished initializing everything that might reasonably
550 * cause a hardware error, and cleared those errors bits as they occur,
551 * we can enable hardware errors in the mask (potentially enabling
552 * freeze mode), and enable hardware errors as errors (along with
553 * everything else) in errormask
555 static void ipath_pe_init_hwerrors(struct ipath_devdata
*dd
)
560 extsval
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_extstatus
);
562 if (!(extsval
& INFINIPATH_EXTS_MEMBIST_ENDTEST
))
563 ipath_dev_err(dd
, "MemBIST did not complete!\n");
565 val
= ~0ULL; /* barring bugs, all hwerrors become interrupts, */
567 if (!dd
->ipath_boardrev
) // no PLL for Emulator
568 val
&= ~INFINIPATH_HWE_SERDESPLLFAILED
;
570 /* workaround bug 9460 in internal interface bus parity checking */
571 val
&= ~INFINIPATH_HWE_PCIEBUSPARITYRADM
;
573 dd
->ipath_hwerrmask
= val
;
577 * ipath_pe_bringup_serdes - bring up the serdes
578 * @dd: the infinipath device
580 static int ipath_pe_bringup_serdes(struct ipath_devdata
*dd
)
582 u64 val
, tmp
, config1
;
583 int ret
= 0, change
= 0;
585 ipath_dbg("Trying to bringup serdes\n");
587 if (ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_hwerrstatus
) &
588 INFINIPATH_HWE_SERDESPLLFAILED
) {
589 ipath_dbg("At start, serdes PLL failed bit set "
590 "in hwerrstatus, clearing and continuing\n");
591 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrclear
,
592 INFINIPATH_HWE_SERDESPLLFAILED
);
595 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_serdesconfig0
);
596 config1
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_serdesconfig1
);
598 ipath_cdbg(VERBOSE
, "SerDes status config0=%llx config1=%llx, "
599 "xgxsconfig %llx\n", (unsigned long long) val
,
600 (unsigned long long) config1
, (unsigned long long)
601 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_xgxsconfig
));
604 * Force reset on, also set rxdetect enable. Must do before reading
605 * serdesstatus at least for simulation, or some of the bits in
606 * serdes status will come back as undefined and cause simulation
609 val
|= INFINIPATH_SERDC0_RESET_PLL
| INFINIPATH_SERDC0_RXDETECT_EN
610 | INFINIPATH_SERDC0_L1PWR_DN
;
611 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_serdesconfig0
, val
);
612 /* be sure chip saw it */
613 tmp
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
614 udelay(5); /* need pll reset set at least for a bit */
616 * after PLL is reset, set the per-lane Resets and TxIdle and
617 * clear the PLL reset and rxdetect (to get falling edge).
618 * Leave L1PWR bits set (permanently)
620 val
&= ~(INFINIPATH_SERDC0_RXDETECT_EN
| INFINIPATH_SERDC0_RESET_PLL
621 | INFINIPATH_SERDC0_L1PWR_DN
);
622 val
|= INFINIPATH_SERDC0_RESET_MASK
| INFINIPATH_SERDC0_TXIDLE
;
623 ipath_cdbg(VERBOSE
, "Clearing pll reset and setting lane resets "
624 "and txidle (%llx)\n", (unsigned long long) val
);
625 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_serdesconfig0
, val
);
626 /* be sure chip saw it */
627 tmp
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
628 /* need PLL reset clear for at least 11 usec before lane
629 * resets cleared; give it a few more to be sure */
631 val
&= ~(INFINIPATH_SERDC0_RESET_MASK
| INFINIPATH_SERDC0_TXIDLE
);
633 ipath_cdbg(VERBOSE
, "Clearing lane resets and txidle "
634 "(writing %llx)\n", (unsigned long long) val
);
635 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_serdesconfig0
, val
);
636 /* be sure chip saw it */
637 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
639 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_xgxsconfig
);
640 if (((val
>> INFINIPATH_XGXS_MDIOADDR_SHIFT
) &
641 INFINIPATH_XGXS_MDIOADDR_MASK
) != 3) {
643 ~(INFINIPATH_XGXS_MDIOADDR_MASK
<<
644 INFINIPATH_XGXS_MDIOADDR_SHIFT
);
646 val
|= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT
;
649 if (val
& INFINIPATH_XGXS_RESET
) {
650 val
&= ~INFINIPATH_XGXS_RESET
;
654 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_xgxsconfig
, val
);
656 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_serdesconfig0
);
658 /* clear current and de-emphasis bits */
659 config1
&= ~0x0ffffffff00ULL
;
660 /* set current to 20ma */
661 config1
|= 0x00000000000ULL
;
662 /* set de-emphasis to -5.68dB */
663 config1
|= 0x0cccc000000ULL
;
664 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_serdesconfig1
, config1
);
666 ipath_cdbg(VERBOSE
, "done: SerDes status config0=%llx "
667 "config1=%llx, sstatus=%llx xgxs=%llx\n",
668 (unsigned long long) val
, (unsigned long long) config1
,
670 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_serdesstatus
),
672 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_xgxsconfig
));
674 if (!ipath_waitfor_mdio_cmdready(dd
)) {
676 dd
, dd
->ipath_kregs
->kr_mdio
,
677 ipath_mdio_req(IPATH_MDIO_CMD_READ
, 31,
678 IPATH_MDIO_CTRL_XGXS_REG_8
, 0));
679 if (ipath_waitfor_complete(dd
, dd
->ipath_kregs
->kr_mdio
,
680 IPATH_MDIO_DATAVALID
, &val
))
681 ipath_dbg("Never got MDIO data for XGXS "
684 ipath_cdbg(VERBOSE
, "MDIO Read reg8, "
685 "'bank' 31 %x\n", (u32
) val
);
687 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
693 * ipath_pe_quiet_serdes - set serdes to txidle
694 * @dd: the infinipath device
695 * Called when driver is being unloaded
697 static void ipath_pe_quiet_serdes(struct ipath_devdata
*dd
)
699 u64 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_serdesconfig0
);
701 val
|= INFINIPATH_SERDC0_TXIDLE
;
702 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
703 (unsigned long long) val
);
704 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_serdesconfig0
, val
);
707 /* this is not yet needed on the PE800, so just return 0. */
708 static int ipath_pe_intconfig(struct ipath_devdata
*dd
)
714 * ipath_setup_pe_setextled - set the state of the two external LEDs
715 * @dd: the infinipath device
717 * @ltst: the LT state
719 * These LEDs indicate the physical and logical state of IB link.
720 * For this chip (at least with recommended board pinouts), LED1
721 * is Yellow (logical state) and LED2 is Green (physical state),
723 * Note: We try to match the Mellanox HCA LED behavior as best
724 * we can. Green indicates physical link state is OK (something is
725 * plugged in, and we can train).
726 * Amber indicates the link is logically up (ACTIVE).
727 * Mellanox further blinks the amber LED to indicate data packet
728 * activity, but we have no hardware support for that, so it would
729 * require waking up every 10-20 msecs and checking the counters
730 * on the chip, and then turning the LED off if appropriate. That's
731 * visible overhead, so not something we will do.
734 static void ipath_setup_pe_setextled(struct ipath_devdata
*dd
, u64 lst
,
739 /* the diags use the LED to indicate diag info, so we leave
740 * the external LED alone when the diags are running */
741 if (ipath_diag_inuse
)
744 extctl
= dd
->ipath_extctrl
& ~(INFINIPATH_EXTC_LED1PRIPORT_ON
|
745 INFINIPATH_EXTC_LED2PRIPORT_ON
);
747 if (ltst
& INFINIPATH_IBCS_LT_STATE_LINKUP
)
748 extctl
|= INFINIPATH_EXTC_LED2PRIPORT_ON
;
749 if (lst
== INFINIPATH_IBCS_L_STATE_ACTIVE
)
750 extctl
|= INFINIPATH_EXTC_LED1PRIPORT_ON
;
751 dd
->ipath_extctrl
= extctl
;
752 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_extctrl
, extctl
);
756 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
757 * @dd: the infinipath device
759 * This is called during driver unload.
760 * We do the pci_disable_msi here, not in generic code, because it
761 * isn't used for the HT-400. If we do end up needing pci_enable_msi
762 * at some point in the future for HT-400, we'll move the call back
763 * into the main init_one code.
765 static void ipath_setup_pe_cleanup(struct ipath_devdata
*dd
)
767 dd
->ipath_msi_lo
= 0; /* just in case unload fails */
768 pci_disable_msi(dd
->pcidev
);
772 * ipath_setup_pe_config - setup PCIe config related stuff
773 * @dd: the infinipath device
774 * @pdev: the PCI device
776 * The pci_enable_msi() call will fail on systems with MSI quirks
777 * such as those with AMD8131, even if the device of interest is not
778 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
780 * All that can be done is to edit the kernel source to remove the quirk
781 * check until that is fixed.
782 * We do not need to call enable_msi() for our HyperTransport chip (HT-400),
783 * even those it uses MSI, and we want to avoid the quirk warning, so
784 * So we call enable_msi only for the PE-800. If we do end up needing
785 * pci_enable_msi at some point in the future for HT-400, we'll move the
786 * call back into the main init_one code.
787 * We save the msi lo and hi values, so we can restore them after
788 * chip reset (the kernel PCI infrastructure doesn't yet handle that
791 static int ipath_setup_pe_config(struct ipath_devdata
*dd
,
792 struct pci_dev
*pdev
)
796 dd
->ipath_msi_lo
= 0; /* used as a flag during reset processing */
797 ret
= pci_enable_msi(dd
->pcidev
);
799 ipath_dev_err(dd
, "pci_enable_msi failed: %d, "
800 "interrupts may not work\n", ret
);
801 /* continue even if it fails, we may still be OK... */
803 if ((pos
= pci_find_capability(dd
->pcidev
, PCI_CAP_ID_MSI
))) {
805 pci_read_config_dword(dd
->pcidev
, pos
+ PCI_MSI_ADDRESS_LO
,
807 pci_read_config_dword(dd
->pcidev
, pos
+ PCI_MSI_ADDRESS_HI
,
809 pci_read_config_word(dd
->pcidev
, pos
+ PCI_MSI_FLAGS
,
811 /* now save the data (vector) info */
812 pci_read_config_word(dd
->pcidev
,
813 pos
+ ((control
& PCI_MSI_FLAGS_64BIT
)
815 &dd
->ipath_msi_data
);
816 ipath_cdbg(VERBOSE
, "Read msi data 0x%x from config offset "
817 "0x%x, control=0x%x\n", dd
->ipath_msi_data
,
818 pos
+ ((control
& PCI_MSI_FLAGS_64BIT
) ? 12 : 8),
820 /* we save the cachelinesize also, although it doesn't
822 pci_read_config_byte(dd
->pcidev
, PCI_CACHE_LINE_SIZE
,
823 &dd
->ipath_pci_cacheline
);
825 ipath_dev_err(dd
, "Can't find MSI capability, "
826 "can't save MSI settings for reset\n");
827 if ((pos
= pci_find_capability(dd
->pcidev
, PCI_CAP_ID_EXP
))) {
829 pci_read_config_word(dd
->pcidev
, pos
+ PCI_EXP_LNKSTA
,
834 ipath_dev_err(dd
, "PCIe width %u, "
835 "performance reduced\n", linkstat
);
838 ipath_dev_err(dd
, "Can't find PCI Express "
843 static void ipath_init_pe_variables(void)
846 * bits for selecting i2c direction and values,
847 * used for I2C serial flash
849 ipath_gpio_sda_num
= _IPATH_GPIO_SDA_NUM
;
850 ipath_gpio_scl_num
= _IPATH_GPIO_SCL_NUM
;
851 ipath_gpio_sda
= IPATH_GPIO_SDA
;
852 ipath_gpio_scl
= IPATH_GPIO_SCL
;
854 /* variables for sanity checking interrupt and errors */
855 infinipath_hwe_bitsextant
=
856 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK
<<
857 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT
) |
858 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
<<
859 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT
) |
860 INFINIPATH_HWE_PCIE1PLLFAILED
|
861 INFINIPATH_HWE_PCIE0PLLFAILED
|
862 INFINIPATH_HWE_PCIEPOISONEDTLP
|
863 INFINIPATH_HWE_PCIECPLTIMEOUT
|
864 INFINIPATH_HWE_PCIEBUSPARITYXTLH
|
865 INFINIPATH_HWE_PCIEBUSPARITYXADM
|
866 INFINIPATH_HWE_PCIEBUSPARITYRADM
|
867 INFINIPATH_HWE_MEMBISTFAILED
|
868 INFINIPATH_HWE_COREPLL_FBSLIP
|
869 INFINIPATH_HWE_COREPLL_RFSLIP
|
870 INFINIPATH_HWE_SERDESPLLFAILED
|
871 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR
|
872 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR
;
873 infinipath_i_bitsextant
=
874 (INFINIPATH_I_RCVURG_MASK
<< INFINIPATH_I_RCVURG_SHIFT
) |
875 (INFINIPATH_I_RCVAVAIL_MASK
<<
876 INFINIPATH_I_RCVAVAIL_SHIFT
) |
877 INFINIPATH_I_ERROR
| INFINIPATH_I_SPIOSENT
|
878 INFINIPATH_I_SPIOBUFAVAIL
| INFINIPATH_I_GPIO
;
879 infinipath_e_bitsextant
=
880 INFINIPATH_E_RFORMATERR
| INFINIPATH_E_RVCRC
|
881 INFINIPATH_E_RICRC
| INFINIPATH_E_RMINPKTLEN
|
882 INFINIPATH_E_RMAXPKTLEN
| INFINIPATH_E_RLONGPKTLEN
|
883 INFINIPATH_E_RSHORTPKTLEN
| INFINIPATH_E_RUNEXPCHAR
|
884 INFINIPATH_E_RUNSUPVL
| INFINIPATH_E_REBP
|
885 INFINIPATH_E_RIBFLOW
| INFINIPATH_E_RBADVERSION
|
886 INFINIPATH_E_RRCVEGRFULL
| INFINIPATH_E_RRCVHDRFULL
|
887 INFINIPATH_E_RBADTID
| INFINIPATH_E_RHDRLEN
|
888 INFINIPATH_E_RHDR
| INFINIPATH_E_RIBLOSTLINK
|
889 INFINIPATH_E_SMINPKTLEN
| INFINIPATH_E_SMAXPKTLEN
|
890 INFINIPATH_E_SUNDERRUN
| INFINIPATH_E_SPKTLEN
|
891 INFINIPATH_E_SDROPPEDSMPPKT
| INFINIPATH_E_SDROPPEDDATAPKT
|
892 INFINIPATH_E_SPIOARMLAUNCH
| INFINIPATH_E_SUNEXPERRPKTNUM
|
893 INFINIPATH_E_SUNSUPVL
| INFINIPATH_E_IBSTATUSCHANGED
|
894 INFINIPATH_E_INVALIDADDR
| INFINIPATH_E_RESET
|
895 INFINIPATH_E_HARDWARE
;
897 infinipath_i_rcvavail_mask
= INFINIPATH_I_RCVAVAIL_MASK
;
898 infinipath_i_rcvurg_mask
= INFINIPATH_I_RCVURG_MASK
;
901 /* setup the MSI stuff again after a reset. I'd like to just call
902 * pci_enable_msi() and request_irq() again, but when I do that,
903 * the MSI enable bit doesn't get set in the command word, and
904 * we switch to to a different interrupt vector, which is confusing,
905 * so I instead just do it all inline. Perhaps somehow can tie this
906 * into the PCIe hotplug support at some point
907 * Note, because I'm doing it all here, I don't call pci_disable_msi()
908 * or free_irq() at the start of ipath_setup_pe_reset().
910 static int ipath_reinit_msi(struct ipath_devdata
*dd
)
916 if (!dd
->ipath_msi_lo
) {
917 dev_info(&dd
->pcidev
->dev
, "Can't restore MSI config, "
918 "initial setup failed?\n");
923 if (!(pos
= pci_find_capability(dd
->pcidev
, PCI_CAP_ID_MSI
))) {
924 ipath_dev_err(dd
, "Can't find MSI capability, "
925 "can't restore MSI settings\n");
929 ipath_cdbg(VERBOSE
, "Writing msi_lo 0x%x to config offset 0x%x\n",
930 dd
->ipath_msi_lo
, pos
+ PCI_MSI_ADDRESS_LO
);
931 pci_write_config_dword(dd
->pcidev
, pos
+ PCI_MSI_ADDRESS_LO
,
933 ipath_cdbg(VERBOSE
, "Writing msi_lo 0x%x to config offset 0x%x\n",
934 dd
->ipath_msi_hi
, pos
+ PCI_MSI_ADDRESS_HI
);
935 pci_write_config_dword(dd
->pcidev
, pos
+ PCI_MSI_ADDRESS_HI
,
937 pci_read_config_word(dd
->pcidev
, pos
+ PCI_MSI_FLAGS
, &control
);
938 if (!(control
& PCI_MSI_FLAGS_ENABLE
)) {
939 ipath_cdbg(VERBOSE
, "MSI control at off %x was %x, "
940 "setting MSI enable (%x)\n", pos
+ PCI_MSI_FLAGS
,
941 control
, control
| PCI_MSI_FLAGS_ENABLE
);
942 control
|= PCI_MSI_FLAGS_ENABLE
;
943 pci_write_config_word(dd
->pcidev
, pos
+ PCI_MSI_FLAGS
,
946 /* now rewrite the data (vector) info */
947 pci_write_config_word(dd
->pcidev
, pos
+
948 ((control
& PCI_MSI_FLAGS_64BIT
) ? 12 : 8),
950 /* we restore the cachelinesize also, although it doesn't really
952 pci_write_config_byte(dd
->pcidev
, PCI_CACHE_LINE_SIZE
,
953 dd
->ipath_pci_cacheline
);
954 /* and now set the pci master bit again */
955 pci_set_master(dd
->pcidev
);
962 /* This routine sleeps, so it can only be called from user context, not
963 * from interrupt context. If we need interrupt context, we can split
964 * it into two routines.
966 static int ipath_setup_pe_reset(struct ipath_devdata
*dd
)
972 /* Use ERROR so it shows up in logs, etc. */
973 ipath_dev_err(dd
, "Resetting PE-800 unit %u\n",
975 /* keep chip from being accessed in a few places */
976 dd
->ipath_flags
&= ~(IPATH_INITTED
|IPATH_PRESENT
);
977 val
= dd
->ipath_control
| INFINIPATH_C_RESET
;
978 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_control
, val
);
981 for (i
= 1; i
<= 5; i
++) {
983 /* allow MBIST, etc. to complete; longer on each retry.
984 * We sometimes get machine checks from bus timeout if no
985 * response, so for now, make it *really* long.
987 msleep(1000 + (1 + i
) * 2000);
989 pci_write_config_dword(dd
->pcidev
, PCI_BASE_ADDRESS_0
,
991 ipath_dev_err(dd
, "rewrite of BAR0 failed: %d\n",
994 pci_write_config_dword(dd
->pcidev
, PCI_BASE_ADDRESS_1
,
996 ipath_dev_err(dd
, "rewrite of BAR1 failed: %d\n",
998 /* now re-enable memory access */
999 if ((r
= pci_enable_device(dd
->pcidev
)))
1000 ipath_dev_err(dd
, "pci_enable_device failed after "
1002 /* whether it worked or not, mark as present, again */
1003 dd
->ipath_flags
|= IPATH_PRESENT
;
1004 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_revision
);
1005 if (val
== dd
->ipath_revision
) {
1006 ipath_cdbg(VERBOSE
, "Got matching revision "
1007 "register %llx on try %d\n",
1008 (unsigned long long) val
, i
);
1009 ret
= ipath_reinit_msi(dd
);
1012 /* Probably getting -1 back */
1013 ipath_dbg("Didn't get expected revision register, "
1014 "got %llx, try %d\n", (unsigned long long) val
,
1017 ret
= 0; /* failed */
1024 * ipath_pe_put_tid - write a TID in chip
1025 * @dd: the infinipath device
1026 * @tidptr: pointer to the expected TID (in chip) to udpate
1027 * @tidtype: 0 for eager, 1 for expected
1028 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1030 * This exists as a separate routine to allow for special locking etc.
1031 * It's used for both the full cleanup on exit, as well as the normal
1032 * setup and teardown.
1034 static void ipath_pe_put_tid(struct ipath_devdata
*dd
, u64 __iomem
*tidptr
,
1035 u32 type
, unsigned long pa
)
1037 u32 __iomem
*tidp32
= (u32 __iomem
*)tidptr
;
1038 unsigned long flags
= 0; /* keep gcc quiet */
1040 if (pa
!= dd
->ipath_tidinvalid
) {
1041 if (pa
& ((1U << 11) - 1)) {
1042 dev_info(&dd
->pcidev
->dev
, "BUG: physaddr %lx "
1043 "not 4KB aligned!\n", pa
);
1047 /* paranoia check */
1050 "BUG: Physical page address 0x%lx "
1051 "has bits set in 31-29\n", pa
);
1054 pa
|= dd
->ipath_tidtemplate
;
1055 else /* for now, always full 4KB page */
1059 /* workaround chip bug 9437 by writing each TID twice
1060 * and holding a spinlock around the writes, so they don't
1061 * intermix with other TID (eager or expected) writes
1062 * Unfortunately, this call can be done from interrupt level
1063 * for the port 0 eager TIDs, so we have to use irqsave
1065 spin_lock_irqsave(&dd
->ipath_tid_lock
, flags
);
1066 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_scratch
, 0xfeeddeaf);
1067 if (dd
->ipath_kregbase
)
1069 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_scratch
, 0xdeadbeef);
1071 spin_unlock_irqrestore(&dd
->ipath_tid_lock
, flags
);
1075 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1076 * @dd: the infinipath device
1079 * clear all TID entries for a port, expected and eager.
1080 * Used from ipath_close(). On PE800, TIDs are only 32 bits,
1081 * not 64, but they are still on 64 bit boundaries, so tidbase
1082 * is declared as u64 * for the pointer math, even though we write 32 bits
1084 static void ipath_pe_clear_tids(struct ipath_devdata
*dd
, unsigned port
)
1086 u64 __iomem
*tidbase
;
1087 unsigned long tidinv
;
1090 if (!dd
->ipath_kregbase
)
1093 ipath_cdbg(VERBOSE
, "Invalidate TIDs for port %u\n", port
);
1095 tidinv
= dd
->ipath_tidinvalid
;
1096 tidbase
= (u64 __iomem
*)
1097 ((char __iomem
*)(dd
->ipath_kregbase
) +
1098 dd
->ipath_rcvtidbase
+
1099 port
* dd
->ipath_rcvtidcnt
* sizeof(*tidbase
));
1101 for (i
= 0; i
< dd
->ipath_rcvtidcnt
; i
++)
1102 ipath_pe_put_tid(dd
, &tidbase
[i
], 0, tidinv
);
1104 tidbase
= (u64 __iomem
*)
1105 ((char __iomem
*)(dd
->ipath_kregbase
) +
1106 dd
->ipath_rcvegrbase
+
1107 port
* dd
->ipath_rcvegrcnt
* sizeof(*tidbase
));
1109 for (i
= 0; i
< dd
->ipath_rcvegrcnt
; i
++)
1110 ipath_pe_put_tid(dd
, &tidbase
[i
], 1, tidinv
);
1114 * ipath_pe_tidtemplate - setup constants for TID updates
1115 * @dd: the infinipath device
1117 * We setup stuff that we use a lot, to avoid calculating each time
1119 static void ipath_pe_tidtemplate(struct ipath_devdata
*dd
)
1121 u32 egrsize
= dd
->ipath_rcvegrbufsize
;
1123 /* For now, we always allocate 4KB buffers (at init) so we can
1124 * receive max size packets. We may want a module parameter to
1125 * specify 2KB or 4KB and/or make be per port instead of per device
1126 * for those who want to reduce memory footprint. Note that the
1127 * ipath_rcvhdrentsize size must be large enough to hold the largest
1128 * IB header (currently 96 bytes) that we expect to handle (plus of
1129 * course the 2 dwords of RHF).
1131 if (egrsize
== 2048)
1132 dd
->ipath_tidtemplate
= 1U << 29;
1133 else if (egrsize
== 4096)
1134 dd
->ipath_tidtemplate
= 2U << 29;
1137 dev_info(&dd
->pcidev
->dev
, "BUG: unsupported egrbufsize "
1138 "%u, using %u\n", dd
->ipath_rcvegrbufsize
,
1140 dd
->ipath_tidtemplate
= 2U << 29;
1142 dd
->ipath_tidinvalid
= 0;
1145 static int ipath_pe_early_init(struct ipath_devdata
*dd
)
1147 dd
->ipath_flags
|= IPATH_4BYTE_TID
;
1150 * For openib, we need to be able to handle an IB header of 96 bytes
1151 * or 24 dwords. HT-400 has arbitrary sized receive buffers, so we
1152 * made them the same size as the PIO buffers. The PE-800 does not
1153 * handle arbitrary size buffers, so we need the header large enough
1154 * to handle largest IB header, but still have room for a 2KB MTU
1155 * standard IB packet.
1157 dd
->ipath_rcvhdrentsize
= 24;
1158 dd
->ipath_rcvhdrsize
= IPATH_DFLT_RCVHDRSIZE
;
1160 /* For HT-400, we allocate a somewhat overly large eager buffer,
1161 * such that we can guarantee that we can receive the largest packet
1162 * that we can send out. To truly support a 4KB MTU, we need to
1163 * bump this to a larger value. We'll do this when I get around to
1164 * testing 4KB sends on the PE-800, which I have not yet done.
1166 dd
->ipath_rcvegrbufsize
= 2048;
1168 * the min() check here is currently a nop, but it may not always
1169 * be, depending on just how we do ipath_rcvegrbufsize
1171 dd
->ipath_ibmaxlen
= min(dd
->ipath_piosize2k
,
1172 dd
->ipath_rcvegrbufsize
+
1173 (dd
->ipath_rcvhdrentsize
<< 2));
1174 dd
->ipath_init_ibmaxlen
= dd
->ipath_ibmaxlen
;
1177 * For PE-800, we can request a receive interrupt for 1 or
1178 * more packets from current offset. For now, we set this
1179 * up for a single packet, to match the HT-400 behavior.
1181 dd
->ipath_rhdrhead_intr_off
= 1ULL<<32;
1183 ipath_get_eeprom_info(dd
);
1188 int __attribute__((weak
)) ipath_unordered_wc(void)
1194 * ipath_init_pe_get_base_info - set chip-specific flags for user code
1195 * @dd: the infinipath device
1196 * @kbase: ipath_base_info pointer
1198 * We set the PCIE flag because the lower bandwidth on PCIe vs
1199 * HyperTransport can affect some user packet algorithims.
1201 static int ipath_pe_get_base_info(struct ipath_portdata
*pd
, void *kbase
)
1203 struct ipath_base_info
*kinfo
= kbase
;
1205 if (ipath_unordered_wc()) {
1206 kinfo
->spi_runtime_flags
|= IPATH_RUNTIME_FORCE_WC_ORDER
;
1207 ipath_cdbg(PROC
, "Intel processor, forcing WC order\n");
1210 ipath_cdbg(PROC
, "Not Intel processor, WC ordered\n");
1212 kinfo
->spi_runtime_flags
|= IPATH_RUNTIME_PCIE
;
1218 * ipath_init_pe800_funcs - set up the chip-specific function pointers
1219 * @dd: the infinipath device
1221 * This is global, and is called directly at init to set up the
1222 * chip-specific function pointers for later use.
1224 void ipath_init_pe800_funcs(struct ipath_devdata
*dd
)
1226 dd
->ipath_f_intrsetup
= ipath_pe_intconfig
;
1227 dd
->ipath_f_bus
= ipath_setup_pe_config
;
1228 dd
->ipath_f_reset
= ipath_setup_pe_reset
;
1229 dd
->ipath_f_get_boardname
= ipath_pe_boardname
;
1230 dd
->ipath_f_init_hwerrors
= ipath_pe_init_hwerrors
;
1231 dd
->ipath_f_early_init
= ipath_pe_early_init
;
1232 dd
->ipath_f_handle_hwerrors
= ipath_pe_handle_hwerrors
;
1233 dd
->ipath_f_quiet_serdes
= ipath_pe_quiet_serdes
;
1234 dd
->ipath_f_bringup_serdes
= ipath_pe_bringup_serdes
;
1235 dd
->ipath_f_clear_tids
= ipath_pe_clear_tids
;
1236 dd
->ipath_f_put_tid
= ipath_pe_put_tid
;
1237 dd
->ipath_f_cleanup
= ipath_setup_pe_cleanup
;
1238 dd
->ipath_f_setextled
= ipath_setup_pe_setextled
;
1239 dd
->ipath_f_get_base_info
= ipath_pe_get_base_info
;
1241 /* initialize chip-specific variables */
1242 dd
->ipath_f_tidtemplate
= ipath_pe_tidtemplate
;
1245 * setup the register offsets, since they are different for each
1248 dd
->ipath_kregs
= &ipath_pe_kregs
;
1249 dd
->ipath_cregs
= &ipath_pe_cregs
;
1251 ipath_init_pe_variables();