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Linux 2.6.17.7
[linux/fpc-iii.git] / drivers / infiniband / hw / mthca / mthca_cmd.c
blob798e13e14faf826695d8b64a0493a5580e24bd73
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 *
34 * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
35 */
36
37 #include <linux/sched.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
40 #include <asm/io.h>
41 #include <rdma/ib_mad.h>
42
43 #include "mthca_dev.h"
44 #include "mthca_config_reg.h"
45 #include "mthca_cmd.h"
46 #include "mthca_memfree.h"
47
48 #define CMD_POLL_TOKEN 0xffff
49
50 enum {
51 HCR_IN_PARAM_OFFSET = 0x00,
52 HCR_IN_MODIFIER_OFFSET = 0x08,
53 HCR_OUT_PARAM_OFFSET = 0x0c,
54 HCR_TOKEN_OFFSET = 0x14,
55 HCR_STATUS_OFFSET = 0x18,
56
57 HCR_OPMOD_SHIFT = 12,
58 HCA_E_BIT = 22,
59 HCR_GO_BIT = 23
60 };
61
62 enum {
63 /* initialization and general commands */
64 CMD_SYS_EN = 0x1,
65 CMD_SYS_DIS = 0x2,
66 CMD_MAP_FA = 0xfff,
67 CMD_UNMAP_FA = 0xffe,
68 CMD_RUN_FW = 0xff6,
69 CMD_MOD_STAT_CFG = 0x34,
70 CMD_QUERY_DEV_LIM = 0x3,
71 CMD_QUERY_FW = 0x4,
72 CMD_ENABLE_LAM = 0xff8,
73 CMD_DISABLE_LAM = 0xff7,
74 CMD_QUERY_DDR = 0x5,
75 CMD_QUERY_ADAPTER = 0x6,
76 CMD_INIT_HCA = 0x7,
77 CMD_CLOSE_HCA = 0x8,
78 CMD_INIT_IB = 0x9,
79 CMD_CLOSE_IB = 0xa,
80 CMD_QUERY_HCA = 0xb,
81 CMD_SET_IB = 0xc,
82 CMD_ACCESS_DDR = 0x2e,
83 CMD_MAP_ICM = 0xffa,
84 CMD_UNMAP_ICM = 0xff9,
85 CMD_MAP_ICM_AUX = 0xffc,
86 CMD_UNMAP_ICM_AUX = 0xffb,
87 CMD_SET_ICM_SIZE = 0xffd,
88
89 /* TPT commands */
90 CMD_SW2HW_MPT = 0xd,
91 CMD_QUERY_MPT = 0xe,
92 CMD_HW2SW_MPT = 0xf,
93 CMD_READ_MTT = 0x10,
94 CMD_WRITE_MTT = 0x11,
95 CMD_SYNC_TPT = 0x2f,
96
97 /* EQ commands */
98 CMD_MAP_EQ = 0x12,
99 CMD_SW2HW_EQ = 0x13,
100 CMD_HW2SW_EQ = 0x14,
101 CMD_QUERY_EQ = 0x15,
102
103 /* CQ commands */
104 CMD_SW2HW_CQ = 0x16,
105 CMD_HW2SW_CQ = 0x17,
106 CMD_QUERY_CQ = 0x18,
107 CMD_RESIZE_CQ = 0x2c,
108
109 /* SRQ commands */
110 CMD_SW2HW_SRQ = 0x35,
111 CMD_HW2SW_SRQ = 0x36,
112 CMD_QUERY_SRQ = 0x37,
113 CMD_ARM_SRQ = 0x40,
114
115 /* QP/EE commands */
116 CMD_RST2INIT_QPEE = 0x19,
117 CMD_INIT2RTR_QPEE = 0x1a,
118 CMD_RTR2RTS_QPEE = 0x1b,
119 CMD_RTS2RTS_QPEE = 0x1c,
120 CMD_SQERR2RTS_QPEE = 0x1d,
121 CMD_2ERR_QPEE = 0x1e,
122 CMD_RTS2SQD_QPEE = 0x1f,
123 CMD_SQD2SQD_QPEE = 0x38,
124 CMD_SQD2RTS_QPEE = 0x20,
125 CMD_ERR2RST_QPEE = 0x21,
126 CMD_QUERY_QPEE = 0x22,
127 CMD_INIT2INIT_QPEE = 0x2d,
128 CMD_SUSPEND_QPEE = 0x32,
129 CMD_UNSUSPEND_QPEE = 0x33,
130 /* special QPs and management commands */
131 CMD_CONF_SPECIAL_QP = 0x23,
132 CMD_MAD_IFC = 0x24,
133
134 /* multicast commands */
135 CMD_READ_MGM = 0x25,
136 CMD_WRITE_MGM = 0x26,
137 CMD_MGID_HASH = 0x27,
138
139 /* miscellaneous commands */
140 CMD_DIAG_RPRT = 0x30,
141 CMD_NOP = 0x31,
142
143 /* debug commands */
144 CMD_QUERY_DEBUG_MSG = 0x2a,
145 CMD_SET_DEBUG_MSG = 0x2b,
146 };
147
148 /*
149 * According to Mellanox code, FW may be starved and never complete
150 * commands. So we can't use strict timeouts described in PRM -- we
151 * just arbitrarily select 60 seconds for now.
152 */
153 #if 0
154 /*
155 * Round up and add 1 to make sure we get the full wait time (since we
156 * will be starting in the middle of a jiffy)
157 */
158 enum {
159 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
160 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
161 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1
162 };
163 #else
164 enum {
165 CMD_TIME_CLASS_A = 60 * HZ,
166 CMD_TIME_CLASS_B = 60 * HZ,
167 CMD_TIME_CLASS_C = 60 * HZ
168 };
169 #endif
170
171 enum {
172 GO_BIT_TIMEOUT = HZ * 10
173 };
174
175 struct mthca_cmd_context {
176 struct completion done;
177 struct timer_list timer;
178 int result;
179 int next;
180 u64 out_param;
181 u16 token;
182 u8 status;
183 };
184
185 static int fw_cmd_doorbell = 0;
186 module_param(fw_cmd_doorbell, int, 0644);
187 MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
188 "(and supported by FW)");
189
190 static inline int go_bit(struct mthca_dev *dev)
191 {
192 return readl(dev->hcr + HCR_STATUS_OFFSET) &
193 swab32(1 << HCR_GO_BIT);
194 }
195
196 static void mthca_cmd_post_dbell(struct mthca_dev *dev,
197 u64 in_param,
198 u64 out_param,
199 u32 in_modifier,
200 u8 op_modifier,
201 u16 op,
202 u16 token)
203 {
204 void __iomem *ptr = dev->cmd.dbell_map;
205 u16 *offs = dev->cmd.dbell_offsets;
206
207 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
208 wmb();
209 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
210 wmb();
211 __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
212 wmb();
213 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
214 wmb();
215 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
216 wmb();
217 __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
218 wmb();
219 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
220 (1 << HCA_E_BIT) |
221 (op_modifier << HCR_OPMOD_SHIFT) |
222 op), ptr + offs[6]);
223 wmb();
224 __raw_writel((__force u32) 0, ptr + offs[7]);
225 wmb();
226 }
227
228 static int mthca_cmd_post_hcr(struct mthca_dev *dev,
229 u64 in_param,
230 u64 out_param,
231 u32 in_modifier,
232 u8 op_modifier,
233 u16 op,
234 u16 token,
235 int event)
236 {
237 if (event) {
238 unsigned long end = jiffies + GO_BIT_TIMEOUT;
239
240 while (go_bit(dev) && time_before(jiffies, end)) {
241 set_current_state(TASK_RUNNING);
242 schedule();
243 }
244 }
245
246 if (go_bit(dev))
247 return -EAGAIN;
248
249 /*
250 * We use writel (instead of something like memcpy_toio)
251 * because writes of less than 32 bits to the HCR don't work
252 * (and some architectures such as ia64 implement memcpy_toio
253 * in terms of writeb).
254 */
255 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
256 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
257 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
258 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
259 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
260 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
261
262 /* __raw_writel may not order writes. */
263 wmb();
264
265 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
266 (event ? (1 << HCA_E_BIT) : 0) |
267 (op_modifier << HCR_OPMOD_SHIFT) |
268 op), dev->hcr + 6 * 4);
269
270 return 0;
271 }
272
273 static int mthca_cmd_post(struct mthca_dev *dev,
274 u64 in_param,
275 u64 out_param,
276 u32 in_modifier,
277 u8 op_modifier,
278 u16 op,
279 u16 token,
280 int event)
281 {
282 int err = 0;
283
284 mutex_lock(&dev->cmd.hcr_mutex);
285
286 if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
287 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
288 op_modifier, op, token);
289 else
290 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
291 op_modifier, op, token, event);
292
293 mutex_unlock(&dev->cmd.hcr_mutex);
294 return err;
295 }
296
297 static int mthca_cmd_poll(struct mthca_dev *dev,
298 u64 in_param,
299 u64 *out_param,
300 int out_is_imm,
301 u32 in_modifier,
302 u8 op_modifier,
303 u16 op,
304 unsigned long timeout,
305 u8 *status)
306 {
307 int err = 0;
308 unsigned long end;
309
310 down(&dev->cmd.poll_sem);
311
312 err = mthca_cmd_post(dev, in_param,
313 out_param ? *out_param : 0,
314 in_modifier, op_modifier,
315 op, CMD_POLL_TOKEN, 0);
316 if (err)
317 goto out;
318
319 end = timeout + jiffies;
320 while (go_bit(dev) && time_before(jiffies, end)) {
321 set_current_state(TASK_RUNNING);
322 schedule();
323 }
324
325 if (go_bit(dev)) {
326 err = -EBUSY;
327 goto out;
328 }
329
330 if (out_is_imm)
331 *out_param =
332 (u64) be32_to_cpu((__force __be32)
333 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
334 (u64) be32_to_cpu((__force __be32)
335 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
336
337 *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
338
339 out:
340 up(&dev->cmd.poll_sem);
341 return err;
342 }
343
344 void mthca_cmd_event(struct mthca_dev *dev,
345 u16 token,
346 u8 status,
347 u64 out_param)
348 {
349 struct mthca_cmd_context *context =
350 &dev->cmd.context[token & dev->cmd.token_mask];
351
352 /* previously timed out command completing at long last */
353 if (token != context->token)
354 return;
355
356 context->result = 0;
357 context->status = status;
358 context->out_param = out_param;
359
360 context->token += dev->cmd.token_mask + 1;
361
362 complete(&context->done);
363 }
364
365 static void event_timeout(unsigned long context_ptr)
366 {
367 struct mthca_cmd_context *context =
368 (struct mthca_cmd_context *) context_ptr;
369
370 context->result = -EBUSY;
371 complete(&context->done);
372 }
373
374 static int mthca_cmd_wait(struct mthca_dev *dev,
375 u64 in_param,
376 u64 *out_param,
377 int out_is_imm,
378 u32 in_modifier,
379 u8 op_modifier,
380 u16 op,
381 unsigned long timeout,
382 u8 *status)
383 {
384 int err = 0;
385 struct mthca_cmd_context *context;
386
387 down(&dev->cmd.event_sem);
388
389 spin_lock(&dev->cmd.context_lock);
390 BUG_ON(dev->cmd.free_head < 0);
391 context = &dev->cmd.context[dev->cmd.free_head];
392 dev->cmd.free_head = context->next;
393 spin_unlock(&dev->cmd.context_lock);
394
395 init_completion(&context->done);
396
397 err = mthca_cmd_post(dev, in_param,
398 out_param ? *out_param : 0,
399 in_modifier, op_modifier,
400 op, context->token, 1);
401 if (err)
402 goto out;
403
404 context->timer.expires = jiffies + timeout;
405 add_timer(&context->timer);
406
407 wait_for_completion(&context->done);
408 del_timer_sync(&context->timer);
409
410 err = context->result;
411 if (err)
412 goto out;
413
414 *status = context->status;
415 if (*status)
416 mthca_dbg(dev, "Command %02x completed with status %02x\n",
417 op, *status);
418
419 if (out_is_imm)
420 *out_param = context->out_param;
421
422 out:
423 spin_lock(&dev->cmd.context_lock);
424 context->next = dev->cmd.free_head;
425 dev->cmd.free_head = context - dev->cmd.context;
426 spin_unlock(&dev->cmd.context_lock);
427
428 up(&dev->cmd.event_sem);
429 return err;
430 }
431
432 /* Invoke a command with an output mailbox */
433 static int mthca_cmd_box(struct mthca_dev *dev,
434 u64 in_param,
435 u64 out_param,
436 u32 in_modifier,
437 u8 op_modifier,
438 u16 op,
439 unsigned long timeout,
440 u8 *status)
441 {
442 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
443 return mthca_cmd_wait(dev, in_param, &out_param, 0,
444 in_modifier, op_modifier, op,
445 timeout, status);
446 else
447 return mthca_cmd_poll(dev, in_param, &out_param, 0,
448 in_modifier, op_modifier, op,
449 timeout, status);
450 }
451
452 /* Invoke a command with no output parameter */
453 static int mthca_cmd(struct mthca_dev *dev,
454 u64 in_param,
455 u32 in_modifier,
456 u8 op_modifier,
457 u16 op,
458 unsigned long timeout,
459 u8 *status)
460 {
461 return mthca_cmd_box(dev, in_param, 0, in_modifier,
462 op_modifier, op, timeout, status);
463 }
464
465 /*
466 * Invoke a command with an immediate output parameter (and copy the
467 * output into the caller's out_param pointer after the command
468 * executes).
469 */
470 static int mthca_cmd_imm(struct mthca_dev *dev,
471 u64 in_param,
472 u64 *out_param,
473 u32 in_modifier,
474 u8 op_modifier,
475 u16 op,
476 unsigned long timeout,
477 u8 *status)
478 {
479 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
480 return mthca_cmd_wait(dev, in_param, out_param, 1,
481 in_modifier, op_modifier, op,
482 timeout, status);
483 else
484 return mthca_cmd_poll(dev, in_param, out_param, 1,
485 in_modifier, op_modifier, op,
486 timeout, status);
487 }
488
489 int mthca_cmd_init(struct mthca_dev *dev)
490 {
491 mutex_init(&dev->cmd.hcr_mutex);
492 sema_init(&dev->cmd.poll_sem, 1);
493 dev->cmd.flags = 0;
494
495 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
496 MTHCA_HCR_SIZE);
497 if (!dev->hcr) {
498 mthca_err(dev, "Couldn't map command register.");
499 return -ENOMEM;
500 }
501
502 dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
503 MTHCA_MAILBOX_SIZE,
504 MTHCA_MAILBOX_SIZE, 0);
505 if (!dev->cmd.pool) {
506 iounmap(dev->hcr);
507 return -ENOMEM;
508 }
509
510 return 0;
511 }
512
513 void mthca_cmd_cleanup(struct mthca_dev *dev)
514 {
515 pci_pool_destroy(dev->cmd.pool);
516 iounmap(dev->hcr);
517 if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
518 iounmap(dev->cmd.dbell_map);
519 }
520
521 /*
522 * Switch to using events to issue FW commands (should be called after
523 * event queue to command events has been initialized).
524 */
525 int mthca_cmd_use_events(struct mthca_dev *dev)
526 {
527 int i;
528
529 dev->cmd.context = kmalloc(dev->cmd.max_cmds *
530 sizeof (struct mthca_cmd_context),
531 GFP_KERNEL);
532 if (!dev->cmd.context)
533 return -ENOMEM;
534
535 for (i = 0; i < dev->cmd.max_cmds; ++i) {
536 dev->cmd.context[i].token = i;
537 dev->cmd.context[i].next = i + 1;
538 init_timer(&dev->cmd.context[i].timer);
539 dev->cmd.context[i].timer.data =
540 (unsigned long) &dev->cmd.context[i];
541 dev->cmd.context[i].timer.function = event_timeout;
542 }
543
544 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
545 dev->cmd.free_head = 0;
546
547 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
548 spin_lock_init(&dev->cmd.context_lock);
549
550 for (dev->cmd.token_mask = 1;
551 dev->cmd.token_mask < dev->cmd.max_cmds;
552 dev->cmd.token_mask <<= 1)
553 ; /* nothing */
554 --dev->cmd.token_mask;
555
556 dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
557
558 down(&dev->cmd.poll_sem);
559
560 return 0;
561 }
562
563 /*
564 * Switch back to polling (used when shutting down the device)
565 */
566 void mthca_cmd_use_polling(struct mthca_dev *dev)
567 {
568 int i;
569
570 dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
571
572 for (i = 0; i < dev->cmd.max_cmds; ++i)
573 down(&dev->cmd.event_sem);
574
575 kfree(dev->cmd.context);
576
577 up(&dev->cmd.poll_sem);
578 }
579
580 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
581 gfp_t gfp_mask)
582 {
583 struct mthca_mailbox *mailbox;
584
585 mailbox = kmalloc(sizeof *mailbox, gfp_mask);
586 if (!mailbox)
587 return ERR_PTR(-ENOMEM);
588
589 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
590 if (!mailbox->buf) {
591 kfree(mailbox);
592 return ERR_PTR(-ENOMEM);
593 }
594
595 return mailbox;
596 }
597
598 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
599 {
600 if (!mailbox)
601 return;
602
603 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
604 kfree(mailbox);
605 }
606
607 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
608 {
609 u64 out;
610 int ret;
611
612 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
613
614 if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
615 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
616 "sladdr=%d, SPD source=%s\n",
617 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
618 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
619
620 return ret;
621 }
622
623 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
624 {
625 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
626 }
627
628 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
629 u64 virt, u8 *status)
630 {
631 struct mthca_mailbox *mailbox;
632 struct mthca_icm_iter iter;
633 __be64 *pages;
634 int lg;
635 int nent = 0;
636 int i;
637 int err = 0;
638 int ts = 0, tc = 0;
639
640 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
641 if (IS_ERR(mailbox))
642 return PTR_ERR(mailbox);
643 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
644 pages = mailbox->buf;
645
646 for (mthca_icm_first(icm, &iter);
647 !mthca_icm_last(&iter);
648 mthca_icm_next(&iter)) {
649 /*
650 * We have to pass pages that are aligned to their
651 * size, so find the least significant 1 in the
652 * address or size and use that as our log2 size.
653 */
654 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
655 if (lg < MTHCA_ICM_PAGE_SHIFT) {
656 mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
657 MTHCA_ICM_PAGE_SIZE,
658 (unsigned long long) mthca_icm_addr(&iter),
659 mthca_icm_size(&iter));
660 err = -EINVAL;
661 goto out;
662 }
663 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
664 if (virt != -1) {
665 pages[nent * 2] = cpu_to_be64(virt);
666 virt += 1 << lg;
667 }
668
669 pages[nent * 2 + 1] =
670 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
671 (lg - MTHCA_ICM_PAGE_SHIFT));
672 ts += 1 << (lg - 10);
673 ++tc;
674
675 if (++nent == MTHCA_MAILBOX_SIZE / 16) {
676 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
677 CMD_TIME_CLASS_B, status);
678 if (err || *status)
679 goto out;
680 nent = 0;
681 }
682 }
683 }
684
685 if (nent)
686 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
687 CMD_TIME_CLASS_B, status);
688
689 switch (op) {
690 case CMD_MAP_FA:
691 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
692 break;
693 case CMD_MAP_ICM_AUX:
694 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
695 break;
696 case CMD_MAP_ICM:
697 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
698 tc, ts, (unsigned long long) virt - (ts << 10));
699 break;
700 }
701
702 out:
703 mthca_free_mailbox(dev, mailbox);
704 return err;
705 }
706
707 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
708 {
709 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
710 }
711
712 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
713 {
714 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
715 }
716
717 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
718 {
719 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
720 }
721
722 static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
723 {
724 unsigned long addr;
725 u16 max_off = 0;
726 int i;
727
728 for (i = 0; i < 8; ++i)
729 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
730
731 if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
732 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
733 "length 0x%x crosses a page boundary\n",
734 (unsigned long long) base, max_off);
735 return;
736 }
737
738 addr = pci_resource_start(dev->pdev, 2) +
739 ((pci_resource_len(dev->pdev, 2) - 1) & base);
740 dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
741 if (!dev->cmd.dbell_map)
742 return;
743
744 dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
745 mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
746 }
747
748 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
749 {
750 struct mthca_mailbox *mailbox;
751 u32 *outbox;
752 u64 base;
753 u32 tmp;
754 int err = 0;
755 u8 lg;
756 int i;
757
758 #define QUERY_FW_OUT_SIZE 0x100
759 #define QUERY_FW_VER_OFFSET 0x00
760 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
761 #define QUERY_FW_ERR_START_OFFSET 0x30
762 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
763
764 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10
765 #define QUERY_FW_CMD_DB_OFFSET 0x50
766 #define QUERY_FW_CMD_DB_BASE 0x60
767
768 #define QUERY_FW_START_OFFSET 0x20
769 #define QUERY_FW_END_OFFSET 0x28
770
771 #define QUERY_FW_SIZE_OFFSET 0x00
772 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
773 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
774 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
775
776 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
777 if (IS_ERR(mailbox))
778 return PTR_ERR(mailbox);
779 outbox = mailbox->buf;
780
781 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
782 CMD_TIME_CLASS_A, status);
783
784 if (err)
785 goto out;
786
787 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
788 /*
789 * FW subminor version is at more signifant bits than minor
790 * version, so swap here.
791 */
792 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
793 ((dev->fw_ver & 0xffff0000ull) >> 16) |
794 ((dev->fw_ver & 0x0000ffffull) << 16);
795
796 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
797 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
798
799 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
800 dev->cmd.max_cmds = 1 << lg;
801 MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
802 MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
803
804 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
805 (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
806
807 MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
808 if (tmp & 0x1) {
809 mthca_dbg(dev, "FW supports commands through doorbells\n");
810
811 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
812 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
813 MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
814 QUERY_FW_CMD_DB_OFFSET + (i << 1));
815
816 mthca_setup_cmd_doorbells(dev, base);
817 }
818
819 if (mthca_is_memfree(dev)) {
820 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
821 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
822 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
823 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
824 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
825
826 /*
827 * Round up number of system pages needed in case
828 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
829 */
830 dev->fw.arbel.fw_pages =
831 ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
832 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
833
834 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
835 (unsigned long long) dev->fw.arbel.clr_int_base,
836 (unsigned long long) dev->fw.arbel.eq_arm_base,
837 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
838 } else {
839 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
840 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
841
842 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
843 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
844 (unsigned long long) dev->fw.tavor.fw_start,
845 (unsigned long long) dev->fw.tavor.fw_end);
846 }
847
848 out:
849 mthca_free_mailbox(dev, mailbox);
850 return err;
851 }
852
853 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
854 {
855 struct mthca_mailbox *mailbox;
856 u8 info;
857 u32 *outbox;
858 int err = 0;
859
860 #define ENABLE_LAM_OUT_SIZE 0x100
861 #define ENABLE_LAM_START_OFFSET 0x00
862 #define ENABLE_LAM_END_OFFSET 0x08
863 #define ENABLE_LAM_INFO_OFFSET 0x13
864
865 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
866 #define ENABLE_LAM_INFO_ECC_MASK 0x3
867
868 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
869 if (IS_ERR(mailbox))
870 return PTR_ERR(mailbox);
871 outbox = mailbox->buf;
872
873 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
874 CMD_TIME_CLASS_C, status);
875
876 if (err)
877 goto out;
878
879 if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
880 goto out;
881
882 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
883 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
884 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
885
886 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
887 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
888 mthca_info(dev, "FW reports that HCA-attached memory "
889 "is %s hidden; does not match PCI config\n",
890 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
891 "" : "not");
892 }
893 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
894 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
895
896 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
897 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
898 (unsigned long long) dev->ddr_start,
899 (unsigned long long) dev->ddr_end);
900
901 out:
902 mthca_free_mailbox(dev, mailbox);
903 return err;
904 }
905
906 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
907 {
908 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
909 }
910
911 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
912 {
913 struct mthca_mailbox *mailbox;
914 u8 info;
915 u32 *outbox;
916 int err = 0;
917
918 #define QUERY_DDR_OUT_SIZE 0x100
919 #define QUERY_DDR_START_OFFSET 0x00
920 #define QUERY_DDR_END_OFFSET 0x08
921 #define QUERY_DDR_INFO_OFFSET 0x13
922
923 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
924 #define QUERY_DDR_INFO_ECC_MASK 0x3
925
926 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
927 if (IS_ERR(mailbox))
928 return PTR_ERR(mailbox);
929 outbox = mailbox->buf;
930
931 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
932 CMD_TIME_CLASS_A, status);
933
934 if (err)
935 goto out;
936
937 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
938 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
939 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
940
941 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
942 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
943 mthca_info(dev, "FW reports that HCA-attached memory "
944 "is %s hidden; does not match PCI config\n",
945 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
946 "" : "not");
947 }
948 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
949 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
950
951 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
952 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
953 (unsigned long long) dev->ddr_start,
954 (unsigned long long) dev->ddr_end);
955
956 out:
957 mthca_free_mailbox(dev, mailbox);
958 return err;
959 }
960
961 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
962 struct mthca_dev_lim *dev_lim, u8 *status)
963 {
964 struct mthca_mailbox *mailbox;
965 u32 *outbox;
966 u8 field;
967 u16 size;
968 u16 stat_rate;
969 int err;
970
971 #define QUERY_DEV_LIM_OUT_SIZE 0x100
972 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
973 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
974 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
975 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
976 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
977 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
978 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
979 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
980 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
981 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
982 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
983 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
984 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
985 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
986 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
987 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
988 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
989 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
990 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
991 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
992 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
993 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
994 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
995 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
996 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
997 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
998 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
999 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
1000 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
1001 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
1002 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
1003 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
1004 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
1005 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
1006 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
1007 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
1008 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
1009 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
1010 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
1011 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
1012 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
1013 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
1014 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
1015 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
1016 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
1017 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
1018 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
1019 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1020 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1021 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1022 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1023 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1024 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1025 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1026 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1027 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1028 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1029 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1030 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1031
1032 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1033 if (IS_ERR(mailbox))
1034 return PTR_ERR(mailbox);
1035 outbox = mailbox->buf;
1036
1037 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1038 CMD_TIME_CLASS_A, status);
1039
1040 if (err)
1041 goto out;
1042
1043 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1044 dev_lim->reserved_qps = 1 << (field & 0xf);
1045 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1046 dev_lim->max_qps = 1 << (field & 0x1f);
1047 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1048 dev_lim->reserved_srqs = 1 << (field >> 4);
1049 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1050 dev_lim->max_srqs = 1 << (field & 0x1f);
1051 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1052 dev_lim->reserved_eecs = 1 << (field & 0xf);
1053 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1054 dev_lim->max_eecs = 1 << (field & 0x1f);
1055 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1056 dev_lim->max_cq_sz = 1 << field;
1057 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1058 dev_lim->reserved_cqs = 1 << (field & 0xf);
1059 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1060 dev_lim->max_cqs = 1 << (field & 0x1f);
1061 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1062 dev_lim->max_mpts = 1 << (field & 0x3f);
1063 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1064 dev_lim->reserved_eqs = 1 << (field & 0xf);
1065 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1066 dev_lim->max_eqs = 1 << (field & 0x7);
1067 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
1068 dev_lim->reserved_mtts = 1 << (field >> 4);
1069 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1070 dev_lim->max_mrw_sz = 1 << field;
1071 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1072 dev_lim->reserved_mrws = 1 << (field & 0xf);
1073 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1074 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1075 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1076 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1077 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1078 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1079 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1080 dev_lim->max_rdma_global = 1 << (field & 0x3f);
1081 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1082 dev_lim->local_ca_ack_delay = field & 0x1f;
1083 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1084 dev_lim->max_mtu = field >> 4;
1085 dev_lim->max_port_width = field & 0xf;
1086 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1087 dev_lim->max_vl = field >> 4;
1088 dev_lim->num_ports = field & 0xf;
1089 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1090 dev_lim->max_gids = 1 << (field & 0xf);
1091 MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1092 dev_lim->stat_rate_support = stat_rate;
1093 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1094 dev_lim->max_pkeys = 1 << (field & 0xf);
1095 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1096 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1097 dev_lim->reserved_uars = field >> 4;
1098 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1099 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1100 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1101 dev_lim->min_page_sz = 1 << field;
1102 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1103 dev_lim->max_sg = field;
1104
1105 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1106 dev_lim->max_desc_sz = size;
1107
1108 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1109 dev_lim->max_qp_per_mcg = 1 << field;
1110 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1111 dev_lim->reserved_mgms = field & 0xf;
1112 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1113 dev_lim->max_mcgs = 1 << field;
1114 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1115 dev_lim->reserved_pds = field >> 4;
1116 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1117 dev_lim->max_pds = 1 << (field & 0x3f);
1118 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1119 dev_lim->reserved_rdds = field >> 4;
1120 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1121 dev_lim->max_rdds = 1 << (field & 0x3f);
1122
1123 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1124 dev_lim->eec_entry_sz = size;
1125 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1126 dev_lim->qpc_entry_sz = size;
1127 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1128 dev_lim->eeec_entry_sz = size;
1129 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1130 dev_lim->eqpc_entry_sz = size;
1131 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1132 dev_lim->eqc_entry_sz = size;
1133 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1134 dev_lim->cqc_entry_sz = size;
1135 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1136 dev_lim->srq_entry_sz = size;
1137 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1138 dev_lim->uar_scratch_entry_sz = size;
1139
1140 if (mthca_is_memfree(dev)) {
1141 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1142 dev_lim->max_srq_sz = 1 << field;
1143 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1144 dev_lim->max_qp_sz = 1 << field;
1145 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1146 dev_lim->hca.arbel.resize_srq = field & 1;
1147 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1148 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1149 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1150 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1151 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1152 dev_lim->mpt_entry_sz = size;
1153 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1154 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1155 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1156 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1157 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1158 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1159 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1160 dev_lim->hca.arbel.lam_required = field & 1;
1161 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1162 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1163
1164 if (dev_lim->hca.arbel.bmme_flags & 1)
1165 mthca_dbg(dev, "Base MM extensions: yes "
1166 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1167 dev_lim->hca.arbel.bmme_flags,
1168 dev_lim->hca.arbel.max_pbl_sz,
1169 dev_lim->hca.arbel.reserved_lkey);
1170 else
1171 mthca_dbg(dev, "Base MM extensions: no\n");
1172
1173 mthca_dbg(dev, "Max ICM size %lld MB\n",
1174 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1175 } else {
1176 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1177 dev_lim->max_srq_sz = (1 << field) - 1;
1178 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1179 dev_lim->max_qp_sz = (1 << field) - 1;
1180 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1181 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1182 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1183 }
1184
1185 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1186 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1187 mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1188 dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1189 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1190 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1191 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1192 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1193 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1194 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1195 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1196 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1197 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1198 dev_lim->max_pds, dev_lim->reserved_mgms);
1199 mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1200 dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1201
1202 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1203
1204 out:
1205 mthca_free_mailbox(dev, mailbox);
1206 return err;
1207 }
1208
1209 static void get_board_id(void *vsd, char *board_id)
1210 {
1211 int i;
1212
1213 #define VSD_OFFSET_SIG1 0x00
1214 #define VSD_OFFSET_SIG2 0xde
1215 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1216 #define VSD_OFFSET_TS_BOARD_ID 0x20
1217
1218 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1219
1220 memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1221
1222 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1223 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1224 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1225 } else {
1226 /*
1227 * The board ID is a string but the firmware byte
1228 * swaps each 4-byte word before passing it back to
1229 * us. Therefore we need to swab it before printing.
1230 */
1231 for (i = 0; i < 4; ++i)
1232 ((u32 *) board_id)[i] =
1233 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1234 }
1235 }
1236
1237 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1238 struct mthca_adapter *adapter, u8 *status)
1239 {
1240 struct mthca_mailbox *mailbox;
1241 u32 *outbox;
1242 int err;
1243
1244 #define QUERY_ADAPTER_OUT_SIZE 0x100
1245 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1246 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1247 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1248 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1249 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1250
1251 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1252 if (IS_ERR(mailbox))
1253 return PTR_ERR(mailbox);
1254 outbox = mailbox->buf;
1255
1256 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1257 CMD_TIME_CLASS_A, status);
1258
1259 if (err)
1260 goto out;
1261
1262 MTHCA_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET);
1263 MTHCA_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET);
1264 MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
1265 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1266
1267 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1268 adapter->board_id);
1269
1270 out:
1271 mthca_free_mailbox(dev, mailbox);
1272 return err;
1273 }
1274
1275 int mthca_INIT_HCA(struct mthca_dev *dev,
1276 struct mthca_init_hca_param *param,
1277 u8 *status)
1278 {
1279 struct mthca_mailbox *mailbox;
1280 __be32 *inbox;
1281 int err;
1282
1283 #define INIT_HCA_IN_SIZE 0x200
1284 #define INIT_HCA_FLAGS1_OFFSET 0x00c
1285 #define INIT_HCA_FLAGS2_OFFSET 0x014
1286 #define INIT_HCA_QPC_OFFSET 0x020
1287 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1288 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1289 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1290 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1291 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1292 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1293 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1294 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1295 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1296 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1297 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1298 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1299 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1300 #define INIT_HCA_UDAV_OFFSET 0x0b0
1301 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1302 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1303 #define INIT_HCA_MCAST_OFFSET 0x0c0
1304 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1305 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1306 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1307 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1308 #define INIT_HCA_TPT_OFFSET 0x0f0
1309 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1310 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1311 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1312 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1313 #define INIT_HCA_UAR_OFFSET 0x120
1314 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1315 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1316 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1317 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1318 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1319 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1320
1321 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1322 if (IS_ERR(mailbox))
1323 return PTR_ERR(mailbox);
1324 inbox = mailbox->buf;
1325
1326 memset(inbox, 0, INIT_HCA_IN_SIZE);
1327
1328 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1329 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1330
1331 #if defined(__LITTLE_ENDIAN)
1332 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1333 #elif defined(__BIG_ENDIAN)
1334 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1335 #else
1336 #error Host endianness not defined
1337 #endif
1338 /* Check port for UD address vector: */
1339 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1340
1341 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1342
1343 /* QPC/EEC/CQC/EQC/RDB attributes */
1344
1345 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1346 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1347 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1348 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1349 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1350 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1351 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1352 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1353 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1354 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1355 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1356 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1357 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1358
1359 /* UD AV attributes */
1360
1361 /* multicast attributes */
1362
1363 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1364 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1365 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1366 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1367
1368 /* TPT attributes */
1369
1370 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
1371 if (!mthca_is_memfree(dev))
1372 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1373 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1374 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1375
1376 /* UAR attributes */
1377 {
1378 u8 uar_page_sz = PAGE_SHIFT - 12;
1379 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1380 }
1381
1382 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1383
1384 if (mthca_is_memfree(dev)) {
1385 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1386 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1387 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1388 }
1389
1390 err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
1391
1392 mthca_free_mailbox(dev, mailbox);
1393 return err;
1394 }
1395
1396 int mthca_INIT_IB(struct mthca_dev *dev,
1397 struct mthca_init_ib_param *param,
1398 int port, u8 *status)
1399 {
1400 struct mthca_mailbox *mailbox;
1401 u32 *inbox;
1402 int err;
1403 u32 flags;
1404
1405 #define INIT_IB_IN_SIZE 56
1406 #define INIT_IB_FLAGS_OFFSET 0x00
1407 #define INIT_IB_FLAG_SIG (1 << 18)
1408 #define INIT_IB_FLAG_NG (1 << 17)
1409 #define INIT_IB_FLAG_G0 (1 << 16)
1410 #define INIT_IB_VL_SHIFT 4
1411 #define INIT_IB_PORT_WIDTH_SHIFT 8
1412 #define INIT_IB_MTU_SHIFT 12
1413 #define INIT_IB_MAX_GID_OFFSET 0x06
1414 #define INIT_IB_MAX_PKEY_OFFSET 0x0a
1415 #define INIT_IB_GUID0_OFFSET 0x10
1416 #define INIT_IB_NODE_GUID_OFFSET 0x18
1417 #define INIT_IB_SI_GUID_OFFSET 0x20
1418
1419 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1420 if (IS_ERR(mailbox))
1421 return PTR_ERR(mailbox);
1422 inbox = mailbox->buf;
1423
1424 memset(inbox, 0, INIT_IB_IN_SIZE);
1425
1426 flags = 0;
1427 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1428 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1429 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1430 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1431 flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1432 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1433 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1434
1435 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1436 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1437 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1438 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1439 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1440
1441 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1442 CMD_TIME_CLASS_A, status);
1443
1444 mthca_free_mailbox(dev, mailbox);
1445 return err;
1446 }
1447
1448 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1449 {
1450 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
1451 }
1452
1453 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1454 {
1455 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
1456 }
1457
1458 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1459 int port, u8 *status)
1460 {
1461 struct mthca_mailbox *mailbox;
1462 u32 *inbox;
1463 int err;
1464 u32 flags = 0;
1465
1466 #define SET_IB_IN_SIZE 0x40
1467 #define SET_IB_FLAGS_OFFSET 0x00
1468 #define SET_IB_FLAG_SIG (1 << 18)
1469 #define SET_IB_FLAG_RQK (1 << 0)
1470 #define SET_IB_CAP_MASK_OFFSET 0x04
1471 #define SET_IB_SI_GUID_OFFSET 0x08
1472
1473 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1474 if (IS_ERR(mailbox))
1475 return PTR_ERR(mailbox);
1476 inbox = mailbox->buf;
1477
1478 memset(inbox, 0, SET_IB_IN_SIZE);
1479
1480 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1481 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1482 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1483
1484 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1485 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1486
1487 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1488 CMD_TIME_CLASS_B, status);
1489
1490 mthca_free_mailbox(dev, mailbox);
1491 return err;
1492 }
1493
1494 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1495 {
1496 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1497 }
1498
1499 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1500 {
1501 struct mthca_mailbox *mailbox;
1502 __be64 *inbox;
1503 int err;
1504
1505 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1506 if (IS_ERR(mailbox))
1507 return PTR_ERR(mailbox);
1508 inbox = mailbox->buf;
1509
1510 inbox[0] = cpu_to_be64(virt);
1511 inbox[1] = cpu_to_be64(dma_addr);
1512
1513 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1514 CMD_TIME_CLASS_B, status);
1515
1516 mthca_free_mailbox(dev, mailbox);
1517
1518 if (!err)
1519 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1520 (unsigned long long) dma_addr, (unsigned long long) virt);
1521
1522 return err;
1523 }
1524
1525 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1526 {
1527 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1528 page_count, (unsigned long long) virt);
1529
1530 return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1531 }
1532
1533 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1534 {
1535 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1536 }
1537
1538 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1539 {
1540 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1541 }
1542
1543 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1544 u8 *status)
1545 {
1546 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1547 CMD_TIME_CLASS_A, status);
1548
1549 if (ret || status)
1550 return ret;
1551
1552 /*
1553 * Round up number of system pages needed in case
1554 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1555 */
1556 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1557 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1558
1559 return 0;
1560 }
1561
1562 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1563 int mpt_index, u8 *status)
1564 {
1565 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1566 CMD_TIME_CLASS_B, status);
1567 }
1568
1569 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1570 int mpt_index, u8 *status)
1571 {
1572 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1573 !mailbox, CMD_HW2SW_MPT,
1574 CMD_TIME_CLASS_B, status);
1575 }
1576
1577 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1578 int num_mtt, u8 *status)
1579 {
1580 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1581 CMD_TIME_CLASS_B, status);
1582 }
1583
1584 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1585 {
1586 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1587 }
1588
1589 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1590 int eq_num, u8 *status)
1591 {
1592 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1593 unmap ? "Clearing" : "Setting",
1594 (unsigned long long) event_mask, eq_num);
1595 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1596 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1597 }
1598
1599 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1600 int eq_num, u8 *status)
1601 {
1602 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1603 CMD_TIME_CLASS_A, status);
1604 }
1605
1606 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1607 int eq_num, u8 *status)
1608 {
1609 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1610 CMD_HW2SW_EQ,
1611 CMD_TIME_CLASS_A, status);
1612 }
1613
1614 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1615 int cq_num, u8 *status)
1616 {
1617 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1618 CMD_TIME_CLASS_A, status);
1619 }
1620
1621 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1622 int cq_num, u8 *status)
1623 {
1624 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1625 CMD_HW2SW_CQ,
1626 CMD_TIME_CLASS_A, status);
1627 }
1628
1629 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size,
1630 u8 *status)
1631 {
1632 struct mthca_mailbox *mailbox;
1633 __be32 *inbox;
1634 int err;
1635
1636 #define RESIZE_CQ_IN_SIZE 0x40
1637 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1638 #define RESIZE_CQ_LKEY_OFFSET 0x1c
1639
1640 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1641 if (IS_ERR(mailbox))
1642 return PTR_ERR(mailbox);
1643 inbox = mailbox->buf;
1644
1645 memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1646 /*
1647 * Leave start address fields zeroed out -- mthca assumes that
1648 * MRs for CQs always start at virtual address 0.
1649 */
1650 MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1651 MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET);
1652
1653 err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
1654 CMD_TIME_CLASS_B, status);
1655
1656 mthca_free_mailbox(dev, mailbox);
1657 return err;
1658 }
1659
1660 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1661 int srq_num, u8 *status)
1662 {
1663 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1664 CMD_TIME_CLASS_A, status);
1665 }
1666
1667 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1668 int srq_num, u8 *status)
1669 {
1670 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1671 CMD_HW2SW_SRQ,
1672 CMD_TIME_CLASS_A, status);
1673 }
1674
1675 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
1676 struct mthca_mailbox *mailbox, u8 *status)
1677 {
1678 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
1679 CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status);
1680 }
1681
1682 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
1683 {
1684 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1685 CMD_TIME_CLASS_B, status);
1686 }
1687
1688 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1689 enum ib_qp_state next, u32 num, int is_ee,
1690 struct mthca_mailbox *mailbox, u32 optmask,
1691 u8 *status)
1692 {
1693 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1694 [IB_QPS_RESET] = {
1695 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1696 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1697 [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
1698 },
1699 [IB_QPS_INIT] = {
1700 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1701 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1702 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
1703 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
1704 },
1705 [IB_QPS_RTR] = {
1706 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1707 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1708 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
1709 },
1710 [IB_QPS_RTS] = {
1711 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1712 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1713 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
1714 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
1715 },
1716 [IB_QPS_SQD] = {
1717 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1718 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1719 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
1720 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
1721 },
1722 [IB_QPS_SQE] = {
1723 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1724 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1725 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
1726 },
1727 [IB_QPS_ERR] = {
1728 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1729 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1730 }
1731 };
1732
1733 u8 op_mod = 0;
1734 int my_mailbox = 0;
1735 int err;
1736
1737 if (op[cur][next] == CMD_ERR2RST_QPEE) {
1738 op_mod = 3; /* don't write outbox, any->reset */
1739
1740 /* For debugging */
1741 if (!mailbox) {
1742 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1743 if (!IS_ERR(mailbox)) {
1744 my_mailbox = 1;
1745 op_mod = 2; /* write outbox, any->reset */
1746 } else
1747 mailbox = NULL;
1748 }
1749
1750 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1751 (!!is_ee << 24) | num, op_mod,
1752 op[cur][next], CMD_TIME_CLASS_C, status);
1753
1754 if (0 && mailbox) {
1755 int i;
1756 mthca_dbg(dev, "Dumping QP context:\n");
1757 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1758 for (i = 0; i < 0x100 / 4; ++i) {
1759 if (i % 8 == 0)
1760 printk("[%02x] ", i * 4);
1761 printk(" %08x",
1762 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1763 if ((i + 1) % 8 == 0)
1764 printk("\n");
1765 }
1766 }
1767
1768 if (my_mailbox)
1769 mthca_free_mailbox(dev, mailbox);
1770 } else {
1771 if (0) {
1772 int i;
1773 mthca_dbg(dev, "Dumping QP context:\n");
1774 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1775 for (i = 0; i < 0x100 / 4; ++i) {
1776 if (i % 8 == 0)
1777 printk(" [%02x] ", i * 4);
1778 printk(" %08x",
1779 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1780 if ((i + 1) % 8 == 0)
1781 printk("\n");
1782 }
1783 }
1784
1785 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1786 op_mod, op[cur][next], CMD_TIME_CLASS_C, status);
1787 }
1788
1789 return err;
1790 }
1791
1792 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1793 struct mthca_mailbox *mailbox, u8 *status)
1794 {
1795 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1796 CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1797 }
1798
1799 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1800 u8 *status)
1801 {
1802 u8 op_mod;
1803
1804 switch (type) {
1805 case IB_QPT_SMI:
1806 op_mod = 0;
1807 break;
1808 case IB_QPT_GSI:
1809 op_mod = 1;
1810 break;
1811 case IB_QPT_RAW_IPV6:
1812 op_mod = 2;
1813 break;
1814 case IB_QPT_RAW_ETY:
1815 op_mod = 3;
1816 break;
1817 default:
1818 return -EINVAL;
1819 }
1820
1821 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1822 CMD_TIME_CLASS_B, status);
1823 }
1824
1825 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1826 int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1827 void *in_mad, void *response_mad, u8 *status)
1828 {
1829 struct mthca_mailbox *inmailbox, *outmailbox;
1830 void *inbox;
1831 int err;
1832 u32 in_modifier = port;
1833 u8 op_modifier = 0;
1834
1835 #define MAD_IFC_BOX_SIZE 0x400
1836 #define MAD_IFC_MY_QPN_OFFSET 0x100
1837 #define MAD_IFC_RQPN_OFFSET 0x104
1838 #define MAD_IFC_SL_OFFSET 0x108
1839 #define MAD_IFC_G_PATH_OFFSET 0x109
1840 #define MAD_IFC_RLID_OFFSET 0x10a
1841 #define MAD_IFC_PKEY_OFFSET 0x10e
1842 #define MAD_IFC_GRH_OFFSET 0x140
1843
1844 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1845 if (IS_ERR(inmailbox))
1846 return PTR_ERR(inmailbox);
1847 inbox = inmailbox->buf;
1848
1849 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1850 if (IS_ERR(outmailbox)) {
1851 mthca_free_mailbox(dev, inmailbox);
1852 return PTR_ERR(outmailbox);
1853 }
1854
1855 memcpy(inbox, in_mad, 256);
1856
1857 /*
1858 * Key check traps can't be generated unless we have in_wc to
1859 * tell us where to send the trap.
1860 */
1861 if (ignore_mkey || !in_wc)
1862 op_modifier |= 0x1;
1863 if (ignore_bkey || !in_wc)
1864 op_modifier |= 0x2;
1865
1866 if (in_wc) {
1867 u8 val;
1868
1869 memset(inbox + 256, 0, 256);
1870
1871 MTHCA_PUT(inbox, in_wc->qp_num, MAD_IFC_MY_QPN_OFFSET);
1872 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1873
1874 val = in_wc->sl << 4;
1875 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
1876
1877 val = in_wc->dlid_path_bits |
1878 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1879 MTHCA_PUT(inbox, val, MAD_IFC_GRH_OFFSET);
1880
1881 MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET);
1882 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1883
1884 if (in_grh)
1885 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1886
1887 op_modifier |= 0x10;
1888
1889 in_modifier |= in_wc->slid << 16;
1890 }
1891
1892 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1893 in_modifier, op_modifier,
1894 CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1895
1896 if (!err && !*status)
1897 memcpy(response_mad, outmailbox->buf, 256);
1898
1899 mthca_free_mailbox(dev, inmailbox);
1900 mthca_free_mailbox(dev, outmailbox);
1901 return err;
1902 }
1903
1904 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1905 struct mthca_mailbox *mailbox, u8 *status)
1906 {
1907 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1908 CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1909 }
1910
1911 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1912 struct mthca_mailbox *mailbox, u8 *status)
1913 {
1914 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1915 CMD_TIME_CLASS_A, status);
1916 }
1917
1918 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1919 u16 *hash, u8 *status)
1920 {
1921 u64 imm;
1922 int err;
1923
1924 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1925 CMD_TIME_CLASS_A, status);
1926
1927 *hash = imm;
1928 return err;
1929 }
1930
1931 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1932 {
1933 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1934 }
Linux with added FPC-III support