drivers/mmc/wbsd.h

   1 /*
   2  *  linux/drivers/mmc/wbsd.h - Winbond W83L51xD SD/MMC driver
   3  *
   4  *  Copyright (C) 2004-2005 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define LOCK_CODE               0xAA
  12
  13 #define WBSD_CONF_SWRST         0x02
  14 #define WBSD_CONF_DEVICE        0x07
  15 #define WBSD_CONF_ID_HI         0x20
  16 #define WBSD_CONF_ID_LO         0x21
  17 #define WBSD_CONF_POWER         0x22
  18 #define WBSD_CONF_PME           0x23
  19 #define WBSD_CONF_PMES          0x24
  20
  21 #define WBSD_CONF_ENABLE        0x30
  22 #define WBSD_CONF_PORT_HI       0x60
  23 #define WBSD_CONF_PORT_LO       0x61
  24 #define WBSD_CONF_IRQ           0x70
  25 #define WBSD_CONF_DRQ           0x74
  26
  27 #define WBSD_CONF_PINS          0xF0
  28
  29 #define DEVICE_SD               0x03
  30
  31 #define WBSD_PINS_DAT3_HI       0x20
  32 #define WBSD_PINS_DAT3_OUT      0x10
  33 #define WBSD_PINS_GP11_HI       0x04
  34 #define WBSD_PINS_DETECT_GP11   0x02
  35 #define WBSD_PINS_DETECT_DAT3   0x01
  36
  37 #define WBSD_CMDR               0x00
  38 #define WBSD_DFR                0x01
  39 #define WBSD_EIR                0x02
  40 #define WBSD_ISR                0x03
  41 #define WBSD_FSR                0x04
  42 #define WBSD_IDXR               0x05
  43 #define WBSD_DATAR              0x06
  44 #define WBSD_CSR                0x07
  45
  46 #define WBSD_EINT_CARD          0x40
  47 #define WBSD_EINT_FIFO_THRE     0x20
  48 #define WBSD_EINT_CCRC          0x10
  49 #define WBSD_EINT_TIMEOUT       0x08
  50 #define WBSD_EINT_PROGEND       0x04
  51 #define WBSD_EINT_CRC           0x02
  52 #define WBSD_EINT_TC            0x01
  53
  54 #define WBSD_INT_PENDING        0x80
  55 #define WBSD_INT_CARD           0x40
  56 #define WBSD_INT_FIFO_THRE      0x20
  57 #define WBSD_INT_CRC            0x10
  58 #define WBSD_INT_TIMEOUT        0x08
  59 #define WBSD_INT_PROGEND        0x04
  60 #define WBSD_INT_BUSYEND        0x02
  61 #define WBSD_INT_TC             0x01
  62
  63 #define WBSD_FIFO_EMPTY         0x80
  64 #define WBSD_FIFO_FULL          0x40
  65 #define WBSD_FIFO_EMTHRE        0x20
  66 #define WBSD_FIFO_FUTHRE        0x10
  67 #define WBSD_FIFO_SZMASK        0x0F
  68
  69 #define WBSD_MSLED              0x20
  70 #define WBSD_POWER_N            0x10
  71 #define WBSD_WRPT               0x04
  72 #define WBSD_CARDPRESENT        0x01
  73
  74 #define WBSD_IDX_CLK            0x01
  75 #define WBSD_IDX_PBSMSB         0x02
  76 #define WBSD_IDX_TAAC           0x03
  77 #define WBSD_IDX_NSAC           0x04
  78 #define WBSD_IDX_PBSLSB         0x05
  79 #define WBSD_IDX_SETUP          0x06
  80 #define WBSD_IDX_DMA            0x07
  81 #define WBSD_IDX_FIFOEN         0x08
  82 #define WBSD_IDX_STATUS         0x10
  83 #define WBSD_IDX_RSPLEN         0x1E
  84 #define WBSD_IDX_RESP0          0x1F
  85 #define WBSD_IDX_RESP1          0x20
  86 #define WBSD_IDX_RESP2          0x21
  87 #define WBSD_IDX_RESP3          0x22
  88 #define WBSD_IDX_RESP4          0x23
  89 #define WBSD_IDX_RESP5          0x24
  90 #define WBSD_IDX_RESP6          0x25
  91 #define WBSD_IDX_RESP7          0x26
  92 #define WBSD_IDX_RESP8          0x27
  93 #define WBSD_IDX_RESP9          0x28
  94 #define WBSD_IDX_RESP10         0x29
  95 #define WBSD_IDX_RESP11         0x2A
  96 #define WBSD_IDX_RESP12         0x2B
  97 #define WBSD_IDX_RESP13         0x2C
  98 #define WBSD_IDX_RESP14         0x2D
  99 #define WBSD_IDX_RESP15         0x2E
 100 #define WBSD_IDX_RESP16         0x2F
 101 #define WBSD_IDX_CRCSTATUS      0x30
 102 #define WBSD_IDX_ISR            0x3F
 103
 104 #define WBSD_CLK_375K           0x00
 105 #define WBSD_CLK_12M            0x01
 106 #define WBSD_CLK_16M            0x02
 107 #define WBSD_CLK_24M            0x03
 108
 109 #define WBSD_DATA_WIDTH         0x01
 110
 111 #define WBSD_DAT3_H             0x08
 112 #define WBSD_FIFO_RESET         0x04
 113 #define WBSD_SOFT_RESET         0x02
 114 #define WBSD_INC_INDEX          0x01
 115
 116 #define WBSD_DMA_SINGLE         0x02
 117 #define WBSD_DMA_ENABLE         0x01
 118
 119 #define WBSD_FIFOEN_EMPTY       0x20
 120 #define WBSD_FIFOEN_FULL        0x10
 121 #define WBSD_FIFO_THREMASK      0x0F
 122
 123 #define WBSD_BLOCK_READ         0x80
 124 #define WBSD_BLOCK_WRITE        0x40
 125 #define WBSD_BUSY               0x20
 126 #define WBSD_CARDTRAFFIC        0x04
 127 #define WBSD_SENDCMD            0x02
 128 #define WBSD_RECVRES            0x01
 129
 130 #define WBSD_RSP_SHORT          0x00
 131 #define WBSD_RSP_LONG           0x01
 132
 133 #define WBSD_CRC_MASK           0x1F
 134 #define WBSD_CRC_OK             0x05 /* S010E (00101) */
 135 #define WBSD_CRC_FAIL           0x0B /* S101E (01011) */
 136
 137 #define WBSD_DMA_SIZE           65536
 138
 139 struct wbsd_host
 140 {
 141         struct mmc_host*        mmc;            /* MMC structure */
 142
 143         spinlock_t              lock;           /* Mutex */
 144
 145         int                     flags;          /* Driver states */
 146
 147 #define WBSD_FCARD_PRESENT      (1<<0)          /* Card is present */
 148 #define WBSD_FIGNORE_DETECT     (1<<1)          /* Ignore card detection */
 149
 150         struct mmc_request*     mrq;            /* Current request */
 151
 152         u8                      isr;            /* Accumulated ISR */
 153
 154         struct scatterlist*     cur_sg;         /* Current SG entry */
 155         unsigned int            num_sg;         /* Number of entries left */
 156         void*                   mapped_sg;      /* vaddr of mapped sg */
 157
 158         unsigned int            offset;         /* Offset into current entry */
 159         unsigned int            remain;         /* Data left in curren entry */
 160
 161         int                     size;           /* Total size of transfer */
 162
 163         char*                   dma_buffer;     /* ISA DMA buffer */
 164         dma_addr_t              dma_addr;       /* Physical address for same */
 165
 166         int                     firsterr;       /* See fifo functions */
 167
 168         u8                      clk;            /* Current clock speed */
 169         unsigned char           bus_width;      /* Current bus width */
 170
 171         int                     config;         /* Config port */
 172         u8                      unlock_code;    /* Code to unlock config */
 173
 174         int                     chip_id;        /* ID of controller */
 175
 176         int                     base;           /* I/O port base */
 177         int                     irq;            /* Interrupt */
 178         int                     dma;            /* DMA channel */
 179
 180         struct tasklet_struct   card_tasklet;   /* Tasklet structures */
 181         struct tasklet_struct   fifo_tasklet;
 182         struct tasklet_struct   crc_tasklet;
 183         struct tasklet_struct   timeout_tasklet;
 184         struct tasklet_struct   finish_tasklet;
 185         struct tasklet_struct   block_tasklet;
 186
 187         struct timer_list       ignore_timer;   /* Ignore detection timer */
 188 };