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Linux 2.6.17.7
[linux/fpc-iii.git] / drivers / net / cassini.c
blobac48f7543500b7c53d5099383fa26c83c247a45e
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2 *
3 * Copyright (C) 2004 Sun Microsystems Inc.
4 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19 * 02111-1307, USA.
20 *
21 * This driver uses the sungem driver (c) David Miller
22 * (davem@redhat.com) as its basis.
23 *
24 * The cassini chip has a number of features that distinguish it from
25 * the gem chip:
26 * 4 transmit descriptor rings that are used for either QoS (VLAN) or
27 * load balancing (non-VLAN mode)
28 * batching of multiple packets
29 * multiple CPU dispatching
30 * page-based RX descriptor engine with separate completion rings
31 * Gigabit support (GMII and PCS interface)
32 * MIF link up/down detection works
33 *
34 * RX is handled by page sized buffers that are attached as fragments to
35 * the skb. here's what's done:
36 * -- driver allocates pages at a time and keeps reference counts
37 * on them.
38 * -- the upper protocol layers assume that the header is in the skb
39 * itself. as a result, cassini will copy a small amount (64 bytes)
40 * to make them happy.
41 * -- driver appends the rest of the data pages as frags to skbuffs
42 * and increments the reference count
43 * -- on page reclamation, the driver swaps the page with a spare page.
44 * if that page is still in use, it frees its reference to that page,
45 * and allocates a new page for use. otherwise, it just recycles the
46 * the page.
47 *
48 * NOTE: cassini can parse the header. however, it's not worth it
49 * as long as the network stack requires a header copy.
50 *
51 * TX has 4 queues. currently these queues are used in a round-robin
52 * fashion for load balancing. They can also be used for QoS. for that
53 * to work, however, QoS information needs to be exposed down to the driver
54 * level so that subqueues get targetted to particular transmit rings.
55 * alternatively, the queues can be configured via use of the all-purpose
56 * ioctl.
57 *
58 * RX DATA: the rx completion ring has all the info, but the rx desc
59 * ring has all of the data. RX can conceivably come in under multiple
60 * interrupts, but the INT# assignment needs to be set up properly by
61 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62 * that. also, the two descriptor rings are designed to distinguish between
63 * encrypted and non-encrypted packets, but we use them for buffering
64 * instead.
65 *
66 * by default, the selective clear mask is set up to process rx packets.
67 */
68
69 #include <linux/config.h>
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/types.h>
74 #include <linux/compiler.h>
75 #include <linux/slab.h>
76 #include <linux/delay.h>
77 #include <linux/init.h>
78 #include <linux/ioport.h>
79 #include <linux/pci.h>
80 #include <linux/mm.h>
81 #include <linux/highmem.h>
82 #include <linux/list.h>
83 #include <linux/dma-mapping.h>
84
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
88 #include <linux/ethtool.h>
89 #include <linux/crc32.h>
90 #include <linux/random.h>
91 #include <linux/mii.h>
92 #include <linux/ip.h>
93 #include <linux/tcp.h>
94 #include <linux/mutex.h>
95
96 #include <net/checksum.h>
97
98 #include <asm/atomic.h>
99 #include <asm/system.h>
100 #include <asm/io.h>
101 #include <asm/byteorder.h>
102 #include <asm/uaccess.h>
103
104 #define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105 #define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
106 #define CAS_NCPUS num_online_cpus()
107
108 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
109 #define USE_NAPI
110 #define cas_skb_release(x) netif_receive_skb(x)
111 #else
112 #define cas_skb_release(x) netif_rx(x)
113 #endif
114
115 /* select which firmware to use */
116 #define USE_HP_WORKAROUND
117 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
118 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
119
120 #include "cassini.h"
121
122 #define USE_TX_COMPWB /* use completion writeback registers */
123 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
124 #define USE_RX_BLANK /* hw interrupt mitigation */
125 #undef USE_ENTROPY_DEV /* don't test for entropy device */
126
127 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
128 * also, we need to make cp->lock finer-grained.
129 */
130 #undef USE_PCI_INTB
131 #undef USE_PCI_INTC
132 #undef USE_PCI_INTD
133 #undef USE_QOS
134
135 #undef USE_VPD_DEBUG /* debug vpd information if defined */
136
137 /* rx processing options */
138 #define USE_PAGE_ORDER /* specify to allocate large rx pages */
139 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
140 #define RX_COPY_ALWAYS 0 /* if 0, use frags */
141 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
142 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
143
144 #define DRV_MODULE_NAME "cassini"
145 #define PFX DRV_MODULE_NAME ": "
146 #define DRV_MODULE_VERSION "1.4"
147 #define DRV_MODULE_RELDATE "1 July 2004"
148
149 #define CAS_DEF_MSG_ENABLE \
150 (NETIF_MSG_DRV | \
151 NETIF_MSG_PROBE | \
152 NETIF_MSG_LINK | \
153 NETIF_MSG_TIMER | \
154 NETIF_MSG_IFDOWN | \
155 NETIF_MSG_IFUP | \
156 NETIF_MSG_RX_ERR | \
157 NETIF_MSG_TX_ERR)
158
159 /* length of time before we decide the hardware is borked,
160 * and dev->tx_timeout() should be called to fix the problem
161 */
162 #define CAS_TX_TIMEOUT (HZ)
163 #define CAS_LINK_TIMEOUT (22*HZ/10)
164 #define CAS_LINK_FAST_TIMEOUT (1)
165
166 /* timeout values for state changing. these specify the number
167 * of 10us delays to be used before giving up.
168 */
169 #define STOP_TRIES_PHY 1000
170 #define STOP_TRIES 5000
171
172 /* specify a minimum frame size to deal with some fifo issues
173 * max mtu == 2 * page size - ethernet header - 64 - swivel =
174 * 2 * page_size - 0x50
175 */
176 #define CAS_MIN_FRAME 97
177 #define CAS_1000MB_MIN_FRAME 255
178 #define CAS_MIN_MTU 60
179 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
180
181 #if 1
182 /*
183 * Eliminate these and use separate atomic counters for each, to
184 * avoid a race condition.
185 */
186 #else
187 #define CAS_RESET_MTU 1
188 #define CAS_RESET_ALL 2
189 #define CAS_RESET_SPARE 3
190 #endif
191
192 static char version[] __devinitdata =
193 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
194
195 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
196 static int link_mode;
197
198 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
199 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
200 MODULE_LICENSE("GPL");
201 module_param(cassini_debug, int, 0);
202 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
203 module_param(link_mode, int, 0);
204 MODULE_PARM_DESC(link_mode, "default link mode");
205
206 /*
207 * Work around for a PCS bug in which the link goes down due to the chip
208 * being confused and never showing a link status of "up."
209 */
210 #define DEFAULT_LINKDOWN_TIMEOUT 5
211 /*
212 * Value in seconds, for user input.
213 */
214 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
215 module_param(linkdown_timeout, int, 0);
216 MODULE_PARM_DESC(linkdown_timeout,
217 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
218
219 /*
220 * value in 'ticks' (units used by jiffies). Set when we init the
221 * module because 'HZ' in actually a function call on some flavors of
222 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
223 */
224 static int link_transition_timeout;
225
226
227
228 static u16 link_modes[] __devinitdata = {
229 BMCR_ANENABLE, /* 0 : autoneg */
230 0, /* 1 : 10bt half duplex */
231 BMCR_SPEED100, /* 2 : 100bt half duplex */
232 BMCR_FULLDPLX, /* 3 : 10bt full duplex */
233 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
234 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
235 };
236
237 static struct pci_device_id cas_pci_tbl[] __devinitdata = {
238 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242 { 0, }
243 };
244
245 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
246
247 static void cas_set_link_modes(struct cas *cp);
248
249 static inline void cas_lock_tx(struct cas *cp)
250 {
251 int i;
252
253 for (i = 0; i < N_TX_RINGS; i++)
254 spin_lock(&cp->tx_lock[i]);
255 }
256
257 static inline void cas_lock_all(struct cas *cp)
258 {
259 spin_lock_irq(&cp->lock);
260 cas_lock_tx(cp);
261 }
262
263 /* WTZ: QA was finding deadlock problems with the previous
264 * versions after long test runs with multiple cards per machine.
265 * See if replacing cas_lock_all with safer versions helps. The
266 * symptoms QA is reporting match those we'd expect if interrupts
267 * aren't being properly restored, and we fixed a previous deadlock
268 * with similar symptoms by using save/restore versions in other
269 * places.
270 */
271 #define cas_lock_all_save(cp, flags) \
272 do { \
273 struct cas *xxxcp = (cp); \
274 spin_lock_irqsave(&xxxcp->lock, flags); \
275 cas_lock_tx(xxxcp); \
276 } while (0)
277
278 static inline void cas_unlock_tx(struct cas *cp)
279 {
280 int i;
281
282 for (i = N_TX_RINGS; i > 0; i--)
283 spin_unlock(&cp->tx_lock[i - 1]);
284 }
285
286 static inline void cas_unlock_all(struct cas *cp)
287 {
288 cas_unlock_tx(cp);
289 spin_unlock_irq(&cp->lock);
290 }
291
292 #define cas_unlock_all_restore(cp, flags) \
293 do { \
294 struct cas *xxxcp = (cp); \
295 cas_unlock_tx(xxxcp); \
296 spin_unlock_irqrestore(&xxxcp->lock, flags); \
297 } while (0)
298
299 static void cas_disable_irq(struct cas *cp, const int ring)
300 {
301 /* Make sure we won't get any more interrupts */
302 if (ring == 0) {
303 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
304 return;
305 }
306
307 /* disable completion interrupts and selectively mask */
308 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
309 switch (ring) {
310 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
311 #ifdef USE_PCI_INTB
312 case 1:
313 #endif
314 #ifdef USE_PCI_INTC
315 case 2:
316 #endif
317 #ifdef USE_PCI_INTD
318 case 3:
319 #endif
320 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
321 cp->regs + REG_PLUS_INTRN_MASK(ring));
322 break;
323 #endif
324 default:
325 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
326 REG_PLUS_INTRN_MASK(ring));
327 break;
328 }
329 }
330 }
331
332 static inline void cas_mask_intr(struct cas *cp)
333 {
334 int i;
335
336 for (i = 0; i < N_RX_COMP_RINGS; i++)
337 cas_disable_irq(cp, i);
338 }
339
340 static inline void cas_buffer_init(cas_page_t *cp)
341 {
342 struct page *page = cp->buffer;
343 atomic_set((atomic_t *)&page->lru.next, 1);
344 }
345
346 static inline int cas_buffer_count(cas_page_t *cp)
347 {
348 struct page *page = cp->buffer;
349 return atomic_read((atomic_t *)&page->lru.next);
350 }
351
352 static inline void cas_buffer_inc(cas_page_t *cp)
353 {
354 struct page *page = cp->buffer;
355 atomic_inc((atomic_t *)&page->lru.next);
356 }
357
358 static inline void cas_buffer_dec(cas_page_t *cp)
359 {
360 struct page *page = cp->buffer;
361 atomic_dec((atomic_t *)&page->lru.next);
362 }
363
364 static void cas_enable_irq(struct cas *cp, const int ring)
365 {
366 if (ring == 0) { /* all but TX_DONE */
367 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
368 return;
369 }
370
371 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
372 switch (ring) {
373 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
374 #ifdef USE_PCI_INTB
375 case 1:
376 #endif
377 #ifdef USE_PCI_INTC
378 case 2:
379 #endif
380 #ifdef USE_PCI_INTD
381 case 3:
382 #endif
383 writel(INTRN_MASK_RX_EN, cp->regs +
384 REG_PLUS_INTRN_MASK(ring));
385 break;
386 #endif
387 default:
388 break;
389 }
390 }
391 }
392
393 static inline void cas_unmask_intr(struct cas *cp)
394 {
395 int i;
396
397 for (i = 0; i < N_RX_COMP_RINGS; i++)
398 cas_enable_irq(cp, i);
399 }
400
401 static inline void cas_entropy_gather(struct cas *cp)
402 {
403 #ifdef USE_ENTROPY_DEV
404 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
405 return;
406
407 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
408 readl(cp->regs + REG_ENTROPY_IV),
409 sizeof(uint64_t)*8);
410 #endif
411 }
412
413 static inline void cas_entropy_reset(struct cas *cp)
414 {
415 #ifdef USE_ENTROPY_DEV
416 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
417 return;
418
419 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
420 cp->regs + REG_BIM_LOCAL_DEV_EN);
421 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
422 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
423
424 /* if we read back 0x0, we don't have an entropy device */
425 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
426 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
427 #endif
428 }
429
430 /* access to the phy. the following assumes that we've initialized the MIF to
431 * be in frame rather than bit-bang mode
432 */
433 static u16 cas_phy_read(struct cas *cp, int reg)
434 {
435 u32 cmd;
436 int limit = STOP_TRIES_PHY;
437
438 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
439 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
440 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
441 cmd |= MIF_FRAME_TURN_AROUND_MSB;
442 writel(cmd, cp->regs + REG_MIF_FRAME);
443
444 /* poll for completion */
445 while (limit-- > 0) {
446 udelay(10);
447 cmd = readl(cp->regs + REG_MIF_FRAME);
448 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
449 return (cmd & MIF_FRAME_DATA_MASK);
450 }
451 return 0xFFFF; /* -1 */
452 }
453
454 static int cas_phy_write(struct cas *cp, int reg, u16 val)
455 {
456 int limit = STOP_TRIES_PHY;
457 u32 cmd;
458
459 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
460 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
461 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
462 cmd |= MIF_FRAME_TURN_AROUND_MSB;
463 cmd |= val & MIF_FRAME_DATA_MASK;
464 writel(cmd, cp->regs + REG_MIF_FRAME);
465
466 /* poll for completion */
467 while (limit-- > 0) {
468 udelay(10);
469 cmd = readl(cp->regs + REG_MIF_FRAME);
470 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
471 return 0;
472 }
473 return -1;
474 }
475
476 static void cas_phy_powerup(struct cas *cp)
477 {
478 u16 ctl = cas_phy_read(cp, MII_BMCR);
479
480 if ((ctl & BMCR_PDOWN) == 0)
481 return;
482 ctl &= ~BMCR_PDOWN;
483 cas_phy_write(cp, MII_BMCR, ctl);
484 }
485
486 static void cas_phy_powerdown(struct cas *cp)
487 {
488 u16 ctl = cas_phy_read(cp, MII_BMCR);
489
490 if (ctl & BMCR_PDOWN)
491 return;
492 ctl |= BMCR_PDOWN;
493 cas_phy_write(cp, MII_BMCR, ctl);
494 }
495
496 /* cp->lock held. note: the last put_page will free the buffer */
497 static int cas_page_free(struct cas *cp, cas_page_t *page)
498 {
499 pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
500 PCI_DMA_FROMDEVICE);
501 cas_buffer_dec(page);
502 __free_pages(page->buffer, cp->page_order);
503 kfree(page);
504 return 0;
505 }
506
507 #ifdef RX_COUNT_BUFFERS
508 #define RX_USED_ADD(x, y) ((x)->used += (y))
509 #define RX_USED_SET(x, y) ((x)->used = (y))
510 #else
511 #define RX_USED_ADD(x, y)
512 #define RX_USED_SET(x, y)
513 #endif
514
515 /* local page allocation routines for the receive buffers. jumbo pages
516 * require at least 8K contiguous and 8K aligned buffers.
517 */
518 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
519 {
520 cas_page_t *page;
521
522 page = kmalloc(sizeof(cas_page_t), flags);
523 if (!page)
524 return NULL;
525
526 INIT_LIST_HEAD(&page->list);
527 RX_USED_SET(page, 0);
528 page->buffer = alloc_pages(flags, cp->page_order);
529 if (!page->buffer)
530 goto page_err;
531 cas_buffer_init(page);
532 page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
533 cp->page_size, PCI_DMA_FROMDEVICE);
534 return page;
535
536 page_err:
537 kfree(page);
538 return NULL;
539 }
540
541 /* initialize spare pool of rx buffers, but allocate during the open */
542 static void cas_spare_init(struct cas *cp)
543 {
544 spin_lock(&cp->rx_inuse_lock);
545 INIT_LIST_HEAD(&cp->rx_inuse_list);
546 spin_unlock(&cp->rx_inuse_lock);
547
548 spin_lock(&cp->rx_spare_lock);
549 INIT_LIST_HEAD(&cp->rx_spare_list);
550 cp->rx_spares_needed = RX_SPARE_COUNT;
551 spin_unlock(&cp->rx_spare_lock);
552 }
553
554 /* used on close. free all the spare buffers. */
555 static void cas_spare_free(struct cas *cp)
556 {
557 struct list_head list, *elem, *tmp;
558
559 /* free spare buffers */
560 INIT_LIST_HEAD(&list);
561 spin_lock(&cp->rx_spare_lock);
562 list_splice(&cp->rx_spare_list, &list);
563 INIT_LIST_HEAD(&cp->rx_spare_list);
564 spin_unlock(&cp->rx_spare_lock);
565 list_for_each_safe(elem, tmp, &list) {
566 cas_page_free(cp, list_entry(elem, cas_page_t, list));
567 }
568
569 INIT_LIST_HEAD(&list);
570 #if 1
571 /*
572 * Looks like Adrian had protected this with a different
573 * lock than used everywhere else to manipulate this list.
574 */
575 spin_lock(&cp->rx_inuse_lock);
576 list_splice(&cp->rx_inuse_list, &list);
577 INIT_LIST_HEAD(&cp->rx_inuse_list);
578 spin_unlock(&cp->rx_inuse_lock);
579 #else
580 spin_lock(&cp->rx_spare_lock);
581 list_splice(&cp->rx_inuse_list, &list);
582 INIT_LIST_HEAD(&cp->rx_inuse_list);
583 spin_unlock(&cp->rx_spare_lock);
584 #endif
585 list_for_each_safe(elem, tmp, &list) {
586 cas_page_free(cp, list_entry(elem, cas_page_t, list));
587 }
588 }
589
590 /* replenish spares if needed */
591 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
592 {
593 struct list_head list, *elem, *tmp;
594 int needed, i;
595
596 /* check inuse list. if we don't need any more free buffers,
597 * just free it
598 */
599
600 /* make a local copy of the list */
601 INIT_LIST_HEAD(&list);
602 spin_lock(&cp->rx_inuse_lock);
603 list_splice(&cp->rx_inuse_list, &list);
604 INIT_LIST_HEAD(&cp->rx_inuse_list);
605 spin_unlock(&cp->rx_inuse_lock);
606
607 list_for_each_safe(elem, tmp, &list) {
608 cas_page_t *page = list_entry(elem, cas_page_t, list);
609
610 if (cas_buffer_count(page) > 1)
611 continue;
612
613 list_del(elem);
614 spin_lock(&cp->rx_spare_lock);
615 if (cp->rx_spares_needed > 0) {
616 list_add(elem, &cp->rx_spare_list);
617 cp->rx_spares_needed--;
618 spin_unlock(&cp->rx_spare_lock);
619 } else {
620 spin_unlock(&cp->rx_spare_lock);
621 cas_page_free(cp, page);
622 }
623 }
624
625 /* put any inuse buffers back on the list */
626 if (!list_empty(&list)) {
627 spin_lock(&cp->rx_inuse_lock);
628 list_splice(&list, &cp->rx_inuse_list);
629 spin_unlock(&cp->rx_inuse_lock);
630 }
631
632 spin_lock(&cp->rx_spare_lock);
633 needed = cp->rx_spares_needed;
634 spin_unlock(&cp->rx_spare_lock);
635 if (!needed)
636 return;
637
638 /* we still need spares, so try to allocate some */
639 INIT_LIST_HEAD(&list);
640 i = 0;
641 while (i < needed) {
642 cas_page_t *spare = cas_page_alloc(cp, flags);
643 if (!spare)
644 break;
645 list_add(&spare->list, &list);
646 i++;
647 }
648
649 spin_lock(&cp->rx_spare_lock);
650 list_splice(&list, &cp->rx_spare_list);
651 cp->rx_spares_needed -= i;
652 spin_unlock(&cp->rx_spare_lock);
653 }
654
655 /* pull a page from the list. */
656 static cas_page_t *cas_page_dequeue(struct cas *cp)
657 {
658 struct list_head *entry;
659 int recover;
660
661 spin_lock(&cp->rx_spare_lock);
662 if (list_empty(&cp->rx_spare_list)) {
663 /* try to do a quick recovery */
664 spin_unlock(&cp->rx_spare_lock);
665 cas_spare_recover(cp, GFP_ATOMIC);
666 spin_lock(&cp->rx_spare_lock);
667 if (list_empty(&cp->rx_spare_list)) {
668 if (netif_msg_rx_err(cp))
669 printk(KERN_ERR "%s: no spare buffers "
670 "available.\n", cp->dev->name);
671 spin_unlock(&cp->rx_spare_lock);
672 return NULL;
673 }
674 }
675
676 entry = cp->rx_spare_list.next;
677 list_del(entry);
678 recover = ++cp->rx_spares_needed;
679 spin_unlock(&cp->rx_spare_lock);
680
681 /* trigger the timer to do the recovery */
682 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
683 #if 1
684 atomic_inc(&cp->reset_task_pending);
685 atomic_inc(&cp->reset_task_pending_spare);
686 schedule_work(&cp->reset_task);
687 #else
688 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
689 schedule_work(&cp->reset_task);
690 #endif
691 }
692 return list_entry(entry, cas_page_t, list);
693 }
694
695
696 static void cas_mif_poll(struct cas *cp, const int enable)
697 {
698 u32 cfg;
699
700 cfg = readl(cp->regs + REG_MIF_CFG);
701 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
702
703 if (cp->phy_type & CAS_PHY_MII_MDIO1)
704 cfg |= MIF_CFG_PHY_SELECT;
705
706 /* poll and interrupt on link status change. */
707 if (enable) {
708 cfg |= MIF_CFG_POLL_EN;
709 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
710 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
711 }
712 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
713 cp->regs + REG_MIF_MASK);
714 writel(cfg, cp->regs + REG_MIF_CFG);
715 }
716
717 /* Must be invoked under cp->lock */
718 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
719 {
720 u16 ctl;
721 #if 1
722 int lcntl;
723 int changed = 0;
724 int oldstate = cp->lstate;
725 int link_was_not_down = !(oldstate == link_down);
726 #endif
727 /* Setup link parameters */
728 if (!ep)
729 goto start_aneg;
730 lcntl = cp->link_cntl;
731 if (ep->autoneg == AUTONEG_ENABLE)
732 cp->link_cntl = BMCR_ANENABLE;
733 else {
734 cp->link_cntl = 0;
735 if (ep->speed == SPEED_100)
736 cp->link_cntl |= BMCR_SPEED100;
737 else if (ep->speed == SPEED_1000)
738 cp->link_cntl |= CAS_BMCR_SPEED1000;
739 if (ep->duplex == DUPLEX_FULL)
740 cp->link_cntl |= BMCR_FULLDPLX;
741 }
742 #if 1
743 changed = (lcntl != cp->link_cntl);
744 #endif
745 start_aneg:
746 if (cp->lstate == link_up) {
747 printk(KERN_INFO "%s: PCS link down.\n",
748 cp->dev->name);
749 } else {
750 if (changed) {
751 printk(KERN_INFO "%s: link configuration changed\n",
752 cp->dev->name);
753 }
754 }
755 cp->lstate = link_down;
756 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
757 if (!cp->hw_running)
758 return;
759 #if 1
760 /*
761 * WTZ: If the old state was link_up, we turn off the carrier
762 * to replicate everything we do elsewhere on a link-down
763 * event when we were already in a link-up state..
764 */
765 if (oldstate == link_up)
766 netif_carrier_off(cp->dev);
767 if (changed && link_was_not_down) {
768 /*
769 * WTZ: This branch will simply schedule a full reset after
770 * we explicitly changed link modes in an ioctl. See if this
771 * fixes the link-problems we were having for forced mode.
772 */
773 atomic_inc(&cp->reset_task_pending);
774 atomic_inc(&cp->reset_task_pending_all);
775 schedule_work(&cp->reset_task);
776 cp->timer_ticks = 0;
777 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
778 return;
779 }
780 #endif
781 if (cp->phy_type & CAS_PHY_SERDES) {
782 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
783
784 if (cp->link_cntl & BMCR_ANENABLE) {
785 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
786 cp->lstate = link_aneg;
787 } else {
788 if (cp->link_cntl & BMCR_FULLDPLX)
789 val |= PCS_MII_CTRL_DUPLEX;
790 val &= ~PCS_MII_AUTONEG_EN;
791 cp->lstate = link_force_ok;
792 }
793 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
794 writel(val, cp->regs + REG_PCS_MII_CTRL);
795
796 } else {
797 cas_mif_poll(cp, 0);
798 ctl = cas_phy_read(cp, MII_BMCR);
799 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
800 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
801 ctl |= cp->link_cntl;
802 if (ctl & BMCR_ANENABLE) {
803 ctl |= BMCR_ANRESTART;
804 cp->lstate = link_aneg;
805 } else {
806 cp->lstate = link_force_ok;
807 }
808 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
809 cas_phy_write(cp, MII_BMCR, ctl);
810 cas_mif_poll(cp, 1);
811 }
812
813 cp->timer_ticks = 0;
814 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
815 }
816
817 /* Must be invoked under cp->lock. */
818 static int cas_reset_mii_phy(struct cas *cp)
819 {
820 int limit = STOP_TRIES_PHY;
821 u16 val;
822
823 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
824 udelay(100);
825 while (limit--) {
826 val = cas_phy_read(cp, MII_BMCR);
827 if ((val & BMCR_RESET) == 0)
828 break;
829 udelay(10);
830 }
831 return (limit <= 0);
832 }
833
834 static void cas_saturn_firmware_load(struct cas *cp)
835 {
836 cas_saturn_patch_t *patch = cas_saturn_patch;
837
838 cas_phy_powerdown(cp);
839
840 /* expanded memory access mode */
841 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
842
843 /* pointer configuration for new firmware */
844 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
845 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
846 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
847 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
848 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
849 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
850 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
851 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
852
853 /* download new firmware */
854 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
855 cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
856 while (patch->addr) {
857 cas_phy_write(cp, DP83065_MII_REGD, patch->val);
858 patch++;
859 }
860
861 /* enable firmware */
862 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
863 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
864 }
865
866
867 /* phy initialization */
868 static void cas_phy_init(struct cas *cp)
869 {
870 u16 val;
871
872 /* if we're in MII/GMII mode, set up phy */
873 if (CAS_PHY_MII(cp->phy_type)) {
874 writel(PCS_DATAPATH_MODE_MII,
875 cp->regs + REG_PCS_DATAPATH_MODE);
876
877 cas_mif_poll(cp, 0);
878 cas_reset_mii_phy(cp); /* take out of isolate mode */
879
880 if (PHY_LUCENT_B0 == cp->phy_id) {
881 /* workaround link up/down issue with lucent */
882 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
883 cas_phy_write(cp, MII_BMCR, 0x00f1);
884 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
885
886 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
887 /* workarounds for broadcom phy */
888 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
889 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
890 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
891 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
892 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
893 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
894 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
895 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
896 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
897 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
898 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
899
900 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
901 val = cas_phy_read(cp, BROADCOM_MII_REG4);
902 val = cas_phy_read(cp, BROADCOM_MII_REG4);
903 if (val & 0x0080) {
904 /* link workaround */
905 cas_phy_write(cp, BROADCOM_MII_REG4,
906 val & ~0x0080);
907 }
908
909 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
910 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
911 SATURN_PCFG_FSI : 0x0,
912 cp->regs + REG_SATURN_PCFG);
913
914 /* load firmware to address 10Mbps auto-negotiation
915 * issue. NOTE: this will need to be changed if the
916 * default firmware gets fixed.
917 */
918 if (PHY_NS_DP83065 == cp->phy_id) {
919 cas_saturn_firmware_load(cp);
920 }
921 cas_phy_powerup(cp);
922 }
923
924 /* advertise capabilities */
925 val = cas_phy_read(cp, MII_BMCR);
926 val &= ~BMCR_ANENABLE;
927 cas_phy_write(cp, MII_BMCR, val);
928 udelay(10);
929
930 cas_phy_write(cp, MII_ADVERTISE,
931 cas_phy_read(cp, MII_ADVERTISE) |
932 (ADVERTISE_10HALF | ADVERTISE_10FULL |
933 ADVERTISE_100HALF | ADVERTISE_100FULL |
934 CAS_ADVERTISE_PAUSE |
935 CAS_ADVERTISE_ASYM_PAUSE));
936
937 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
938 /* make sure that we don't advertise half
939 * duplex to avoid a chip issue
940 */
941 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
942 val &= ~CAS_ADVERTISE_1000HALF;
943 val |= CAS_ADVERTISE_1000FULL;
944 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
945 }
946
947 } else {
948 /* reset pcs for serdes */
949 u32 val;
950 int limit;
951
952 writel(PCS_DATAPATH_MODE_SERDES,
953 cp->regs + REG_PCS_DATAPATH_MODE);
954
955 /* enable serdes pins on saturn */
956 if (cp->cas_flags & CAS_FLAG_SATURN)
957 writel(0, cp->regs + REG_SATURN_PCFG);
958
959 /* Reset PCS unit. */
960 val = readl(cp->regs + REG_PCS_MII_CTRL);
961 val |= PCS_MII_RESET;
962 writel(val, cp->regs + REG_PCS_MII_CTRL);
963
964 limit = STOP_TRIES;
965 while (limit-- > 0) {
966 udelay(10);
967 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
968 PCS_MII_RESET) == 0)
969 break;
970 }
971 if (limit <= 0)
972 printk(KERN_WARNING "%s: PCS reset bit would not "
973 "clear [%08x].\n", cp->dev->name,
974 readl(cp->regs + REG_PCS_STATE_MACHINE));
975
976 /* Make sure PCS is disabled while changing advertisement
977 * configuration.
978 */
979 writel(0x0, cp->regs + REG_PCS_CFG);
980
981 /* Advertise all capabilities except half-duplex. */
982 val = readl(cp->regs + REG_PCS_MII_ADVERT);
983 val &= ~PCS_MII_ADVERT_HD;
984 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
985 PCS_MII_ADVERT_ASYM_PAUSE);
986 writel(val, cp->regs + REG_PCS_MII_ADVERT);
987
988 /* enable PCS */
989 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
990
991 /* pcs workaround: enable sync detect */
992 writel(PCS_SERDES_CTRL_SYNCD_EN,
993 cp->regs + REG_PCS_SERDES_CTRL);
994 }
995 }
996
997
998 static int cas_pcs_link_check(struct cas *cp)
999 {
1000 u32 stat, state_machine;
1001 int retval = 0;
1002
1003 /* The link status bit latches on zero, so you must
1004 * read it twice in such a case to see a transition
1005 * to the link being up.
1006 */
1007 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1008 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1009 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1010
1011 /* The remote-fault indication is only valid
1012 * when autoneg has completed.
1013 */
1014 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1015 PCS_MII_STATUS_REMOTE_FAULT)) ==
1016 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
1017 if (netif_msg_link(cp))
1018 printk(KERN_INFO "%s: PCS RemoteFault\n",
1019 cp->dev->name);
1020 }
1021
1022 /* work around link detection issue by querying the PCS state
1023 * machine directly.
1024 */
1025 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1026 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1027 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1028 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1029 stat |= PCS_MII_STATUS_LINK_STATUS;
1030 }
1031
1032 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1033 if (cp->lstate != link_up) {
1034 if (cp->opened) {
1035 cp->lstate = link_up;
1036 cp->link_transition = LINK_TRANSITION_LINK_UP;
1037
1038 cas_set_link_modes(cp);
1039 netif_carrier_on(cp->dev);
1040 }
1041 }
1042 } else if (cp->lstate == link_up) {
1043 cp->lstate = link_down;
1044 if (link_transition_timeout != 0 &&
1045 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1046 !cp->link_transition_jiffies_valid) {
1047 /*
1048 * force a reset, as a workaround for the
1049 * link-failure problem. May want to move this to a
1050 * point a bit earlier in the sequence. If we had
1051 * generated a reset a short time ago, we'll wait for
1052 * the link timer to check the status until a
1053 * timer expires (link_transistion_jiffies_valid is
1054 * true when the timer is running.) Instead of using
1055 * a system timer, we just do a check whenever the
1056 * link timer is running - this clears the flag after
1057 * a suitable delay.
1058 */
1059 retval = 1;
1060 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1061 cp->link_transition_jiffies = jiffies;
1062 cp->link_transition_jiffies_valid = 1;
1063 } else {
1064 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1065 }
1066 netif_carrier_off(cp->dev);
1067 if (cp->opened && netif_msg_link(cp)) {
1068 printk(KERN_INFO "%s: PCS link down.\n",
1069 cp->dev->name);
1070 }
1071
1072 /* Cassini only: if you force a mode, there can be
1073 * sync problems on link down. to fix that, the following
1074 * things need to be checked:
1075 * 1) read serialink state register
1076 * 2) read pcs status register to verify link down.
1077 * 3) if link down and serial link == 0x03, then you need
1078 * to global reset the chip.
1079 */
1080 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1081 /* should check to see if we're in a forced mode */
1082 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1083 if (stat == 0x03)
1084 return 1;
1085 }
1086 } else if (cp->lstate == link_down) {
1087 if (link_transition_timeout != 0 &&
1088 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1089 !cp->link_transition_jiffies_valid) {
1090 /* force a reset, as a workaround for the
1091 * link-failure problem. May want to move
1092 * this to a point a bit earlier in the
1093 * sequence.
1094 */
1095 retval = 1;
1096 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1097 cp->link_transition_jiffies = jiffies;
1098 cp->link_transition_jiffies_valid = 1;
1099 } else {
1100 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1101 }
1102 }
1103
1104 return retval;
1105 }
1106
1107 static int cas_pcs_interrupt(struct net_device *dev,
1108 struct cas *cp, u32 status)
1109 {
1110 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1111
1112 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1113 return 0;
1114 return cas_pcs_link_check(cp);
1115 }
1116
1117 static int cas_txmac_interrupt(struct net_device *dev,
1118 struct cas *cp, u32 status)
1119 {
1120 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1121
1122 if (!txmac_stat)
1123 return 0;
1124
1125 if (netif_msg_intr(cp))
1126 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1127 cp->dev->name, txmac_stat);
1128
1129 /* Defer timer expiration is quite normal,
1130 * don't even log the event.
1131 */
1132 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1133 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1134 return 0;
1135
1136 spin_lock(&cp->stat_lock[0]);
1137 if (txmac_stat & MAC_TX_UNDERRUN) {
1138 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1139 dev->name);
1140 cp->net_stats[0].tx_fifo_errors++;
1141 }
1142
1143 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1144 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1145 dev->name);
1146 cp->net_stats[0].tx_errors++;
1147 }
1148
1149 /* The rest are all cases of one of the 16-bit TX
1150 * counters expiring.
1151 */
1152 if (txmac_stat & MAC_TX_COLL_NORMAL)
1153 cp->net_stats[0].collisions += 0x10000;
1154
1155 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1156 cp->net_stats[0].tx_aborted_errors += 0x10000;
1157 cp->net_stats[0].collisions += 0x10000;
1158 }
1159
1160 if (txmac_stat & MAC_TX_COLL_LATE) {
1161 cp->net_stats[0].tx_aborted_errors += 0x10000;
1162 cp->net_stats[0].collisions += 0x10000;
1163 }
1164 spin_unlock(&cp->stat_lock[0]);
1165
1166 /* We do not keep track of MAC_TX_COLL_FIRST and
1167 * MAC_TX_PEAK_ATTEMPTS events.
1168 */
1169 return 0;
1170 }
1171
1172 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1173 {
1174 cas_hp_inst_t *inst;
1175 u32 val;
1176 int i;
1177
1178 i = 0;
1179 while ((inst = firmware) && inst->note) {
1180 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1181
1182 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1183 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1184 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1185
1186 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1187 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1188 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1189 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1190 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1191 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1192 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1193 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1194
1195 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1196 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1197 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1198 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1199 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1200 ++firmware;
1201 ++i;
1202 }
1203 }
1204
1205 static void cas_init_rx_dma(struct cas *cp)
1206 {
1207 u64 desc_dma = cp->block_dvma;
1208 u32 val;
1209 int i, size;
1210
1211 /* rx free descriptors */
1212 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1213 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1214 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1215 if ((N_RX_DESC_RINGS > 1) &&
1216 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
1217 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1218 writel(val, cp->regs + REG_RX_CFG);
1219
1220 val = (unsigned long) cp->init_rxds[0] -
1221 (unsigned long) cp->init_block;
1222 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1223 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1224 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1225
1226 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1227 /* rx desc 2 is for IPSEC packets. however,
1228 * we don't it that for that purpose.
1229 */
1230 val = (unsigned long) cp->init_rxds[1] -
1231 (unsigned long) cp->init_block;
1232 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1233 writel((desc_dma + val) & 0xffffffff, cp->regs +
1234 REG_PLUS_RX_DB1_LOW);
1235 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1236 REG_PLUS_RX_KICK1);
1237 }
1238
1239 /* rx completion registers */
1240 val = (unsigned long) cp->init_rxcs[0] -
1241 (unsigned long) cp->init_block;
1242 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1243 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1244
1245 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1246 /* rx comp 2-4 */
1247 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1248 val = (unsigned long) cp->init_rxcs[i] -
1249 (unsigned long) cp->init_block;
1250 writel((desc_dma + val) >> 32, cp->regs +
1251 REG_PLUS_RX_CBN_HI(i));
1252 writel((desc_dma + val) & 0xffffffff, cp->regs +
1253 REG_PLUS_RX_CBN_LOW(i));
1254 }
1255 }
1256
1257 /* read selective clear regs to prevent spurious interrupts
1258 * on reset because complete == kick.
1259 * selective clear set up to prevent interrupts on resets
1260 */
1261 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1262 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1263 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1264 for (i = 1; i < N_RX_COMP_RINGS; i++)
1265 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1266
1267 /* 2 is different from 3 and 4 */
1268 if (N_RX_COMP_RINGS > 1)
1269 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1270 cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1271
1272 for (i = 2; i < N_RX_COMP_RINGS; i++)
1273 writel(INTR_RX_DONE_ALT,
1274 cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1275 }
1276
1277 /* set up pause thresholds */
1278 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1279 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1280 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1281 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1282 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1283
1284 /* zero out dma reassembly buffers */
1285 for (i = 0; i < 64; i++) {
1286 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1287 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1288 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1289 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1290 }
1291
1292 /* make sure address register is 0 for normal operation */
1293 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1294 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1295
1296 /* interrupt mitigation */
1297 #ifdef USE_RX_BLANK
1298 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1299 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1300 writel(val, cp->regs + REG_RX_BLANK);
1301 #else
1302 writel(0x0, cp->regs + REG_RX_BLANK);
1303 #endif
1304
1305 /* interrupt generation as a function of low water marks for
1306 * free desc and completion entries. these are used to trigger
1307 * housekeeping for rx descs. we don't use the free interrupt
1308 * as it's not very useful
1309 */
1310 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1311 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1312 writel(val, cp->regs + REG_RX_AE_THRESH);
1313 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1314 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1315 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1316 }
1317
1318 /* Random early detect registers. useful for congestion avoidance.
1319 * this should be tunable.
1320 */
1321 writel(0x0, cp->regs + REG_RX_RED);
1322
1323 /* receive page sizes. default == 2K (0x800) */
1324 val = 0;
1325 if (cp->page_size == 0x1000)
1326 val = 0x1;
1327 else if (cp->page_size == 0x2000)
1328 val = 0x2;
1329 else if (cp->page_size == 0x4000)
1330 val = 0x3;
1331
1332 /* round mtu + offset. constrain to page size. */
1333 size = cp->dev->mtu + 64;
1334 if (size > cp->page_size)
1335 size = cp->page_size;
1336
1337 if (size <= 0x400)
1338 i = 0x0;
1339 else if (size <= 0x800)
1340 i = 0x1;
1341 else if (size <= 0x1000)
1342 i = 0x2;
1343 else
1344 i = 0x3;
1345
1346 cp->mtu_stride = 1 << (i + 10);
1347 val = CAS_BASE(RX_PAGE_SIZE, val);
1348 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1349 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1350 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1351 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1352
1353 /* enable the header parser if desired */
1354 if (CAS_HP_FIRMWARE == cas_prog_null)
1355 return;
1356
1357 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1358 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1359 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1360 writel(val, cp->regs + REG_HP_CFG);
1361 }
1362
1363 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1364 {
1365 memset(rxc, 0, sizeof(*rxc));
1366 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1367 }
1368
1369 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1370 * flipping is protected by the fact that the chip will not
1371 * hand back the same page index while it's being processed.
1372 */
1373 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1374 {
1375 cas_page_t *page = cp->rx_pages[1][index];
1376 cas_page_t *new;
1377
1378 if (cas_buffer_count(page) == 1)
1379 return page;
1380
1381 new = cas_page_dequeue(cp);
1382 if (new) {
1383 spin_lock(&cp->rx_inuse_lock);
1384 list_add(&page->list, &cp->rx_inuse_list);
1385 spin_unlock(&cp->rx_inuse_lock);
1386 }
1387 return new;
1388 }
1389
1390 /* this needs to be changed if we actually use the ENC RX DESC ring */
1391 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1392 const int index)
1393 {
1394 cas_page_t **page0 = cp->rx_pages[0];
1395 cas_page_t **page1 = cp->rx_pages[1];
1396
1397 /* swap if buffer is in use */
1398 if (cas_buffer_count(page0[index]) > 1) {
1399 cas_page_t *new = cas_page_spare(cp, index);
1400 if (new) {
1401 page1[index] = page0[index];
1402 page0[index] = new;
1403 }
1404 }
1405 RX_USED_SET(page0[index], 0);
1406 return page0[index];
1407 }
1408
1409 static void cas_clean_rxds(struct cas *cp)
1410 {
1411 /* only clean ring 0 as ring 1 is used for spare buffers */
1412 struct cas_rx_desc *rxd = cp->init_rxds[0];
1413 int i, size;
1414
1415 /* release all rx flows */
1416 for (i = 0; i < N_RX_FLOWS; i++) {
1417 struct sk_buff *skb;
1418 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1419 cas_skb_release(skb);
1420 }
1421 }
1422
1423 /* initialize descriptors */
1424 size = RX_DESC_RINGN_SIZE(0);
1425 for (i = 0; i < size; i++) {
1426 cas_page_t *page = cas_page_swap(cp, 0, i);
1427 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1428 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1429 CAS_BASE(RX_INDEX_RING, 0));
1430 }
1431
1432 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1433 cp->rx_last[0] = 0;
1434 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1435 }
1436
1437 static void cas_clean_rxcs(struct cas *cp)
1438 {
1439 int i, j;
1440
1441 /* take ownership of rx comp descriptors */
1442 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1443 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1444 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1445 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1446 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1447 cas_rxc_init(rxc + j);
1448 }
1449 }
1450 }
1451
1452 #if 0
1453 /* When we get a RX fifo overflow, the RX unit is probably hung
1454 * so we do the following.
1455 *
1456 * If any part of the reset goes wrong, we return 1 and that causes the
1457 * whole chip to be reset.
1458 */
1459 static int cas_rxmac_reset(struct cas *cp)
1460 {
1461 struct net_device *dev = cp->dev;
1462 int limit;
1463 u32 val;
1464
1465 /* First, reset MAC RX. */
1466 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1467 for (limit = 0; limit < STOP_TRIES; limit++) {
1468 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1469 break;
1470 udelay(10);
1471 }
1472 if (limit == STOP_TRIES) {
1473 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1474 "chip.\n", dev->name);
1475 return 1;
1476 }
1477
1478 /* Second, disable RX DMA. */
1479 writel(0, cp->regs + REG_RX_CFG);
1480 for (limit = 0; limit < STOP_TRIES; limit++) {
1481 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1482 break;
1483 udelay(10);
1484 }
1485 if (limit == STOP_TRIES) {
1486 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1487 "chip.\n", dev->name);
1488 return 1;
1489 }
1490
1491 mdelay(5);
1492
1493 /* Execute RX reset command. */
1494 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1495 for (limit = 0; limit < STOP_TRIES; limit++) {
1496 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1497 break;
1498 udelay(10);
1499 }
1500 if (limit == STOP_TRIES) {
1501 printk(KERN_ERR "%s: RX reset command will not execute, "
1502 "resetting whole chip.\n", dev->name);
1503 return 1;
1504 }
1505
1506 /* reset driver rx state */
1507 cas_clean_rxds(cp);
1508 cas_clean_rxcs(cp);
1509
1510 /* Now, reprogram the rest of RX unit. */
1511 cas_init_rx_dma(cp);
1512
1513 /* re-enable */
1514 val = readl(cp->regs + REG_RX_CFG);
1515 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1516 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1517 val = readl(cp->regs + REG_MAC_RX_CFG);
1518 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1519 return 0;
1520 }
1521 #endif
1522
1523 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1524 u32 status)
1525 {
1526 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1527
1528 if (!stat)
1529 return 0;
1530
1531 if (netif_msg_intr(cp))
1532 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1533 cp->dev->name, stat);
1534
1535 /* these are all rollovers */
1536 spin_lock(&cp->stat_lock[0]);
1537 if (stat & MAC_RX_ALIGN_ERR)
1538 cp->net_stats[0].rx_frame_errors += 0x10000;
1539
1540 if (stat & MAC_RX_CRC_ERR)
1541 cp->net_stats[0].rx_crc_errors += 0x10000;
1542
1543 if (stat & MAC_RX_LEN_ERR)
1544 cp->net_stats[0].rx_length_errors += 0x10000;
1545
1546 if (stat & MAC_RX_OVERFLOW) {
1547 cp->net_stats[0].rx_over_errors++;
1548 cp->net_stats[0].rx_fifo_errors++;
1549 }
1550
1551 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1552 * events.
1553 */
1554 spin_unlock(&cp->stat_lock[0]);
1555 return 0;
1556 }
1557
1558 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1559 u32 status)
1560 {
1561 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1562
1563 if (!stat)
1564 return 0;
1565
1566 if (netif_msg_intr(cp))
1567 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1568 cp->dev->name, stat);
1569
1570 /* This interrupt is just for pause frame and pause
1571 * tracking. It is useful for diagnostics and debug
1572 * but probably by default we will mask these events.
1573 */
1574 if (stat & MAC_CTRL_PAUSE_STATE)
1575 cp->pause_entered++;
1576
1577 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1578 cp->pause_last_time_recvd = (stat >> 16);
1579
1580 return 0;
1581 }
1582
1583
1584 /* Must be invoked under cp->lock. */
1585 static inline int cas_mdio_link_not_up(struct cas *cp)
1586 {
1587 u16 val;
1588
1589 switch (cp->lstate) {
1590 case link_force_ret:
1591 if (netif_msg_link(cp))
1592 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1593 " forced mode\n", cp->dev->name);
1594 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1595 cp->timer_ticks = 5;
1596 cp->lstate = link_force_ok;
1597 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1598 break;
1599
1600 case link_aneg:
1601 val = cas_phy_read(cp, MII_BMCR);
1602
1603 /* Try forced modes. we try things in the following order:
1604 * 1000 full -> 100 full/half -> 10 half
1605 */
1606 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1607 val |= BMCR_FULLDPLX;
1608 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1609 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1610 cas_phy_write(cp, MII_BMCR, val);
1611 cp->timer_ticks = 5;
1612 cp->lstate = link_force_try;
1613 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1614 break;
1615
1616 case link_force_try:
1617 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1618 val = cas_phy_read(cp, MII_BMCR);
1619 cp->timer_ticks = 5;
1620 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1621 val &= ~CAS_BMCR_SPEED1000;
1622 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1623 cas_phy_write(cp, MII_BMCR, val);
1624 break;
1625 }
1626
1627 if (val & BMCR_SPEED100) {
1628 if (val & BMCR_FULLDPLX) /* fd failed */
1629 val &= ~BMCR_FULLDPLX;
1630 else { /* 100Mbps failed */
1631 val &= ~BMCR_SPEED100;
1632 }
1633 cas_phy_write(cp, MII_BMCR, val);
1634 break;
1635 }
1636 default:
1637 break;
1638 }
1639 return 0;
1640 }
1641
1642
1643 /* must be invoked with cp->lock held */
1644 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1645 {
1646 int restart;
1647
1648 if (bmsr & BMSR_LSTATUS) {
1649 /* Ok, here we got a link. If we had it due to a forced
1650 * fallback, and we were configured for autoneg, we
1651 * retry a short autoneg pass. If you know your hub is
1652 * broken, use ethtool ;)
1653 */
1654 if ((cp->lstate == link_force_try) &&
1655 (cp->link_cntl & BMCR_ANENABLE)) {
1656 cp->lstate = link_force_ret;
1657 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1658 cas_mif_poll(cp, 0);
1659 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1660 cp->timer_ticks = 5;
1661 if (cp->opened && netif_msg_link(cp))
1662 printk(KERN_INFO "%s: Got link after fallback, retrying"
1663 " autoneg once...\n", cp->dev->name);
1664 cas_phy_write(cp, MII_BMCR,
1665 cp->link_fcntl | BMCR_ANENABLE |
1666 BMCR_ANRESTART);
1667 cas_mif_poll(cp, 1);
1668
1669 } else if (cp->lstate != link_up) {
1670 cp->lstate = link_up;
1671 cp->link_transition = LINK_TRANSITION_LINK_UP;
1672
1673 if (cp->opened) {
1674 cas_set_link_modes(cp);
1675 netif_carrier_on(cp->dev);
1676 }
1677 }
1678 return 0;
1679 }
1680
1681 /* link not up. if the link was previously up, we restart the
1682 * whole process
1683 */
1684 restart = 0;
1685 if (cp->lstate == link_up) {
1686 cp->lstate = link_down;
1687 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1688
1689 netif_carrier_off(cp->dev);
1690 if (cp->opened && netif_msg_link(cp))
1691 printk(KERN_INFO "%s: Link down\n",
1692 cp->dev->name);
1693 restart = 1;
1694
1695 } else if (++cp->timer_ticks > 10)
1696 cas_mdio_link_not_up(cp);
1697
1698 return restart;
1699 }
1700
1701 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1702 u32 status)
1703 {
1704 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1705 u16 bmsr;
1706
1707 /* check for a link change */
1708 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1709 return 0;
1710
1711 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1712 return cas_mii_link_check(cp, bmsr);
1713 }
1714
1715 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1716 u32 status)
1717 {
1718 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1719
1720 if (!stat)
1721 return 0;
1722
1723 printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1724 readl(cp->regs + REG_BIM_DIAG));
1725
1726 /* cassini+ has this reserved */
1727 if ((stat & PCI_ERR_BADACK) &&
1728 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1729 printk("<No ACK64# during ABS64 cycle> ");
1730
1731 if (stat & PCI_ERR_DTRTO)
1732 printk("<Delayed transaction timeout> ");
1733 if (stat & PCI_ERR_OTHER)
1734 printk("<other> ");
1735 if (stat & PCI_ERR_BIM_DMA_WRITE)
1736 printk("<BIM DMA 0 write req> ");
1737 if (stat & PCI_ERR_BIM_DMA_READ)
1738 printk("<BIM DMA 0 read req> ");
1739 printk("\n");
1740
1741 if (stat & PCI_ERR_OTHER) {
1742 u16 cfg;
1743
1744 /* Interrogate PCI config space for the
1745 * true cause.
1746 */
1747 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1748 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1749 dev->name, cfg);
1750 if (cfg & PCI_STATUS_PARITY)
1751 printk(KERN_ERR "%s: PCI parity error detected.\n",
1752 dev->name);
1753 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1754 printk(KERN_ERR "%s: PCI target abort.\n",
1755 dev->name);
1756 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1757 printk(KERN_ERR "%s: PCI master acks target abort.\n",
1758 dev->name);
1759 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1760 printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1761 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1762 printk(KERN_ERR "%s: PCI system error SERR#.\n",
1763 dev->name);
1764 if (cfg & PCI_STATUS_DETECTED_PARITY)
1765 printk(KERN_ERR "%s: PCI parity error.\n",
1766 dev->name);
1767
1768 /* Write the error bits back to clear them. */
1769 cfg &= (PCI_STATUS_PARITY |
1770 PCI_STATUS_SIG_TARGET_ABORT |
1771 PCI_STATUS_REC_TARGET_ABORT |
1772 PCI_STATUS_REC_MASTER_ABORT |
1773 PCI_STATUS_SIG_SYSTEM_ERROR |
1774 PCI_STATUS_DETECTED_PARITY);
1775 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1776 }
1777
1778 /* For all PCI errors, we should reset the chip. */
1779 return 1;
1780 }
1781
1782 /* All non-normal interrupt conditions get serviced here.
1783 * Returns non-zero if we should just exit the interrupt
1784 * handler right now (ie. if we reset the card which invalidates
1785 * all of the other original irq status bits).
1786 */
1787 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1788 u32 status)
1789 {
1790 if (status & INTR_RX_TAG_ERROR) {
1791 /* corrupt RX tag framing */
1792 if (netif_msg_rx_err(cp))
1793 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1794 cp->dev->name);
1795 spin_lock(&cp->stat_lock[0]);
1796 cp->net_stats[0].rx_errors++;
1797 spin_unlock(&cp->stat_lock[0]);
1798 goto do_reset;
1799 }
1800
1801 if (status & INTR_RX_LEN_MISMATCH) {
1802 /* length mismatch. */
1803 if (netif_msg_rx_err(cp))
1804 printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1805 cp->dev->name);
1806 spin_lock(&cp->stat_lock[0]);
1807 cp->net_stats[0].rx_errors++;
1808 spin_unlock(&cp->stat_lock[0]);
1809 goto do_reset;
1810 }
1811
1812 if (status & INTR_PCS_STATUS) {
1813 if (cas_pcs_interrupt(dev, cp, status))
1814 goto do_reset;
1815 }
1816
1817 if (status & INTR_TX_MAC_STATUS) {
1818 if (cas_txmac_interrupt(dev, cp, status))
1819 goto do_reset;
1820 }
1821
1822 if (status & INTR_RX_MAC_STATUS) {
1823 if (cas_rxmac_interrupt(dev, cp, status))
1824 goto do_reset;
1825 }
1826
1827 if (status & INTR_MAC_CTRL_STATUS) {
1828 if (cas_mac_interrupt(dev, cp, status))
1829 goto do_reset;
1830 }
1831
1832 if (status & INTR_MIF_STATUS) {
1833 if (cas_mif_interrupt(dev, cp, status))
1834 goto do_reset;
1835 }
1836
1837 if (status & INTR_PCI_ERROR_STATUS) {
1838 if (cas_pci_interrupt(dev, cp, status))
1839 goto do_reset;
1840 }
1841 return 0;
1842
1843 do_reset:
1844 #if 1
1845 atomic_inc(&cp->reset_task_pending);
1846 atomic_inc(&cp->reset_task_pending_all);
1847 printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1848 dev->name, status);
1849 schedule_work(&cp->reset_task);
1850 #else
1851 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1852 printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1853 schedule_work(&cp->reset_task);
1854 #endif
1855 return 1;
1856 }
1857
1858 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1859 * determining whether to do a netif_stop/wakeup
1860 */
1861 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1862 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1863 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1864 const int len)
1865 {
1866 unsigned long off = addr + len;
1867
1868 if (CAS_TABORT(cp) == 1)
1869 return 0;
1870 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1871 return 0;
1872 return TX_TARGET_ABORT_LEN;
1873 }
1874
1875 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1876 {
1877 struct cas_tx_desc *txds;
1878 struct sk_buff **skbs;
1879 struct net_device *dev = cp->dev;
1880 int entry, count;
1881
1882 spin_lock(&cp->tx_lock[ring]);
1883 txds = cp->init_txds[ring];
1884 skbs = cp->tx_skbs[ring];
1885 entry = cp->tx_old[ring];
1886
1887 count = TX_BUFF_COUNT(ring, entry, limit);
1888 while (entry != limit) {
1889 struct sk_buff *skb = skbs[entry];
1890 dma_addr_t daddr;
1891 u32 dlen;
1892 int frag;
1893
1894 if (!skb) {
1895 /* this should never occur */
1896 entry = TX_DESC_NEXT(ring, entry);
1897 continue;
1898 }
1899
1900 /* however, we might get only a partial skb release. */
1901 count -= skb_shinfo(skb)->nr_frags +
1902 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1903 if (count < 0)
1904 break;
1905
1906 if (netif_msg_tx_done(cp))
1907 printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1908 cp->dev->name, ring, entry);
1909
1910 skbs[entry] = NULL;
1911 cp->tx_tiny_use[ring][entry].nbufs = 0;
1912
1913 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1914 struct cas_tx_desc *txd = txds + entry;
1915
1916 daddr = le64_to_cpu(txd->buffer);
1917 dlen = CAS_VAL(TX_DESC_BUFLEN,
1918 le64_to_cpu(txd->control));
1919 pci_unmap_page(cp->pdev, daddr, dlen,
1920 PCI_DMA_TODEVICE);
1921 entry = TX_DESC_NEXT(ring, entry);
1922
1923 /* tiny buffer may follow */
1924 if (cp->tx_tiny_use[ring][entry].used) {
1925 cp->tx_tiny_use[ring][entry].used = 0;
1926 entry = TX_DESC_NEXT(ring, entry);
1927 }
1928 }
1929
1930 spin_lock(&cp->stat_lock[ring]);
1931 cp->net_stats[ring].tx_packets++;
1932 cp->net_stats[ring].tx_bytes += skb->len;
1933 spin_unlock(&cp->stat_lock[ring]);
1934 dev_kfree_skb_irq(skb);
1935 }
1936 cp->tx_old[ring] = entry;
1937
1938 /* this is wrong for multiple tx rings. the net device needs
1939 * multiple queues for this to do the right thing. we wait
1940 * for 2*packets to be available when using tiny buffers
1941 */
1942 if (netif_queue_stopped(dev) &&
1943 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1944 netif_wake_queue(dev);
1945 spin_unlock(&cp->tx_lock[ring]);
1946 }
1947
1948 static void cas_tx(struct net_device *dev, struct cas *cp,
1949 u32 status)
1950 {
1951 int limit, ring;
1952 #ifdef USE_TX_COMPWB
1953 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1954 #endif
1955 if (netif_msg_intr(cp))
1956 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n",
1957 cp->dev->name, status, (unsigned long long)compwb);
1958 /* process all the rings */
1959 for (ring = 0; ring < N_TX_RINGS; ring++) {
1960 #ifdef USE_TX_COMPWB
1961 /* use the completion writeback registers */
1962 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1963 CAS_VAL(TX_COMPWB_LSB, compwb);
1964 compwb = TX_COMPWB_NEXT(compwb);
1965 #else
1966 limit = readl(cp->regs + REG_TX_COMPN(ring));
1967 #endif
1968 if (cp->tx_old[ring] != limit)
1969 cas_tx_ringN(cp, ring, limit);
1970 }
1971 }
1972
1973
1974 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1975 int entry, const u64 *words,
1976 struct sk_buff **skbref)
1977 {
1978 int dlen, hlen, len, i, alloclen;
1979 int off, swivel = RX_SWIVEL_OFF_VAL;
1980 struct cas_page *page;
1981 struct sk_buff *skb;
1982 void *addr, *crcaddr;
1983 char *p;
1984
1985 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1986 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1987 len = hlen + dlen;
1988
1989 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1990 alloclen = len;
1991 else
1992 alloclen = max(hlen, RX_COPY_MIN);
1993
1994 skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1995 if (skb == NULL)
1996 return -1;
1997
1998 *skbref = skb;
1999 skb->dev = cp->dev;
2000 skb_reserve(skb, swivel);
2001
2002 p = skb->data;
2003 addr = crcaddr = NULL;
2004 if (hlen) { /* always copy header pages */
2005 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2006 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2007 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
2008 swivel;
2009
2010 i = hlen;
2011 if (!dlen) /* attach FCS */
2012 i += cp->crc_size;
2013 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2014 PCI_DMA_FROMDEVICE);
2015 addr = cas_page_map(page->buffer);
2016 memcpy(p, addr + off, i);
2017 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2018 PCI_DMA_FROMDEVICE);
2019 cas_page_unmap(addr);
2020 RX_USED_ADD(page, 0x100);
2021 p += hlen;
2022 swivel = 0;
2023 }
2024
2025
2026 if (alloclen < (hlen + dlen)) {
2027 skb_frag_t *frag = skb_shinfo(skb)->frags;
2028
2029 /* normal or jumbo packets. we use frags */
2030 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2031 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2032 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2033
2034 hlen = min(cp->page_size - off, dlen);
2035 if (hlen < 0) {
2036 if (netif_msg_rx_err(cp)) {
2037 printk(KERN_DEBUG "%s: rx page overflow: "
2038 "%d\n", cp->dev->name, hlen);
2039 }
2040 dev_kfree_skb_irq(skb);
2041 return -1;
2042 }
2043 i = hlen;
2044 if (i == dlen) /* attach FCS */
2045 i += cp->crc_size;
2046 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2047 PCI_DMA_FROMDEVICE);
2048
2049 /* make sure we always copy a header */
2050 swivel = 0;
2051 if (p == (char *) skb->data) { /* not split */
2052 addr = cas_page_map(page->buffer);
2053 memcpy(p, addr + off, RX_COPY_MIN);
2054 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2055 PCI_DMA_FROMDEVICE);
2056 cas_page_unmap(addr);
2057 off += RX_COPY_MIN;
2058 swivel = RX_COPY_MIN;
2059 RX_USED_ADD(page, cp->mtu_stride);
2060 } else {
2061 RX_USED_ADD(page, hlen);
2062 }
2063 skb_put(skb, alloclen);
2064
2065 skb_shinfo(skb)->nr_frags++;
2066 skb->data_len += hlen - swivel;
2067 skb->len += hlen - swivel;
2068
2069 get_page(page->buffer);
2070 cas_buffer_inc(page);
2071 frag->page = page->buffer;
2072 frag->page_offset = off;
2073 frag->size = hlen - swivel;
2074
2075 /* any more data? */
2076 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2077 hlen = dlen;
2078 off = 0;
2079
2080 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2081 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2082 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2083 hlen + cp->crc_size,
2084 PCI_DMA_FROMDEVICE);
2085 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2086 hlen + cp->crc_size,
2087 PCI_DMA_FROMDEVICE);
2088
2089 skb_shinfo(skb)->nr_frags++;
2090 skb->data_len += hlen;
2091 skb->len += hlen;
2092 frag++;
2093
2094 get_page(page->buffer);
2095 cas_buffer_inc(page);
2096 frag->page = page->buffer;
2097 frag->page_offset = 0;
2098 frag->size = hlen;
2099 RX_USED_ADD(page, hlen + cp->crc_size);
2100 }
2101
2102 if (cp->crc_size) {
2103 addr = cas_page_map(page->buffer);
2104 crcaddr = addr + off + hlen;
2105 }
2106
2107 } else {
2108 /* copying packet */
2109 if (!dlen)
2110 goto end_copy_pkt;
2111
2112 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2113 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2114 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2115 hlen = min(cp->page_size - off, dlen);
2116 if (hlen < 0) {
2117 if (netif_msg_rx_err(cp)) {
2118 printk(KERN_DEBUG "%s: rx page overflow: "
2119 "%d\n", cp->dev->name, hlen);
2120 }
2121 dev_kfree_skb_irq(skb);
2122 return -1;
2123 }
2124 i = hlen;
2125 if (i == dlen) /* attach FCS */
2126 i += cp->crc_size;
2127 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2128 PCI_DMA_FROMDEVICE);
2129 addr = cas_page_map(page->buffer);
2130 memcpy(p, addr + off, i);
2131 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2132 PCI_DMA_FROMDEVICE);
2133 cas_page_unmap(addr);
2134 if (p == (char *) skb->data) /* not split */
2135 RX_USED_ADD(page, cp->mtu_stride);
2136 else
2137 RX_USED_ADD(page, i);
2138
2139 /* any more data? */
2140 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2141 p += hlen;
2142 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2143 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2144 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2145 dlen + cp->crc_size,
2146 PCI_DMA_FROMDEVICE);
2147 addr = cas_page_map(page->buffer);
2148 memcpy(p, addr, dlen + cp->crc_size);
2149 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2150 dlen + cp->crc_size,
2151 PCI_DMA_FROMDEVICE);
2152 cas_page_unmap(addr);
2153 RX_USED_ADD(page, dlen + cp->crc_size);
2154 }
2155 end_copy_pkt:
2156 if (cp->crc_size) {
2157 addr = NULL;
2158 crcaddr = skb->data + alloclen;
2159 }
2160 skb_put(skb, alloclen);
2161 }
2162
2163 i = CAS_VAL(RX_COMP4_TCP_CSUM, words[3]);
2164 if (cp->crc_size) {
2165 /* checksum includes FCS. strip it out. */
2166 i = csum_fold(csum_partial(crcaddr, cp->crc_size, i));
2167 if (addr)
2168 cas_page_unmap(addr);
2169 }
2170 skb->csum = ntohs(i ^ 0xffff);
2171 skb->ip_summed = CHECKSUM_HW;
2172 skb->protocol = eth_type_trans(skb, cp->dev);
2173 return len;
2174 }
2175
2176
2177 /* we can handle up to 64 rx flows at a time. we do the same thing
2178 * as nonreassm except that we batch up the buffers.
2179 * NOTE: we currently just treat each flow as a bunch of packets that
2180 * we pass up. a better way would be to coalesce the packets
2181 * into a jumbo packet. to do that, we need to do the following:
2182 * 1) the first packet will have a clean split between header and
2183 * data. save both.
2184 * 2) each time the next flow packet comes in, extend the
2185 * data length and merge the checksums.
2186 * 3) on flow release, fix up the header.
2187 * 4) make sure the higher layer doesn't care.
2188 * because packets get coalesced, we shouldn't run into fragment count
2189 * issues.
2190 */
2191 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2192 struct sk_buff *skb)
2193 {
2194 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2195 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2196
2197 /* this is protected at a higher layer, so no need to
2198 * do any additional locking here. stick the buffer
2199 * at the end.
2200 */
2201 __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
2202 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2203 while ((skb = __skb_dequeue(flow))) {
2204 cas_skb_release(skb);
2205 }
2206 }
2207 }
2208
2209 /* put rx descriptor back on ring. if a buffer is in use by a higher
2210 * layer, this will need to put in a replacement.
2211 */
2212 static void cas_post_page(struct cas *cp, const int ring, const int index)
2213 {
2214 cas_page_t *new;
2215 int entry;
2216
2217 entry = cp->rx_old[ring];
2218
2219 new = cas_page_swap(cp, ring, index);
2220 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2221 cp->init_rxds[ring][entry].index =
2222 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2223 CAS_BASE(RX_INDEX_RING, ring));
2224
2225 entry = RX_DESC_ENTRY(ring, entry + 1);
2226 cp->rx_old[ring] = entry;
2227
2228 if (entry % 4)
2229 return;
2230
2231 if (ring == 0)
2232 writel(entry, cp->regs + REG_RX_KICK);
2233 else if ((N_RX_DESC_RINGS > 1) &&
2234 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2235 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2236 }
2237
2238
2239 /* only when things are bad */
2240 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2241 {
2242 unsigned int entry, last, count, released;
2243 int cluster;
2244 cas_page_t **page = cp->rx_pages[ring];
2245
2246 entry = cp->rx_old[ring];
2247
2248 if (netif_msg_intr(cp))
2249 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2250 cp->dev->name, ring, entry);
2251
2252 cluster = -1;
2253 count = entry & 0x3;
2254 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2255 released = 0;
2256 while (entry != last) {
2257 /* make a new buffer if it's still in use */
2258 if (cas_buffer_count(page[entry]) > 1) {
2259 cas_page_t *new = cas_page_dequeue(cp);
2260 if (!new) {
2261 /* let the timer know that we need to
2262 * do this again
2263 */
2264 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2265 if (!timer_pending(&cp->link_timer))
2266 mod_timer(&cp->link_timer, jiffies +
2267 CAS_LINK_FAST_TIMEOUT);
2268 cp->rx_old[ring] = entry;
2269 cp->rx_last[ring] = num ? num - released : 0;
2270 return -ENOMEM;
2271 }
2272 spin_lock(&cp->rx_inuse_lock);
2273 list_add(&page[entry]->list, &cp->rx_inuse_list);
2274 spin_unlock(&cp->rx_inuse_lock);
2275 cp->init_rxds[ring][entry].buffer =
2276 cpu_to_le64(new->dma_addr);
2277 page[entry] = new;
2278
2279 }
2280
2281 if (++count == 4) {
2282 cluster = entry;
2283 count = 0;
2284 }
2285 released++;
2286 entry = RX_DESC_ENTRY(ring, entry + 1);
2287 }
2288 cp->rx_old[ring] = entry;
2289
2290 if (cluster < 0)
2291 return 0;
2292
2293 if (ring == 0)
2294 writel(cluster, cp->regs + REG_RX_KICK);
2295 else if ((N_RX_DESC_RINGS > 1) &&
2296 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2297 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2298 return 0;
2299 }
2300
2301
2302 /* process a completion ring. packets are set up in three basic ways:
2303 * small packets: should be copied header + data in single buffer.
2304 * large packets: header and data in a single buffer.
2305 * split packets: header in a separate buffer from data.
2306 * data may be in multiple pages. data may be > 256
2307 * bytes but in a single page.
2308 *
2309 * NOTE: RX page posting is done in this routine as well. while there's
2310 * the capability of using multiple RX completion rings, it isn't
2311 * really worthwhile due to the fact that the page posting will
2312 * force serialization on the single descriptor ring.
2313 */
2314 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2315 {
2316 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2317 int entry, drops;
2318 int npackets = 0;
2319
2320 if (netif_msg_intr(cp))
2321 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2322 cp->dev->name, ring,
2323 readl(cp->regs + REG_RX_COMP_HEAD),
2324 cp->rx_new[ring]);
2325
2326 entry = cp->rx_new[ring];
2327 drops = 0;
2328 while (1) {
2329 struct cas_rx_comp *rxc = rxcs + entry;
2330 struct sk_buff *skb;
2331 int type, len;
2332 u64 words[4];
2333 int i, dring;
2334
2335 words[0] = le64_to_cpu(rxc->word1);
2336 words[1] = le64_to_cpu(rxc->word2);
2337 words[2] = le64_to_cpu(rxc->word3);
2338 words[3] = le64_to_cpu(rxc->word4);
2339
2340 /* don't touch if still owned by hw */
2341 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2342 if (type == 0)
2343 break;
2344
2345 /* hw hasn't cleared the zero bit yet */
2346 if (words[3] & RX_COMP4_ZERO) {
2347 break;
2348 }
2349
2350 /* get info on the packet */
2351 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2352 spin_lock(&cp->stat_lock[ring]);
2353 cp->net_stats[ring].rx_errors++;
2354 if (words[3] & RX_COMP4_LEN_MISMATCH)
2355 cp->net_stats[ring].rx_length_errors++;
2356 if (words[3] & RX_COMP4_BAD)
2357 cp->net_stats[ring].rx_crc_errors++;
2358 spin_unlock(&cp->stat_lock[ring]);
2359
2360 /* We'll just return it to Cassini. */
2361 drop_it:
2362 spin_lock(&cp->stat_lock[ring]);
2363 ++cp->net_stats[ring].rx_dropped;
2364 spin_unlock(&cp->stat_lock[ring]);
2365 goto next;
2366 }
2367
2368 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2369 if (len < 0) {
2370 ++drops;
2371 goto drop_it;
2372 }
2373
2374 /* see if it's a flow re-assembly or not. the driver
2375 * itself handles release back up.
2376 */
2377 if (RX_DONT_BATCH || (type == 0x2)) {
2378 /* non-reassm: these always get released */
2379 cas_skb_release(skb);
2380 } else {
2381 cas_rx_flow_pkt(cp, words, skb);
2382 }
2383
2384 spin_lock(&cp->stat_lock[ring]);
2385 cp->net_stats[ring].rx_packets++;
2386 cp->net_stats[ring].rx_bytes += len;
2387 spin_unlock(&cp->stat_lock[ring]);
2388 cp->dev->last_rx = jiffies;
2389
2390 next:
2391 npackets++;
2392
2393 /* should it be released? */
2394 if (words[0] & RX_COMP1_RELEASE_HDR) {
2395 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2396 dring = CAS_VAL(RX_INDEX_RING, i);
2397 i = CAS_VAL(RX_INDEX_NUM, i);
2398 cas_post_page(cp, dring, i);
2399 }
2400
2401 if (words[0] & RX_COMP1_RELEASE_DATA) {
2402 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2403 dring = CAS_VAL(RX_INDEX_RING, i);
2404 i = CAS_VAL(RX_INDEX_NUM, i);
2405 cas_post_page(cp, dring, i);
2406 }
2407
2408 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2409 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2410 dring = CAS_VAL(RX_INDEX_RING, i);
2411 i = CAS_VAL(RX_INDEX_NUM, i);
2412 cas_post_page(cp, dring, i);
2413 }
2414
2415 /* skip to the next entry */
2416 entry = RX_COMP_ENTRY(ring, entry + 1 +
2417 CAS_VAL(RX_COMP1_SKIP, words[0]));
2418 #ifdef USE_NAPI
2419 if (budget && (npackets >= budget))
2420 break;
2421 #endif
2422 }
2423 cp->rx_new[ring] = entry;
2424
2425 if (drops)
2426 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2427 cp->dev->name);
2428 return npackets;
2429 }
2430
2431
2432 /* put completion entries back on the ring */
2433 static void cas_post_rxcs_ringN(struct net_device *dev,
2434 struct cas *cp, int ring)
2435 {
2436 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2437 int last, entry;
2438
2439 last = cp->rx_cur[ring];
2440 entry = cp->rx_new[ring];
2441 if (netif_msg_intr(cp))
2442 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2443 dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2444 entry);
2445
2446 /* zero and re-mark descriptors */
2447 while (last != entry) {
2448 cas_rxc_init(rxc + last);
2449 last = RX_COMP_ENTRY(ring, last + 1);
2450 }
2451 cp->rx_cur[ring] = last;
2452
2453 if (ring == 0)
2454 writel(last, cp->regs + REG_RX_COMP_TAIL);
2455 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2456 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2457 }
2458
2459
2460
2461 /* cassini can use all four PCI interrupts for the completion ring.
2462 * rings 3 and 4 are identical
2463 */
2464 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2465 static inline void cas_handle_irqN(struct net_device *dev,
2466 struct cas *cp, const u32 status,
2467 const int ring)
2468 {
2469 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2470 cas_post_rxcs_ringN(dev, cp, ring);
2471 }
2472
2473 static irqreturn_t cas_interruptN(int irq, void *dev_id, struct pt_regs *regs)
2474 {
2475 struct net_device *dev = dev_id;
2476 struct cas *cp = netdev_priv(dev);
2477 unsigned long flags;
2478 int ring;
2479 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2480
2481 /* check for shared irq */
2482 if (status == 0)
2483 return IRQ_NONE;
2484
2485 ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2486 spin_lock_irqsave(&cp->lock, flags);
2487 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2488 #ifdef USE_NAPI
2489 cas_mask_intr(cp);
2490 netif_rx_schedule(dev);
2491 #else
2492 cas_rx_ringN(cp, ring, 0);
2493 #endif
2494 status &= ~INTR_RX_DONE_ALT;
2495 }
2496
2497 if (status)
2498 cas_handle_irqN(dev, cp, status, ring);
2499 spin_unlock_irqrestore(&cp->lock, flags);
2500 return IRQ_HANDLED;
2501 }
2502 #endif
2503
2504 #ifdef USE_PCI_INTB
2505 /* everything but rx packets */
2506 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2507 {
2508 if (status & INTR_RX_BUF_UNAVAIL_1) {
2509 /* Frame arrived, no free RX buffers available.
2510 * NOTE: we can get this on a link transition. */
2511 cas_post_rxds_ringN(cp, 1, 0);
2512 spin_lock(&cp->stat_lock[1]);
2513 cp->net_stats[1].rx_dropped++;
2514 spin_unlock(&cp->stat_lock[1]);
2515 }
2516
2517 if (status & INTR_RX_BUF_AE_1)
2518 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2519 RX_AE_FREEN_VAL(1));
2520
2521 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2522 cas_post_rxcs_ringN(cp, 1);
2523 }
2524
2525 /* ring 2 handles a few more events than 3 and 4 */
2526 static irqreturn_t cas_interrupt1(int irq, void *dev_id, struct pt_regs *regs)
2527 {
2528 struct net_device *dev = dev_id;
2529 struct cas *cp = netdev_priv(dev);
2530 unsigned long flags;
2531 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2532
2533 /* check for shared interrupt */
2534 if (status == 0)
2535 return IRQ_NONE;
2536
2537 spin_lock_irqsave(&cp->lock, flags);
2538 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2539 #ifdef USE_NAPI
2540 cas_mask_intr(cp);
2541 netif_rx_schedule(dev);
2542 #else
2543 cas_rx_ringN(cp, 1, 0);
2544 #endif
2545 status &= ~INTR_RX_DONE_ALT;
2546 }
2547 if (status)
2548 cas_handle_irq1(cp, status);
2549 spin_unlock_irqrestore(&cp->lock, flags);
2550 return IRQ_HANDLED;
2551 }
2552 #endif
2553
2554 static inline void cas_handle_irq(struct net_device *dev,
2555 struct cas *cp, const u32 status)
2556 {
2557 /* housekeeping interrupts */
2558 if (status & INTR_ERROR_MASK)
2559 cas_abnormal_irq(dev, cp, status);
2560
2561 if (status & INTR_RX_BUF_UNAVAIL) {
2562 /* Frame arrived, no free RX buffers available.
2563 * NOTE: we can get this on a link transition.
2564 */
2565 cas_post_rxds_ringN(cp, 0, 0);
2566 spin_lock(&cp->stat_lock[0]);
2567 cp->net_stats[0].rx_dropped++;
2568 spin_unlock(&cp->stat_lock[0]);
2569 } else if (status & INTR_RX_BUF_AE) {
2570 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2571 RX_AE_FREEN_VAL(0));
2572 }
2573
2574 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2575 cas_post_rxcs_ringN(dev, cp, 0);
2576 }
2577
2578 static irqreturn_t cas_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2579 {
2580 struct net_device *dev = dev_id;
2581 struct cas *cp = netdev_priv(dev);
2582 unsigned long flags;
2583 u32 status = readl(cp->regs + REG_INTR_STATUS);
2584
2585 if (status == 0)
2586 return IRQ_NONE;
2587
2588 spin_lock_irqsave(&cp->lock, flags);
2589 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2590 cas_tx(dev, cp, status);
2591 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2592 }
2593
2594 if (status & INTR_RX_DONE) {
2595 #ifdef USE_NAPI
2596 cas_mask_intr(cp);
2597 netif_rx_schedule(dev);
2598 #else
2599 cas_rx_ringN(cp, 0, 0);
2600 #endif
2601 status &= ~INTR_RX_DONE;
2602 }
2603
2604 if (status)
2605 cas_handle_irq(dev, cp, status);
2606 spin_unlock_irqrestore(&cp->lock, flags);
2607 return IRQ_HANDLED;
2608 }
2609
2610
2611 #ifdef USE_NAPI
2612 static int cas_poll(struct net_device *dev, int *budget)
2613 {
2614 struct cas *cp = netdev_priv(dev);
2615 int i, enable_intr, todo, credits;
2616 u32 status = readl(cp->regs + REG_INTR_STATUS);
2617 unsigned long flags;
2618
2619 spin_lock_irqsave(&cp->lock, flags);
2620 cas_tx(dev, cp, status);
2621 spin_unlock_irqrestore(&cp->lock, flags);
2622
2623 /* NAPI rx packets. we spread the credits across all of the
2624 * rxc rings
2625 */
2626 todo = min(*budget, dev->quota);
2627
2628 /* to make sure we're fair with the work we loop through each
2629 * ring N_RX_COMP_RING times with a request of
2630 * todo / N_RX_COMP_RINGS
2631 */
2632 enable_intr = 1;
2633 credits = 0;
2634 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2635 int j;
2636 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2637 credits += cas_rx_ringN(cp, j, todo / N_RX_COMP_RINGS);
2638 if (credits >= todo) {
2639 enable_intr = 0;
2640 goto rx_comp;
2641 }
2642 }
2643 }
2644
2645 rx_comp:
2646 *budget -= credits;
2647 dev->quota -= credits;
2648
2649 /* final rx completion */
2650 spin_lock_irqsave(&cp->lock, flags);
2651 if (status)
2652 cas_handle_irq(dev, cp, status);
2653
2654 #ifdef USE_PCI_INTB
2655 if (N_RX_COMP_RINGS > 1) {
2656 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2657 if (status)
2658 cas_handle_irq1(dev, cp, status);
2659 }
2660 #endif
2661
2662 #ifdef USE_PCI_INTC
2663 if (N_RX_COMP_RINGS > 2) {
2664 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2665 if (status)
2666 cas_handle_irqN(dev, cp, status, 2);
2667 }
2668 #endif
2669
2670 #ifdef USE_PCI_INTD
2671 if (N_RX_COMP_RINGS > 3) {
2672 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2673 if (status)
2674 cas_handle_irqN(dev, cp, status, 3);
2675 }
2676 #endif
2677 spin_unlock_irqrestore(&cp->lock, flags);
2678 if (enable_intr) {
2679 netif_rx_complete(dev);
2680 cas_unmask_intr(cp);
2681 return 0;
2682 }
2683 return 1;
2684 }
2685 #endif
2686
2687 #ifdef CONFIG_NET_POLL_CONTROLLER
2688 static void cas_netpoll(struct net_device *dev)
2689 {
2690 struct cas *cp = netdev_priv(dev);
2691
2692 cas_disable_irq(cp, 0);
2693 cas_interrupt(cp->pdev->irq, dev, NULL);
2694 cas_enable_irq(cp, 0);
2695
2696 #ifdef USE_PCI_INTB
2697 if (N_RX_COMP_RINGS > 1) {
2698 /* cas_interrupt1(); */
2699 }
2700 #endif
2701 #ifdef USE_PCI_INTC
2702 if (N_RX_COMP_RINGS > 2) {
2703 /* cas_interruptN(); */
2704 }
2705 #endif
2706 #ifdef USE_PCI_INTD
2707 if (N_RX_COMP_RINGS > 3) {
2708 /* cas_interruptN(); */
2709 }
2710 #endif
2711 }
2712 #endif
2713
2714 static void cas_tx_timeout(struct net_device *dev)
2715 {
2716 struct cas *cp = netdev_priv(dev);
2717
2718 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2719 if (!cp->hw_running) {
2720 printk("%s: hrm.. hw not running!\n", dev->name);
2721 return;
2722 }
2723
2724 printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2725 dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2726
2727 printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2728 dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2729
2730 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2731 "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2732 dev->name,
2733 readl(cp->regs + REG_TX_CFG),
2734 readl(cp->regs + REG_MAC_TX_STATUS),
2735 readl(cp->regs + REG_MAC_TX_CFG),
2736 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2737 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2738 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2739 readl(cp->regs + REG_TX_SM_1),
2740 readl(cp->regs + REG_TX_SM_2));
2741
2742 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2743 dev->name,
2744 readl(cp->regs + REG_RX_CFG),
2745 readl(cp->regs + REG_MAC_RX_STATUS),
2746 readl(cp->regs + REG_MAC_RX_CFG));
2747
2748 printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2749 dev->name,
2750 readl(cp->regs + REG_HP_STATE_MACHINE),
2751 readl(cp->regs + REG_HP_STATUS0),
2752 readl(cp->regs + REG_HP_STATUS1),
2753 readl(cp->regs + REG_HP_STATUS2));
2754
2755 #if 1
2756 atomic_inc(&cp->reset_task_pending);
2757 atomic_inc(&cp->reset_task_pending_all);
2758 schedule_work(&cp->reset_task);
2759 #else
2760 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2761 schedule_work(&cp->reset_task);
2762 #endif
2763 }
2764
2765 static inline int cas_intme(int ring, int entry)
2766 {
2767 /* Algorithm: IRQ every 1/2 of descriptors. */
2768 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2769 return 1;
2770 return 0;
2771 }
2772
2773
2774 static void cas_write_txd(struct cas *cp, int ring, int entry,
2775 dma_addr_t mapping, int len, u64 ctrl, int last)
2776 {
2777 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2778
2779 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2780 if (cas_intme(ring, entry))
2781 ctrl |= TX_DESC_INTME;
2782 if (last)
2783 ctrl |= TX_DESC_EOF;
2784 txd->control = cpu_to_le64(ctrl);
2785 txd->buffer = cpu_to_le64(mapping);
2786 }
2787
2788 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2789 const int entry)
2790 {
2791 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2792 }
2793
2794 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2795 const int entry, const int tentry)
2796 {
2797 cp->tx_tiny_use[ring][tentry].nbufs++;
2798 cp->tx_tiny_use[ring][entry].used = 1;
2799 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2800 }
2801
2802 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2803 struct sk_buff *skb)
2804 {
2805 struct net_device *dev = cp->dev;
2806 int entry, nr_frags, frag, tabort, tentry;
2807 dma_addr_t mapping;
2808 unsigned long flags;
2809 u64 ctrl;
2810 u32 len;
2811
2812 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2813
2814 /* This is a hard error, log it. */
2815 if (TX_BUFFS_AVAIL(cp, ring) <=
2816 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2817 netif_stop_queue(dev);
2818 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2819 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2820 "queue awake!\n", dev->name);
2821 return 1;
2822 }
2823
2824 ctrl = 0;
2825 if (skb->ip_summed == CHECKSUM_HW) {
2826 u64 csum_start_off, csum_stuff_off;
2827
2828 csum_start_off = (u64) (skb->h.raw - skb->data);
2829 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
2830
2831 ctrl = TX_DESC_CSUM_EN |
2832 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2833 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2834 }
2835
2836 entry = cp->tx_new[ring];
2837 cp->tx_skbs[ring][entry] = skb;
2838
2839 nr_frags = skb_shinfo(skb)->nr_frags;
2840 len = skb_headlen(skb);
2841 mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2842 offset_in_page(skb->data), len,
2843 PCI_DMA_TODEVICE);
2844
2845 tentry = entry;
2846 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2847 if (unlikely(tabort)) {
2848 /* NOTE: len is always > tabort */
2849 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2850 ctrl | TX_DESC_SOF, 0);
2851 entry = TX_DESC_NEXT(ring, entry);
2852
2853 memcpy(tx_tiny_buf(cp, ring, entry), skb->data +
2854 len - tabort, tabort);
2855 mapping = tx_tiny_map(cp, ring, entry, tentry);
2856 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2857 (nr_frags == 0));
2858 } else {
2859 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2860 TX_DESC_SOF, (nr_frags == 0));
2861 }
2862 entry = TX_DESC_NEXT(ring, entry);
2863
2864 for (frag = 0; frag < nr_frags; frag++) {
2865 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2866
2867 len = fragp->size;
2868 mapping = pci_map_page(cp->pdev, fragp->page,
2869 fragp->page_offset, len,
2870 PCI_DMA_TODEVICE);
2871
2872 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2873 if (unlikely(tabort)) {
2874 void *addr;
2875
2876 /* NOTE: len is always > tabort */
2877 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2878 ctrl, 0);
2879 entry = TX_DESC_NEXT(ring, entry);
2880
2881 addr = cas_page_map(fragp->page);
2882 memcpy(tx_tiny_buf(cp, ring, entry),
2883 addr + fragp->page_offset + len - tabort,
2884 tabort);
2885 cas_page_unmap(addr);
2886 mapping = tx_tiny_map(cp, ring, entry, tentry);
2887 len = tabort;
2888 }
2889
2890 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2891 (frag + 1 == nr_frags));
2892 entry = TX_DESC_NEXT(ring, entry);
2893 }
2894
2895 cp->tx_new[ring] = entry;
2896 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2897 netif_stop_queue(dev);
2898
2899 if (netif_msg_tx_queued(cp))
2900 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2901 "avail %d\n",
2902 dev->name, ring, entry, skb->len,
2903 TX_BUFFS_AVAIL(cp, ring));
2904 writel(entry, cp->regs + REG_TX_KICKN(ring));
2905 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2906 return 0;
2907 }
2908
2909 static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2910 {
2911 struct cas *cp = netdev_priv(dev);
2912
2913 /* this is only used as a load-balancing hint, so it doesn't
2914 * need to be SMP safe
2915 */
2916 static int ring;
2917
2918 skb = skb_padto(skb, cp->min_frame_size);
2919 if (!skb)
2920 return 0;
2921
2922 /* XXX: we need some higher-level QoS hooks to steer packets to
2923 * individual queues.
2924 */
2925 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2926 return 1;
2927 dev->trans_start = jiffies;
2928 return 0;
2929 }
2930
2931 static void cas_init_tx_dma(struct cas *cp)
2932 {
2933 u64 desc_dma = cp->block_dvma;
2934 unsigned long off;
2935 u32 val;
2936 int i;
2937
2938 /* set up tx completion writeback registers. must be 8-byte aligned */
2939 #ifdef USE_TX_COMPWB
2940 off = offsetof(struct cas_init_block, tx_compwb);
2941 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2942 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2943 #endif
2944
2945 /* enable completion writebacks, enable paced mode,
2946 * disable read pipe, and disable pre-interrupt compwbs
2947 */
2948 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2949 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2950 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2951 TX_CFG_INTR_COMPWB_DIS;
2952
2953 /* write out tx ring info and tx desc bases */
2954 for (i = 0; i < MAX_TX_RINGS; i++) {
2955 off = (unsigned long) cp->init_txds[i] -
2956 (unsigned long) cp->init_block;
2957
2958 val |= CAS_TX_RINGN_BASE(i);
2959 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2960 writel((desc_dma + off) & 0xffffffff, cp->regs +
2961 REG_TX_DBN_LOW(i));
2962 /* don't zero out the kick register here as the system
2963 * will wedge
2964 */
2965 }
2966 writel(val, cp->regs + REG_TX_CFG);
2967
2968 /* program max burst sizes. these numbers should be different
2969 * if doing QoS.
2970 */
2971 #ifdef USE_QOS
2972 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2973 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2974 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2975 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2976 #else
2977 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2978 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2979 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2980 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2981 #endif
2982 }
2983
2984 /* Must be invoked under cp->lock. */
2985 static inline void cas_init_dma(struct cas *cp)
2986 {
2987 cas_init_tx_dma(cp);
2988 cas_init_rx_dma(cp);
2989 }
2990
2991 /* Must be invoked under cp->lock. */
2992 static u32 cas_setup_multicast(struct cas *cp)
2993 {
2994 u32 rxcfg = 0;
2995 int i;
2996
2997 if (cp->dev->flags & IFF_PROMISC) {
2998 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2999
3000 } else if (cp->dev->flags & IFF_ALLMULTI) {
3001 for (i=0; i < 16; i++)
3002 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
3003 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3004
3005 } else {
3006 u16 hash_table[16];
3007 u32 crc;
3008 struct dev_mc_list *dmi = cp->dev->mc_list;
3009 int i;
3010
3011 /* use the alternate mac address registers for the
3012 * first 15 multicast addresses
3013 */
3014 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
3015 if (!dmi) {
3016 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
3017 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
3018 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
3019 continue;
3020 }
3021 writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5],
3022 cp->regs + REG_MAC_ADDRN(i*3 + 0));
3023 writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3],
3024 cp->regs + REG_MAC_ADDRN(i*3 + 1));
3025 writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1],
3026 cp->regs + REG_MAC_ADDRN(i*3 + 2));
3027 dmi = dmi->next;
3028 }
3029
3030 /* use hw hash table for the next series of
3031 * multicast addresses
3032 */
3033 memset(hash_table, 0, sizeof(hash_table));
3034 while (dmi) {
3035 crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
3036 crc >>= 24;
3037 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
3038 dmi = dmi->next;
3039 }
3040 for (i=0; i < 16; i++)
3041 writel(hash_table[i], cp->regs +
3042 REG_MAC_HASH_TABLEN(i));
3043 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3044 }
3045
3046 return rxcfg;
3047 }
3048
3049 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3050 static void cas_clear_mac_err(struct cas *cp)
3051 {
3052 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3053 writel(0, cp->regs + REG_MAC_COLL_FIRST);
3054 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3055 writel(0, cp->regs + REG_MAC_COLL_LATE);
3056 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3057 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3058 writel(0, cp->regs + REG_MAC_RECV_FRAME);
3059 writel(0, cp->regs + REG_MAC_LEN_ERR);
3060 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3061 writel(0, cp->regs + REG_MAC_FCS_ERR);
3062 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3063 }
3064
3065
3066 static void cas_mac_reset(struct cas *cp)
3067 {
3068 int i;
3069
3070 /* do both TX and RX reset */
3071 writel(0x1, cp->regs + REG_MAC_TX_RESET);
3072 writel(0x1, cp->regs + REG_MAC_RX_RESET);
3073
3074 /* wait for TX */
3075 i = STOP_TRIES;
3076 while (i-- > 0) {
3077 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3078 break;
3079 udelay(10);
3080 }
3081
3082 /* wait for RX */
3083 i = STOP_TRIES;
3084 while (i-- > 0) {
3085 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3086 break;
3087 udelay(10);
3088 }
3089
3090 if (readl(cp->regs + REG_MAC_TX_RESET) |
3091 readl(cp->regs + REG_MAC_RX_RESET))
3092 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3093 cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3094 readl(cp->regs + REG_MAC_RX_RESET),
3095 readl(cp->regs + REG_MAC_STATE_MACHINE));
3096 }
3097
3098
3099 /* Must be invoked under cp->lock. */
3100 static void cas_init_mac(struct cas *cp)
3101 {
3102 unsigned char *e = &cp->dev->dev_addr[0];
3103 int i;
3104 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3105 u32 rxcfg;
3106 #endif
3107 cas_mac_reset(cp);
3108
3109 /* setup core arbitration weight register */
3110 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3111
3112 /* XXX Use pci_dma_burst_advice() */
3113 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3114 /* set the infinite burst register for chips that don't have
3115 * pci issues.
3116 */
3117 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3118 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3119 #endif
3120
3121 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3122
3123 writel(0x00, cp->regs + REG_MAC_IPG0);
3124 writel(0x08, cp->regs + REG_MAC_IPG1);
3125 writel(0x04, cp->regs + REG_MAC_IPG2);
3126
3127 /* change later for 802.3z */
3128 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3129
3130 /* min frame + FCS */
3131 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3132
3133 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3134 * specify the maximum frame size to prevent RX tag errors on
3135 * oversized frames.
3136 */
3137 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3138 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3139 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3140 cp->regs + REG_MAC_FRAMESIZE_MAX);
3141
3142 /* NOTE: crc_size is used as a surrogate for half-duplex.
3143 * workaround saturn half-duplex issue by increasing preamble
3144 * size to 65 bytes.
3145 */
3146 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3147 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3148 else
3149 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3150 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3151 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3152 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3153
3154 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3155
3156 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3157 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3158 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3159 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3160 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3161
3162 /* setup mac address in perfect filter array */
3163 for (i = 0; i < 45; i++)
3164 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3165
3166 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3167 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3168 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3169
3170 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3171 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3172 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3173
3174 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3175 cp->mac_rx_cfg = cas_setup_multicast(cp);
3176 #else
3177 /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3178 * a writel does not seem to be necessary because Cassini
3179 * seems to preserve the configuration when we do the reset.
3180 * If the chip is in trouble, though, it is not clear if we
3181 * can really count on this behavior. cas_set_multicast uses
3182 * spin_lock_irqsave, but we are called only in cas_init_hw and
3183 * cas_init_hw is protected by cas_lock_all, which calls
3184 * spin_lock_irq (so it doesn't need to save the flags, and
3185 * we should be OK for the writel, as that is the only
3186 * difference).
3187 */
3188 cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3189 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3190 #endif
3191 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3192 cas_clear_mac_err(cp);
3193 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3194
3195 /* Setup MAC interrupts. We want to get all of the interesting
3196 * counter expiration events, but we do not want to hear about
3197 * normal rx/tx as the DMA engine tells us that.
3198 */
3199 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3200 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3201
3202 /* Don't enable even the PAUSE interrupts for now, we
3203 * make no use of those events other than to record them.
3204 */
3205 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3206 }
3207
3208 /* Must be invoked under cp->lock. */
3209 static void cas_init_pause_thresholds(struct cas *cp)
3210 {
3211 /* Calculate pause thresholds. Setting the OFF threshold to the
3212 * full RX fifo size effectively disables PAUSE generation
3213 */
3214 if (cp->rx_fifo_size <= (2 * 1024)) {
3215 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3216 } else {
3217 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3218 if (max_frame * 3 > cp->rx_fifo_size) {
3219 cp->rx_pause_off = 7104;
3220 cp->rx_pause_on = 960;
3221 } else {
3222 int off = (cp->rx_fifo_size - (max_frame * 2));
3223 int on = off - max_frame;
3224 cp->rx_pause_off = off;
3225 cp->rx_pause_on = on;
3226 }
3227 }
3228 }
3229
3230 static int cas_vpd_match(const void __iomem *p, const char *str)
3231 {
3232 int len = strlen(str) + 1;
3233 int i;
3234
3235 for (i = 0; i < len; i++) {
3236 if (readb(p + i) != str[i])
3237 return 0;
3238 }
3239 return 1;
3240 }
3241
3242
3243 /* get the mac address by reading the vpd information in the rom.
3244 * also get the phy type and determine if there's an entropy generator.
3245 * NOTE: this is a bit convoluted for the following reasons:
3246 * 1) vpd info has order-dependent mac addresses for multinic cards
3247 * 2) the only way to determine the nic order is to use the slot
3248 * number.
3249 * 3) fiber cards don't have bridges, so their slot numbers don't
3250 * mean anything.
3251 * 4) we don't actually know we have a fiber card until after
3252 * the mac addresses are parsed.
3253 */
3254 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3255 const int offset)
3256 {
3257 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3258 void __iomem *base, *kstart;
3259 int i, len;
3260 int found = 0;
3261 #define VPD_FOUND_MAC 0x01
3262 #define VPD_FOUND_PHY 0x02
3263
3264 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3265 int mac_off = 0;
3266
3267 /* give us access to the PROM */
3268 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3269 cp->regs + REG_BIM_LOCAL_DEV_EN);
3270
3271 /* check for an expansion rom */
3272 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3273 goto use_random_mac_addr;
3274
3275 /* search for beginning of vpd */
3276 base = NULL;
3277 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3278 /* check for PCIR */
3279 if ((readb(p + i + 0) == 0x50) &&
3280 (readb(p + i + 1) == 0x43) &&
3281 (readb(p + i + 2) == 0x49) &&
3282 (readb(p + i + 3) == 0x52)) {
3283 base = p + (readb(p + i + 8) |
3284 (readb(p + i + 9) << 8));
3285 break;
3286 }
3287 }
3288
3289 if (!base || (readb(base) != 0x82))
3290 goto use_random_mac_addr;
3291
3292 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3293 while (i < EXPANSION_ROM_SIZE) {
3294 if (readb(base + i) != 0x90) /* no vpd found */
3295 goto use_random_mac_addr;
3296
3297 /* found a vpd field */
3298 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3299
3300 /* extract keywords */
3301 kstart = base + i + 3;
3302 p = kstart;
3303 while ((p - kstart) < len) {
3304 int klen = readb(p + 2);
3305 int j;
3306 char type;
3307
3308 p += 3;
3309
3310 /* look for the following things:
3311 * -- correct length == 29
3312 * 3 (type) + 2 (size) +
3313 * 18 (strlen("local-mac-address") + 1) +
3314 * 6 (mac addr)
3315 * -- VPD Instance 'I'
3316 * -- VPD Type Bytes 'B'
3317 * -- VPD data length == 6
3318 * -- property string == local-mac-address
3319 *
3320 * -- correct length == 24
3321 * 3 (type) + 2 (size) +
3322 * 12 (strlen("entropy-dev") + 1) +
3323 * 7 (strlen("vms110") + 1)
3324 * -- VPD Instance 'I'
3325 * -- VPD Type String 'B'
3326 * -- VPD data length == 7
3327 * -- property string == entropy-dev
3328 *
3329 * -- correct length == 18
3330 * 3 (type) + 2 (size) +
3331 * 9 (strlen("phy-type") + 1) +
3332 * 4 (strlen("pcs") + 1)
3333 * -- VPD Instance 'I'
3334 * -- VPD Type String 'S'
3335 * -- VPD data length == 4
3336 * -- property string == phy-type
3337 *
3338 * -- correct length == 23
3339 * 3 (type) + 2 (size) +
3340 * 14 (strlen("phy-interface") + 1) +
3341 * 4 (strlen("pcs") + 1)
3342 * -- VPD Instance 'I'
3343 * -- VPD Type String 'S'
3344 * -- VPD data length == 4
3345 * -- property string == phy-interface
3346 */
3347 if (readb(p) != 'I')
3348 goto next;
3349
3350 /* finally, check string and length */
3351 type = readb(p + 3);
3352 if (type == 'B') {
3353 if ((klen == 29) && readb(p + 4) == 6 &&
3354 cas_vpd_match(p + 5,
3355 "local-mac-address")) {
3356 if (mac_off++ > offset)
3357 goto next;
3358
3359 /* set mac address */
3360 for (j = 0; j < 6; j++)
3361 dev_addr[j] =
3362 readb(p + 23 + j);
3363 goto found_mac;
3364 }
3365 }
3366
3367 if (type != 'S')
3368 goto next;
3369
3370 #ifdef USE_ENTROPY_DEV
3371 if ((klen == 24) &&
3372 cas_vpd_match(p + 5, "entropy-dev") &&
3373 cas_vpd_match(p + 17, "vms110")) {
3374 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3375 goto next;
3376 }
3377 #endif
3378
3379 if (found & VPD_FOUND_PHY)
3380 goto next;
3381
3382 if ((klen == 18) && readb(p + 4) == 4 &&
3383 cas_vpd_match(p + 5, "phy-type")) {
3384 if (cas_vpd_match(p + 14, "pcs")) {
3385 phy_type = CAS_PHY_SERDES;
3386 goto found_phy;
3387 }
3388 }
3389
3390 if ((klen == 23) && readb(p + 4) == 4 &&
3391 cas_vpd_match(p + 5, "phy-interface")) {
3392 if (cas_vpd_match(p + 19, "pcs")) {
3393 phy_type = CAS_PHY_SERDES;
3394 goto found_phy;
3395 }
3396 }
3397 found_mac:
3398 found |= VPD_FOUND_MAC;
3399 goto next;
3400
3401 found_phy:
3402 found |= VPD_FOUND_PHY;
3403
3404 next:
3405 p += klen;
3406 }
3407 i += len + 3;
3408 }
3409
3410 use_random_mac_addr:
3411 if (found & VPD_FOUND_MAC)
3412 goto done;
3413
3414 /* Sun MAC prefix then 3 random bytes. */
3415 printk(PFX "MAC address not found in ROM VPD\n");
3416 dev_addr[0] = 0x08;
3417 dev_addr[1] = 0x00;
3418 dev_addr[2] = 0x20;
3419 get_random_bytes(dev_addr + 3, 3);
3420
3421 done:
3422 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3423 return phy_type;
3424 }
3425
3426 /* check pci invariants */
3427 static void cas_check_pci_invariants(struct cas *cp)
3428 {
3429 struct pci_dev *pdev = cp->pdev;
3430 u8 rev;
3431
3432 cp->cas_flags = 0;
3433 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
3434 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3435 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3436 if (rev >= CAS_ID_REVPLUS)
3437 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3438 if (rev < CAS_ID_REVPLUS02u)
3439 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3440
3441 /* Original Cassini supports HW CSUM, but it's not
3442 * enabled by default as it can trigger TX hangs.
3443 */
3444 if (rev < CAS_ID_REV2)
3445 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3446 } else {
3447 /* Only sun has original cassini chips. */
3448 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3449
3450 /* We use a flag because the same phy might be externally
3451 * connected.
3452 */
3453 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3454 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3455 cp->cas_flags |= CAS_FLAG_SATURN;
3456 }
3457 }
3458
3459
3460 static int cas_check_invariants(struct cas *cp)
3461 {
3462 struct pci_dev *pdev = cp->pdev;
3463 u32 cfg;
3464 int i;
3465
3466 /* get page size for rx buffers. */
3467 cp->page_order = 0;
3468 #ifdef USE_PAGE_ORDER
3469 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3470 /* see if we can allocate larger pages */
3471 struct page *page = alloc_pages(GFP_ATOMIC,
3472 CAS_JUMBO_PAGE_SHIFT -
3473 PAGE_SHIFT);
3474 if (page) {
3475 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3476 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3477 } else {
3478 printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU);
3479 }
3480 }
3481 #endif
3482 cp->page_size = (PAGE_SIZE << cp->page_order);
3483
3484 /* Fetch the FIFO configurations. */
3485 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3486 cp->rx_fifo_size = RX_FIFO_SIZE;
3487
3488 /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3489 * they're both connected.
3490 */
3491 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3492 PCI_SLOT(pdev->devfn));
3493 if (cp->phy_type & CAS_PHY_SERDES) {
3494 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3495 return 0; /* no more checking needed */
3496 }
3497
3498 /* MII */
3499 cfg = readl(cp->regs + REG_MIF_CFG);
3500 if (cfg & MIF_CFG_MDIO_1) {
3501 cp->phy_type = CAS_PHY_MII_MDIO1;
3502 } else if (cfg & MIF_CFG_MDIO_0) {
3503 cp->phy_type = CAS_PHY_MII_MDIO0;
3504 }
3505
3506 cas_mif_poll(cp, 0);
3507 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3508
3509 for (i = 0; i < 32; i++) {
3510 u32 phy_id;
3511 int j;
3512
3513 for (j = 0; j < 3; j++) {
3514 cp->phy_addr = i;
3515 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3516 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3517 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3518 cp->phy_id = phy_id;
3519 goto done;
3520 }
3521 }
3522 }
3523 printk(KERN_ERR PFX "MII phy did not respond [%08x]\n",
3524 readl(cp->regs + REG_MIF_STATE_MACHINE));
3525 return -1;
3526
3527 done:
3528 /* see if we can do gigabit */
3529 cfg = cas_phy_read(cp, MII_BMSR);
3530 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3531 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3532 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3533 return 0;
3534 }
3535
3536 /* Must be invoked under cp->lock. */
3537 static inline void cas_start_dma(struct cas *cp)
3538 {
3539 int i;
3540 u32 val;
3541 int txfailed = 0;
3542
3543 /* enable dma */
3544 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3545 writel(val, cp->regs + REG_TX_CFG);
3546 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3547 writel(val, cp->regs + REG_RX_CFG);
3548
3549 /* enable the mac */
3550 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3551 writel(val, cp->regs + REG_MAC_TX_CFG);
3552 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3553 writel(val, cp->regs + REG_MAC_RX_CFG);
3554
3555 i = STOP_TRIES;
3556 while (i-- > 0) {
3557 val = readl(cp->regs + REG_MAC_TX_CFG);
3558 if ((val & MAC_TX_CFG_EN))
3559 break;
3560 udelay(10);
3561 }
3562 if (i < 0) txfailed = 1;
3563 i = STOP_TRIES;
3564 while (i-- > 0) {
3565 val = readl(cp->regs + REG_MAC_RX_CFG);
3566 if ((val & MAC_RX_CFG_EN)) {
3567 if (txfailed) {
3568 printk(KERN_ERR
3569 "%s: enabling mac failed [tx:%08x:%08x].\n",
3570 cp->dev->name,
3571 readl(cp->regs + REG_MIF_STATE_MACHINE),
3572 readl(cp->regs + REG_MAC_STATE_MACHINE));
3573 }
3574 goto enable_rx_done;
3575 }
3576 udelay(10);
3577 }
3578 printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n",
3579 cp->dev->name,
3580 (txfailed? "tx,rx":"rx"),
3581 readl(cp->regs + REG_MIF_STATE_MACHINE),
3582 readl(cp->regs + REG_MAC_STATE_MACHINE));
3583
3584 enable_rx_done:
3585 cas_unmask_intr(cp); /* enable interrupts */
3586 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3587 writel(0, cp->regs + REG_RX_COMP_TAIL);
3588
3589 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3590 if (N_RX_DESC_RINGS > 1)
3591 writel(RX_DESC_RINGN_SIZE(1) - 4,
3592 cp->regs + REG_PLUS_RX_KICK1);
3593
3594 for (i = 1; i < N_RX_COMP_RINGS; i++)
3595 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3596 }
3597 }
3598
3599 /* Must be invoked under cp->lock. */
3600 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3601 int *pause)
3602 {
3603 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3604 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3605 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3606 if (val & PCS_MII_LPA_ASYM_PAUSE)
3607 *pause |= 0x10;
3608 *spd = 1000;
3609 }
3610
3611 /* Must be invoked under cp->lock. */
3612 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3613 int *pause)
3614 {
3615 u32 val;
3616
3617 *fd = 0;
3618 *spd = 10;
3619 *pause = 0;
3620
3621 /* use GMII registers */
3622 val = cas_phy_read(cp, MII_LPA);
3623 if (val & CAS_LPA_PAUSE)
3624 *pause = 0x01;
3625
3626 if (val & CAS_LPA_ASYM_PAUSE)
3627 *pause |= 0x10;
3628
3629 if (val & LPA_DUPLEX)
3630 *fd = 1;
3631 if (val & LPA_100)
3632 *spd = 100;
3633
3634 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3635 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3636 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3637 *spd = 1000;
3638 if (val & CAS_LPA_1000FULL)
3639 *fd = 1;
3640 }
3641 }
3642
3643 /* A link-up condition has occurred, initialize and enable the
3644 * rest of the chip.
3645 *
3646 * Must be invoked under cp->lock.
3647 */
3648 static void cas_set_link_modes(struct cas *cp)
3649 {
3650 u32 val;
3651 int full_duplex, speed, pause;
3652
3653 full_duplex = 0;
3654 speed = 10;
3655 pause = 0;
3656
3657 if (CAS_PHY_MII(cp->phy_type)) {
3658 cas_mif_poll(cp, 0);
3659 val = cas_phy_read(cp, MII_BMCR);
3660 if (val & BMCR_ANENABLE) {
3661 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3662 &pause);
3663 } else {
3664 if (val & BMCR_FULLDPLX)
3665 full_duplex = 1;
3666
3667 if (val & BMCR_SPEED100)
3668 speed = 100;
3669 else if (val & CAS_BMCR_SPEED1000)
3670 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3671 1000 : 100;
3672 }
3673 cas_mif_poll(cp, 1);
3674
3675 } else {
3676 val = readl(cp->regs + REG_PCS_MII_CTRL);
3677 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3678 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3679 if (val & PCS_MII_CTRL_DUPLEX)
3680 full_duplex = 1;
3681 }
3682 }
3683
3684 if (netif_msg_link(cp))
3685 printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n",
3686 cp->dev->name, speed, (full_duplex ? "full" : "half"));
3687
3688 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3689 if (CAS_PHY_MII(cp->phy_type)) {
3690 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3691 if (!full_duplex)
3692 val |= MAC_XIF_DISABLE_ECHO;
3693 }
3694 if (full_duplex)
3695 val |= MAC_XIF_FDPLX_LED;
3696 if (speed == 1000)
3697 val |= MAC_XIF_GMII_MODE;
3698 writel(val, cp->regs + REG_MAC_XIF_CFG);
3699
3700 /* deal with carrier and collision detect. */
3701 val = MAC_TX_CFG_IPG_EN;
3702 if (full_duplex) {
3703 val |= MAC_TX_CFG_IGNORE_CARRIER;
3704 val |= MAC_TX_CFG_IGNORE_COLL;
3705 } else {
3706 #ifndef USE_CSMA_CD_PROTO
3707 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3708 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3709 #endif
3710 }
3711 /* val now set up for REG_MAC_TX_CFG */
3712
3713 /* If gigabit and half-duplex, enable carrier extension
3714 * mode. increase slot time to 512 bytes as well.
3715 * else, disable it and make sure slot time is 64 bytes.
3716 * also activate checksum bug workaround
3717 */
3718 if ((speed == 1000) && !full_duplex) {
3719 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3720 cp->regs + REG_MAC_TX_CFG);
3721
3722 val = readl(cp->regs + REG_MAC_RX_CFG);
3723 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3724 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3725 cp->regs + REG_MAC_RX_CFG);
3726
3727 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3728
3729 cp->crc_size = 4;
3730 /* minimum size gigabit frame at half duplex */
3731 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3732
3733 } else {
3734 writel(val, cp->regs + REG_MAC_TX_CFG);
3735
3736 /* checksum bug workaround. don't strip FCS when in
3737 * half-duplex mode
3738 */
3739 val = readl(cp->regs + REG_MAC_RX_CFG);
3740 if (full_duplex) {
3741 val |= MAC_RX_CFG_STRIP_FCS;
3742 cp->crc_size = 0;
3743 cp->min_frame_size = CAS_MIN_MTU;
3744 } else {
3745 val &= ~MAC_RX_CFG_STRIP_FCS;
3746 cp->crc_size = 4;
3747 cp->min_frame_size = CAS_MIN_FRAME;
3748 }
3749 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3750 cp->regs + REG_MAC_RX_CFG);
3751 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3752 }
3753
3754 if (netif_msg_link(cp)) {
3755 if (pause & 0x01) {
3756 printk(KERN_INFO "%s: Pause is enabled "
3757 "(rxfifo: %d off: %d on: %d)\n",
3758 cp->dev->name,
3759 cp->rx_fifo_size,
3760 cp->rx_pause_off,
3761 cp->rx_pause_on);
3762 } else if (pause & 0x10) {
3763 printk(KERN_INFO "%s: TX pause enabled\n",
3764 cp->dev->name);
3765 } else {
3766 printk(KERN_INFO "%s: Pause is disabled\n",
3767 cp->dev->name);
3768 }
3769 }
3770
3771 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3772 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3773 if (pause) { /* symmetric or asymmetric pause */
3774 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3775 if (pause & 0x01) { /* symmetric pause */
3776 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3777 }
3778 }
3779 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3780 cas_start_dma(cp);
3781 }
3782
3783 /* Must be invoked under cp->lock. */
3784 static void cas_init_hw(struct cas *cp, int restart_link)
3785 {
3786 if (restart_link)
3787 cas_phy_init(cp);
3788
3789 cas_init_pause_thresholds(cp);
3790 cas_init_mac(cp);
3791 cas_init_dma(cp);
3792
3793 if (restart_link) {
3794 /* Default aneg parameters */
3795 cp->timer_ticks = 0;
3796 cas_begin_auto_negotiation(cp, NULL);
3797 } else if (cp->lstate == link_up) {
3798 cas_set_link_modes(cp);
3799 netif_carrier_on(cp->dev);
3800 }
3801 }
3802
3803 /* Must be invoked under cp->lock. on earlier cassini boards,
3804 * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3805 * let it settle out, and then restore pci state.
3806 */
3807 static void cas_hard_reset(struct cas *cp)
3808 {
3809 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3810 udelay(20);
3811 pci_restore_state(cp->pdev);
3812 }
3813
3814
3815 static void cas_global_reset(struct cas *cp, int blkflag)
3816 {
3817 int limit;
3818
3819 /* issue a global reset. don't use RSTOUT. */
3820 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3821 /* For PCS, when the blkflag is set, we should set the
3822 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3823 * the last autonegotiation from being cleared. We'll
3824 * need some special handling if the chip is set into a
3825 * loopback mode.
3826 */
3827 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3828 cp->regs + REG_SW_RESET);
3829 } else {
3830 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3831 }
3832
3833 /* need to wait at least 3ms before polling register */
3834 mdelay(3);
3835
3836 limit = STOP_TRIES;
3837 while (limit-- > 0) {
3838 u32 val = readl(cp->regs + REG_SW_RESET);
3839 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3840 goto done;
3841 udelay(10);
3842 }
3843 printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name);
3844
3845 done:
3846 /* enable various BIM interrupts */
3847 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3848 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3849
3850 /* clear out pci error status mask for handled errors.
3851 * we don't deal with DMA counter overflows as they happen
3852 * all the time.
3853 */
3854 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3855 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3856 PCI_ERR_BIM_DMA_READ), cp->regs +
3857 REG_PCI_ERR_STATUS_MASK);
3858
3859 /* set up for MII by default to address mac rx reset timeout
3860 * issue
3861 */
3862 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3863 }
3864
3865 static void cas_reset(struct cas *cp, int blkflag)
3866 {
3867 u32 val;
3868
3869 cas_mask_intr(cp);
3870 cas_global_reset(cp, blkflag);
3871 cas_mac_reset(cp);
3872 cas_entropy_reset(cp);
3873
3874 /* disable dma engines. */
3875 val = readl(cp->regs + REG_TX_CFG);
3876 val &= ~TX_CFG_DMA_EN;
3877 writel(val, cp->regs + REG_TX_CFG);
3878
3879 val = readl(cp->regs + REG_RX_CFG);
3880 val &= ~RX_CFG_DMA_EN;
3881 writel(val, cp->regs + REG_RX_CFG);
3882
3883 /* program header parser */
3884 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3885 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3886 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3887 } else {
3888 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3889 }
3890
3891 /* clear out error registers */
3892 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3893 cas_clear_mac_err(cp);
3894 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3895 }
3896
3897 /* Shut down the chip, must be called with pm_mutex held. */
3898 static void cas_shutdown(struct cas *cp)
3899 {
3900 unsigned long flags;
3901
3902 /* Make us not-running to avoid timers respawning */
3903 cp->hw_running = 0;
3904
3905 del_timer_sync(&cp->link_timer);
3906
3907 /* Stop the reset task */
3908 #if 0
3909 while (atomic_read(&cp->reset_task_pending_mtu) ||
3910 atomic_read(&cp->reset_task_pending_spare) ||
3911 atomic_read(&cp->reset_task_pending_all))
3912 schedule();
3913
3914 #else
3915 while (atomic_read(&cp->reset_task_pending))
3916 schedule();
3917 #endif
3918 /* Actually stop the chip */
3919 cas_lock_all_save(cp, flags);
3920 cas_reset(cp, 0);
3921 if (cp->cas_flags & CAS_FLAG_SATURN)
3922 cas_phy_powerdown(cp);
3923 cas_unlock_all_restore(cp, flags);
3924 }
3925
3926 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3927 {
3928 struct cas *cp = netdev_priv(dev);
3929
3930 if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3931 return -EINVAL;
3932
3933 dev->mtu = new_mtu;
3934 if (!netif_running(dev) || !netif_device_present(dev))
3935 return 0;
3936
3937 /* let the reset task handle it */
3938 #if 1
3939 atomic_inc(&cp->reset_task_pending);
3940 if ((cp->phy_type & CAS_PHY_SERDES)) {
3941 atomic_inc(&cp->reset_task_pending_all);
3942 } else {
3943 atomic_inc(&cp->reset_task_pending_mtu);
3944 }
3945 schedule_work(&cp->reset_task);
3946 #else
3947 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3948 CAS_RESET_ALL : CAS_RESET_MTU);
3949 printk(KERN_ERR "reset called in cas_change_mtu\n");
3950 schedule_work(&cp->reset_task);
3951 #endif
3952
3953 flush_scheduled_work();
3954 return 0;
3955 }
3956
3957 static void cas_clean_txd(struct cas *cp, int ring)
3958 {
3959 struct cas_tx_desc *txd = cp->init_txds[ring];
3960 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3961 u64 daddr, dlen;
3962 int i, size;
3963
3964 size = TX_DESC_RINGN_SIZE(ring);
3965 for (i = 0; i < size; i++) {
3966 int frag;
3967
3968 if (skbs[i] == NULL)
3969 continue;
3970
3971 skb = skbs[i];
3972 skbs[i] = NULL;
3973
3974 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3975 int ent = i & (size - 1);
3976
3977 /* first buffer is never a tiny buffer and so
3978 * needs to be unmapped.
3979 */
3980 daddr = le64_to_cpu(txd[ent].buffer);
3981 dlen = CAS_VAL(TX_DESC_BUFLEN,
3982 le64_to_cpu(txd[ent].control));
3983 pci_unmap_page(cp->pdev, daddr, dlen,
3984 PCI_DMA_TODEVICE);
3985
3986 if (frag != skb_shinfo(skb)->nr_frags) {
3987 i++;
3988
3989 /* next buffer might by a tiny buffer.
3990 * skip past it.
3991 */
3992 ent = i & (size - 1);
3993 if (cp->tx_tiny_use[ring][ent].used)
3994 i++;
3995 }
3996 }
3997 dev_kfree_skb_any(skb);
3998 }
3999
4000 /* zero out tiny buf usage */
4001 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
4002 }
4003
4004 /* freed on close */
4005 static inline void cas_free_rx_desc(struct cas *cp, int ring)
4006 {
4007 cas_page_t **page = cp->rx_pages[ring];
4008 int i, size;
4009
4010 size = RX_DESC_RINGN_SIZE(ring);
4011 for (i = 0; i < size; i++) {
4012 if (page[i]) {
4013 cas_page_free(cp, page[i]);
4014 page[i] = NULL;
4015 }
4016 }
4017 }
4018
4019 static void cas_free_rxds(struct cas *cp)
4020 {
4021 int i;
4022
4023 for (i = 0; i < N_RX_DESC_RINGS; i++)
4024 cas_free_rx_desc(cp, i);
4025 }
4026
4027 /* Must be invoked under cp->lock. */
4028 static void cas_clean_rings(struct cas *cp)
4029 {
4030 int i;
4031
4032 /* need to clean all tx rings */
4033 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
4034 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
4035 for (i = 0; i < N_TX_RINGS; i++)
4036 cas_clean_txd(cp, i);
4037
4038 /* zero out init block */
4039 memset(cp->init_block, 0, sizeof(struct cas_init_block));
4040 cas_clean_rxds(cp);
4041 cas_clean_rxcs(cp);
4042 }
4043
4044 /* allocated on open */
4045 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
4046 {
4047 cas_page_t **page = cp->rx_pages[ring];
4048 int size, i = 0;
4049
4050 size = RX_DESC_RINGN_SIZE(ring);
4051 for (i = 0; i < size; i++) {
4052 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
4053 return -1;
4054 }
4055 return 0;
4056 }
4057
4058 static int cas_alloc_rxds(struct cas *cp)
4059 {
4060 int i;
4061
4062 for (i = 0; i < N_RX_DESC_RINGS; i++) {
4063 if (cas_alloc_rx_desc(cp, i) < 0) {
4064 cas_free_rxds(cp);
4065 return -1;
4066 }
4067 }
4068 return 0;
4069 }
4070
4071 static void cas_reset_task(void *data)
4072 {
4073 struct cas *cp = (struct cas *) data;
4074 #if 0
4075 int pending = atomic_read(&cp->reset_task_pending);
4076 #else
4077 int pending_all = atomic_read(&cp->reset_task_pending_all);
4078 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4079 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4080
4081 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4082 /* We can have more tasks scheduled than actually
4083 * needed.
4084 */
4085 atomic_dec(&cp->reset_task_pending);
4086 return;
4087 }
4088 #endif
4089 /* The link went down, we reset the ring, but keep
4090 * DMA stopped. Use this function for reset
4091 * on error as well.
4092 */
4093 if (cp->hw_running) {
4094 unsigned long flags;
4095
4096 /* Make sure we don't get interrupts or tx packets */
4097 netif_device_detach(cp->dev);
4098 cas_lock_all_save(cp, flags);
4099
4100 if (cp->opened) {
4101 /* We call cas_spare_recover when we call cas_open.
4102 * but we do not initialize the lists cas_spare_recover
4103 * uses until cas_open is called.
4104 */
4105 cas_spare_recover(cp, GFP_ATOMIC);
4106 }
4107 #if 1
4108 /* test => only pending_spare set */
4109 if (!pending_all && !pending_mtu)
4110 goto done;
4111 #else
4112 if (pending == CAS_RESET_SPARE)
4113 goto done;
4114 #endif
4115 /* when pending == CAS_RESET_ALL, the following
4116 * call to cas_init_hw will restart auto negotiation.
4117 * Setting the second argument of cas_reset to
4118 * !(pending == CAS_RESET_ALL) will set this argument
4119 * to 1 (avoiding reinitializing the PHY for the normal
4120 * PCS case) when auto negotiation is not restarted.
4121 */
4122 #if 1
4123 cas_reset(cp, !(pending_all > 0));
4124 if (cp->opened)
4125 cas_clean_rings(cp);
4126 cas_init_hw(cp, (pending_all > 0));
4127 #else
4128 cas_reset(cp, !(pending == CAS_RESET_ALL));
4129 if (cp->opened)
4130 cas_clean_rings(cp);
4131 cas_init_hw(cp, pending == CAS_RESET_ALL);
4132 #endif
4133
4134 done:
4135 cas_unlock_all_restore(cp, flags);
4136 netif_device_attach(cp->dev);
4137 }
4138 #if 1
4139 atomic_sub(pending_all, &cp->reset_task_pending_all);
4140 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4141 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4142 atomic_dec(&cp->reset_task_pending);
4143 #else
4144 atomic_set(&cp->reset_task_pending, 0);
4145 #endif
4146 }
4147
4148 static void cas_link_timer(unsigned long data)
4149 {
4150 struct cas *cp = (struct cas *) data;
4151 int mask, pending = 0, reset = 0;
4152 unsigned long flags;
4153
4154 if (link_transition_timeout != 0 &&
4155 cp->link_transition_jiffies_valid &&
4156 ((jiffies - cp->link_transition_jiffies) >
4157 (link_transition_timeout))) {
4158 /* One-second counter so link-down workaround doesn't
4159 * cause resets to occur so fast as to fool the switch
4160 * into thinking the link is down.
4161 */
4162 cp->link_transition_jiffies_valid = 0;
4163 }
4164
4165 if (!cp->hw_running)
4166 return;
4167
4168 spin_lock_irqsave(&cp->lock, flags);
4169 cas_lock_tx(cp);
4170 cas_entropy_gather(cp);
4171
4172 /* If the link task is still pending, we just
4173 * reschedule the link timer
4174 */
4175 #if 1
4176 if (atomic_read(&cp->reset_task_pending_all) ||
4177 atomic_read(&cp->reset_task_pending_spare) ||
4178 atomic_read(&cp->reset_task_pending_mtu))
4179 goto done;
4180 #else
4181 if (atomic_read(&cp->reset_task_pending))
4182 goto done;
4183 #endif
4184
4185 /* check for rx cleaning */
4186 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4187 int i, rmask;
4188
4189 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4190 rmask = CAS_FLAG_RXD_POST(i);
4191 if ((mask & rmask) == 0)
4192 continue;
4193
4194 /* post_rxds will do a mod_timer */
4195 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4196 pending = 1;
4197 continue;
4198 }
4199 cp->cas_flags &= ~rmask;
4200 }
4201 }
4202
4203 if (CAS_PHY_MII(cp->phy_type)) {
4204 u16 bmsr;
4205 cas_mif_poll(cp, 0);
4206 bmsr = cas_phy_read(cp, MII_BMSR);
4207 /* WTZ: Solaris driver reads this twice, but that
4208 * may be due to the PCS case and the use of a
4209 * common implementation. Read it twice here to be
4210 * safe.
4211 */
4212 bmsr = cas_phy_read(cp, MII_BMSR);
4213 cas_mif_poll(cp, 1);
4214 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4215 reset = cas_mii_link_check(cp, bmsr);
4216 } else {
4217 reset = cas_pcs_link_check(cp);
4218 }
4219
4220 if (reset)
4221 goto done;
4222
4223 /* check for tx state machine confusion */
4224 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4225 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4226 u32 wptr, rptr;
4227 int tlm = CAS_VAL(MAC_SM_TLM, val);
4228
4229 if (((tlm == 0x5) || (tlm == 0x3)) &&
4230 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4231 if (netif_msg_tx_err(cp))
4232 printk(KERN_DEBUG "%s: tx err: "
4233 "MAC_STATE[%08x]\n",
4234 cp->dev->name, val);
4235 reset = 1;
4236 goto done;
4237 }
4238
4239 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4240 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4241 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4242 if ((val == 0) && (wptr != rptr)) {
4243 if (netif_msg_tx_err(cp))
4244 printk(KERN_DEBUG "%s: tx err: "
4245 "TX_FIFO[%08x:%08x:%08x]\n",
4246 cp->dev->name, val, wptr, rptr);
4247 reset = 1;
4248 }
4249
4250 if (reset)
4251 cas_hard_reset(cp);
4252 }
4253
4254 done:
4255 if (reset) {
4256 #if 1
4257 atomic_inc(&cp->reset_task_pending);
4258 atomic_inc(&cp->reset_task_pending_all);
4259 schedule_work(&cp->reset_task);
4260 #else
4261 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4262 printk(KERN_ERR "reset called in cas_link_timer\n");
4263 schedule_work(&cp->reset_task);
4264 #endif
4265 }
4266
4267 if (!pending)
4268 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4269 cas_unlock_tx(cp);
4270 spin_unlock_irqrestore(&cp->lock, flags);
4271 }
4272
4273 /* tiny buffers are used to avoid target abort issues with
4274 * older cassini's
4275 */
4276 static void cas_tx_tiny_free(struct cas *cp)
4277 {
4278 struct pci_dev *pdev = cp->pdev;
4279 int i;
4280
4281 for (i = 0; i < N_TX_RINGS; i++) {
4282 if (!cp->tx_tiny_bufs[i])
4283 continue;
4284
4285 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4286 cp->tx_tiny_bufs[i],
4287 cp->tx_tiny_dvma[i]);
4288 cp->tx_tiny_bufs[i] = NULL;
4289 }
4290 }
4291
4292 static int cas_tx_tiny_alloc(struct cas *cp)
4293 {
4294 struct pci_dev *pdev = cp->pdev;
4295 int i;
4296
4297 for (i = 0; i < N_TX_RINGS; i++) {
4298 cp->tx_tiny_bufs[i] =
4299 pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4300 &cp->tx_tiny_dvma[i]);
4301 if (!cp->tx_tiny_bufs[i]) {
4302 cas_tx_tiny_free(cp);
4303 return -1;
4304 }
4305 }
4306 return 0;
4307 }
4308
4309
4310 static int cas_open(struct net_device *dev)
4311 {
4312 struct cas *cp = netdev_priv(dev);
4313 int hw_was_up, err;
4314 unsigned long flags;
4315
4316 mutex_lock(&cp->pm_mutex);
4317
4318 hw_was_up = cp->hw_running;
4319
4320 /* The power-management mutex protects the hw_running
4321 * etc. state so it is safe to do this bit without cp->lock
4322 */
4323 if (!cp->hw_running) {
4324 /* Reset the chip */
4325 cas_lock_all_save(cp, flags);
4326 /* We set the second arg to cas_reset to zero
4327 * because cas_init_hw below will have its second
4328 * argument set to non-zero, which will force
4329 * autonegotiation to start.
4330 */
4331 cas_reset(cp, 0);
4332 cp->hw_running = 1;
4333 cas_unlock_all_restore(cp, flags);
4334 }
4335
4336 if (cas_tx_tiny_alloc(cp) < 0)
4337 return -ENOMEM;
4338
4339 /* alloc rx descriptors */
4340 err = -ENOMEM;
4341 if (cas_alloc_rxds(cp) < 0)
4342 goto err_tx_tiny;
4343
4344 /* allocate spares */
4345 cas_spare_init(cp);
4346 cas_spare_recover(cp, GFP_KERNEL);
4347
4348 /* We can now request the interrupt as we know it's masked
4349 * on the controller. cassini+ has up to 4 interrupts
4350 * that can be used, but you need to do explicit pci interrupt
4351 * mapping to expose them
4352 */
4353 if (request_irq(cp->pdev->irq, cas_interrupt,
4354 SA_SHIRQ, dev->name, (void *) dev)) {
4355 printk(KERN_ERR "%s: failed to request irq !\n",
4356 cp->dev->name);
4357 err = -EAGAIN;
4358 goto err_spare;
4359 }
4360
4361 /* init hw */
4362 cas_lock_all_save(cp, flags);
4363 cas_clean_rings(cp);
4364 cas_init_hw(cp, !hw_was_up);
4365 cp->opened = 1;
4366 cas_unlock_all_restore(cp, flags);
4367
4368 netif_start_queue(dev);
4369 mutex_unlock(&cp->pm_mutex);
4370 return 0;
4371
4372 err_spare:
4373 cas_spare_free(cp);
4374 cas_free_rxds(cp);
4375 err_tx_tiny:
4376 cas_tx_tiny_free(cp);
4377 mutex_unlock(&cp->pm_mutex);
4378 return err;
4379 }
4380
4381 static int cas_close(struct net_device *dev)
4382 {
4383 unsigned long flags;
4384 struct cas *cp = netdev_priv(dev);
4385
4386 /* Make sure we don't get distracted by suspend/resume */
4387 mutex_lock(&cp->pm_mutex);
4388
4389 netif_stop_queue(dev);
4390
4391 /* Stop traffic, mark us closed */
4392 cas_lock_all_save(cp, flags);
4393 cp->opened = 0;
4394 cas_reset(cp, 0);
4395 cas_phy_init(cp);
4396 cas_begin_auto_negotiation(cp, NULL);
4397 cas_clean_rings(cp);
4398 cas_unlock_all_restore(cp, flags);
4399
4400 free_irq(cp->pdev->irq, (void *) dev);
4401 cas_spare_free(cp);
4402 cas_free_rxds(cp);
4403 cas_tx_tiny_free(cp);
4404 mutex_unlock(&cp->pm_mutex);
4405 return 0;
4406 }
4407
4408 static struct {
4409 const char name[ETH_GSTRING_LEN];
4410 } ethtool_cassini_statnames[] = {
4411 {"collisions"},
4412 {"rx_bytes"},
4413 {"rx_crc_errors"},
4414 {"rx_dropped"},
4415 {"rx_errors"},
4416 {"rx_fifo_errors"},
4417 {"rx_frame_errors"},
4418 {"rx_length_errors"},
4419 {"rx_over_errors"},
4420 {"rx_packets"},
4421 {"tx_aborted_errors"},
4422 {"tx_bytes"},
4423 {"tx_dropped"},
4424 {"tx_errors"},
4425 {"tx_fifo_errors"},
4426 {"tx_packets"}
4427 };
4428 #define CAS_NUM_STAT_KEYS (sizeof(ethtool_cassini_statnames)/ETH_GSTRING_LEN)
4429
4430 static struct {
4431 const int offsets; /* neg. values for 2nd arg to cas_read_phy */
4432 } ethtool_register_table[] = {
4433 {-MII_BMSR},
4434 {-MII_BMCR},
4435 {REG_CAWR},
4436 {REG_INF_BURST},
4437 {REG_BIM_CFG},
4438 {REG_RX_CFG},
4439 {REG_HP_CFG},
4440 {REG_MAC_TX_CFG},
4441 {REG_MAC_RX_CFG},
4442 {REG_MAC_CTRL_CFG},
4443 {REG_MAC_XIF_CFG},
4444 {REG_MIF_CFG},
4445 {REG_PCS_CFG},
4446 {REG_SATURN_PCFG},
4447 {REG_PCS_MII_STATUS},
4448 {REG_PCS_STATE_MACHINE},
4449 {REG_MAC_COLL_EXCESS},
4450 {REG_MAC_COLL_LATE}
4451 };
4452 #define CAS_REG_LEN (sizeof(ethtool_register_table)/sizeof(int))
4453 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4454
4455 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4456 {
4457 u8 *p;
4458 int i;
4459 unsigned long flags;
4460
4461 spin_lock_irqsave(&cp->lock, flags);
4462 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4463 u16 hval;
4464 u32 val;
4465 if (ethtool_register_table[i].offsets < 0) {
4466 hval = cas_phy_read(cp,
4467 -ethtool_register_table[i].offsets);
4468 val = hval;
4469 } else {
4470 val= readl(cp->regs+ethtool_register_table[i].offsets);
4471 }
4472 memcpy(p, (u8 *)&val, sizeof(u32));
4473 }
4474 spin_unlock_irqrestore(&cp->lock, flags);
4475 }
4476
4477 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4478 {
4479 struct cas *cp = netdev_priv(dev);
4480 struct net_device_stats *stats = cp->net_stats;
4481 unsigned long flags;
4482 int i;
4483 unsigned long tmp;
4484
4485 /* we collate all of the stats into net_stats[N_TX_RING] */
4486 if (!cp->hw_running)
4487 return stats + N_TX_RINGS;
4488
4489 /* collect outstanding stats */
4490 /* WTZ: the Cassini spec gives these as 16 bit counters but
4491 * stored in 32-bit words. Added a mask of 0xffff to be safe,
4492 * in case the chip somehow puts any garbage in the other bits.
4493 * Also, counter usage didn't seem to mach what Adrian did
4494 * in the parts of the code that set these quantities. Made
4495 * that consistent.
4496 */
4497 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4498 stats[N_TX_RINGS].rx_crc_errors +=
4499 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4500 stats[N_TX_RINGS].rx_frame_errors +=
4501 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4502 stats[N_TX_RINGS].rx_length_errors +=
4503 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4504 #if 1
4505 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4506 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4507 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4508 stats[N_TX_RINGS].collisions +=
4509 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4510 #else
4511 stats[N_TX_RINGS].tx_aborted_errors +=
4512 readl(cp->regs + REG_MAC_COLL_EXCESS);
4513 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4514 readl(cp->regs + REG_MAC_COLL_LATE);
4515 #endif
4516 cas_clear_mac_err(cp);
4517
4518 /* saved bits that are unique to ring 0 */
4519 spin_lock(&cp->stat_lock[0]);
4520 stats[N_TX_RINGS].collisions += stats[0].collisions;
4521 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4522 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4523 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4524 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4525 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4526 spin_unlock(&cp->stat_lock[0]);
4527
4528 for (i = 0; i < N_TX_RINGS; i++) {
4529 spin_lock(&cp->stat_lock[i]);
4530 stats[N_TX_RINGS].rx_length_errors +=
4531 stats[i].rx_length_errors;
4532 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4533 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4534 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4535 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4536 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4537 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4538 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4539 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4540 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4541 memset(stats + i, 0, sizeof(struct net_device_stats));
4542 spin_unlock(&cp->stat_lock[i]);
4543 }
4544 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4545 return stats + N_TX_RINGS;
4546 }
4547
4548
4549 static void cas_set_multicast(struct net_device *dev)
4550 {
4551 struct cas *cp = netdev_priv(dev);
4552 u32 rxcfg, rxcfg_new;
4553 unsigned long flags;
4554 int limit = STOP_TRIES;
4555
4556 if (!cp->hw_running)
4557 return;
4558
4559 spin_lock_irqsave(&cp->lock, flags);
4560 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4561
4562 /* disable RX MAC and wait for completion */
4563 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4564 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4565 if (!limit--)
4566 break;
4567 udelay(10);
4568 }
4569
4570 /* disable hash filter and wait for completion */
4571 limit = STOP_TRIES;
4572 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4573 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4574 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4575 if (!limit--)
4576 break;
4577 udelay(10);
4578 }
4579
4580 /* program hash filters */
4581 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4582 rxcfg |= rxcfg_new;
4583 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4584 spin_unlock_irqrestore(&cp->lock, flags);
4585 }
4586
4587 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4588 {
4589 struct cas *cp = netdev_priv(dev);
4590 strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4591 strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4592 info->fw_version[0] = '\0';
4593 strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4594 info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4595 cp->casreg_len : CAS_MAX_REGS;
4596 info->n_stats = CAS_NUM_STAT_KEYS;
4597 }
4598
4599 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4600 {
4601 struct cas *cp = netdev_priv(dev);
4602 u16 bmcr;
4603 int full_duplex, speed, pause;
4604 unsigned long flags;
4605 enum link_state linkstate = link_up;
4606
4607 cmd->advertising = 0;
4608 cmd->supported = SUPPORTED_Autoneg;
4609 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4610 cmd->supported |= SUPPORTED_1000baseT_Full;
4611 cmd->advertising |= ADVERTISED_1000baseT_Full;
4612 }
4613
4614 /* Record PHY settings if HW is on. */
4615 spin_lock_irqsave(&cp->lock, flags);
4616 bmcr = 0;
4617 linkstate = cp->lstate;
4618 if (CAS_PHY_MII(cp->phy_type)) {
4619 cmd->port = PORT_MII;
4620 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4621 XCVR_INTERNAL : XCVR_EXTERNAL;
4622 cmd->phy_address = cp->phy_addr;
4623 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4624 ADVERTISED_10baseT_Half |
4625 ADVERTISED_10baseT_Full |
4626 ADVERTISED_100baseT_Half |
4627 ADVERTISED_100baseT_Full;
4628
4629 cmd->supported |=
4630 (SUPPORTED_10baseT_Half |
4631 SUPPORTED_10baseT_Full |
4632 SUPPORTED_100baseT_Half |
4633 SUPPORTED_100baseT_Full |
4634 SUPPORTED_TP | SUPPORTED_MII);
4635
4636 if (cp->hw_running) {
4637 cas_mif_poll(cp, 0);
4638 bmcr = cas_phy_read(cp, MII_BMCR);
4639 cas_read_mii_link_mode(cp, &full_duplex,
4640 &speed, &pause);
4641 cas_mif_poll(cp, 1);
4642 }
4643
4644 } else {
4645 cmd->port = PORT_FIBRE;
4646 cmd->transceiver = XCVR_INTERNAL;
4647 cmd->phy_address = 0;
4648 cmd->supported |= SUPPORTED_FIBRE;
4649 cmd->advertising |= ADVERTISED_FIBRE;
4650
4651 if (cp->hw_running) {
4652 /* pcs uses the same bits as mii */
4653 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4654 cas_read_pcs_link_mode(cp, &full_duplex,
4655 &speed, &pause);
4656 }
4657 }
4658 spin_unlock_irqrestore(&cp->lock, flags);
4659
4660 if (bmcr & BMCR_ANENABLE) {
4661 cmd->advertising |= ADVERTISED_Autoneg;
4662 cmd->autoneg = AUTONEG_ENABLE;
4663 cmd->speed = ((speed == 10) ?
4664 SPEED_10 :
4665 ((speed == 1000) ?
4666 SPEED_1000 : SPEED_100));
4667 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4668 } else {
4669 cmd->autoneg = AUTONEG_DISABLE;
4670 cmd->speed =
4671 (bmcr & CAS_BMCR_SPEED1000) ?
4672 SPEED_1000 :
4673 ((bmcr & BMCR_SPEED100) ? SPEED_100:
4674 SPEED_10);
4675 cmd->duplex =
4676 (bmcr & BMCR_FULLDPLX) ?
4677 DUPLEX_FULL : DUPLEX_HALF;
4678 }
4679 if (linkstate != link_up) {
4680 /* Force these to "unknown" if the link is not up and
4681 * autonogotiation in enabled. We can set the link
4682 * speed to 0, but not cmd->duplex,
4683 * because its legal values are 0 and 1. Ethtool will
4684 * print the value reported in parentheses after the
4685 * word "Unknown" for unrecognized values.
4686 *
4687 * If in forced mode, we report the speed and duplex
4688 * settings that we configured.
4689 */
4690 if (cp->link_cntl & BMCR_ANENABLE) {
4691 cmd->speed = 0;
4692 cmd->duplex = 0xff;
4693 } else {
4694 cmd->speed = SPEED_10;
4695 if (cp->link_cntl & BMCR_SPEED100) {
4696 cmd->speed = SPEED_100;
4697 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4698 cmd->speed = SPEED_1000;
4699 }
4700 cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4701 DUPLEX_FULL : DUPLEX_HALF;
4702 }
4703 }
4704 return 0;
4705 }
4706
4707 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4708 {
4709 struct cas *cp = netdev_priv(dev);
4710 unsigned long flags;
4711
4712 /* Verify the settings we care about. */
4713 if (cmd->autoneg != AUTONEG_ENABLE &&
4714 cmd->autoneg != AUTONEG_DISABLE)
4715 return -EINVAL;
4716
4717 if (cmd->autoneg == AUTONEG_DISABLE &&
4718 ((cmd->speed != SPEED_1000 &&
4719 cmd->speed != SPEED_100 &&
4720 cmd->speed != SPEED_10) ||
4721 (cmd->duplex != DUPLEX_HALF &&
4722 cmd->duplex != DUPLEX_FULL)))
4723 return -EINVAL;
4724
4725 /* Apply settings and restart link process. */
4726 spin_lock_irqsave(&cp->lock, flags);
4727 cas_begin_auto_negotiation(cp, cmd);
4728 spin_unlock_irqrestore(&cp->lock, flags);
4729 return 0;
4730 }
4731
4732 static int cas_nway_reset(struct net_device *dev)
4733 {
4734 struct cas *cp = netdev_priv(dev);
4735 unsigned long flags;
4736
4737 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4738 return -EINVAL;
4739
4740 /* Restart link process. */
4741 spin_lock_irqsave(&cp->lock, flags);
4742 cas_begin_auto_negotiation(cp, NULL);
4743 spin_unlock_irqrestore(&cp->lock, flags);
4744
4745 return 0;
4746 }
4747
4748 static u32 cas_get_link(struct net_device *dev)
4749 {
4750 struct cas *cp = netdev_priv(dev);
4751 return cp->lstate == link_up;
4752 }
4753
4754 static u32 cas_get_msglevel(struct net_device *dev)
4755 {
4756 struct cas *cp = netdev_priv(dev);
4757 return cp->msg_enable;
4758 }
4759
4760 static void cas_set_msglevel(struct net_device *dev, u32 value)
4761 {
4762 struct cas *cp = netdev_priv(dev);
4763 cp->msg_enable = value;
4764 }
4765
4766 static int cas_get_regs_len(struct net_device *dev)
4767 {
4768 struct cas *cp = netdev_priv(dev);
4769 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4770 }
4771
4772 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4773 void *p)
4774 {
4775 struct cas *cp = netdev_priv(dev);
4776 regs->version = 0;
4777 /* cas_read_regs handles locks (cp->lock). */
4778 cas_read_regs(cp, p, regs->len / sizeof(u32));
4779 }
4780
4781 static int cas_get_stats_count(struct net_device *dev)
4782 {
4783 return CAS_NUM_STAT_KEYS;
4784 }
4785
4786 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4787 {
4788 memcpy(data, &ethtool_cassini_statnames,
4789 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4790 }
4791
4792 static void cas_get_ethtool_stats(struct net_device *dev,
4793 struct ethtool_stats *estats, u64 *data)
4794 {
4795 struct cas *cp = netdev_priv(dev);
4796 struct net_device_stats *stats = cas_get_stats(cp->dev);
4797 int i = 0;
4798 data[i++] = stats->collisions;
4799 data[i++] = stats->rx_bytes;
4800 data[i++] = stats->rx_crc_errors;
4801 data[i++] = stats->rx_dropped;
4802 data[i++] = stats->rx_errors;
4803 data[i++] = stats->rx_fifo_errors;
4804 data[i++] = stats->rx_frame_errors;
4805 data[i++] = stats->rx_length_errors;
4806 data[i++] = stats->rx_over_errors;
4807 data[i++] = stats->rx_packets;
4808 data[i++] = stats->tx_aborted_errors;
4809 data[i++] = stats->tx_bytes;
4810 data[i++] = stats->tx_dropped;
4811 data[i++] = stats->tx_errors;
4812 data[i++] = stats->tx_fifo_errors;
4813 data[i++] = stats->tx_packets;
4814 BUG_ON(i != CAS_NUM_STAT_KEYS);
4815 }
4816
4817 static struct ethtool_ops cas_ethtool_ops = {
4818 .get_drvinfo = cas_get_drvinfo,
4819 .get_settings = cas_get_settings,
4820 .set_settings = cas_set_settings,
4821 .nway_reset = cas_nway_reset,
4822 .get_link = cas_get_link,
4823 .get_msglevel = cas_get_msglevel,
4824 .set_msglevel = cas_set_msglevel,
4825 .get_regs_len = cas_get_regs_len,
4826 .get_regs = cas_get_regs,
4827 .get_stats_count = cas_get_stats_count,
4828 .get_strings = cas_get_strings,
4829 .get_ethtool_stats = cas_get_ethtool_stats,
4830 };
4831
4832 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4833 {
4834 struct cas *cp = netdev_priv(dev);
4835 struct mii_ioctl_data *data = if_mii(ifr);
4836 unsigned long flags;
4837 int rc = -EOPNOTSUPP;
4838
4839 /* Hold the PM mutex while doing ioctl's or we may collide
4840 * with open/close and power management and oops.
4841 */
4842 mutex_lock(&cp->pm_mutex);
4843 switch (cmd) {
4844 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
4845 data->phy_id = cp->phy_addr;
4846 /* Fallthrough... */
4847
4848 case SIOCGMIIREG: /* Read MII PHY register. */
4849 spin_lock_irqsave(&cp->lock, flags);
4850 cas_mif_poll(cp, 0);
4851 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4852 cas_mif_poll(cp, 1);
4853 spin_unlock_irqrestore(&cp->lock, flags);
4854 rc = 0;
4855 break;
4856
4857 case SIOCSMIIREG: /* Write MII PHY register. */
4858 if (!capable(CAP_NET_ADMIN)) {
4859 rc = -EPERM;
4860 break;
4861 }
4862 spin_lock_irqsave(&cp->lock, flags);
4863 cas_mif_poll(cp, 0);
4864 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4865 cas_mif_poll(cp, 1);
4866 spin_unlock_irqrestore(&cp->lock, flags);
4867 break;
4868 default:
4869 break;
4870 };
4871
4872 mutex_unlock(&cp->pm_mutex);
4873 return rc;
4874 }
4875
4876 static int __devinit cas_init_one(struct pci_dev *pdev,
4877 const struct pci_device_id *ent)
4878 {
4879 static int cas_version_printed = 0;
4880 unsigned long casreg_base, casreg_len;
4881 struct net_device *dev;
4882 struct cas *cp;
4883 int i, err, pci_using_dac;
4884 u16 pci_cmd;
4885 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4886
4887 if (cas_version_printed++ == 0)
4888 printk(KERN_INFO "%s", version);
4889
4890 err = pci_enable_device(pdev);
4891 if (err) {
4892 printk(KERN_ERR PFX "Cannot enable PCI device, "
4893 "aborting.\n");
4894 return err;
4895 }
4896
4897 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4898 printk(KERN_ERR PFX "Cannot find proper PCI device "
4899 "base address, aborting.\n");
4900 err = -ENODEV;
4901 goto err_out_disable_pdev;
4902 }
4903
4904 dev = alloc_etherdev(sizeof(*cp));
4905 if (!dev) {
4906 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
4907 err = -ENOMEM;
4908 goto err_out_disable_pdev;
4909 }
4910 SET_MODULE_OWNER(dev);
4911 SET_NETDEV_DEV(dev, &pdev->dev);
4912
4913 err = pci_request_regions(pdev, dev->name);
4914 if (err) {
4915 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
4916 "aborting.\n");
4917 goto err_out_free_netdev;
4918 }
4919 pci_set_master(pdev);
4920
4921 /* we must always turn on parity response or else parity
4922 * doesn't get generated properly. disable SERR/PERR as well.
4923 * in addition, we want to turn MWI on.
4924 */
4925 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4926 pci_cmd &= ~PCI_COMMAND_SERR;
4927 pci_cmd |= PCI_COMMAND_PARITY;
4928 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4929 pci_set_mwi(pdev);
4930 /*
4931 * On some architectures, the default cache line size set
4932 * by pci_set_mwi reduces perforamnce. We have to increase
4933 * it for this case. To start, we'll print some configuration
4934 * data.
4935 */
4936 #if 1
4937 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4938 &orig_cacheline_size);
4939 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4940 cas_cacheline_size =
4941 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4942 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4943 if (pci_write_config_byte(pdev,
4944 PCI_CACHE_LINE_SIZE,
4945 cas_cacheline_size)) {
4946 printk(KERN_ERR PFX "Could not set PCI cache "
4947 "line size\n");
4948 goto err_write_cacheline;
4949 }
4950 }
4951 #endif
4952
4953
4954 /* Configure DMA attributes. */
4955 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
4956 pci_using_dac = 1;
4957 err = pci_set_consistent_dma_mask(pdev,
4958 DMA_64BIT_MASK);
4959 if (err < 0) {
4960 printk(KERN_ERR PFX "Unable to obtain 64-bit DMA "
4961 "for consistent allocations\n");
4962 goto err_out_free_res;
4963 }
4964
4965 } else {
4966 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4967 if (err) {
4968 printk(KERN_ERR PFX "No usable DMA configuration, "
4969 "aborting.\n");
4970 goto err_out_free_res;
4971 }
4972 pci_using_dac = 0;
4973 }
4974
4975 casreg_base = pci_resource_start(pdev, 0);
4976 casreg_len = pci_resource_len(pdev, 0);
4977
4978 cp = netdev_priv(dev);
4979 cp->pdev = pdev;
4980 #if 1
4981 /* A value of 0 indicates we never explicitly set it */
4982 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
4983 #endif
4984 cp->dev = dev;
4985 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
4986 cassini_debug;
4987
4988 cp->link_transition = LINK_TRANSITION_UNKNOWN;
4989 cp->link_transition_jiffies_valid = 0;
4990
4991 spin_lock_init(&cp->lock);
4992 spin_lock_init(&cp->rx_inuse_lock);
4993 spin_lock_init(&cp->rx_spare_lock);
4994 for (i = 0; i < N_TX_RINGS; i++) {
4995 spin_lock_init(&cp->stat_lock[i]);
4996 spin_lock_init(&cp->tx_lock[i]);
4997 }
4998 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
4999 mutex_init(&cp->pm_mutex);
5000
5001 init_timer(&cp->link_timer);
5002 cp->link_timer.function = cas_link_timer;
5003 cp->link_timer.data = (unsigned long) cp;
5004
5005 #if 1
5006 /* Just in case the implementation of atomic operations
5007 * change so that an explicit initialization is necessary.
5008 */
5009 atomic_set(&cp->reset_task_pending, 0);
5010 atomic_set(&cp->reset_task_pending_all, 0);
5011 atomic_set(&cp->reset_task_pending_spare, 0);
5012 atomic_set(&cp->reset_task_pending_mtu, 0);
5013 #endif
5014 INIT_WORK(&cp->reset_task, cas_reset_task, cp);
5015
5016 /* Default link parameters */
5017 if (link_mode >= 0 && link_mode <= 6)
5018 cp->link_cntl = link_modes[link_mode];
5019 else
5020 cp->link_cntl = BMCR_ANENABLE;
5021 cp->lstate = link_down;
5022 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5023 netif_carrier_off(cp->dev);
5024 cp->timer_ticks = 0;
5025
5026 /* give us access to cassini registers */
5027 cp->regs = ioremap(casreg_base, casreg_len);
5028 if (cp->regs == 0UL) {
5029 printk(KERN_ERR PFX "Cannot map device registers, "
5030 "aborting.\n");
5031 goto err_out_free_res;
5032 }
5033 cp->casreg_len = casreg_len;
5034
5035 pci_save_state(pdev);
5036 cas_check_pci_invariants(cp);
5037 cas_hard_reset(cp);
5038 cas_reset(cp, 0);
5039 if (cas_check_invariants(cp))
5040 goto err_out_iounmap;
5041
5042 cp->init_block = (struct cas_init_block *)
5043 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5044 &cp->block_dvma);
5045 if (!cp->init_block) {
5046 printk(KERN_ERR PFX "Cannot allocate init block, "
5047 "aborting.\n");
5048 goto err_out_iounmap;
5049 }
5050
5051 for (i = 0; i < N_TX_RINGS; i++)
5052 cp->init_txds[i] = cp->init_block->txds[i];
5053
5054 for (i = 0; i < N_RX_DESC_RINGS; i++)
5055 cp->init_rxds[i] = cp->init_block->rxds[i];
5056
5057 for (i = 0; i < N_RX_COMP_RINGS; i++)
5058 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5059
5060 for (i = 0; i < N_RX_FLOWS; i++)
5061 skb_queue_head_init(&cp->rx_flows[i]);
5062
5063 dev->open = cas_open;
5064 dev->stop = cas_close;
5065 dev->hard_start_xmit = cas_start_xmit;
5066 dev->get_stats = cas_get_stats;
5067 dev->set_multicast_list = cas_set_multicast;
5068 dev->do_ioctl = cas_ioctl;
5069 dev->ethtool_ops = &cas_ethtool_ops;
5070 dev->tx_timeout = cas_tx_timeout;
5071 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5072 dev->change_mtu = cas_change_mtu;
5073 #ifdef USE_NAPI
5074 dev->poll = cas_poll;
5075 dev->weight = 64;
5076 #endif
5077 #ifdef CONFIG_NET_POLL_CONTROLLER
5078 dev->poll_controller = cas_netpoll;
5079 #endif
5080 dev->irq = pdev->irq;
5081 dev->dma = 0;
5082
5083 /* Cassini features. */
5084 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5085 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5086
5087 if (pci_using_dac)
5088 dev->features |= NETIF_F_HIGHDMA;
5089
5090 if (register_netdev(dev)) {
5091 printk(KERN_ERR PFX "Cannot register net device, "
5092 "aborting.\n");
5093 goto err_out_free_consistent;
5094 }
5095
5096 i = readl(cp->regs + REG_BIM_CFG);
5097 printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
5098 "Ethernet[%d] ", dev->name,
5099 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5100 (i & BIM_CFG_32BIT) ? "32" : "64",
5101 (i & BIM_CFG_66MHZ) ? "66" : "33",
5102 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq);
5103
5104 for (i = 0; i < 6; i++)
5105 printk("%2.2x%c", dev->dev_addr[i],
5106 i == 5 ? ' ' : ':');
5107 printk("\n");
5108
5109 pci_set_drvdata(pdev, dev);
5110 cp->hw_running = 1;
5111 cas_entropy_reset(cp);
5112 cas_phy_init(cp);
5113 cas_begin_auto_negotiation(cp, NULL);
5114 return 0;
5115
5116 err_out_free_consistent:
5117 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5118 cp->init_block, cp->block_dvma);
5119
5120 err_out_iounmap:
5121 mutex_lock(&cp->pm_mutex);
5122 if (cp->hw_running)
5123 cas_shutdown(cp);
5124 mutex_unlock(&cp->pm_mutex);
5125
5126 iounmap(cp->regs);
5127
5128
5129 err_out_free_res:
5130 pci_release_regions(pdev);
5131
5132 err_write_cacheline:
5133 /* Try to restore it in case the error occured after we
5134 * set it.
5135 */
5136 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5137
5138 err_out_free_netdev:
5139 free_netdev(dev);
5140
5141 err_out_disable_pdev:
5142 pci_disable_device(pdev);
5143 pci_set_drvdata(pdev, NULL);
5144 return -ENODEV;
5145 }
5146
5147 static void __devexit cas_remove_one(struct pci_dev *pdev)
5148 {
5149 struct net_device *dev = pci_get_drvdata(pdev);
5150 struct cas *cp;
5151 if (!dev)
5152 return;
5153
5154 cp = netdev_priv(dev);
5155 unregister_netdev(dev);
5156
5157 mutex_lock(&cp->pm_mutex);
5158 flush_scheduled_work();
5159 if (cp->hw_running)
5160 cas_shutdown(cp);
5161 mutex_unlock(&cp->pm_mutex);
5162
5163 #if 1
5164 if (cp->orig_cacheline_size) {
5165 /* Restore the cache line size if we had modified
5166 * it.
5167 */
5168 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5169 cp->orig_cacheline_size);
5170 }
5171 #endif
5172 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5173 cp->init_block, cp->block_dvma);
5174 iounmap(cp->regs);
5175 free_netdev(dev);
5176 pci_release_regions(pdev);
5177 pci_disable_device(pdev);
5178 pci_set_drvdata(pdev, NULL);
5179 }
5180
5181 #ifdef CONFIG_PM
5182 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5183 {
5184 struct net_device *dev = pci_get_drvdata(pdev);
5185 struct cas *cp = netdev_priv(dev);
5186 unsigned long flags;
5187
5188 mutex_lock(&cp->pm_mutex);
5189
5190 /* If the driver is opened, we stop the DMA */
5191 if (cp->opened) {
5192 netif_device_detach(dev);
5193
5194 cas_lock_all_save(cp, flags);
5195
5196 /* We can set the second arg of cas_reset to 0
5197 * because on resume, we'll call cas_init_hw with
5198 * its second arg set so that autonegotiation is
5199 * restarted.
5200 */
5201 cas_reset(cp, 0);
5202 cas_clean_rings(cp);
5203 cas_unlock_all_restore(cp, flags);
5204 }
5205
5206 if (cp->hw_running)
5207 cas_shutdown(cp);
5208 mutex_unlock(&cp->pm_mutex);
5209
5210 return 0;
5211 }
5212
5213 static int cas_resume(struct pci_dev *pdev)
5214 {
5215 struct net_device *dev = pci_get_drvdata(pdev);
5216 struct cas *cp = netdev_priv(dev);
5217
5218 printk(KERN_INFO "%s: resuming\n", dev->name);
5219
5220 mutex_lock(&cp->pm_mutex);
5221 cas_hard_reset(cp);
5222 if (cp->opened) {
5223 unsigned long flags;
5224 cas_lock_all_save(cp, flags);
5225 cas_reset(cp, 0);
5226 cp->hw_running = 1;
5227 cas_clean_rings(cp);
5228 cas_init_hw(cp, 1);
5229 cas_unlock_all_restore(cp, flags);
5230
5231 netif_device_attach(dev);
5232 }
5233 mutex_unlock(&cp->pm_mutex);
5234 return 0;
5235 }
5236 #endif /* CONFIG_PM */
5237
5238 static struct pci_driver cas_driver = {
5239 .name = DRV_MODULE_NAME,
5240 .id_table = cas_pci_tbl,
5241 .probe = cas_init_one,
5242 .remove = __devexit_p(cas_remove_one),
5243 #ifdef CONFIG_PM
5244 .suspend = cas_suspend,
5245 .resume = cas_resume
5246 #endif
5247 };
5248
5249 static int __init cas_init(void)
5250 {
5251 if (linkdown_timeout > 0)
5252 link_transition_timeout = linkdown_timeout * HZ;
5253 else
5254 link_transition_timeout = 0;
5255
5256 return pci_module_init(&cas_driver);
5257 }
5258
5259 static void __exit cas_cleanup(void)
5260 {
5261 pci_unregister_driver(&cas_driver);
5262 }
5263
5264 module_init(cas_init);
5265 module_exit(cas_cleanup);
Linux with added FPC-III support