drivers/net/cs89x0.h

   1 /*  Copyright, 1988-1992, Russell Nelson, Crynwr Software
   2
   3    This program is free software; you can redistribute it and/or modify
   4    it under the terms of the GNU General Public License as published by
   5    the Free Software Foundation, version 1.
   6
   7    This program is distributed in the hope that it will be useful,
   8    but WITHOUT ANY WARRANTY; without even the implied warranty of
   9    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10    GNU General Public License for more details.
  11
  12    You should have received a copy of the GNU General Public License
  13    along with this program; if not, write to the Free Software
  14    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15    */
  16
  17 #include <linux/config.h>
  18
  19 #define PP_ChipID 0x0000        /* offset   0h -> Corp -ID              */
  20                                 /* offset   2h -> Model/Product Number  */
  21                                 /* offset   3h -> Chip Revision Number  */
  22
  23 #define PP_ISAIOB 0x0020        /*  IO base address */
  24 #define PP_CS8900_ISAINT 0x0022 /*  ISA interrupt select */
  25 #define PP_CS8920_ISAINT 0x0370 /*  ISA interrupt select */
  26 #define PP_CS8900_ISADMA 0x0024 /*  ISA Rec DMA channel */
  27 #define PP_CS8920_ISADMA 0x0374 /*  ISA Rec DMA channel */
  28 #define PP_ISASOF 0x0026        /*  ISA DMA offset */
  29 #define PP_DmaFrameCnt 0x0028   /*  ISA DMA Frame count */
  30 #define PP_DmaByteCnt 0x002A    /*  ISA DMA Byte count */
  31 #define PP_CS8900_ISAMemB 0x002C        /*  Memory base */
  32 #define PP_CS8920_ISAMemB 0x0348 /*  */
  33
  34 #define PP_ISABootBase 0x0030   /*  Boot Prom base  */
  35 #define PP_ISABootMask 0x0034   /*  Boot Prom Mask */
  36
  37 /* EEPROM data and command registers */
  38 #define PP_EECMD 0x0040         /*  NVR Interface Command register */
  39 #define PP_EEData 0x0042        /*  NVR Interface Data Register */
  40 #define PP_DebugReg 0x0044      /*  Debug Register */
  41
  42 #define PP_RxCFG 0x0102         /*  Rx Bus config */
  43 #define PP_RxCTL 0x0104         /*  Receive Control Register */
  44 #define PP_TxCFG 0x0106         /*  Transmit Config Register */
  45 #define PP_TxCMD 0x0108         /*  Transmit Command Register */
  46 #define PP_BufCFG 0x010A        /*  Bus configuration Register */
  47 #define PP_LineCTL 0x0112       /*  Line Config Register */
  48 #define PP_SelfCTL 0x0114       /*  Self Command Register */
  49 #define PP_BusCTL 0x0116        /*  ISA bus control Register */
  50 #define PP_TestCTL 0x0118       /*  Test Register */
  51 #define PP_AutoNegCTL 0x011C    /*  Auto Negotiation Ctrl */
  52
  53 #define PP_ISQ 0x0120           /*  Interrupt Status */
  54 #define PP_RxEvent 0x0124       /*  Rx Event Register */
  55 #define PP_TxEvent 0x0128       /*  Tx Event Register */
  56 #define PP_BufEvent 0x012C      /*  Bus Event Register */
  57 #define PP_RxMiss 0x0130        /*  Receive Miss Count */
  58 #define PP_TxCol 0x0132         /*  Transmit Collision Count */
  59 #define PP_LineST 0x0134        /*  Line State Register */
  60 #define PP_SelfST 0x0136        /*  Self State register */
  61 #define PP_BusST 0x0138         /*  Bus Status */
  62 #define PP_TDR 0x013C           /*  Time Domain Reflectometry */
  63 #define PP_AutoNegST 0x013E     /*  Auto Neg Status */
  64 #define PP_TxCommand 0x0144     /*  Tx Command */
  65 #define PP_TxLength 0x0146      /*  Tx Length */
  66 #define PP_LAF 0x0150           /*  Hash Table */
  67 #define PP_IA 0x0158            /*  Physical Address Register */
  68
  69 #define PP_RxStatus 0x0400      /*  Receive start of frame */
  70 #define PP_RxLength 0x0402      /*  Receive Length of frame */
  71 #define PP_RxFrame 0x0404       /*  Receive frame pointer */
  72 #define PP_TxFrame 0x0A00       /*  Transmit frame pointer */
  73
  74 /*  Primary I/O Base Address. If no I/O base is supplied by the user, then this */
  75 /*  can be used as the default I/O base to access the PacketPage Area. */
  76 #define DEFAULTIOBASE 0x0300
  77 #define FIRST_IO 0x020C         /*  First I/O port to check */
  78 #define LAST_IO 0x037C          /*  Last I/O port to check (+10h) */
  79 #define ADD_MASK 0x3000         /*  Mask it use of the ADD_PORT register */
  80 #define ADD_SIG 0x3000          /*  Expected ID signature */
  81
  82 /* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */
  83 #ifdef CONFIG_MAC
  84 #define LCSLOTBASE 0xfee00000
  85 #define MMIOBASE 0x40000
  86 #endif
  87
  88 #define CHIP_EISA_ID_SIG 0x630E   /*  Product ID Code for Crystal Chip (CS8900 spec 4.3) */
  89 #define CHIP_EISA_ID_SIG_STR "0x630E"
  90
  91 #ifdef IBMEIPKT
  92 #define EISA_ID_SIG 0x4D24      /*  IBM */
  93 #define PART_NO_SIG 0x1010      /*  IBM */
  94 #define MONGOOSE_BIT 0x0000     /*  IBM */
  95 #else
  96 #define EISA_ID_SIG 0x630E      /*  PnP Vendor ID (same as chip id for Crystal board) */
  97 #define PART_NO_SIG 0x4000      /*  ID code CS8920 board (PnP Vendor Product code) */
  98 #define MONGOOSE_BIT 0x2000     /*  PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
  99 #endif
 100
 101 #define PRODUCT_ID_ADD 0x0002   /*  Address of product ID */
 102
 103 /*  Mask to find out the types of  registers */
 104 #define REG_TYPE_MASK 0x001F
 105
 106 /*  Eeprom Commands */
 107 #define ERSE_WR_ENBL 0x00F0
 108 #define ERSE_WR_DISABLE 0x0000
 109
 110 /*  Defines Control/Config register quintuplet numbers */
 111 #define RX_BUF_CFG 0x0003
 112 #define RX_CONTROL 0x0005
 113 #define TX_CFG 0x0007
 114 #define TX_COMMAND 0x0009
 115 #define BUF_CFG 0x000B
 116 #define LINE_CONTROL 0x0013
 117 #define SELF_CONTROL 0x0015
 118 #define BUS_CONTROL 0x0017
 119 #define TEST_CONTROL 0x0019
 120
 121 /*  Defines Status/Count registers quintuplet numbers */
 122 #define RX_EVENT 0x0004
 123 #define TX_EVENT 0x0008
 124 #define BUF_EVENT 0x000C
 125 #define RX_MISS_COUNT 0x0010
 126 #define TX_COL_COUNT 0x0012
 127 #define LINE_STATUS 0x0014
 128 #define SELF_STATUS 0x0016
 129 #define BUS_STATUS 0x0018
 130 #define TDR 0x001C
 131
 132 /* PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition -  Read/write */
 133 #define SKIP_1 0x0040
 134 #define RX_STREAM_ENBL 0x0080
 135 #define RX_OK_ENBL 0x0100
 136 #define RX_DMA_ONLY 0x0200
 137 #define AUTO_RX_DMA 0x0400
 138 #define BUFFER_CRC 0x0800
 139 #define RX_CRC_ERROR_ENBL 0x1000
 140 #define RX_RUNT_ENBL 0x2000
 141 #define RX_EXTRA_DATA_ENBL 0x4000
 142
 143 /* PP_RxCTL - Receive Control bit definition - Read/write */
 144 #define RX_IA_HASH_ACCEPT 0x0040
 145 #define RX_PROM_ACCEPT 0x0080
 146 #define RX_OK_ACCEPT 0x0100
 147 #define RX_MULTCAST_ACCEPT 0x0200
 148 #define RX_IA_ACCEPT 0x0400
 149 #define RX_BROADCAST_ACCEPT 0x0800
 150 #define RX_BAD_CRC_ACCEPT 0x1000
 151 #define RX_RUNT_ACCEPT 0x2000
 152 #define RX_EXTRA_DATA_ACCEPT 0x4000
 153 #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
 154 /*  Default receive mode - individually addressed, broadcast, and error free */
 155 #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
 156
 157 /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
 158 #define TX_LOST_CRS_ENBL 0x0040
 159 #define TX_SQE_ERROR_ENBL 0x0080
 160 #define TX_OK_ENBL 0x0100
 161 #define TX_LATE_COL_ENBL 0x0200
 162 #define TX_JBR_ENBL 0x0400
 163 #define TX_ANY_COL_ENBL 0x0800
 164 #define TX_16_COL_ENBL 0x8000
 165
 166 /* PP_TxCMD - Transmit Command bit definition - Read-only */
 167 #define TX_START_4_BYTES 0x0000
 168 #define TX_START_64_BYTES 0x0040
 169 #define TX_START_128_BYTES 0x0080
 170 #define TX_START_ALL_BYTES 0x00C0
 171 #define TX_FORCE 0x0100
 172 #define TX_ONE_COL 0x0200
 173 #define TX_TWO_PART_DEFF_DISABLE 0x0400
 174 #define TX_NO_CRC 0x1000
 175 #define TX_RUNT 0x2000
 176
 177 /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
 178 #define GENERATE_SW_INTERRUPT 0x0040
 179 #define RX_DMA_ENBL 0x0080
 180 #define READY_FOR_TX_ENBL 0x0100
 181 #define TX_UNDERRUN_ENBL 0x0200
 182 #define RX_MISS_ENBL 0x0400
 183 #define RX_128_BYTE_ENBL 0x0800
 184 #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
 185 #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
 186 #define RX_DEST_MATCH_ENBL 0x8000
 187
 188 /* PP_LineCTL - Line Control bit definition - Read/write */
 189 #define SERIAL_RX_ON 0x0040
 190 #define SERIAL_TX_ON 0x0080
 191 #define AUI_ONLY 0x0100
 192 #define AUTO_AUI_10BASET 0x0200
 193 #define MODIFIED_BACKOFF 0x0800
 194 #define NO_AUTO_POLARITY 0x1000
 195 #define TWO_PART_DEFDIS 0x2000
 196 #define LOW_RX_SQUELCH 0x4000
 197
 198 /* PP_SelfCTL - Software Self Control bit definition - Read/write */
 199 #define POWER_ON_RESET 0x0040
 200 #define SW_STOP 0x0100
 201 #define SLEEP_ON 0x0200
 202 #define AUTO_WAKEUP 0x0400
 203 #define HCB0_ENBL 0x1000
 204 #define HCB1_ENBL 0x2000
 205 #define HCB0 0x4000
 206 #define HCB1 0x8000
 207
 208 /* PP_BusCTL - ISA Bus Control bit definition - Read/write */
 209 #define RESET_RX_DMA 0x0040
 210 #define MEMORY_ON 0x0400
 211 #define DMA_BURST_MODE 0x0800
 212 #define IO_CHANNEL_READY_ON 0x1000
 213 #define RX_DMA_SIZE_64K 0x2000
 214 #define ENABLE_IRQ 0x8000
 215
 216 /* PP_TestCTL - Test Control bit definition - Read/write */
 217 #define LINK_OFF 0x0080
 218 #define ENDEC_LOOPBACK 0x0200
 219 #define AUI_LOOPBACK 0x0400
 220 #define BACKOFF_OFF 0x0800
 221 #define FDX_8900 0x4000
 222 #define FAST_TEST 0x8000
 223
 224 /* PP_RxEvent - Receive Event Bit definition - Read-only */
 225 #define RX_IA_HASHED 0x0040
 226 #define RX_DRIBBLE 0x0080
 227 #define RX_OK 0x0100
 228 #define RX_HASHED 0x0200
 229 #define RX_IA 0x0400
 230 #define RX_BROADCAST 0x0800
 231 #define RX_CRC_ERROR 0x1000
 232 #define RX_RUNT 0x2000
 233 #define RX_EXTRA_DATA 0x4000
 234
 235 #define HASH_INDEX_MASK 0x0FC00
 236
 237 /* PP_TxEvent - Transmit Event Bit definition - Read-only */
 238 #define TX_LOST_CRS 0x0040
 239 #define TX_SQE_ERROR 0x0080
 240 #define TX_OK 0x0100
 241 #define TX_LATE_COL 0x0200
 242 #define TX_JBR 0x0400
 243 #define TX_16_COL 0x8000
 244 #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
 245 #define TX_COL_COUNT_MASK 0x7800
 246
 247 /* PP_BufEvent - Buffer Event Bit definition - Read-only */
 248 #define SW_INTERRUPT 0x0040
 249 #define RX_DMA 0x0080
 250 #define READY_FOR_TX 0x0100
 251 #define TX_UNDERRUN 0x0200
 252 #define RX_MISS 0x0400
 253 #define RX_128_BYTE 0x0800
 254 #define TX_COL_OVRFLW 0x1000
 255 #define RX_MISS_OVRFLW 0x2000
 256 #define RX_DEST_MATCH 0x8000
 257
 258 /* PP_LineST - Ethernet Line Status bit definition - Read-only */
 259 #define LINK_OK 0x0080
 260 #define AUI_ON 0x0100
 261 #define TENBASET_ON 0x0200
 262 #define POLARITY_OK 0x1000
 263 #define CRS_OK 0x4000
 264
 265 /* PP_SelfST - Chip Software Status bit definition */
 266 #define ACTIVE_33V 0x0040
 267 #define INIT_DONE 0x0080
 268 #define SI_BUSY 0x0100
 269 #define EEPROM_PRESENT 0x0200
 270 #define EEPROM_OK 0x0400
 271 #define EL_PRESENT 0x0800
 272 #define EE_SIZE_64 0x1000
 273
 274 /* PP_BusST - ISA Bus Status bit definition */
 275 #define TX_BID_ERROR 0x0080
 276 #define READY_FOR_TX_NOW 0x0100
 277
 278 /* PP_AutoNegCTL - Auto Negotiation Control bit definition */
 279 #define RE_NEG_NOW 0x0040
 280 #define ALLOW_FDX 0x0080
 281 #define AUTO_NEG_ENABLE 0x0100
 282 #define NLP_ENABLE 0x0200
 283 #define FORCE_FDX 0x8000
 284 #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
 285 #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
 286
 287 /* PP_AutoNegST - Auto Negotiation Status bit definition */
 288 #define AUTO_NEG_BUSY 0x0080
 289 #define FLP_LINK 0x0100
 290 #define FLP_LINK_GOOD 0x0800
 291 #define LINK_FAULT 0x1000
 292 #define HDX_ACTIVE 0x4000
 293 #define FDX_ACTIVE 0x8000
 294
 295 /*  The following block defines the ISQ event types */
 296 #define ISQ_RECEIVER_EVENT 0x04
 297 #define ISQ_TRANSMITTER_EVENT 0x08
 298 #define ISQ_BUFFER_EVENT 0x0c
 299 #define ISQ_RX_MISS_EVENT 0x10
 300 #define ISQ_TX_COL_EVENT 0x12
 301
 302 #define ISQ_EVENT_MASK 0x003F   /*  ISQ mask to find out type of event */
 303 #define ISQ_HIST 16             /*  small history buffer */
 304 #define AUTOINCREMENT 0x8000    /*  Bit mask to set bit-15 for autoincrement */
 305
 306 #define TXRXBUFSIZE 0x0600
 307 #define RXDMABUFSIZE 0x8000
 308 #define RXDMASIZE 0x4000
 309 #define TXRX_LENGTH_MASK 0x07FF
 310
 311 /*  rx options bits */
 312 #define RCV_WITH_RXON   1       /*  Set SerRx ON */
 313 #define RCV_COUNTS      2       /*  Use Framecnt1 */
 314 #define RCV_PONG        4       /*  Pong respondent */
 315 #define RCV_DONG        8       /*  Dong operation */
 316 #define RCV_POLLING     0x10    /*  Poll RxEvent */
 317 #define RCV_ISQ         0x20    /*  Use ISQ, int */
 318 #define RCV_AUTO_DMA    0x100   /*  Set AutoRxDMAE */
 319 #define RCV_DMA         0x200   /*  Set RxDMA only */
 320 #define RCV_DMA_ALL     0x400   /*  Copy all DMA'ed */
 321 #define RCV_FIXED_DATA  0x800   /*  Every frame same */
 322 #define RCV_IO          0x1000  /*  Use ISA IO only */
 323 #define RCV_MEMORY      0x2000  /*  Use ISA Memory */
 324
 325 #define RAM_SIZE        0x1000       /*  The card has 4k bytes or RAM */
 326 #define PKT_START PP_TxFrame  /*  Start of packet RAM */
 327
 328 #define RX_FRAME_PORT   0x0000
 329 #define TX_FRAME_PORT RX_FRAME_PORT
 330 #define TX_CMD_PORT     0x0004
 331 #define TX_NOW          0x0000       /*  Tx packet after   5 bytes copied */
 332 #define TX_AFTER_381    0x0040       /*  Tx packet after 381 bytes copied */
 333 #define TX_AFTER_ALL    0x00c0       /*  Tx packet after all bytes copied */
 334 #define TX_LEN_PORT     0x0006
 335 #define ISQ_PORT        0x0008
 336 #define ADD_PORT        0x000A
 337 #define DATA_PORT       0x000C
 338
 339 #define EEPROM_WRITE_EN         0x00F0
 340 #define EEPROM_WRITE_DIS        0x0000
 341 #define EEPROM_WRITE_CMD        0x0100
 342 #define EEPROM_READ_CMD         0x0200
 343
 344 /*  Receive Header */
 345 /*  Description of header of each packet in receive area of memory */
 346 #define RBUF_EVENT_LOW  0   /*  Low byte of RxEvent - status of received frame */
 347 #define RBUF_EVENT_HIGH 1   /*  High byte of RxEvent - status of received frame */
 348 #define RBUF_LEN_LOW    2   /*  Length of received data - low byte */
 349 #define RBUF_LEN_HI     3   /*  Length of received data - high byte */
 350 #define RBUF_HEAD_LEN   4   /*  Length of this header */
 351
 352 #define CHIP_READ 0x1   /*  Used to mark state of the repins code (chip or dma) */
 353 #define DMA_READ 0x2   /*  Used to mark state of the repins code (chip or dma) */
 354
 355 /*  for bios scan */
 356 /*  */
 357 #ifdef CSDEBUG
 358 /*  use these values for debugging bios scan */
 359 #define BIOS_START_SEG 0x00000
 360 #define BIOS_OFFSET_INC 0x0010
 361 #else
 362 #define BIOS_START_SEG 0x0c000
 363 #define BIOS_OFFSET_INC 0x0200
 364 #endif
 365
 366 #define BIOS_LAST_OFFSET 0x0fc00
 367
 368 /*  Byte offsets into the EEPROM configuration buffer */
 369 #define ISA_CNF_OFFSET 0x6
 370 #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8)                      /*  8900 eeprom */
 371 #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8)                /*  8920 eeprom */
 372
 373   /*  the assumption here is that the bits in the eeprom are generally  */
 374   /*  in the same position as those in the autonegctl register. */
 375   /*  Of course the IMM bit is not in that register so it must be  */
 376   /*  masked out */
 377 #define EE_FORCE_FDX  0x8000
 378 #define EE_NLP_ENABLE 0x0200
 379 #define EE_AUTO_NEG_ENABLE 0x0100
 380 #define EE_ALLOW_FDX 0x0080
 381 #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
 382
 383 #define IMM_BIT 0x0040          /*  ignore missing media         */
 384
 385 #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
 386 #define A_CNF_10B_T 0x0001
 387 #define A_CNF_AUI 0x0002
 388 #define A_CNF_10B_2 0x0004
 389 #define A_CNF_MEDIA_TYPE 0x0070
 390 #define A_CNF_MEDIA_AUTO 0x0070
 391 #define A_CNF_MEDIA_10B_T 0x0020
 392 #define A_CNF_MEDIA_AUI 0x0040
 393 #define A_CNF_MEDIA_10B_2 0x0010
 394 #define A_CNF_DC_DC_POLARITY 0x0080
 395 #define A_CNF_NO_AUTO_POLARITY 0x2000
 396 #define A_CNF_LOW_RX_SQUELCH 0x4000
 397 #define A_CNF_EXTND_10B_2 0x8000
 398
 399 #define PACKET_PAGE_OFFSET 0x8
 400
 401 /*  Bit definitions for the ISA configuration word from the EEPROM */
 402 #define INT_NO_MASK 0x000F
 403 #define DMA_NO_MASK 0x0070
 404 #define ISA_DMA_SIZE 0x0200
 405 #define ISA_AUTO_RxDMA 0x0400
 406 #define ISA_RxDMA 0x0800
 407 #define DMA_BURST 0x1000
 408 #define STREAM_TRANSFER 0x2000
 409 #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
 410
 411 /*  DMA controller registers */
 412 #define DMA_BASE 0x00     /*  DMA controller base */
 413 #define DMA_BASE_2 0x0C0    /*  DMA controller base */
 414
 415 #define DMA_STAT 0x0D0    /*  DMA controller status register */
 416 #define DMA_MASK 0x0D4    /*  DMA controller mask register */
 417 #define DMA_MODE 0x0D6    /*  DMA controller mode register */
 418 #define DMA_RESETFF 0x0D8    /*  DMA controller first/last flip flop */
 419
 420 /*  DMA data */
 421 #define DMA_DISABLE 0x04     /*  Disable channel n */
 422 #define DMA_ENABLE 0x00     /*  Enable channel n */
 423 /*  Demand transfers, incr. address, auto init, writes, ch. n */
 424 #define DMA_RX_MODE 0x14
 425 /*  Demand transfers, incr. address, auto init, reads, ch. n */
 426 #define DMA_TX_MODE 0x18
 427
 428 #define DMA_SIZE (16*1024) /*  Size of dma buffer - 16k */
 429
 430 #define CS8900 0x0000
 431 #define CS8920 0x4000
 432 #define CS8920M 0x6000
 433 #define REVISON_BITS 0x1F00
 434 #define EEVER_NUMBER 0x12
 435 #define CHKSUM_LEN 0x14
 436 #define CHKSUM_VAL 0x0000
 437 #define START_EEPROM_DATA 0x001c /*  Offset into eeprom for start of data */
 438 #define IRQ_MAP_EEPROM_DATA 0x0046 /*  Offset into eeprom for the IRQ map */
 439 #define IRQ_MAP_LEN 0x0004 /*  No of bytes to read for the IRQ map */
 440 #define PNP_IRQ_FRMT 0x0022 /*  PNP small item IRQ format */
 441 #ifdef CONFIG_SH_HICOSH4
 442 #define CS8900_IRQ_MAP 0x0002 /* HiCO-SH4 board has its IRQ on #1 */
 443 #else
 444 #define CS8900_IRQ_MAP 0x1c20 /*  This IRQ map is fixed */
 445 #endif
 446
 447 #define CS8920_NO_INTS 0x0F   /*  Max CS8920 interrupt select # */
 448
 449 #define PNP_ADD_PORT 0x0279
 450 #define PNP_WRITE_PORT 0x0A79
 451
 452 #define GET_PNP_ISA_STRUCT 0x40
 453 #define PNP_ISA_STRUCT_LEN 0x06
 454 #define PNP_CSN_CNT_OFF 0x01
 455 #define PNP_RD_PORT_OFF 0x02
 456 #define PNP_FUNCTION_OK 0x00
 457 #define PNP_WAKE 0x03
 458 #define PNP_RSRC_DATA 0x04
 459 #define PNP_RSRC_READY 0x01
 460 #define PNP_STATUS 0x05
 461 #define PNP_ACTIVATE 0x30
 462 #define PNP_CNF_IO_H 0x60
 463 #define PNP_CNF_IO_L 0x61
 464 #define PNP_CNF_INT 0x70
 465 #define PNP_CNF_DMA 0x74
 466 #define PNP_CNF_MEM 0x48
 467
 468 #define BIT0 1
 469 #define BIT15 0x8000
 470