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Linux 2.6.17.7
[linux/fpc-iii.git] / drivers / net / ns83820.c
blob706aed7d717f5ec5200a0287476c446cc7e8a901
1 #define VERSION "0.22"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/config.h>
100 #include <linux/module.h>
101 #include <linux/moduleparam.h>
102 #include <linux/types.h>
103 #include <linux/pci.h>
104 #include <linux/dma-mapping.h>
105 #include <linux/netdevice.h>
106 #include <linux/etherdevice.h>
107 #include <linux/delay.h>
108 #include <linux/smp_lock.h>
109 #include <linux/workqueue.h>
110 #include <linux/init.h>
111 #include <linux/ip.h> /* for iph */
112 #include <linux/in.h> /* for IPPROTO_... */
113 #include <linux/compiler.h>
114 #include <linux/prefetch.h>
115 #include <linux/ethtool.h>
116 #include <linux/timer.h>
117 #include <linux/if_vlan.h>
118 #include <linux/rtnetlink.h>
119 #include <linux/jiffies.h>
120
121 #include <asm/io.h>
122 #include <asm/uaccess.h>
123 #include <asm/system.h>
124
125 #define DRV_NAME "ns83820"
126
127 /* Global parameters. See module_param near the bottom. */
128 static int ihr = 2;
129 static int reset_phy = 0;
130 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
131
132 /* Dprintk is used for more interesting debug events */
133 #undef Dprintk
134 #define Dprintk dprintk
135
136 /* tunables */
137 #define RX_BUF_SIZE 1500 /* 8192 */
138 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
139 #define NS83820_VLAN_ACCEL_SUPPORT
140 #endif
141
142 /* Must not exceed ~65000. */
143 #define NR_RX_DESC 64
144 #define NR_TX_DESC 128
145
146 /* not tunable */
147 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
148
149 #define MIN_TX_DESC_FREE 8
150
151 /* register defines */
152 #define CFGCS 0x04
153
154 #define CR_TXE 0x00000001
155 #define CR_TXD 0x00000002
156 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
157 * The Receive engine skips one descriptor and moves
158 * onto the next one!! */
159 #define CR_RXE 0x00000004
160 #define CR_RXD 0x00000008
161 #define CR_TXR 0x00000010
162 #define CR_RXR 0x00000020
163 #define CR_SWI 0x00000080
164 #define CR_RST 0x00000100
165
166 #define PTSCR_EEBIST_FAIL 0x00000001
167 #define PTSCR_EEBIST_EN 0x00000002
168 #define PTSCR_EELOAD_EN 0x00000004
169 #define PTSCR_RBIST_FAIL 0x000001b8
170 #define PTSCR_RBIST_DONE 0x00000200
171 #define PTSCR_RBIST_EN 0x00000400
172 #define PTSCR_RBIST_RST 0x00002000
173
174 #define MEAR_EEDI 0x00000001
175 #define MEAR_EEDO 0x00000002
176 #define MEAR_EECLK 0x00000004
177 #define MEAR_EESEL 0x00000008
178 #define MEAR_MDIO 0x00000010
179 #define MEAR_MDDIR 0x00000020
180 #define MEAR_MDC 0x00000040
181
182 #define ISR_TXDESC3 0x40000000
183 #define ISR_TXDESC2 0x20000000
184 #define ISR_TXDESC1 0x10000000
185 #define ISR_TXDESC0 0x08000000
186 #define ISR_RXDESC3 0x04000000
187 #define ISR_RXDESC2 0x02000000
188 #define ISR_RXDESC1 0x01000000
189 #define ISR_RXDESC0 0x00800000
190 #define ISR_TXRCMP 0x00400000
191 #define ISR_RXRCMP 0x00200000
192 #define ISR_DPERR 0x00100000
193 #define ISR_SSERR 0x00080000
194 #define ISR_RMABT 0x00040000
195 #define ISR_RTABT 0x00020000
196 #define ISR_RXSOVR 0x00010000
197 #define ISR_HIBINT 0x00008000
198 #define ISR_PHY 0x00004000
199 #define ISR_PME 0x00002000
200 #define ISR_SWI 0x00001000
201 #define ISR_MIB 0x00000800
202 #define ISR_TXURN 0x00000400
203 #define ISR_TXIDLE 0x00000200
204 #define ISR_TXERR 0x00000100
205 #define ISR_TXDESC 0x00000080
206 #define ISR_TXOK 0x00000040
207 #define ISR_RXORN 0x00000020
208 #define ISR_RXIDLE 0x00000010
209 #define ISR_RXEARLY 0x00000008
210 #define ISR_RXERR 0x00000004
211 #define ISR_RXDESC 0x00000002
212 #define ISR_RXOK 0x00000001
213
214 #define TXCFG_CSI 0x80000000
215 #define TXCFG_HBI 0x40000000
216 #define TXCFG_MLB 0x20000000
217 #define TXCFG_ATP 0x10000000
218 #define TXCFG_ECRETRY 0x00800000
219 #define TXCFG_BRST_DIS 0x00080000
220 #define TXCFG_MXDMA1024 0x00000000
221 #define TXCFG_MXDMA512 0x00700000
222 #define TXCFG_MXDMA256 0x00600000
223 #define TXCFG_MXDMA128 0x00500000
224 #define TXCFG_MXDMA64 0x00400000
225 #define TXCFG_MXDMA32 0x00300000
226 #define TXCFG_MXDMA16 0x00200000
227 #define TXCFG_MXDMA8 0x00100000
228
229 #define CFG_LNKSTS 0x80000000
230 #define CFG_SPDSTS 0x60000000
231 #define CFG_SPDSTS1 0x40000000
232 #define CFG_SPDSTS0 0x20000000
233 #define CFG_DUPSTS 0x10000000
234 #define CFG_TBI_EN 0x01000000
235 #define CFG_MODE_1000 0x00400000
236 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
237 * Read the Phy response and then configure the MAC accordingly */
238 #define CFG_AUTO_1000 0x00200000
239 #define CFG_PINT_CTL 0x001c0000
240 #define CFG_PINT_DUPSTS 0x00100000
241 #define CFG_PINT_LNKSTS 0x00080000
242 #define CFG_PINT_SPDSTS 0x00040000
243 #define CFG_TMRTEST 0x00020000
244 #define CFG_MRM_DIS 0x00010000
245 #define CFG_MWI_DIS 0x00008000
246 #define CFG_T64ADDR 0x00004000
247 #define CFG_PCI64_DET 0x00002000
248 #define CFG_DATA64_EN 0x00001000
249 #define CFG_M64ADDR 0x00000800
250 #define CFG_PHY_RST 0x00000400
251 #define CFG_PHY_DIS 0x00000200
252 #define CFG_EXTSTS_EN 0x00000100
253 #define CFG_REQALG 0x00000080
254 #define CFG_SB 0x00000040
255 #define CFG_POW 0x00000020
256 #define CFG_EXD 0x00000010
257 #define CFG_PESEL 0x00000008
258 #define CFG_BROM_DIS 0x00000004
259 #define CFG_EXT_125 0x00000002
260 #define CFG_BEM 0x00000001
261
262 #define EXTSTS_UDPPKT 0x00200000
263 #define EXTSTS_TCPPKT 0x00080000
264 #define EXTSTS_IPPKT 0x00020000
265 #define EXTSTS_VPKT 0x00010000
266 #define EXTSTS_VTG_MASK 0x0000ffff
267
268 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
269
270 #define MIBC_MIBS 0x00000008
271 #define MIBC_ACLR 0x00000004
272 #define MIBC_FRZ 0x00000002
273 #define MIBC_WRN 0x00000001
274
275 #define PCR_PSEN (1 << 31)
276 #define PCR_PS_MCAST (1 << 30)
277 #define PCR_PS_DA (1 << 29)
278 #define PCR_STHI_8 (3 << 23)
279 #define PCR_STLO_4 (1 << 23)
280 #define PCR_FFHI_8K (3 << 21)
281 #define PCR_FFLO_4K (1 << 21)
282 #define PCR_PAUSE_CNT 0xFFFE
283
284 #define RXCFG_AEP 0x80000000
285 #define RXCFG_ARP 0x40000000
286 #define RXCFG_STRIPCRC 0x20000000
287 #define RXCFG_RX_FD 0x10000000
288 #define RXCFG_ALP 0x08000000
289 #define RXCFG_AIRL 0x04000000
290 #define RXCFG_MXDMA512 0x00700000
291 #define RXCFG_DRTH 0x0000003e
292 #define RXCFG_DRTH0 0x00000002
293
294 #define RFCR_RFEN 0x80000000
295 #define RFCR_AAB 0x40000000
296 #define RFCR_AAM 0x20000000
297 #define RFCR_AAU 0x10000000
298 #define RFCR_APM 0x08000000
299 #define RFCR_APAT 0x07800000
300 #define RFCR_APAT3 0x04000000
301 #define RFCR_APAT2 0x02000000
302 #define RFCR_APAT1 0x01000000
303 #define RFCR_APAT0 0x00800000
304 #define RFCR_AARP 0x00400000
305 #define RFCR_MHEN 0x00200000
306 #define RFCR_UHEN 0x00100000
307 #define RFCR_ULM 0x00080000
308
309 #define VRCR_RUDPE 0x00000080
310 #define VRCR_RTCPE 0x00000040
311 #define VRCR_RIPE 0x00000020
312 #define VRCR_IPEN 0x00000010
313 #define VRCR_DUTF 0x00000008
314 #define VRCR_DVTF 0x00000004
315 #define VRCR_VTREN 0x00000002
316 #define VRCR_VTDEN 0x00000001
317
318 #define VTCR_PPCHK 0x00000008
319 #define VTCR_GCHK 0x00000004
320 #define VTCR_VPPTI 0x00000002
321 #define VTCR_VGTI 0x00000001
322
323 #define CR 0x00
324 #define CFG 0x04
325 #define MEAR 0x08
326 #define PTSCR 0x0c
327 #define ISR 0x10
328 #define IMR 0x14
329 #define IER 0x18
330 #define IHR 0x1c
331 #define TXDP 0x20
332 #define TXDP_HI 0x24
333 #define TXCFG 0x28
334 #define GPIOR 0x2c
335 #define RXDP 0x30
336 #define RXDP_HI 0x34
337 #define RXCFG 0x38
338 #define PQCR 0x3c
339 #define WCSR 0x40
340 #define PCR 0x44
341 #define RFCR 0x48
342 #define RFDR 0x4c
343
344 #define SRR 0x58
345
346 #define VRCR 0xbc
347 #define VTCR 0xc0
348 #define VDR 0xc4
349 #define CCSR 0xcc
350
351 #define TBICR 0xe0
352 #define TBISR 0xe4
353 #define TANAR 0xe8
354 #define TANLPAR 0xec
355 #define TANER 0xf0
356 #define TESR 0xf4
357
358 #define TBICR_MR_AN_ENABLE 0x00001000
359 #define TBICR_MR_RESTART_AN 0x00000200
360
361 #define TBISR_MR_LINK_STATUS 0x00000020
362 #define TBISR_MR_AN_COMPLETE 0x00000004
363
364 #define TANAR_PS2 0x00000100
365 #define TANAR_PS1 0x00000080
366 #define TANAR_HALF_DUP 0x00000040
367 #define TANAR_FULL_DUP 0x00000020
368
369 #define GPIOR_GP5_OE 0x00000200
370 #define GPIOR_GP4_OE 0x00000100
371 #define GPIOR_GP3_OE 0x00000080
372 #define GPIOR_GP2_OE 0x00000040
373 #define GPIOR_GP1_OE 0x00000020
374 #define GPIOR_GP3_OUT 0x00000004
375 #define GPIOR_GP1_OUT 0x00000001
376
377 #define LINK_AUTONEGOTIATE 0x01
378 #define LINK_DOWN 0x02
379 #define LINK_UP 0x04
380
381 #define HW_ADDR_LEN sizeof(dma_addr_t)
382 #define desc_addr_set(desc, addr) \
383 do { \
384 ((desc)[0] = cpu_to_le32(addr)); \
385 if (HW_ADDR_LEN == 8) \
386 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
387 } while(0)
388 #define desc_addr_get(desc) \
389 (le32_to_cpu((desc)[0]) | \
390 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
391
392 #define DESC_LINK 0
393 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
394 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
395 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
396
397 #define CMDSTS_OWN 0x80000000
398 #define CMDSTS_MORE 0x40000000
399 #define CMDSTS_INTR 0x20000000
400 #define CMDSTS_ERR 0x10000000
401 #define CMDSTS_OK 0x08000000
402 #define CMDSTS_RUNT 0x00200000
403 #define CMDSTS_LEN_MASK 0x0000ffff
404
405 #define CMDSTS_DEST_MASK 0x01800000
406 #define CMDSTS_DEST_SELF 0x00800000
407 #define CMDSTS_DEST_MULTI 0x01000000
408
409 #define DESC_SIZE 8 /* Should be cache line sized */
410
411 struct rx_info {
412 spinlock_t lock;
413 int up;
414 long idle;
415
416 struct sk_buff *skbs[NR_RX_DESC];
417
418 u32 *next_rx_desc;
419 u16 next_rx, next_empty;
420
421 u32 *descs;
422 dma_addr_t phy_descs;
423 };
424
425
426 struct ns83820 {
427 struct net_device_stats stats;
428 u8 __iomem *base;
429
430 struct pci_dev *pci_dev;
431
432 #ifdef NS83820_VLAN_ACCEL_SUPPORT
433 struct vlan_group *vlgrp;
434 #endif
435
436 struct rx_info rx_info;
437 struct tasklet_struct rx_tasklet;
438
439 unsigned ihr;
440 struct work_struct tq_refill;
441
442 /* protects everything below. irqsave when using. */
443 spinlock_t misc_lock;
444
445 u32 CFG_cache;
446
447 u32 MEAR_cache;
448 u32 IMR_cache;
449
450 unsigned linkstate;
451
452 spinlock_t tx_lock;
453
454 u16 tx_done_idx;
455 u16 tx_idx;
456 volatile u16 tx_free_idx; /* idx of free desc chain */
457 u16 tx_intr_idx;
458
459 atomic_t nr_tx_skbs;
460 struct sk_buff *tx_skbs[NR_TX_DESC];
461
462 char pad[16] __attribute__((aligned(16)));
463 u32 *tx_descs;
464 dma_addr_t tx_phy_descs;
465
466 struct timer_list tx_watchdog;
467 };
468
469 static inline struct ns83820 *PRIV(struct net_device *dev)
470 {
471 return netdev_priv(dev);
472 }
473
474 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
475
476 static inline void kick_rx(struct net_device *ndev)
477 {
478 struct ns83820 *dev = PRIV(ndev);
479 dprintk("kick_rx: maybe kicking\n");
480 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
481 dprintk("actually kicking\n");
482 writel(dev->rx_info.phy_descs +
483 (4 * DESC_SIZE * dev->rx_info.next_rx),
484 dev->base + RXDP);
485 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
486 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
487 ndev->name);
488 __kick_rx(dev);
489 }
490 }
491
492 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
493 #define start_tx_okay(dev) \
494 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
495
496
497 #ifdef NS83820_VLAN_ACCEL_SUPPORT
498 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
499 {
500 struct ns83820 *dev = PRIV(ndev);
501
502 spin_lock_irq(&dev->misc_lock);
503 spin_lock(&dev->tx_lock);
504
505 dev->vlgrp = grp;
506
507 spin_unlock(&dev->tx_lock);
508 spin_unlock_irq(&dev->misc_lock);
509 }
510
511 static void ns83820_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
512 {
513 struct ns83820 *dev = PRIV(ndev);
514
515 spin_lock_irq(&dev->misc_lock);
516 spin_lock(&dev->tx_lock);
517 if (dev->vlgrp)
518 dev->vlgrp->vlan_devices[vid] = NULL;
519 spin_unlock(&dev->tx_lock);
520 spin_unlock_irq(&dev->misc_lock);
521 }
522 #endif
523
524 /* Packet Receiver
525 *
526 * The hardware supports linked lists of receive descriptors for
527 * which ownership is transfered back and forth by means of an
528 * ownership bit. While the hardware does support the use of a
529 * ring for receive descriptors, we only make use of a chain in
530 * an attempt to reduce bus traffic under heavy load scenarios.
531 * This will also make bugs a bit more obvious. The current code
532 * only makes use of a single rx chain; I hope to implement
533 * priority based rx for version 1.0. Goal: even under overload
534 * conditions, still route realtime traffic with as low jitter as
535 * possible.
536 */
537 static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
538 {
539 desc_addr_set(desc + DESC_LINK, link);
540 desc_addr_set(desc + DESC_BUFPTR, buf);
541 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
542 mb();
543 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
544 }
545
546 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
547 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
548 {
549 unsigned next_empty;
550 u32 cmdsts;
551 u32 *sg;
552 dma_addr_t buf;
553
554 next_empty = dev->rx_info.next_empty;
555
556 /* don't overrun last rx marker */
557 if (unlikely(nr_rx_empty(dev) <= 2)) {
558 kfree_skb(skb);
559 return 1;
560 }
561
562 #if 0
563 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
564 dev->rx_info.next_empty,
565 dev->rx_info.nr_used,
566 dev->rx_info.next_rx
567 );
568 #endif
569
570 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
571 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
572 dev->rx_info.skbs[next_empty] = skb;
573
574 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
575 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
576 buf = pci_map_single(dev->pci_dev, skb->data,
577 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
578 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
579 /* update link of previous rx */
580 if (likely(next_empty != dev->rx_info.next_rx))
581 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
582
583 return 0;
584 }
585
586 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
587 {
588 struct ns83820 *dev = PRIV(ndev);
589 unsigned i;
590 unsigned long flags = 0;
591
592 if (unlikely(nr_rx_empty(dev) <= 2))
593 return 0;
594
595 dprintk("rx_refill(%p)\n", ndev);
596 if (gfp == GFP_ATOMIC)
597 spin_lock_irqsave(&dev->rx_info.lock, flags);
598 for (i=0; i<NR_RX_DESC; i++) {
599 struct sk_buff *skb;
600 long res;
601 /* extra 16 bytes for alignment */
602 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
603 if (unlikely(!skb))
604 break;
605
606 res = (long)skb->data & 0xf;
607 res = 0x10 - res;
608 res &= 0xf;
609 skb_reserve(skb, res);
610
611 skb->dev = ndev;
612 if (gfp != GFP_ATOMIC)
613 spin_lock_irqsave(&dev->rx_info.lock, flags);
614 res = ns83820_add_rx_skb(dev, skb);
615 if (gfp != GFP_ATOMIC)
616 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
617 if (res) {
618 i = 1;
619 break;
620 }
621 }
622 if (gfp == GFP_ATOMIC)
623 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
624
625 return i ? 0 : -ENOMEM;
626 }
627
628 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
629 static void fastcall rx_refill_atomic(struct net_device *ndev)
630 {
631 rx_refill(ndev, GFP_ATOMIC);
632 }
633
634 /* REFILL */
635 static inline void queue_refill(void *_dev)
636 {
637 struct net_device *ndev = _dev;
638 struct ns83820 *dev = PRIV(ndev);
639
640 rx_refill(ndev, GFP_KERNEL);
641 if (dev->rx_info.up)
642 kick_rx(ndev);
643 }
644
645 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
646 {
647 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
648 }
649
650 static void FASTCALL(phy_intr(struct net_device *ndev));
651 static void fastcall phy_intr(struct net_device *ndev)
652 {
653 struct ns83820 *dev = PRIV(ndev);
654 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
655 u32 cfg, new_cfg;
656 u32 tbisr, tanar, tanlpar;
657 int speed, fullduplex, newlinkstate;
658
659 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
660
661 if (dev->CFG_cache & CFG_TBI_EN) {
662 /* we have an optical transceiver */
663 tbisr = readl(dev->base + TBISR);
664 tanar = readl(dev->base + TANAR);
665 tanlpar = readl(dev->base + TANLPAR);
666 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
667 tbisr, tanar, tanlpar);
668
669 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
670 && (tanar & TANAR_FULL_DUP)) ) {
671
672 /* both of us are full duplex */
673 writel(readl(dev->base + TXCFG)
674 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
675 dev->base + TXCFG);
676 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
677 dev->base + RXCFG);
678 /* Light up full duplex LED */
679 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
680 dev->base + GPIOR);
681
682 } else if(((tanlpar & TANAR_HALF_DUP)
683 && (tanar & TANAR_HALF_DUP))
684 || ((tanlpar & TANAR_FULL_DUP)
685 && (tanar & TANAR_HALF_DUP))
686 || ((tanlpar & TANAR_HALF_DUP)
687 && (tanar & TANAR_FULL_DUP))) {
688
689 /* one or both of us are half duplex */
690 writel((readl(dev->base + TXCFG)
691 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
692 dev->base + TXCFG);
693 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
694 dev->base + RXCFG);
695 /* Turn off full duplex LED */
696 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
697 dev->base + GPIOR);
698 }
699
700 speed = 4; /* 1000F */
701
702 } else {
703 /* we have a copper transceiver */
704 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
705
706 if (cfg & CFG_SPDSTS1)
707 new_cfg |= CFG_MODE_1000;
708 else
709 new_cfg &= ~CFG_MODE_1000;
710
711 speed = ((cfg / CFG_SPDSTS0) & 3);
712 fullduplex = (cfg & CFG_DUPSTS);
713
714 if (fullduplex) {
715 new_cfg |= CFG_SB;
716 writel(readl(dev->base + TXCFG)
717 | TXCFG_CSI | TXCFG_HBI,
718 dev->base + TXCFG);
719 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
720 dev->base + RXCFG);
721 } else {
722 writel(readl(dev->base + TXCFG)
723 & ~(TXCFG_CSI | TXCFG_HBI),
724 dev->base + TXCFG);
725 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
726 dev->base + RXCFG);
727 }
728
729 if ((cfg & CFG_LNKSTS) &&
730 ((new_cfg ^ dev->CFG_cache) != 0)) {
731 writel(new_cfg, dev->base + CFG);
732 dev->CFG_cache = new_cfg;
733 }
734
735 dev->CFG_cache &= ~CFG_SPDSTS;
736 dev->CFG_cache |= cfg & CFG_SPDSTS;
737 }
738
739 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
740
741 if (newlinkstate & LINK_UP
742 && dev->linkstate != newlinkstate) {
743 netif_start_queue(ndev);
744 netif_wake_queue(ndev);
745 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
746 ndev->name,
747 speeds[speed],
748 fullduplex ? "full" : "half");
749 } else if (newlinkstate & LINK_DOWN
750 && dev->linkstate != newlinkstate) {
751 netif_stop_queue(ndev);
752 printk(KERN_INFO "%s: link now down.\n", ndev->name);
753 }
754
755 dev->linkstate = newlinkstate;
756 }
757
758 static int ns83820_setup_rx(struct net_device *ndev)
759 {
760 struct ns83820 *dev = PRIV(ndev);
761 unsigned i;
762 int ret;
763
764 dprintk("ns83820_setup_rx(%p)\n", ndev);
765
766 dev->rx_info.idle = 1;
767 dev->rx_info.next_rx = 0;
768 dev->rx_info.next_rx_desc = dev->rx_info.descs;
769 dev->rx_info.next_empty = 0;
770
771 for (i=0; i<NR_RX_DESC; i++)
772 clear_rx_desc(dev, i);
773
774 writel(0, dev->base + RXDP_HI);
775 writel(dev->rx_info.phy_descs, dev->base + RXDP);
776
777 ret = rx_refill(ndev, GFP_KERNEL);
778 if (!ret) {
779 dprintk("starting receiver\n");
780 /* prevent the interrupt handler from stomping on us */
781 spin_lock_irq(&dev->rx_info.lock);
782
783 writel(0x0001, dev->base + CCSR);
784 writel(0, dev->base + RFCR);
785 writel(0x7fc00000, dev->base + RFCR);
786 writel(0xffc00000, dev->base + RFCR);
787
788 dev->rx_info.up = 1;
789
790 phy_intr(ndev);
791
792 /* Okay, let it rip */
793 spin_lock_irq(&dev->misc_lock);
794 dev->IMR_cache |= ISR_PHY;
795 dev->IMR_cache |= ISR_RXRCMP;
796 //dev->IMR_cache |= ISR_RXERR;
797 //dev->IMR_cache |= ISR_RXOK;
798 dev->IMR_cache |= ISR_RXORN;
799 dev->IMR_cache |= ISR_RXSOVR;
800 dev->IMR_cache |= ISR_RXDESC;
801 dev->IMR_cache |= ISR_RXIDLE;
802 dev->IMR_cache |= ISR_TXDESC;
803 dev->IMR_cache |= ISR_TXIDLE;
804
805 writel(dev->IMR_cache, dev->base + IMR);
806 writel(1, dev->base + IER);
807 spin_unlock_irq(&dev->misc_lock);
808
809 kick_rx(ndev);
810
811 spin_unlock_irq(&dev->rx_info.lock);
812 }
813 return ret;
814 }
815
816 static void ns83820_cleanup_rx(struct ns83820 *dev)
817 {
818 unsigned i;
819 unsigned long flags;
820
821 dprintk("ns83820_cleanup_rx(%p)\n", dev);
822
823 /* disable receive interrupts */
824 spin_lock_irqsave(&dev->misc_lock, flags);
825 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
826 writel(dev->IMR_cache, dev->base + IMR);
827 spin_unlock_irqrestore(&dev->misc_lock, flags);
828
829 /* synchronize with the interrupt handler and kill it */
830 dev->rx_info.up = 0;
831 synchronize_irq(dev->pci_dev->irq);
832
833 /* touch the pci bus... */
834 readl(dev->base + IMR);
835
836 /* assumes the transmitter is already disabled and reset */
837 writel(0, dev->base + RXDP_HI);
838 writel(0, dev->base + RXDP);
839
840 for (i=0; i<NR_RX_DESC; i++) {
841 struct sk_buff *skb = dev->rx_info.skbs[i];
842 dev->rx_info.skbs[i] = NULL;
843 clear_rx_desc(dev, i);
844 if (skb)
845 kfree_skb(skb);
846 }
847 }
848
849 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
850 static void fastcall ns83820_rx_kick(struct net_device *ndev)
851 {
852 struct ns83820 *dev = PRIV(ndev);
853 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
854 if (dev->rx_info.up) {
855 rx_refill_atomic(ndev);
856 kick_rx(ndev);
857 }
858 }
859
860 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
861 schedule_work(&dev->tq_refill);
862 else
863 kick_rx(ndev);
864 if (dev->rx_info.idle)
865 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
866 }
867
868 /* rx_irq
869 *
870 */
871 static void FASTCALL(rx_irq(struct net_device *ndev));
872 static void fastcall rx_irq(struct net_device *ndev)
873 {
874 struct ns83820 *dev = PRIV(ndev);
875 struct rx_info *info = &dev->rx_info;
876 unsigned next_rx;
877 int rx_rc, len;
878 u32 cmdsts, *desc;
879 unsigned long flags;
880 int nr = 0;
881
882 dprintk("rx_irq(%p)\n", ndev);
883 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
884 readl(dev->base + RXDP),
885 (long)(dev->rx_info.phy_descs),
886 (int)dev->rx_info.next_rx,
887 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
888 (int)dev->rx_info.next_empty,
889 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
890 );
891
892 spin_lock_irqsave(&info->lock, flags);
893 if (!info->up)
894 goto out;
895
896 dprintk("walking descs\n");
897 next_rx = info->next_rx;
898 desc = info->next_rx_desc;
899 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
900 (cmdsts != CMDSTS_OWN)) {
901 struct sk_buff *skb;
902 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
903 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
904
905 dprintk("cmdsts: %08x\n", cmdsts);
906 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
907 dprintk("extsts: %08x\n", extsts);
908
909 skb = info->skbs[next_rx];
910 info->skbs[next_rx] = NULL;
911 info->next_rx = (next_rx + 1) % NR_RX_DESC;
912
913 mb();
914 clear_rx_desc(dev, next_rx);
915
916 pci_unmap_single(dev->pci_dev, bufptr,
917 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
918 len = cmdsts & CMDSTS_LEN_MASK;
919 #ifdef NS83820_VLAN_ACCEL_SUPPORT
920 /* NH: As was mentioned below, this chip is kinda
921 * brain dead about vlan tag stripping. Frames
922 * that are 64 bytes with a vlan header appended
923 * like arp frames, or pings, are flagged as Runts
924 * when the tag is stripped and hardware. This
925 * also means that the OK bit in the descriptor
926 * is cleared when the frame comes in so we have
927 * to do a specific length check here to make sure
928 * the frame would have been ok, had we not stripped
929 * the tag.
930 */
931 if (likely((CMDSTS_OK & cmdsts) ||
932 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
933 #else
934 if (likely(CMDSTS_OK & cmdsts)) {
935 #endif
936 skb_put(skb, len);
937 if (unlikely(!skb))
938 goto netdev_mangle_me_harder_failed;
939 if (cmdsts & CMDSTS_DEST_MULTI)
940 dev->stats.multicast ++;
941 dev->stats.rx_packets ++;
942 dev->stats.rx_bytes += len;
943 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
944 skb->ip_summed = CHECKSUM_UNNECESSARY;
945 } else {
946 skb->ip_summed = CHECKSUM_NONE;
947 }
948 skb->protocol = eth_type_trans(skb, ndev);
949 #ifdef NS83820_VLAN_ACCEL_SUPPORT
950 if(extsts & EXTSTS_VPKT) {
951 unsigned short tag;
952 tag = ntohs(extsts & EXTSTS_VTG_MASK);
953 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
954 } else {
955 rx_rc = netif_rx(skb);
956 }
957 #else
958 rx_rc = netif_rx(skb);
959 #endif
960 if (NET_RX_DROP == rx_rc) {
961 netdev_mangle_me_harder_failed:
962 dev->stats.rx_dropped ++;
963 }
964 } else {
965 kfree_skb(skb);
966 }
967
968 nr++;
969 next_rx = info->next_rx;
970 desc = info->descs + (DESC_SIZE * next_rx);
971 }
972 info->next_rx = next_rx;
973 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
974
975 out:
976 if (0 && !nr) {
977 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
978 }
979
980 spin_unlock_irqrestore(&info->lock, flags);
981 }
982
983 static void rx_action(unsigned long _dev)
984 {
985 struct net_device *ndev = (void *)_dev;
986 struct ns83820 *dev = PRIV(ndev);
987 rx_irq(ndev);
988 writel(ihr, dev->base + IHR);
989
990 spin_lock_irq(&dev->misc_lock);
991 dev->IMR_cache |= ISR_RXDESC;
992 writel(dev->IMR_cache, dev->base + IMR);
993 spin_unlock_irq(&dev->misc_lock);
994
995 rx_irq(ndev);
996 ns83820_rx_kick(ndev);
997 }
998
999 /* Packet Transmit code
1000 */
1001 static inline void kick_tx(struct ns83820 *dev)
1002 {
1003 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
1004 dev, dev->tx_idx, dev->tx_free_idx);
1005 writel(CR_TXE, dev->base + CR);
1006 }
1007
1008 /* No spinlock needed on the transmit irq path as the interrupt handler is
1009 * serialized.
1010 */
1011 static void do_tx_done(struct net_device *ndev)
1012 {
1013 struct ns83820 *dev = PRIV(ndev);
1014 u32 cmdsts, tx_done_idx, *desc;
1015
1016 spin_lock_irq(&dev->tx_lock);
1017
1018 dprintk("do_tx_done(%p)\n", ndev);
1019 tx_done_idx = dev->tx_done_idx;
1020 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1021
1022 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1023 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1024 while ((tx_done_idx != dev->tx_free_idx) &&
1025 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1026 struct sk_buff *skb;
1027 unsigned len;
1028 dma_addr_t addr;
1029
1030 if (cmdsts & CMDSTS_ERR)
1031 dev->stats.tx_errors ++;
1032 if (cmdsts & CMDSTS_OK)
1033 dev->stats.tx_packets ++;
1034 if (cmdsts & CMDSTS_OK)
1035 dev->stats.tx_bytes += cmdsts & 0xffff;
1036
1037 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1038 tx_done_idx, dev->tx_free_idx, cmdsts);
1039 skb = dev->tx_skbs[tx_done_idx];
1040 dev->tx_skbs[tx_done_idx] = NULL;
1041 dprintk("done(%p)\n", skb);
1042
1043 len = cmdsts & CMDSTS_LEN_MASK;
1044 addr = desc_addr_get(desc + DESC_BUFPTR);
1045 if (skb) {
1046 pci_unmap_single(dev->pci_dev,
1047 addr,
1048 len,
1049 PCI_DMA_TODEVICE);
1050 dev_kfree_skb_irq(skb);
1051 atomic_dec(&dev->nr_tx_skbs);
1052 } else
1053 pci_unmap_page(dev->pci_dev,
1054 addr,
1055 len,
1056 PCI_DMA_TODEVICE);
1057
1058 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1059 dev->tx_done_idx = tx_done_idx;
1060 desc[DESC_CMDSTS] = cpu_to_le32(0);
1061 mb();
1062 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1063 }
1064
1065 /* Allow network stack to resume queueing packets after we've
1066 * finished transmitting at least 1/4 of the packets in the queue.
1067 */
1068 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1069 dprintk("start_queue(%p)\n", ndev);
1070 netif_start_queue(ndev);
1071 netif_wake_queue(ndev);
1072 }
1073 spin_unlock_irq(&dev->tx_lock);
1074 }
1075
1076 static void ns83820_cleanup_tx(struct ns83820 *dev)
1077 {
1078 unsigned i;
1079
1080 for (i=0; i<NR_TX_DESC; i++) {
1081 struct sk_buff *skb = dev->tx_skbs[i];
1082 dev->tx_skbs[i] = NULL;
1083 if (skb) {
1084 u32 *desc = dev->tx_descs + (i * DESC_SIZE);
1085 pci_unmap_single(dev->pci_dev,
1086 desc_addr_get(desc + DESC_BUFPTR),
1087 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1088 PCI_DMA_TODEVICE);
1089 dev_kfree_skb_irq(skb);
1090 atomic_dec(&dev->nr_tx_skbs);
1091 }
1092 }
1093
1094 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1095 }
1096
1097 /* transmit routine. This code relies on the network layer serializing
1098 * its calls in, but will run happily in parallel with the interrupt
1099 * handler. This code currently has provisions for fragmenting tx buffers
1100 * while trying to track down a bug in either the zero copy code or
1101 * the tx fifo (hence the MAX_FRAG_LEN).
1102 */
1103 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1104 {
1105 struct ns83820 *dev = PRIV(ndev);
1106 u32 free_idx, cmdsts, extsts;
1107 int nr_free, nr_frags;
1108 unsigned tx_done_idx, last_idx;
1109 dma_addr_t buf;
1110 unsigned len;
1111 skb_frag_t *frag;
1112 int stopped = 0;
1113 int do_intr = 0;
1114 volatile u32 *first_desc;
1115
1116 dprintk("ns83820_hard_start_xmit\n");
1117
1118 nr_frags = skb_shinfo(skb)->nr_frags;
1119 again:
1120 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1121 netif_stop_queue(ndev);
1122 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1123 return 1;
1124 netif_start_queue(ndev);
1125 }
1126
1127 last_idx = free_idx = dev->tx_free_idx;
1128 tx_done_idx = dev->tx_done_idx;
1129 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1130 nr_free -= 1;
1131 if (nr_free <= nr_frags) {
1132 dprintk("stop_queue - not enough(%p)\n", ndev);
1133 netif_stop_queue(ndev);
1134
1135 /* Check again: we may have raced with a tx done irq */
1136 if (dev->tx_done_idx != tx_done_idx) {
1137 dprintk("restart queue(%p)\n", ndev);
1138 netif_start_queue(ndev);
1139 goto again;
1140 }
1141 return 1;
1142 }
1143
1144 if (free_idx == dev->tx_intr_idx) {
1145 do_intr = 1;
1146 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1147 }
1148
1149 nr_free -= nr_frags;
1150 if (nr_free < MIN_TX_DESC_FREE) {
1151 dprintk("stop_queue - last entry(%p)\n", ndev);
1152 netif_stop_queue(ndev);
1153 stopped = 1;
1154 }
1155
1156 frag = skb_shinfo(skb)->frags;
1157 if (!nr_frags)
1158 frag = NULL;
1159 extsts = 0;
1160 if (skb->ip_summed == CHECKSUM_HW) {
1161 extsts |= EXTSTS_IPPKT;
1162 if (IPPROTO_TCP == skb->nh.iph->protocol)
1163 extsts |= EXTSTS_TCPPKT;
1164 else if (IPPROTO_UDP == skb->nh.iph->protocol)
1165 extsts |= EXTSTS_UDPPKT;
1166 }
1167
1168 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1169 if(vlan_tx_tag_present(skb)) {
1170 /* fetch the vlan tag info out of the
1171 * ancilliary data if the vlan code
1172 * is using hw vlan acceleration
1173 */
1174 short tag = vlan_tx_tag_get(skb);
1175 extsts |= (EXTSTS_VPKT | htons(tag));
1176 }
1177 #endif
1178
1179 len = skb->len;
1180 if (nr_frags)
1181 len -= skb->data_len;
1182 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1183
1184 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1185
1186 for (;;) {
1187 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1188
1189 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1190 (unsigned long long)buf);
1191 last_idx = free_idx;
1192 free_idx = (free_idx + 1) % NR_TX_DESC;
1193 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1194 desc_addr_set(desc + DESC_BUFPTR, buf);
1195 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1196
1197 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1198 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1199 cmdsts |= len;
1200 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1201
1202 if (!nr_frags)
1203 break;
1204
1205 buf = pci_map_page(dev->pci_dev, frag->page,
1206 frag->page_offset,
1207 frag->size, PCI_DMA_TODEVICE);
1208 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1209 (long long)buf, (long) page_to_pfn(frag->page),
1210 frag->page_offset);
1211 len = frag->size;
1212 frag++;
1213 nr_frags--;
1214 }
1215 dprintk("done pkt\n");
1216
1217 spin_lock_irq(&dev->tx_lock);
1218 dev->tx_skbs[last_idx] = skb;
1219 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1220 dev->tx_free_idx = free_idx;
1221 atomic_inc(&dev->nr_tx_skbs);
1222 spin_unlock_irq(&dev->tx_lock);
1223
1224 kick_tx(dev);
1225
1226 /* Check again: we may have raced with a tx done irq */
1227 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1228 netif_start_queue(ndev);
1229
1230 /* set the transmit start time to catch transmit timeouts */
1231 ndev->trans_start = jiffies;
1232 return 0;
1233 }
1234
1235 static void ns83820_update_stats(struct ns83820 *dev)
1236 {
1237 u8 __iomem *base = dev->base;
1238
1239 /* the DP83820 will freeze counters, so we need to read all of them */
1240 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1241 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1242 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1243 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1244 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1245 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1246 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1247 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1248 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1249 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1250 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1251 }
1252
1253 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1254 {
1255 struct ns83820 *dev = PRIV(ndev);
1256
1257 /* somewhat overkill */
1258 spin_lock_irq(&dev->misc_lock);
1259 ns83820_update_stats(dev);
1260 spin_unlock_irq(&dev->misc_lock);
1261
1262 return &dev->stats;
1263 }
1264
1265 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1266 {
1267 struct ns83820 *dev = PRIV(ndev);
1268 strcpy(info->driver, "ns83820");
1269 strcpy(info->version, VERSION);
1270 strcpy(info->bus_info, pci_name(dev->pci_dev));
1271 }
1272
1273 static u32 ns83820_get_link(struct net_device *ndev)
1274 {
1275 struct ns83820 *dev = PRIV(ndev);
1276 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1277 return cfg & CFG_LNKSTS ? 1 : 0;
1278 }
1279
1280 static struct ethtool_ops ops = {
1281 .get_drvinfo = ns83820_get_drvinfo,
1282 .get_link = ns83820_get_link
1283 };
1284
1285 static void ns83820_mib_isr(struct ns83820 *dev)
1286 {
1287 spin_lock(&dev->misc_lock);
1288 ns83820_update_stats(dev);
1289 spin_unlock(&dev->misc_lock);
1290 }
1291
1292 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1293 static irqreturn_t ns83820_irq(int foo, void *data, struct pt_regs *regs)
1294 {
1295 struct net_device *ndev = data;
1296 struct ns83820 *dev = PRIV(ndev);
1297 u32 isr;
1298 dprintk("ns83820_irq(%p)\n", ndev);
1299
1300 dev->ihr = 0;
1301
1302 isr = readl(dev->base + ISR);
1303 dprintk("irq: %08x\n", isr);
1304 ns83820_do_isr(ndev, isr);
1305 return IRQ_HANDLED;
1306 }
1307
1308 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1309 {
1310 struct ns83820 *dev = PRIV(ndev);
1311 #ifdef DEBUG
1312 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1313 Dprintk("odd isr? 0x%08x\n", isr);
1314 #endif
1315
1316 if (ISR_RXIDLE & isr) {
1317 dev->rx_info.idle = 1;
1318 Dprintk("oh dear, we are idle\n");
1319 ns83820_rx_kick(ndev);
1320 }
1321
1322 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1323 prefetch(dev->rx_info.next_rx_desc);
1324
1325 spin_lock_irq(&dev->misc_lock);
1326 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1327 writel(dev->IMR_cache, dev->base + IMR);
1328 spin_unlock_irq(&dev->misc_lock);
1329
1330 tasklet_schedule(&dev->rx_tasklet);
1331 //rx_irq(ndev);
1332 //writel(4, dev->base + IHR);
1333 }
1334
1335 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1336 ns83820_rx_kick(ndev);
1337
1338 if (unlikely(ISR_RXSOVR & isr)) {
1339 //printk("overrun: rxsovr\n");
1340 dev->stats.rx_fifo_errors ++;
1341 }
1342
1343 if (unlikely(ISR_RXORN & isr)) {
1344 //printk("overrun: rxorn\n");
1345 dev->stats.rx_fifo_errors ++;
1346 }
1347
1348 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1349 writel(CR_RXE, dev->base + CR);
1350
1351 if (ISR_TXIDLE & isr) {
1352 u32 txdp;
1353 txdp = readl(dev->base + TXDP);
1354 dprintk("txdp: %08x\n", txdp);
1355 txdp -= dev->tx_phy_descs;
1356 dev->tx_idx = txdp / (DESC_SIZE * 4);
1357 if (dev->tx_idx >= NR_TX_DESC) {
1358 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1359 dev->tx_idx = 0;
1360 }
1361 /* The may have been a race between a pci originated read
1362 * and the descriptor update from the cpu. Just in case,
1363 * kick the transmitter if the hardware thinks it is on a
1364 * different descriptor than we are.
1365 */
1366 if (dev->tx_idx != dev->tx_free_idx)
1367 kick_tx(dev);
1368 }
1369
1370 /* Defer tx ring processing until more than a minimum amount of
1371 * work has accumulated
1372 */
1373 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1374 do_tx_done(ndev);
1375
1376 /* Disable TxOk if there are no outstanding tx packets.
1377 */
1378 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1379 (dev->IMR_cache & ISR_TXOK)) {
1380 spin_lock_irq(&dev->misc_lock);
1381 dev->IMR_cache &= ~ISR_TXOK;
1382 writel(dev->IMR_cache, dev->base + IMR);
1383 spin_unlock_irq(&dev->misc_lock);
1384 }
1385 }
1386
1387 /* The TxIdle interrupt can come in before the transmit has
1388 * completed. Normally we reap packets off of the combination
1389 * of TxDesc and TxIdle and leave TxOk disabled (since it
1390 * occurs on every packet), but when no further irqs of this
1391 * nature are expected, we must enable TxOk.
1392 */
1393 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1394 spin_lock_irq(&dev->misc_lock);
1395 dev->IMR_cache |= ISR_TXOK;
1396 writel(dev->IMR_cache, dev->base + IMR);
1397 spin_unlock_irq(&dev->misc_lock);
1398 }
1399
1400 /* MIB interrupt: one of the statistics counters is about to overflow */
1401 if (unlikely(ISR_MIB & isr))
1402 ns83820_mib_isr(dev);
1403
1404 /* PHY: Link up/down/negotiation state change */
1405 if (unlikely(ISR_PHY & isr))
1406 phy_intr(ndev);
1407
1408 #if 0 /* Still working on the interrupt mitigation strategy */
1409 if (dev->ihr)
1410 writel(dev->ihr, dev->base + IHR);
1411 #endif
1412 }
1413
1414 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1415 {
1416 Dprintk("resetting chip...\n");
1417 writel(which, dev->base + CR);
1418 do {
1419 schedule();
1420 } while (readl(dev->base + CR) & which);
1421 Dprintk("okay!\n");
1422 }
1423
1424 static int ns83820_stop(struct net_device *ndev)
1425 {
1426 struct ns83820 *dev = PRIV(ndev);
1427
1428 /* FIXME: protect against interrupt handler? */
1429 del_timer_sync(&dev->tx_watchdog);
1430
1431 /* disable interrupts */
1432 writel(0, dev->base + IMR);
1433 writel(0, dev->base + IER);
1434 readl(dev->base + IER);
1435
1436 dev->rx_info.up = 0;
1437 synchronize_irq(dev->pci_dev->irq);
1438
1439 ns83820_do_reset(dev, CR_RST);
1440
1441 synchronize_irq(dev->pci_dev->irq);
1442
1443 spin_lock_irq(&dev->misc_lock);
1444 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1445 spin_unlock_irq(&dev->misc_lock);
1446
1447 ns83820_cleanup_rx(dev);
1448 ns83820_cleanup_tx(dev);
1449
1450 return 0;
1451 }
1452
1453 static void ns83820_tx_timeout(struct net_device *ndev)
1454 {
1455 struct ns83820 *dev = PRIV(ndev);
1456 u32 tx_done_idx, *desc;
1457 unsigned long flags;
1458
1459 local_irq_save(flags);
1460
1461 tx_done_idx = dev->tx_done_idx;
1462 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1463
1464 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1465 ndev->name,
1466 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1467
1468 #if defined(DEBUG)
1469 {
1470 u32 isr;
1471 isr = readl(dev->base + ISR);
1472 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1473 ns83820_do_isr(ndev, isr);
1474 }
1475 #endif
1476
1477 do_tx_done(ndev);
1478
1479 tx_done_idx = dev->tx_done_idx;
1480 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1481
1482 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1483 ndev->name,
1484 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1485
1486 local_irq_restore(flags);
1487 }
1488
1489 static void ns83820_tx_watch(unsigned long data)
1490 {
1491 struct net_device *ndev = (void *)data;
1492 struct ns83820 *dev = PRIV(ndev);
1493
1494 #if defined(DEBUG)
1495 printk("ns83820_tx_watch: %u %u %d\n",
1496 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1497 );
1498 #endif
1499
1500 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1501 dev->tx_done_idx != dev->tx_free_idx) {
1502 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1503 ndev->name,
1504 dev->tx_done_idx, dev->tx_free_idx,
1505 atomic_read(&dev->nr_tx_skbs));
1506 ns83820_tx_timeout(ndev);
1507 }
1508
1509 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1510 }
1511
1512 static int ns83820_open(struct net_device *ndev)
1513 {
1514 struct ns83820 *dev = PRIV(ndev);
1515 unsigned i;
1516 u32 desc;
1517 int ret;
1518
1519 dprintk("ns83820_open\n");
1520
1521 writel(0, dev->base + PQCR);
1522
1523 ret = ns83820_setup_rx(ndev);
1524 if (ret)
1525 goto failed;
1526
1527 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1528 for (i=0; i<NR_TX_DESC; i++) {
1529 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1530 = cpu_to_le32(
1531 dev->tx_phy_descs
1532 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1533 }
1534
1535 dev->tx_idx = 0;
1536 dev->tx_done_idx = 0;
1537 desc = dev->tx_phy_descs;
1538 writel(0, dev->base + TXDP_HI);
1539 writel(desc, dev->base + TXDP);
1540
1541 init_timer(&dev->tx_watchdog);
1542 dev->tx_watchdog.data = (unsigned long)ndev;
1543 dev->tx_watchdog.function = ns83820_tx_watch;
1544 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1545
1546 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1547
1548 return 0;
1549
1550 failed:
1551 ns83820_stop(ndev);
1552 return ret;
1553 }
1554
1555 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1556 {
1557 unsigned i;
1558 for (i=0; i<3; i++) {
1559 u32 data;
1560
1561 /* Read from the perfect match memory: this is loaded by
1562 * the chip from the EEPROM via the EELOAD self test.
1563 */
1564 writel(i*2, dev->base + RFCR);
1565 data = readl(dev->base + RFDR);
1566
1567 *mac++ = data;
1568 *mac++ = data >> 8;
1569 }
1570 }
1571
1572 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1573 {
1574 if (new_mtu > RX_BUF_SIZE)
1575 return -EINVAL;
1576 ndev->mtu = new_mtu;
1577 return 0;
1578 }
1579
1580 static void ns83820_set_multicast(struct net_device *ndev)
1581 {
1582 struct ns83820 *dev = PRIV(ndev);
1583 u8 __iomem *rfcr = dev->base + RFCR;
1584 u32 and_mask = 0xffffffff;
1585 u32 or_mask = 0;
1586 u32 val;
1587
1588 if (ndev->flags & IFF_PROMISC)
1589 or_mask |= RFCR_AAU | RFCR_AAM;
1590 else
1591 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1592
1593 if (ndev->flags & IFF_ALLMULTI)
1594 or_mask |= RFCR_AAM;
1595 else
1596 and_mask &= ~RFCR_AAM;
1597
1598 spin_lock_irq(&dev->misc_lock);
1599 val = (readl(rfcr) & and_mask) | or_mask;
1600 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1601 writel(val & ~RFCR_RFEN, rfcr);
1602 writel(val, rfcr);
1603 spin_unlock_irq(&dev->misc_lock);
1604 }
1605
1606 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1607 {
1608 struct ns83820 *dev = PRIV(ndev);
1609 int timed_out = 0;
1610 unsigned long start;
1611 u32 status;
1612 int loops = 0;
1613
1614 dprintk("%s: start %s\n", ndev->name, name);
1615
1616 start = jiffies;
1617
1618 writel(enable, dev->base + PTSCR);
1619 for (;;) {
1620 loops++;
1621 status = readl(dev->base + PTSCR);
1622 if (!(status & enable))
1623 break;
1624 if (status & done)
1625 break;
1626 if (status & fail)
1627 break;
1628 if (time_after_eq(jiffies, start + HZ)) {
1629 timed_out = 1;
1630 break;
1631 }
1632 schedule_timeout_uninterruptible(1);
1633 }
1634
1635 if (status & fail)
1636 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1637 ndev->name, name, status, fail);
1638 else if (timed_out)
1639 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1640 ndev->name, name, status);
1641
1642 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1643 }
1644
1645 #ifdef PHY_CODE_IS_FINISHED
1646 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1647 {
1648 /* drive MDC low */
1649 dev->MEAR_cache &= ~MEAR_MDC;
1650 writel(dev->MEAR_cache, dev->base + MEAR);
1651 readl(dev->base + MEAR);
1652
1653 /* enable output, set bit */
1654 dev->MEAR_cache |= MEAR_MDDIR;
1655 if (bit)
1656 dev->MEAR_cache |= MEAR_MDIO;
1657 else
1658 dev->MEAR_cache &= ~MEAR_MDIO;
1659
1660 /* set the output bit */
1661 writel(dev->MEAR_cache, dev->base + MEAR);
1662 readl(dev->base + MEAR);
1663
1664 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1665 udelay(1);
1666
1667 /* drive MDC high causing the data bit to be latched */
1668 dev->MEAR_cache |= MEAR_MDC;
1669 writel(dev->MEAR_cache, dev->base + MEAR);
1670 readl(dev->base + MEAR);
1671
1672 /* Wait again... */
1673 udelay(1);
1674 }
1675
1676 static int ns83820_mii_read_bit(struct ns83820 *dev)
1677 {
1678 int bit;
1679
1680 /* drive MDC low, disable output */
1681 dev->MEAR_cache &= ~MEAR_MDC;
1682 dev->MEAR_cache &= ~MEAR_MDDIR;
1683 writel(dev->MEAR_cache, dev->base + MEAR);
1684 readl(dev->base + MEAR);
1685
1686 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1687 udelay(1);
1688
1689 /* drive MDC high causing the data bit to be latched */
1690 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1691 dev->MEAR_cache |= MEAR_MDC;
1692 writel(dev->MEAR_cache, dev->base + MEAR);
1693
1694 /* Wait again... */
1695 udelay(1);
1696
1697 return bit;
1698 }
1699
1700 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1701 {
1702 unsigned data = 0;
1703 int i;
1704
1705 /* read some garbage so that we eventually sync up */
1706 for (i=0; i<64; i++)
1707 ns83820_mii_read_bit(dev);
1708
1709 ns83820_mii_write_bit(dev, 0); /* start */
1710 ns83820_mii_write_bit(dev, 1);
1711 ns83820_mii_write_bit(dev, 1); /* opcode read */
1712 ns83820_mii_write_bit(dev, 0);
1713
1714 /* write out the phy address: 5 bits, msb first */
1715 for (i=0; i<5; i++)
1716 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1717
1718 /* write out the register address, 5 bits, msb first */
1719 for (i=0; i<5; i++)
1720 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1721
1722 ns83820_mii_read_bit(dev); /* turn around cycles */
1723 ns83820_mii_read_bit(dev);
1724
1725 /* read in the register data, 16 bits msb first */
1726 for (i=0; i<16; i++) {
1727 data <<= 1;
1728 data |= ns83820_mii_read_bit(dev);
1729 }
1730
1731 return data;
1732 }
1733
1734 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1735 {
1736 int i;
1737
1738 /* read some garbage so that we eventually sync up */
1739 for (i=0; i<64; i++)
1740 ns83820_mii_read_bit(dev);
1741
1742 ns83820_mii_write_bit(dev, 0); /* start */
1743 ns83820_mii_write_bit(dev, 1);
1744 ns83820_mii_write_bit(dev, 0); /* opcode read */
1745 ns83820_mii_write_bit(dev, 1);
1746
1747 /* write out the phy address: 5 bits, msb first */
1748 for (i=0; i<5; i++)
1749 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1750
1751 /* write out the register address, 5 bits, msb first */
1752 for (i=0; i<5; i++)
1753 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1754
1755 ns83820_mii_read_bit(dev); /* turn around cycles */
1756 ns83820_mii_read_bit(dev);
1757
1758 /* read in the register data, 16 bits msb first */
1759 for (i=0; i<16; i++)
1760 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1761
1762 return data;
1763 }
1764
1765 static void ns83820_probe_phy(struct net_device *ndev)
1766 {
1767 struct ns83820 *dev = PRIV(ndev);
1768 static int first;
1769 int i;
1770 #define MII_PHYIDR1 0x02
1771 #define MII_PHYIDR2 0x03
1772
1773 #if 0
1774 if (!first) {
1775 unsigned tmp;
1776 ns83820_mii_read_reg(dev, 1, 0x09);
1777 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1778
1779 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1780 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1781 udelay(1300);
1782 ns83820_mii_read_reg(dev, 1, 0x09);
1783 }
1784 #endif
1785 first = 1;
1786
1787 for (i=1; i<2; i++) {
1788 int j;
1789 unsigned a, b;
1790 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1791 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1792
1793 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1794 // ndev->name, i, a, b);
1795
1796 for (j=0; j<0x16; j+=4) {
1797 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1798 ndev->name, j,
1799 ns83820_mii_read_reg(dev, i, 0 + j),
1800 ns83820_mii_read_reg(dev, i, 1 + j),
1801 ns83820_mii_read_reg(dev, i, 2 + j),
1802 ns83820_mii_read_reg(dev, i, 3 + j)
1803 );
1804 }
1805 }
1806 {
1807 unsigned a, b;
1808 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1809 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1810 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1811 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1812
1813 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1814 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1815 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1816 dprintk("version: 0x%04x 0x%04x\n", a, b);
1817 }
1818 }
1819 #endif
1820
1821 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1822 {
1823 struct net_device *ndev;
1824 struct ns83820 *dev;
1825 long addr;
1826 int err;
1827 int using_dac = 0;
1828
1829 /* See if we can set the dma mask early on; failure is fatal. */
1830 if (sizeof(dma_addr_t) == 8 &&
1831 !pci_set_dma_mask(pci_dev, DMA_64BIT_MASK)) {
1832 using_dac = 1;
1833 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1834 using_dac = 0;
1835 } else {
1836 printk(KERN_WARNING "ns83820.c: pci_set_dma_mask failed!\n");
1837 return -ENODEV;
1838 }
1839
1840 ndev = alloc_etherdev(sizeof(struct ns83820));
1841 dev = PRIV(ndev);
1842 err = -ENOMEM;
1843 if (!dev)
1844 goto out;
1845
1846 spin_lock_init(&dev->rx_info.lock);
1847 spin_lock_init(&dev->tx_lock);
1848 spin_lock_init(&dev->misc_lock);
1849 dev->pci_dev = pci_dev;
1850
1851 SET_MODULE_OWNER(ndev);
1852 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1853
1854 INIT_WORK(&dev->tq_refill, queue_refill, ndev);
1855 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1856
1857 err = pci_enable_device(pci_dev);
1858 if (err) {
1859 printk(KERN_INFO "ns83820: pci_enable_dev failed: %d\n", err);
1860 goto out_free;
1861 }
1862
1863 pci_set_master(pci_dev);
1864 addr = pci_resource_start(pci_dev, 1);
1865 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1866 dev->tx_descs = pci_alloc_consistent(pci_dev,
1867 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1868 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1869 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1870 err = -ENOMEM;
1871 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1872 goto out_disable;
1873
1874 dprintk("%p: %08lx %p: %08lx\n",
1875 dev->tx_descs, (long)dev->tx_phy_descs,
1876 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1877
1878 /* disable interrupts */
1879 writel(0, dev->base + IMR);
1880 writel(0, dev->base + IER);
1881 readl(dev->base + IER);
1882
1883 dev->IMR_cache = 0;
1884
1885 err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ,
1886 DRV_NAME, ndev);
1887 if (err) {
1888 printk(KERN_INFO "ns83820: unable to register irq %d\n",
1889 pci_dev->irq);
1890 goto out_disable;
1891 }
1892
1893 /*
1894 * FIXME: we are holding rtnl_lock() over obscenely long area only
1895 * because some of the setup code uses dev->name. It's Wrong(tm) -
1896 * we should be using driver-specific names for all that stuff.
1897 * For now that will do, but we really need to come back and kill
1898 * most of the dev_alloc_name() users later.
1899 */
1900 rtnl_lock();
1901 err = dev_alloc_name(ndev, ndev->name);
1902 if (err < 0) {
1903 printk(KERN_INFO "ns83820: unable to get netdev name: %d\n", err);
1904 goto out_free_irq;
1905 }
1906
1907 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1908 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1909 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1910
1911 ndev->open = ns83820_open;
1912 ndev->stop = ns83820_stop;
1913 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1914 ndev->get_stats = ns83820_get_stats;
1915 ndev->change_mtu = ns83820_change_mtu;
1916 ndev->set_multicast_list = ns83820_set_multicast;
1917 SET_ETHTOOL_OPS(ndev, &ops);
1918 ndev->tx_timeout = ns83820_tx_timeout;
1919 ndev->watchdog_timeo = 5 * HZ;
1920 pci_set_drvdata(pci_dev, ndev);
1921
1922 ns83820_do_reset(dev, CR_RST);
1923
1924 /* Must reset the ram bist before running it */
1925 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1926 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1927 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1928 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1929 PTSCR_EEBIST_FAIL);
1930 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1931
1932 /* I love config registers */
1933 dev->CFG_cache = readl(dev->base + CFG);
1934
1935 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1936 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1937 ndev->name);
1938 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1939 if (!(dev->CFG_cache & CFG_DATA64_EN))
1940 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1941 ndev->name);
1942 } else
1943 dev->CFG_cache &= ~(CFG_DATA64_EN);
1944
1945 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1946 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1947 CFG_M64ADDR);
1948 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1949 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1950 dev->CFG_cache |= CFG_REQALG;
1951 dev->CFG_cache |= CFG_POW;
1952 dev->CFG_cache |= CFG_TMRTEST;
1953
1954 /* When compiled with 64 bit addressing, we must always enable
1955 * the 64 bit descriptor format.
1956 */
1957 if (sizeof(dma_addr_t) == 8)
1958 dev->CFG_cache |= CFG_M64ADDR;
1959 if (using_dac)
1960 dev->CFG_cache |= CFG_T64ADDR;
1961
1962 /* Big endian mode does not seem to do what the docs suggest */
1963 dev->CFG_cache &= ~CFG_BEM;
1964
1965 /* setup optical transceiver if we have one */
1966 if (dev->CFG_cache & CFG_TBI_EN) {
1967 printk(KERN_INFO "%s: enabling optical transceiver\n",
1968 ndev->name);
1969 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1970
1971 /* setup auto negotiation feature advertisement */
1972 writel(readl(dev->base + TANAR)
1973 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1974 dev->base + TANAR);
1975
1976 /* start auto negotiation */
1977 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1978 dev->base + TBICR);
1979 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1980 dev->linkstate = LINK_AUTONEGOTIATE;
1981
1982 dev->CFG_cache |= CFG_MODE_1000;
1983 }
1984
1985 writel(dev->CFG_cache, dev->base + CFG);
1986 dprintk("CFG: %08x\n", dev->CFG_cache);
1987
1988 if (reset_phy) {
1989 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1990 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1991 msleep(10);
1992 writel(dev->CFG_cache, dev->base + CFG);
1993 }
1994
1995 #if 0 /* Huh? This sets the PCI latency register. Should be done via
1996 * the PCI layer. FIXME.
1997 */
1998 if (readl(dev->base + SRR))
1999 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2000 #endif
2001
2002 /* Note! The DMA burst size interacts with packet
2003 * transmission, such that the largest packet that
2004 * can be transmitted is 8192 - FLTH - burst size.
2005 * If only the transmit fifo was larger...
2006 */
2007 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2008 * some DELL and COMPAQ SMP systems */
2009 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2010 | ((1600 / 32) * 0x100),
2011 dev->base + TXCFG);
2012
2013 /* Flush the interrupt holdoff timer */
2014 writel(0x000, dev->base + IHR);
2015 writel(0x100, dev->base + IHR);
2016 writel(0x000, dev->base + IHR);
2017
2018 /* Set Rx to full duplex, don't accept runt, errored, long or length
2019 * range errored packets. Use 512 byte DMA.
2020 */
2021 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2022 * some DELL and COMPAQ SMP systems
2023 * Turn on ALP, only we are accpeting Jumbo Packets */
2024 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2025 | RXCFG_STRIPCRC
2026 //| RXCFG_ALP
2027 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2028
2029 /* Disable priority queueing */
2030 writel(0, dev->base + PQCR);
2031
2032 /* Enable IP checksum validation and detetion of VLAN headers.
2033 * Note: do not set the reject options as at least the 0x102
2034 * revision of the chip does not properly accept IP fragments
2035 * at least for UDP.
2036 */
2037 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2038 * the MAC it calculates the packetsize AFTER stripping the VLAN
2039 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2040 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2041 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2042 * it discrards it!. These guys......
2043 * also turn on tag stripping if hardware acceleration is enabled
2044 */
2045 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2046 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2047 #else
2048 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2049 #endif
2050 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2051
2052 /* Enable per-packet TCP/UDP/IP checksumming
2053 * and per packet vlan tag insertion if
2054 * vlan hardware acceleration is enabled
2055 */
2056 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2057 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2058 #else
2059 #define VTCR_INIT_VALUE VTCR_PPCHK
2060 #endif
2061 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2062
2063 /* Ramit : Enable async and sync pause frames */
2064 /* writel(0, dev->base + PCR); */
2065 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2066 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2067 dev->base + PCR);
2068
2069 /* Disable Wake On Lan */
2070 writel(0, dev->base + WCSR);
2071
2072 ns83820_getmac(dev, ndev->dev_addr);
2073
2074 /* Yes, we support dumb IP checksum on transmit */
2075 ndev->features |= NETIF_F_SG;
2076 ndev->features |= NETIF_F_IP_CSUM;
2077
2078 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2079 /* We also support hardware vlan acceleration */
2080 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2081 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2082 ndev->vlan_rx_kill_vid = ns83820_vlan_rx_kill_vid;
2083 #endif
2084
2085 if (using_dac) {
2086 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2087 ndev->name);
2088 ndev->features |= NETIF_F_HIGHDMA;
2089 }
2090
2091 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2092 ndev->name,
2093 (unsigned)readl(dev->base + SRR) >> 8,
2094 (unsigned)readl(dev->base + SRR) & 0xff,
2095 ndev->dev_addr[0], ndev->dev_addr[1],
2096 ndev->dev_addr[2], ndev->dev_addr[3],
2097 ndev->dev_addr[4], ndev->dev_addr[5],
2098 addr, pci_dev->irq,
2099 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2100 );
2101
2102 #ifdef PHY_CODE_IS_FINISHED
2103 ns83820_probe_phy(ndev);
2104 #endif
2105
2106 err = register_netdevice(ndev);
2107 if (err) {
2108 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2109 goto out_cleanup;
2110 }
2111 rtnl_unlock();
2112
2113 return 0;
2114
2115 out_cleanup:
2116 writel(0, dev->base + IMR); /* paranoia */
2117 writel(0, dev->base + IER);
2118 readl(dev->base + IER);
2119 out_free_irq:
2120 rtnl_unlock();
2121 free_irq(pci_dev->irq, ndev);
2122 out_disable:
2123 if (dev->base)
2124 iounmap(dev->base);
2125 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2126 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2127 pci_disable_device(pci_dev);
2128 out_free:
2129 free_netdev(ndev);
2130 pci_set_drvdata(pci_dev, NULL);
2131 out:
2132 return err;
2133 }
2134
2135 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2136 {
2137 struct net_device *ndev = pci_get_drvdata(pci_dev);
2138 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2139
2140 if (!ndev) /* paranoia */
2141 return;
2142
2143 writel(0, dev->base + IMR); /* paranoia */
2144 writel(0, dev->base + IER);
2145 readl(dev->base + IER);
2146
2147 unregister_netdev(ndev);
2148 free_irq(dev->pci_dev->irq, ndev);
2149 iounmap(dev->base);
2150 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2151 dev->tx_descs, dev->tx_phy_descs);
2152 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2153 dev->rx_info.descs, dev->rx_info.phy_descs);
2154 pci_disable_device(dev->pci_dev);
2155 free_netdev(ndev);
2156 pci_set_drvdata(pci_dev, NULL);
2157 }
2158
2159 static struct pci_device_id ns83820_pci_tbl[] = {
2160 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2161 { 0, },
2162 };
2163
2164 static struct pci_driver driver = {
2165 .name = "ns83820",
2166 .id_table = ns83820_pci_tbl,
2167 .probe = ns83820_init_one,
2168 .remove = __devexit_p(ns83820_remove_one),
2169 #if 0 /* FIXME: implement */
2170 .suspend = ,
2171 .resume = ,
2172 #endif
2173 };
2174
2175
2176 static int __init ns83820_init(void)
2177 {
2178 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2179 return pci_module_init(&driver);
2180 }
2181
2182 static void __exit ns83820_exit(void)
2183 {
2184 pci_unregister_driver(&driver);
2185 }
2186
2187 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2188 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2189 MODULE_LICENSE("GPL");
2190
2191 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2192
2193 module_param(lnksts, int, 0);
2194 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2195
2196 module_param(ihr, int, 0);
2197 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2198
2199 module_param(reset_phy, int, 0);
2200 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2201
2202 module_init(ns83820_init);
2203 module_exit(ns83820_exit);
Linux with added FPC-III support