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Linux 2.6.17.7
[linux/fpc-iii.git] / drivers / net / tg3.c
blob862c226dbbe24cb59326100cd9c1738d2d10aa0c
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18 #include <linux/config.h>
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/workqueue.h>
40 #include <linux/prefetch.h>
41 #include <linux/dma-mapping.h>
42
43 #include <net/checksum.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC64
51 #include <asm/idprom.h>
52 #include <asm/oplib.h>
53 #include <asm/pbm.h>
54 #endif
55
56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
57 #define TG3_VLAN_TAG_USED 1
58 #else
59 #define TG3_VLAN_TAG_USED 0
60 #endif
61
62 #ifdef NETIF_F_TSO
63 #define TG3_TSO_SUPPORT 1
64 #else
65 #define TG3_TSO_SUPPORT 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME "tg3"
71 #define PFX DRV_MODULE_NAME ": "
72 #define DRV_MODULE_VERSION "3.59"
73 #define DRV_MODULE_RELDATE "June 8, 2006"
74
75 #define TG3_DEF_MAC_MODE 0
76 #define TG3_DEF_RX_MODE 0
77 #define TG3_DEF_TX_MODE 0
78 #define TG3_DEF_MSG_ENABLE \
79 (NETIF_MSG_DRV | \
80 NETIF_MSG_PROBE | \
81 NETIF_MSG_LINK | \
82 NETIF_MSG_TIMER | \
83 NETIF_MSG_IFDOWN | \
84 NETIF_MSG_IFUP | \
85 NETIF_MSG_RX_ERR | \
86 NETIF_MSG_TX_ERR)
87
88 /* length of time before we decide the hardware is borked,
89 * and dev->tx_timeout() should be called to fix the problem
90 */
91 #define TG3_TX_TIMEOUT (5 * HZ)
92
93 /* hardware minimum and maximum for a single frame's data payload */
94 #define TG3_MIN_MTU 60
95 #define TG3_MAX_MTU(tp) \
96 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
97
98 /* These numbers seem to be hard coded in the NIC firmware somehow.
99 * You can't change the ring sizes, but you can change where you place
100 * them in the NIC onboard memory.
101 */
102 #define TG3_RX_RING_SIZE 512
103 #define TG3_DEF_RX_RING_PENDING 200
104 #define TG3_RX_JUMBO_RING_SIZE 256
105 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
106
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RING_SIZE)
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
127 #define TX_BUFFS_AVAIL(TP) \
128 ((TP)->tx_pending - \
129 (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
130 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
131
132 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
133 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
134
135 /* minimum number of free TX descriptors required to wake up TX process */
136 #define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
137
138 /* number of ETHTOOL_GSTATS u64's */
139 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
140
141 #define TG3_NUM_TEST 6
142
143 static char version[] __devinitdata =
144 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
145
146 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
147 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
148 MODULE_LICENSE("GPL");
149 MODULE_VERSION(DRV_MODULE_VERSION);
150
151 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
152 module_param(tg3_debug, int, 0);
153 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
154
155 static struct pci_device_id tg3_pci_tbl[] = {
156 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
158 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
160 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
162 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
164 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
166 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
168 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
170 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
172 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
174 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
176 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
178 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
180 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
182 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
184 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
186 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
188 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
190 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
192 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
194 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
196 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
198 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
200 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
202 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
204 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
206 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
208 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
210 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
212 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
214 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
216 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
218 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
220 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
228 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
230 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
232 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
236 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
244 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
246 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
248 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
250 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
252 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
254 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
256 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
258 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
260 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
262 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
264 { 0, }
265 };
266
267 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
268
269 static struct {
270 const char string[ETH_GSTRING_LEN];
271 } ethtool_stats_keys[TG3_NUM_STATS] = {
272 { "rx_octets" },
273 { "rx_fragments" },
274 { "rx_ucast_packets" },
275 { "rx_mcast_packets" },
276 { "rx_bcast_packets" },
277 { "rx_fcs_errors" },
278 { "rx_align_errors" },
279 { "rx_xon_pause_rcvd" },
280 { "rx_xoff_pause_rcvd" },
281 { "rx_mac_ctrl_rcvd" },
282 { "rx_xoff_entered" },
283 { "rx_frame_too_long_errors" },
284 { "rx_jabbers" },
285 { "rx_undersize_packets" },
286 { "rx_in_length_errors" },
287 { "rx_out_length_errors" },
288 { "rx_64_or_less_octet_packets" },
289 { "rx_65_to_127_octet_packets" },
290 { "rx_128_to_255_octet_packets" },
291 { "rx_256_to_511_octet_packets" },
292 { "rx_512_to_1023_octet_packets" },
293 { "rx_1024_to_1522_octet_packets" },
294 { "rx_1523_to_2047_octet_packets" },
295 { "rx_2048_to_4095_octet_packets" },
296 { "rx_4096_to_8191_octet_packets" },
297 { "rx_8192_to_9022_octet_packets" },
298
299 { "tx_octets" },
300 { "tx_collisions" },
301
302 { "tx_xon_sent" },
303 { "tx_xoff_sent" },
304 { "tx_flow_control" },
305 { "tx_mac_errors" },
306 { "tx_single_collisions" },
307 { "tx_mult_collisions" },
308 { "tx_deferred" },
309 { "tx_excessive_collisions" },
310 { "tx_late_collisions" },
311 { "tx_collide_2times" },
312 { "tx_collide_3times" },
313 { "tx_collide_4times" },
314 { "tx_collide_5times" },
315 { "tx_collide_6times" },
316 { "tx_collide_7times" },
317 { "tx_collide_8times" },
318 { "tx_collide_9times" },
319 { "tx_collide_10times" },
320 { "tx_collide_11times" },
321 { "tx_collide_12times" },
322 { "tx_collide_13times" },
323 { "tx_collide_14times" },
324 { "tx_collide_15times" },
325 { "tx_ucast_packets" },
326 { "tx_mcast_packets" },
327 { "tx_bcast_packets" },
328 { "tx_carrier_sense_errors" },
329 { "tx_discards" },
330 { "tx_errors" },
331
332 { "dma_writeq_full" },
333 { "dma_write_prioq_full" },
334 { "rxbds_empty" },
335 { "rx_discards" },
336 { "rx_errors" },
337 { "rx_threshold_hit" },
338
339 { "dma_readq_full" },
340 { "dma_read_prioq_full" },
341 { "tx_comp_queue_full" },
342
343 { "ring_set_send_prod_index" },
344 { "ring_status_update" },
345 { "nic_irqs" },
346 { "nic_avoided_irqs" },
347 { "nic_tx_threshold_hit" }
348 };
349
350 static struct {
351 const char string[ETH_GSTRING_LEN];
352 } ethtool_test_keys[TG3_NUM_TEST] = {
353 { "nvram test (online) " },
354 { "link test (online) " },
355 { "register test (offline)" },
356 { "memory test (offline)" },
357 { "loopback test (offline)" },
358 { "interrupt test (offline)" },
359 };
360
361 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
362 {
363 writel(val, tp->regs + off);
364 }
365
366 static u32 tg3_read32(struct tg3 *tp, u32 off)
367 {
368 return (readl(tp->regs + off));
369 }
370
371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
372 {
373 unsigned long flags;
374
375 spin_lock_irqsave(&tp->indirect_lock, flags);
376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
379 }
380
381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
382 {
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
385 }
386
387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
388 {
389 unsigned long flags;
390 u32 val;
391
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
396 return val;
397 }
398
399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
400 {
401 unsigned long flags;
402
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
406 return;
407 }
408 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
411 return;
412 }
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
421 */
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
423 (val == 0x1)) {
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
426 }
427 }
428
429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
430 {
431 unsigned long flags;
432 u32 val;
433
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
438 return val;
439 }
440
441 /* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
445 */
446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
447 {
448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
452 else {
453 /* Posted method */
454 tg3_write32(tp, off, val);
455 if (usec_wait)
456 udelay(usec_wait);
457 tp->read32(tp, off);
458 }
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
461 */
462 if (usec_wait)
463 udelay(usec_wait);
464 }
465
466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
467 {
468 tp->write32_mbox(tp, off, val);
469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
472 }
473
474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
475 {
476 void __iomem *mbox = tp->regs + off;
477 writel(val, mbox);
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
479 writel(val, mbox);
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
481 readl(mbox);
482 }
483
484 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
485 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
486 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
487 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
488 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
489
490 #define tw32(reg,val) tp->write32(tp, reg, val)
491 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
492 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
493 #define tr32(reg) tp->read32(tp, reg)
494
495 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
496 {
497 unsigned long flags;
498
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
501 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
502 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
503
504 /* Always leave this as zero. */
505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 } else {
507 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
508 tw32_f(TG3PCI_MEM_WIN_DATA, val);
509
510 /* Always leave this as zero. */
511 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
512 }
513 spin_unlock_irqrestore(&tp->indirect_lock, flags);
514 }
515
516 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
517 {
518 unsigned long flags;
519
520 spin_lock_irqsave(&tp->indirect_lock, flags);
521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
524
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
535 }
536
537 static void tg3_disable_ints(struct tg3 *tp)
538 {
539 tw32(TG3PCI_MISC_HOST_CTRL,
540 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
541 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
542 }
543
544 static inline void tg3_cond_int(struct tg3 *tp)
545 {
546 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
547 (tp->hw_status->status & SD_STATUS_UPDATED))
548 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
549 }
550
551 static void tg3_enable_ints(struct tg3 *tp)
552 {
553 tp->irq_sync = 0;
554 wmb();
555
556 tw32(TG3PCI_MISC_HOST_CTRL,
557 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
558 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
559 (tp->last_tag << 24));
560 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
561 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
562 (tp->last_tag << 24));
563 tg3_cond_int(tp);
564 }
565
566 static inline unsigned int tg3_has_work(struct tg3 *tp)
567 {
568 struct tg3_hw_status *sblk = tp->hw_status;
569 unsigned int work_exists = 0;
570
571 /* check for phy events */
572 if (!(tp->tg3_flags &
573 (TG3_FLAG_USE_LINKCHG_REG |
574 TG3_FLAG_POLL_SERDES))) {
575 if (sblk->status & SD_STATUS_LINK_CHG)
576 work_exists = 1;
577 }
578 /* check for RX/TX work to do */
579 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
580 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
581 work_exists = 1;
582
583 return work_exists;
584 }
585
586 /* tg3_restart_ints
587 * similar to tg3_enable_ints, but it accurately determines whether there
588 * is new work pending and can return without flushing the PIO write
589 * which reenables interrupts
590 */
591 static void tg3_restart_ints(struct tg3 *tp)
592 {
593 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
594 tp->last_tag << 24);
595 mmiowb();
596
597 /* When doing tagged status, this work check is unnecessary.
598 * The last_tag we write above tells the chip which piece of
599 * work we've completed.
600 */
601 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
602 tg3_has_work(tp))
603 tw32(HOSTCC_MODE, tp->coalesce_mode |
604 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
605 }
606
607 static inline void tg3_netif_stop(struct tg3 *tp)
608 {
609 tp->dev->trans_start = jiffies; /* prevent tx timeout */
610 netif_poll_disable(tp->dev);
611 netif_tx_disable(tp->dev);
612 }
613
614 static inline void tg3_netif_start(struct tg3 *tp)
615 {
616 netif_wake_queue(tp->dev);
617 /* NOTE: unconditional netif_wake_queue is only appropriate
618 * so long as all callers are assured to have free tx slots
619 * (such as after tg3_init_hw)
620 */
621 netif_poll_enable(tp->dev);
622 tp->hw_status->status |= SD_STATUS_UPDATED;
623 tg3_enable_ints(tp);
624 }
625
626 static void tg3_switch_clocks(struct tg3 *tp)
627 {
628 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
629 u32 orig_clock_ctrl;
630
631 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
632 return;
633
634 orig_clock_ctrl = clock_ctrl;
635 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
636 CLOCK_CTRL_CLKRUN_OENABLE |
637 0x1f);
638 tp->pci_clock_ctrl = clock_ctrl;
639
640 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
641 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
642 tw32_wait_f(TG3PCI_CLOCK_CTRL,
643 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
644 }
645 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
646 tw32_wait_f(TG3PCI_CLOCK_CTRL,
647 clock_ctrl |
648 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
649 40);
650 tw32_wait_f(TG3PCI_CLOCK_CTRL,
651 clock_ctrl | (CLOCK_CTRL_ALTCLK),
652 40);
653 }
654 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
655 }
656
657 #define PHY_BUSY_LOOPS 5000
658
659 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
660 {
661 u32 frame_val;
662 unsigned int loops;
663 int ret;
664
665 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
666 tw32_f(MAC_MI_MODE,
667 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
668 udelay(80);
669 }
670
671 *val = 0x0;
672
673 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
674 MI_COM_PHY_ADDR_MASK);
675 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
676 MI_COM_REG_ADDR_MASK);
677 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
678
679 tw32_f(MAC_MI_COM, frame_val);
680
681 loops = PHY_BUSY_LOOPS;
682 while (loops != 0) {
683 udelay(10);
684 frame_val = tr32(MAC_MI_COM);
685
686 if ((frame_val & MI_COM_BUSY) == 0) {
687 udelay(5);
688 frame_val = tr32(MAC_MI_COM);
689 break;
690 }
691 loops -= 1;
692 }
693
694 ret = -EBUSY;
695 if (loops != 0) {
696 *val = frame_val & MI_COM_DATA_MASK;
697 ret = 0;
698 }
699
700 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
701 tw32_f(MAC_MI_MODE, tp->mi_mode);
702 udelay(80);
703 }
704
705 return ret;
706 }
707
708 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
709 {
710 u32 frame_val;
711 unsigned int loops;
712 int ret;
713
714 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
715 tw32_f(MAC_MI_MODE,
716 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
717 udelay(80);
718 }
719
720 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
721 MI_COM_PHY_ADDR_MASK);
722 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
723 MI_COM_REG_ADDR_MASK);
724 frame_val |= (val & MI_COM_DATA_MASK);
725 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
726
727 tw32_f(MAC_MI_COM, frame_val);
728
729 loops = PHY_BUSY_LOOPS;
730 while (loops != 0) {
731 udelay(10);
732 frame_val = tr32(MAC_MI_COM);
733 if ((frame_val & MI_COM_BUSY) == 0) {
734 udelay(5);
735 frame_val = tr32(MAC_MI_COM);
736 break;
737 }
738 loops -= 1;
739 }
740
741 ret = -EBUSY;
742 if (loops != 0)
743 ret = 0;
744
745 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
746 tw32_f(MAC_MI_MODE, tp->mi_mode);
747 udelay(80);
748 }
749
750 return ret;
751 }
752
753 static void tg3_phy_set_wirespeed(struct tg3 *tp)
754 {
755 u32 val;
756
757 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
758 return;
759
760 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
761 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
762 tg3_writephy(tp, MII_TG3_AUX_CTRL,
763 (val | (1 << 15) | (1 << 4)));
764 }
765
766 static int tg3_bmcr_reset(struct tg3 *tp)
767 {
768 u32 phy_control;
769 int limit, err;
770
771 /* OK, reset it, and poll the BMCR_RESET bit until it
772 * clears or we time out.
773 */
774 phy_control = BMCR_RESET;
775 err = tg3_writephy(tp, MII_BMCR, phy_control);
776 if (err != 0)
777 return -EBUSY;
778
779 limit = 5000;
780 while (limit--) {
781 err = tg3_readphy(tp, MII_BMCR, &phy_control);
782 if (err != 0)
783 return -EBUSY;
784
785 if ((phy_control & BMCR_RESET) == 0) {
786 udelay(40);
787 break;
788 }
789 udelay(10);
790 }
791 if (limit <= 0)
792 return -EBUSY;
793
794 return 0;
795 }
796
797 static int tg3_wait_macro_done(struct tg3 *tp)
798 {
799 int limit = 100;
800
801 while (limit--) {
802 u32 tmp32;
803
804 if (!tg3_readphy(tp, 0x16, &tmp32)) {
805 if ((tmp32 & 0x1000) == 0)
806 break;
807 }
808 }
809 if (limit <= 0)
810 return -EBUSY;
811
812 return 0;
813 }
814
815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
816 {
817 static const u32 test_pat[4][6] = {
818 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
819 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
820 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
821 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
822 };
823 int chan;
824
825 for (chan = 0; chan < 4; chan++) {
826 int i;
827
828 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
829 (chan * 0x2000) | 0x0200);
830 tg3_writephy(tp, 0x16, 0x0002);
831
832 for (i = 0; i < 6; i++)
833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
834 test_pat[chan][i]);
835
836 tg3_writephy(tp, 0x16, 0x0202);
837 if (tg3_wait_macro_done(tp)) {
838 *resetp = 1;
839 return -EBUSY;
840 }
841
842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
843 (chan * 0x2000) | 0x0200);
844 tg3_writephy(tp, 0x16, 0x0082);
845 if (tg3_wait_macro_done(tp)) {
846 *resetp = 1;
847 return -EBUSY;
848 }
849
850 tg3_writephy(tp, 0x16, 0x0802);
851 if (tg3_wait_macro_done(tp)) {
852 *resetp = 1;
853 return -EBUSY;
854 }
855
856 for (i = 0; i < 6; i += 2) {
857 u32 low, high;
858
859 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
860 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
861 tg3_wait_macro_done(tp)) {
862 *resetp = 1;
863 return -EBUSY;
864 }
865 low &= 0x7fff;
866 high &= 0x000f;
867 if (low != test_pat[chan][i] ||
868 high != test_pat[chan][i+1]) {
869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
871 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
872
873 return -EBUSY;
874 }
875 }
876 }
877
878 return 0;
879 }
880
881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
882 {
883 int chan;
884
885 for (chan = 0; chan < 4; chan++) {
886 int i;
887
888 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
889 (chan * 0x2000) | 0x0200);
890 tg3_writephy(tp, 0x16, 0x0002);
891 for (i = 0; i < 6; i++)
892 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
893 tg3_writephy(tp, 0x16, 0x0202);
894 if (tg3_wait_macro_done(tp))
895 return -EBUSY;
896 }
897
898 return 0;
899 }
900
901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
902 {
903 u32 reg32, phy9_orig;
904 int retries, do_phy_reset, err;
905
906 retries = 10;
907 do_phy_reset = 1;
908 do {
909 if (do_phy_reset) {
910 err = tg3_bmcr_reset(tp);
911 if (err)
912 return err;
913 do_phy_reset = 0;
914 }
915
916 /* Disable transmitter and interrupt. */
917 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
918 continue;
919
920 reg32 |= 0x3000;
921 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
922
923 /* Set full-duplex, 1000 mbps. */
924 tg3_writephy(tp, MII_BMCR,
925 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
926
927 /* Set to master mode. */
928 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
929 continue;
930
931 tg3_writephy(tp, MII_TG3_CTRL,
932 (MII_TG3_CTRL_AS_MASTER |
933 MII_TG3_CTRL_ENABLE_AS_MASTER));
934
935 /* Enable SM_DSP_CLOCK and 6dB. */
936 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
937
938 /* Block the PHY control access. */
939 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
940 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
941
942 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
943 if (!err)
944 break;
945 } while (--retries);
946
947 err = tg3_phy_reset_chanpat(tp);
948 if (err)
949 return err;
950
951 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
953
954 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
955 tg3_writephy(tp, 0x16, 0x0000);
956
957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
959 /* Set Extended packet length bit for jumbo frames */
960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
961 }
962 else {
963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
964 }
965
966 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
967
968 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
969 reg32 &= ~0x3000;
970 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
971 } else if (!err)
972 err = -EBUSY;
973
974 return err;
975 }
976
977 static void tg3_link_report(struct tg3 *);
978
979 /* This will reset the tigon3 PHY if there is no valid
980 * link unless the FORCE argument is non-zero.
981 */
982 static int tg3_phy_reset(struct tg3 *tp)
983 {
984 u32 phy_status;
985 int err;
986
987 err = tg3_readphy(tp, MII_BMSR, &phy_status);
988 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
989 if (err != 0)
990 return -EBUSY;
991
992 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
993 netif_carrier_off(tp->dev);
994 tg3_link_report(tp);
995 }
996
997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1000 err = tg3_phy_reset_5703_4_5(tp);
1001 if (err)
1002 return err;
1003 goto out;
1004 }
1005
1006 err = tg3_bmcr_reset(tp);
1007 if (err)
1008 return err;
1009
1010 out:
1011 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1014 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1015 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1016 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1017 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1018 }
1019 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1020 tg3_writephy(tp, 0x1c, 0x8d68);
1021 tg3_writephy(tp, 0x1c, 0x8d68);
1022 }
1023 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1024 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1025 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1026 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1027 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1028 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1031 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1032 }
1033 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1034 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1035 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1036 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1037 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1038 }
1039 /* Set Extended packet length bit (bit 14) on all chips that */
1040 /* support jumbo frames */
1041 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1042 /* Cannot do read-modify-write on 5401 */
1043 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1044 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1045 u32 phy_reg;
1046
1047 /* Set bit 14 with read-modify-write to preserve other bits */
1048 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1049 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1050 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1051 }
1052
1053 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1054 * jumbo frames transmission.
1055 */
1056 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1057 u32 phy_reg;
1058
1059 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1060 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1061 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1062 }
1063
1064 tg3_phy_set_wirespeed(tp);
1065 return 0;
1066 }
1067
1068 static void tg3_frob_aux_power(struct tg3 *tp)
1069 {
1070 struct tg3 *tp_peer = tp;
1071
1072 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1073 return;
1074
1075 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1076 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1077 struct net_device *dev_peer;
1078
1079 dev_peer = pci_get_drvdata(tp->pdev_peer);
1080 /* remove_one() may have been run on the peer. */
1081 if (!dev_peer)
1082 tp_peer = tp;
1083 else
1084 tp_peer = netdev_priv(dev_peer);
1085 }
1086
1087 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1088 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1089 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1090 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1094 (GRC_LCLCTRL_GPIO_OE0 |
1095 GRC_LCLCTRL_GPIO_OE1 |
1096 GRC_LCLCTRL_GPIO_OE2 |
1097 GRC_LCLCTRL_GPIO_OUTPUT0 |
1098 GRC_LCLCTRL_GPIO_OUTPUT1),
1099 100);
1100 } else {
1101 u32 no_gpio2;
1102 u32 grc_local_ctrl = 0;
1103
1104 if (tp_peer != tp &&
1105 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1106 return;
1107
1108 /* Workaround to prevent overdrawing Amps. */
1109 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1110 ASIC_REV_5714) {
1111 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1112 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1113 grc_local_ctrl, 100);
1114 }
1115
1116 /* On 5753 and variants, GPIO2 cannot be used. */
1117 no_gpio2 = tp->nic_sram_data_cfg &
1118 NIC_SRAM_DATA_CFG_NO_GPIO2;
1119
1120 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1121 GRC_LCLCTRL_GPIO_OE1 |
1122 GRC_LCLCTRL_GPIO_OE2 |
1123 GRC_LCLCTRL_GPIO_OUTPUT1 |
1124 GRC_LCLCTRL_GPIO_OUTPUT2;
1125 if (no_gpio2) {
1126 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1127 GRC_LCLCTRL_GPIO_OUTPUT2);
1128 }
1129 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1130 grc_local_ctrl, 100);
1131
1132 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1133
1134 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1135 grc_local_ctrl, 100);
1136
1137 if (!no_gpio2) {
1138 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140 grc_local_ctrl, 100);
1141 }
1142 }
1143 } else {
1144 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1145 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1146 if (tp_peer != tp &&
1147 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1148 return;
1149
1150 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1151 (GRC_LCLCTRL_GPIO_OE1 |
1152 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1153
1154 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1155 GRC_LCLCTRL_GPIO_OE1, 100);
1156
1157 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1158 (GRC_LCLCTRL_GPIO_OE1 |
1159 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1160 }
1161 }
1162 }
1163
1164 static int tg3_setup_phy(struct tg3 *, int);
1165
1166 #define RESET_KIND_SHUTDOWN 0
1167 #define RESET_KIND_INIT 1
1168 #define RESET_KIND_SUSPEND 2
1169
1170 static void tg3_write_sig_post_reset(struct tg3 *, int);
1171 static int tg3_halt_cpu(struct tg3 *, u32);
1172 static int tg3_nvram_lock(struct tg3 *);
1173 static void tg3_nvram_unlock(struct tg3 *);
1174
1175 static void tg3_power_down_phy(struct tg3 *tp)
1176 {
1177 /* The PHY should not be powered down on some chips because
1178 * of bugs.
1179 */
1180 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1181 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1182 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1183 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1184 return;
1185 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1186 }
1187
1188 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1189 {
1190 u32 misc_host_ctrl;
1191 u16 power_control, power_caps;
1192 int pm = tp->pm_cap;
1193
1194 /* Make sure register accesses (indirect or otherwise)
1195 * will function correctly.
1196 */
1197 pci_write_config_dword(tp->pdev,
1198 TG3PCI_MISC_HOST_CTRL,
1199 tp->misc_host_ctrl);
1200
1201 pci_read_config_word(tp->pdev,
1202 pm + PCI_PM_CTRL,
1203 &power_control);
1204 power_control |= PCI_PM_CTRL_PME_STATUS;
1205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1206 switch (state) {
1207 case PCI_D0:
1208 power_control |= 0;
1209 pci_write_config_word(tp->pdev,
1210 pm + PCI_PM_CTRL,
1211 power_control);
1212 udelay(100); /* Delay after power state change */
1213
1214 /* Switch out of Vaux if it is not a LOM */
1215 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1216 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1217
1218 return 0;
1219
1220 case PCI_D1:
1221 power_control |= 1;
1222 break;
1223
1224 case PCI_D2:
1225 power_control |= 2;
1226 break;
1227
1228 case PCI_D3hot:
1229 power_control |= 3;
1230 break;
1231
1232 default:
1233 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1234 "requested.\n",
1235 tp->dev->name, state);
1236 return -EINVAL;
1237 };
1238
1239 power_control |= PCI_PM_CTRL_PME_ENABLE;
1240
1241 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1242 tw32(TG3PCI_MISC_HOST_CTRL,
1243 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1244
1245 if (tp->link_config.phy_is_low_power == 0) {
1246 tp->link_config.phy_is_low_power = 1;
1247 tp->link_config.orig_speed = tp->link_config.speed;
1248 tp->link_config.orig_duplex = tp->link_config.duplex;
1249 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1250 }
1251
1252 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1253 tp->link_config.speed = SPEED_10;
1254 tp->link_config.duplex = DUPLEX_HALF;
1255 tp->link_config.autoneg = AUTONEG_ENABLE;
1256 tg3_setup_phy(tp, 0);
1257 }
1258
1259 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1260 int i;
1261 u32 val;
1262
1263 for (i = 0; i < 200; i++) {
1264 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1265 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1266 break;
1267 msleep(1);
1268 }
1269 }
1270 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1271 WOL_DRV_STATE_SHUTDOWN |
1272 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1273
1274 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1275
1276 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1277 u32 mac_mode;
1278
1279 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1280 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1281 udelay(40);
1282
1283 mac_mode = MAC_MODE_PORT_MODE_MII;
1284
1285 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1286 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1287 mac_mode |= MAC_MODE_LINK_POLARITY;
1288 } else {
1289 mac_mode = MAC_MODE_PORT_MODE_TBI;
1290 }
1291
1292 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1293 tw32(MAC_LED_CTRL, tp->led_ctrl);
1294
1295 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1296 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1297 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1298
1299 tw32_f(MAC_MODE, mac_mode);
1300 udelay(100);
1301
1302 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1303 udelay(10);
1304 }
1305
1306 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1307 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1309 u32 base_val;
1310
1311 base_val = tp->pci_clock_ctrl;
1312 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1313 CLOCK_CTRL_TXCLK_DISABLE);
1314
1315 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1316 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1317 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1318 /* do nothing */
1319 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1320 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1321 u32 newbits1, newbits2;
1322
1323 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1325 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1326 CLOCK_CTRL_TXCLK_DISABLE |
1327 CLOCK_CTRL_ALTCLK);
1328 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1329 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1330 newbits1 = CLOCK_CTRL_625_CORE;
1331 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1332 } else {
1333 newbits1 = CLOCK_CTRL_ALTCLK;
1334 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1335 }
1336
1337 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1338 40);
1339
1340 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1341 40);
1342
1343 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1344 u32 newbits3;
1345
1346 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1347 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1348 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1349 CLOCK_CTRL_TXCLK_DISABLE |
1350 CLOCK_CTRL_44MHZ_CORE);
1351 } else {
1352 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1353 }
1354
1355 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1356 tp->pci_clock_ctrl | newbits3, 40);
1357 }
1358 }
1359
1360 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1361 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1362 /* Turn off the PHY */
1363 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1364 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1365 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1366 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1367 tg3_power_down_phy(tp);
1368 }
1369 }
1370
1371 tg3_frob_aux_power(tp);
1372
1373 /* Workaround for unstable PLL clock */
1374 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1375 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1376 u32 val = tr32(0x7d00);
1377
1378 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1379 tw32(0x7d00, val);
1380 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1381 int err;
1382
1383 err = tg3_nvram_lock(tp);
1384 tg3_halt_cpu(tp, RX_CPU_BASE);
1385 if (!err)
1386 tg3_nvram_unlock(tp);
1387 }
1388 }
1389
1390 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1391
1392 /* Finally, set the new power state. */
1393 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1394 udelay(100); /* Delay after power state change */
1395
1396 return 0;
1397 }
1398
1399 static void tg3_link_report(struct tg3 *tp)
1400 {
1401 if (!netif_carrier_ok(tp->dev)) {
1402 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1403 } else {
1404 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1405 tp->dev->name,
1406 (tp->link_config.active_speed == SPEED_1000 ?
1407 1000 :
1408 (tp->link_config.active_speed == SPEED_100 ?
1409 100 : 10)),
1410 (tp->link_config.active_duplex == DUPLEX_FULL ?
1411 "full" : "half"));
1412
1413 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1414 "%s for RX.\n",
1415 tp->dev->name,
1416 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1417 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1418 }
1419 }
1420
1421 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1422 {
1423 u32 new_tg3_flags = 0;
1424 u32 old_rx_mode = tp->rx_mode;
1425 u32 old_tx_mode = tp->tx_mode;
1426
1427 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1428
1429 /* Convert 1000BaseX flow control bits to 1000BaseT
1430 * bits before resolving flow control.
1431 */
1432 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1433 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1434 ADVERTISE_PAUSE_ASYM);
1435 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1436
1437 if (local_adv & ADVERTISE_1000XPAUSE)
1438 local_adv |= ADVERTISE_PAUSE_CAP;
1439 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1440 local_adv |= ADVERTISE_PAUSE_ASYM;
1441 if (remote_adv & LPA_1000XPAUSE)
1442 remote_adv |= LPA_PAUSE_CAP;
1443 if (remote_adv & LPA_1000XPAUSE_ASYM)
1444 remote_adv |= LPA_PAUSE_ASYM;
1445 }
1446
1447 if (local_adv & ADVERTISE_PAUSE_CAP) {
1448 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1449 if (remote_adv & LPA_PAUSE_CAP)
1450 new_tg3_flags |=
1451 (TG3_FLAG_RX_PAUSE |
1452 TG3_FLAG_TX_PAUSE);
1453 else if (remote_adv & LPA_PAUSE_ASYM)
1454 new_tg3_flags |=
1455 (TG3_FLAG_RX_PAUSE);
1456 } else {
1457 if (remote_adv & LPA_PAUSE_CAP)
1458 new_tg3_flags |=
1459 (TG3_FLAG_RX_PAUSE |
1460 TG3_FLAG_TX_PAUSE);
1461 }
1462 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1463 if ((remote_adv & LPA_PAUSE_CAP) &&
1464 (remote_adv & LPA_PAUSE_ASYM))
1465 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1466 }
1467
1468 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1469 tp->tg3_flags |= new_tg3_flags;
1470 } else {
1471 new_tg3_flags = tp->tg3_flags;
1472 }
1473
1474 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1475 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1476 else
1477 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1478
1479 if (old_rx_mode != tp->rx_mode) {
1480 tw32_f(MAC_RX_MODE, tp->rx_mode);
1481 }
1482
1483 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1484 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1485 else
1486 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1487
1488 if (old_tx_mode != tp->tx_mode) {
1489 tw32_f(MAC_TX_MODE, tp->tx_mode);
1490 }
1491 }
1492
1493 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1494 {
1495 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1496 case MII_TG3_AUX_STAT_10HALF:
1497 *speed = SPEED_10;
1498 *duplex = DUPLEX_HALF;
1499 break;
1500
1501 case MII_TG3_AUX_STAT_10FULL:
1502 *speed = SPEED_10;
1503 *duplex = DUPLEX_FULL;
1504 break;
1505
1506 case MII_TG3_AUX_STAT_100HALF:
1507 *speed = SPEED_100;
1508 *duplex = DUPLEX_HALF;
1509 break;
1510
1511 case MII_TG3_AUX_STAT_100FULL:
1512 *speed = SPEED_100;
1513 *duplex = DUPLEX_FULL;
1514 break;
1515
1516 case MII_TG3_AUX_STAT_1000HALF:
1517 *speed = SPEED_1000;
1518 *duplex = DUPLEX_HALF;
1519 break;
1520
1521 case MII_TG3_AUX_STAT_1000FULL:
1522 *speed = SPEED_1000;
1523 *duplex = DUPLEX_FULL;
1524 break;
1525
1526 default:
1527 *speed = SPEED_INVALID;
1528 *duplex = DUPLEX_INVALID;
1529 break;
1530 };
1531 }
1532
1533 static void tg3_phy_copper_begin(struct tg3 *tp)
1534 {
1535 u32 new_adv;
1536 int i;
1537
1538 if (tp->link_config.phy_is_low_power) {
1539 /* Entering low power mode. Disable gigabit and
1540 * 100baseT advertisements.
1541 */
1542 tg3_writephy(tp, MII_TG3_CTRL, 0);
1543
1544 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1545 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1546 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1547 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1548
1549 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1550 } else if (tp->link_config.speed == SPEED_INVALID) {
1551 tp->link_config.advertising =
1552 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1553 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1554 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1555 ADVERTISED_Autoneg | ADVERTISED_MII);
1556
1557 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1558 tp->link_config.advertising &=
1559 ~(ADVERTISED_1000baseT_Half |
1560 ADVERTISED_1000baseT_Full);
1561
1562 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1563 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1564 new_adv |= ADVERTISE_10HALF;
1565 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1566 new_adv |= ADVERTISE_10FULL;
1567 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1568 new_adv |= ADVERTISE_100HALF;
1569 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1570 new_adv |= ADVERTISE_100FULL;
1571 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1572
1573 if (tp->link_config.advertising &
1574 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1575 new_adv = 0;
1576 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1577 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1578 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1579 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1580 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1581 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1582 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1583 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1584 MII_TG3_CTRL_ENABLE_AS_MASTER);
1585 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1586 } else {
1587 tg3_writephy(tp, MII_TG3_CTRL, 0);
1588 }
1589 } else {
1590 /* Asking for a specific link mode. */
1591 if (tp->link_config.speed == SPEED_1000) {
1592 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1593 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1594
1595 if (tp->link_config.duplex == DUPLEX_FULL)
1596 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1597 else
1598 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1599 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1600 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1601 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1602 MII_TG3_CTRL_ENABLE_AS_MASTER);
1603 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1604 } else {
1605 tg3_writephy(tp, MII_TG3_CTRL, 0);
1606
1607 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1608 if (tp->link_config.speed == SPEED_100) {
1609 if (tp->link_config.duplex == DUPLEX_FULL)
1610 new_adv |= ADVERTISE_100FULL;
1611 else
1612 new_adv |= ADVERTISE_100HALF;
1613 } else {
1614 if (tp->link_config.duplex == DUPLEX_FULL)
1615 new_adv |= ADVERTISE_10FULL;
1616 else
1617 new_adv |= ADVERTISE_10HALF;
1618 }
1619 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1620 }
1621 }
1622
1623 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1624 tp->link_config.speed != SPEED_INVALID) {
1625 u32 bmcr, orig_bmcr;
1626
1627 tp->link_config.active_speed = tp->link_config.speed;
1628 tp->link_config.active_duplex = tp->link_config.duplex;
1629
1630 bmcr = 0;
1631 switch (tp->link_config.speed) {
1632 default:
1633 case SPEED_10:
1634 break;
1635
1636 case SPEED_100:
1637 bmcr |= BMCR_SPEED100;
1638 break;
1639
1640 case SPEED_1000:
1641 bmcr |= TG3_BMCR_SPEED1000;
1642 break;
1643 };
1644
1645 if (tp->link_config.duplex == DUPLEX_FULL)
1646 bmcr |= BMCR_FULLDPLX;
1647
1648 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1649 (bmcr != orig_bmcr)) {
1650 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1651 for (i = 0; i < 1500; i++) {
1652 u32 tmp;
1653
1654 udelay(10);
1655 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1656 tg3_readphy(tp, MII_BMSR, &tmp))
1657 continue;
1658 if (!(tmp & BMSR_LSTATUS)) {
1659 udelay(40);
1660 break;
1661 }
1662 }
1663 tg3_writephy(tp, MII_BMCR, bmcr);
1664 udelay(40);
1665 }
1666 } else {
1667 tg3_writephy(tp, MII_BMCR,
1668 BMCR_ANENABLE | BMCR_ANRESTART);
1669 }
1670 }
1671
1672 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1673 {
1674 int err;
1675
1676 /* Turn off tap power management. */
1677 /* Set Extended packet length bit */
1678 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1679
1680 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1681 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1682
1683 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1684 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1685
1686 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1687 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1688
1689 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1690 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1691
1692 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1693 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1694
1695 udelay(40);
1696
1697 return err;
1698 }
1699
1700 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1701 {
1702 u32 adv_reg, all_mask;
1703
1704 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1705 return 0;
1706
1707 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1708 ADVERTISE_100HALF | ADVERTISE_100FULL);
1709 if ((adv_reg & all_mask) != all_mask)
1710 return 0;
1711 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1712 u32 tg3_ctrl;
1713
1714 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1715 return 0;
1716
1717 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1718 MII_TG3_CTRL_ADV_1000_FULL);
1719 if ((tg3_ctrl & all_mask) != all_mask)
1720 return 0;
1721 }
1722 return 1;
1723 }
1724
1725 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1726 {
1727 int current_link_up;
1728 u32 bmsr, dummy;
1729 u16 current_speed;
1730 u8 current_duplex;
1731 int i, err;
1732
1733 tw32(MAC_EVENT, 0);
1734
1735 tw32_f(MAC_STATUS,
1736 (MAC_STATUS_SYNC_CHANGED |
1737 MAC_STATUS_CFG_CHANGED |
1738 MAC_STATUS_MI_COMPLETION |
1739 MAC_STATUS_LNKSTATE_CHANGED));
1740 udelay(40);
1741
1742 tp->mi_mode = MAC_MI_MODE_BASE;
1743 tw32_f(MAC_MI_MODE, tp->mi_mode);
1744 udelay(80);
1745
1746 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1747
1748 /* Some third-party PHYs need to be reset on link going
1749 * down.
1750 */
1751 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1752 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1753 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1754 netif_carrier_ok(tp->dev)) {
1755 tg3_readphy(tp, MII_BMSR, &bmsr);
1756 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1757 !(bmsr & BMSR_LSTATUS))
1758 force_reset = 1;
1759 }
1760 if (force_reset)
1761 tg3_phy_reset(tp);
1762
1763 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1764 tg3_readphy(tp, MII_BMSR, &bmsr);
1765 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1766 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1767 bmsr = 0;
1768
1769 if (!(bmsr & BMSR_LSTATUS)) {
1770 err = tg3_init_5401phy_dsp(tp);
1771 if (err)
1772 return err;
1773
1774 tg3_readphy(tp, MII_BMSR, &bmsr);
1775 for (i = 0; i < 1000; i++) {
1776 udelay(10);
1777 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1778 (bmsr & BMSR_LSTATUS)) {
1779 udelay(40);
1780 break;
1781 }
1782 }
1783
1784 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1785 !(bmsr & BMSR_LSTATUS) &&
1786 tp->link_config.active_speed == SPEED_1000) {
1787 err = tg3_phy_reset(tp);
1788 if (!err)
1789 err = tg3_init_5401phy_dsp(tp);
1790 if (err)
1791 return err;
1792 }
1793 }
1794 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1795 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1796 /* 5701 {A0,B0} CRC bug workaround */
1797 tg3_writephy(tp, 0x15, 0x0a75);
1798 tg3_writephy(tp, 0x1c, 0x8c68);
1799 tg3_writephy(tp, 0x1c, 0x8d68);
1800 tg3_writephy(tp, 0x1c, 0x8c68);
1801 }
1802
1803 /* Clear pending interrupts... */
1804 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1805 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1806
1807 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1808 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1809 else
1810 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1811
1812 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1813 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1814 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1815 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1816 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1817 else
1818 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1819 }
1820
1821 current_link_up = 0;
1822 current_speed = SPEED_INVALID;
1823 current_duplex = DUPLEX_INVALID;
1824
1825 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1826 u32 val;
1827
1828 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1829 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1830 if (!(val & (1 << 10))) {
1831 val |= (1 << 10);
1832 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1833 goto relink;
1834 }
1835 }
1836
1837 bmsr = 0;
1838 for (i = 0; i < 100; i++) {
1839 tg3_readphy(tp, MII_BMSR, &bmsr);
1840 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1841 (bmsr & BMSR_LSTATUS))
1842 break;
1843 udelay(40);
1844 }
1845
1846 if (bmsr & BMSR_LSTATUS) {
1847 u32 aux_stat, bmcr;
1848
1849 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1850 for (i = 0; i < 2000; i++) {
1851 udelay(10);
1852 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1853 aux_stat)
1854 break;
1855 }
1856
1857 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1858 &current_speed,
1859 &current_duplex);
1860
1861 bmcr = 0;
1862 for (i = 0; i < 200; i++) {
1863 tg3_readphy(tp, MII_BMCR, &bmcr);
1864 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1865 continue;
1866 if (bmcr && bmcr != 0x7fff)
1867 break;
1868 udelay(10);
1869 }
1870
1871 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1872 if (bmcr & BMCR_ANENABLE) {
1873 current_link_up = 1;
1874
1875 /* Force autoneg restart if we are exiting
1876 * low power mode.
1877 */
1878 if (!tg3_copper_is_advertising_all(tp))
1879 current_link_up = 0;
1880 } else {
1881 current_link_up = 0;
1882 }
1883 } else {
1884 if (!(bmcr & BMCR_ANENABLE) &&
1885 tp->link_config.speed == current_speed &&
1886 tp->link_config.duplex == current_duplex) {
1887 current_link_up = 1;
1888 } else {
1889 current_link_up = 0;
1890 }
1891 }
1892
1893 tp->link_config.active_speed = current_speed;
1894 tp->link_config.active_duplex = current_duplex;
1895 }
1896
1897 if (current_link_up == 1 &&
1898 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1899 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1900 u32 local_adv, remote_adv;
1901
1902 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1903 local_adv = 0;
1904 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1905
1906 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1907 remote_adv = 0;
1908
1909 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1910
1911 /* If we are not advertising full pause capability,
1912 * something is wrong. Bring the link down and reconfigure.
1913 */
1914 if (local_adv != ADVERTISE_PAUSE_CAP) {
1915 current_link_up = 0;
1916 } else {
1917 tg3_setup_flow_control(tp, local_adv, remote_adv);
1918 }
1919 }
1920 relink:
1921 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1922 u32 tmp;
1923
1924 tg3_phy_copper_begin(tp);
1925
1926 tg3_readphy(tp, MII_BMSR, &tmp);
1927 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1928 (tmp & BMSR_LSTATUS))
1929 current_link_up = 1;
1930 }
1931
1932 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1933 if (current_link_up == 1) {
1934 if (tp->link_config.active_speed == SPEED_100 ||
1935 tp->link_config.active_speed == SPEED_10)
1936 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1937 else
1938 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1939 } else
1940 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1941
1942 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1943 if (tp->link_config.active_duplex == DUPLEX_HALF)
1944 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1945
1946 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1948 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1949 (current_link_up == 1 &&
1950 tp->link_config.active_speed == SPEED_10))
1951 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1952 } else {
1953 if (current_link_up == 1)
1954 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1955 }
1956
1957 /* ??? Without this setting Netgear GA302T PHY does not
1958 * ??? send/receive packets...
1959 */
1960 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1961 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1962 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1963 tw32_f(MAC_MI_MODE, tp->mi_mode);
1964 udelay(80);
1965 }
1966
1967 tw32_f(MAC_MODE, tp->mac_mode);
1968 udelay(40);
1969
1970 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1971 /* Polled via timer. */
1972 tw32_f(MAC_EVENT, 0);
1973 } else {
1974 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1975 }
1976 udelay(40);
1977
1978 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1979 current_link_up == 1 &&
1980 tp->link_config.active_speed == SPEED_1000 &&
1981 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1982 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1983 udelay(120);
1984 tw32_f(MAC_STATUS,
1985 (MAC_STATUS_SYNC_CHANGED |
1986 MAC_STATUS_CFG_CHANGED));
1987 udelay(40);
1988 tg3_write_mem(tp,
1989 NIC_SRAM_FIRMWARE_MBOX,
1990 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1991 }
1992
1993 if (current_link_up != netif_carrier_ok(tp->dev)) {
1994 if (current_link_up)
1995 netif_carrier_on(tp->dev);
1996 else
1997 netif_carrier_off(tp->dev);
1998 tg3_link_report(tp);
1999 }
2000
2001 return 0;
2002 }
2003
2004 struct tg3_fiber_aneginfo {
2005 int state;
2006 #define ANEG_STATE_UNKNOWN 0
2007 #define ANEG_STATE_AN_ENABLE 1
2008 #define ANEG_STATE_RESTART_INIT 2
2009 #define ANEG_STATE_RESTART 3
2010 #define ANEG_STATE_DISABLE_LINK_OK 4
2011 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2012 #define ANEG_STATE_ABILITY_DETECT 6
2013 #define ANEG_STATE_ACK_DETECT_INIT 7
2014 #define ANEG_STATE_ACK_DETECT 8
2015 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2016 #define ANEG_STATE_COMPLETE_ACK 10
2017 #define ANEG_STATE_IDLE_DETECT_INIT 11
2018 #define ANEG_STATE_IDLE_DETECT 12
2019 #define ANEG_STATE_LINK_OK 13
2020 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2021 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2022
2023 u32 flags;
2024 #define MR_AN_ENABLE 0x00000001
2025 #define MR_RESTART_AN 0x00000002
2026 #define MR_AN_COMPLETE 0x00000004
2027 #define MR_PAGE_RX 0x00000008
2028 #define MR_NP_LOADED 0x00000010
2029 #define MR_TOGGLE_TX 0x00000020
2030 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2031 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2032 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2033 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2034 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2035 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2036 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2037 #define MR_TOGGLE_RX 0x00002000
2038 #define MR_NP_RX 0x00004000
2039
2040 #define MR_LINK_OK 0x80000000
2041
2042 unsigned long link_time, cur_time;
2043
2044 u32 ability_match_cfg;
2045 int ability_match_count;
2046
2047 char ability_match, idle_match, ack_match;
2048
2049 u32 txconfig, rxconfig;
2050 #define ANEG_CFG_NP 0x00000080
2051 #define ANEG_CFG_ACK 0x00000040
2052 #define ANEG_CFG_RF2 0x00000020
2053 #define ANEG_CFG_RF1 0x00000010
2054 #define ANEG_CFG_PS2 0x00000001
2055 #define ANEG_CFG_PS1 0x00008000
2056 #define ANEG_CFG_HD 0x00004000
2057 #define ANEG_CFG_FD 0x00002000
2058 #define ANEG_CFG_INVAL 0x00001f06
2059
2060 };
2061 #define ANEG_OK 0
2062 #define ANEG_DONE 1
2063 #define ANEG_TIMER_ENAB 2
2064 #define ANEG_FAILED -1
2065
2066 #define ANEG_STATE_SETTLE_TIME 10000
2067
2068 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2069 struct tg3_fiber_aneginfo *ap)
2070 {
2071 unsigned long delta;
2072 u32 rx_cfg_reg;
2073 int ret;
2074
2075 if (ap->state == ANEG_STATE_UNKNOWN) {
2076 ap->rxconfig = 0;
2077 ap->link_time = 0;
2078 ap->cur_time = 0;
2079 ap->ability_match_cfg = 0;
2080 ap->ability_match_count = 0;
2081 ap->ability_match = 0;
2082 ap->idle_match = 0;
2083 ap->ack_match = 0;
2084 }
2085 ap->cur_time++;
2086
2087 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2088 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2089
2090 if (rx_cfg_reg != ap->ability_match_cfg) {
2091 ap->ability_match_cfg = rx_cfg_reg;
2092 ap->ability_match = 0;
2093 ap->ability_match_count = 0;
2094 } else {
2095 if (++ap->ability_match_count > 1) {
2096 ap->ability_match = 1;
2097 ap->ability_match_cfg = rx_cfg_reg;
2098 }
2099 }
2100 if (rx_cfg_reg & ANEG_CFG_ACK)
2101 ap->ack_match = 1;
2102 else
2103 ap->ack_match = 0;
2104
2105 ap->idle_match = 0;
2106 } else {
2107 ap->idle_match = 1;
2108 ap->ability_match_cfg = 0;
2109 ap->ability_match_count = 0;
2110 ap->ability_match = 0;
2111 ap->ack_match = 0;
2112
2113 rx_cfg_reg = 0;
2114 }
2115
2116 ap->rxconfig = rx_cfg_reg;
2117 ret = ANEG_OK;
2118
2119 switch(ap->state) {
2120 case ANEG_STATE_UNKNOWN:
2121 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2122 ap->state = ANEG_STATE_AN_ENABLE;
2123
2124 /* fallthru */
2125 case ANEG_STATE_AN_ENABLE:
2126 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2127 if (ap->flags & MR_AN_ENABLE) {
2128 ap->link_time = 0;
2129 ap->cur_time = 0;
2130 ap->ability_match_cfg = 0;
2131 ap->ability_match_count = 0;
2132 ap->ability_match = 0;
2133 ap->idle_match = 0;
2134 ap->ack_match = 0;
2135
2136 ap->state = ANEG_STATE_RESTART_INIT;
2137 } else {
2138 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2139 }
2140 break;
2141
2142 case ANEG_STATE_RESTART_INIT:
2143 ap->link_time = ap->cur_time;
2144 ap->flags &= ~(MR_NP_LOADED);
2145 ap->txconfig = 0;
2146 tw32(MAC_TX_AUTO_NEG, 0);
2147 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2148 tw32_f(MAC_MODE, tp->mac_mode);
2149 udelay(40);
2150
2151 ret = ANEG_TIMER_ENAB;
2152 ap->state = ANEG_STATE_RESTART;
2153
2154 /* fallthru */
2155 case ANEG_STATE_RESTART:
2156 delta = ap->cur_time - ap->link_time;
2157 if (delta > ANEG_STATE_SETTLE_TIME) {
2158 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2159 } else {
2160 ret = ANEG_TIMER_ENAB;
2161 }
2162 break;
2163
2164 case ANEG_STATE_DISABLE_LINK_OK:
2165 ret = ANEG_DONE;
2166 break;
2167
2168 case ANEG_STATE_ABILITY_DETECT_INIT:
2169 ap->flags &= ~(MR_TOGGLE_TX);
2170 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2171 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2172 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2173 tw32_f(MAC_MODE, tp->mac_mode);
2174 udelay(40);
2175
2176 ap->state = ANEG_STATE_ABILITY_DETECT;
2177 break;
2178
2179 case ANEG_STATE_ABILITY_DETECT:
2180 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2181 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2182 }
2183 break;
2184
2185 case ANEG_STATE_ACK_DETECT_INIT:
2186 ap->txconfig |= ANEG_CFG_ACK;
2187 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2188 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2189 tw32_f(MAC_MODE, tp->mac_mode);
2190 udelay(40);
2191
2192 ap->state = ANEG_STATE_ACK_DETECT;
2193
2194 /* fallthru */
2195 case ANEG_STATE_ACK_DETECT:
2196 if (ap->ack_match != 0) {
2197 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2198 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2199 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2200 } else {
2201 ap->state = ANEG_STATE_AN_ENABLE;
2202 }
2203 } else if (ap->ability_match != 0 &&
2204 ap->rxconfig == 0) {
2205 ap->state = ANEG_STATE_AN_ENABLE;
2206 }
2207 break;
2208
2209 case ANEG_STATE_COMPLETE_ACK_INIT:
2210 if (ap->rxconfig & ANEG_CFG_INVAL) {
2211 ret = ANEG_FAILED;
2212 break;
2213 }
2214 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2215 MR_LP_ADV_HALF_DUPLEX |
2216 MR_LP_ADV_SYM_PAUSE |
2217 MR_LP_ADV_ASYM_PAUSE |
2218 MR_LP_ADV_REMOTE_FAULT1 |
2219 MR_LP_ADV_REMOTE_FAULT2 |
2220 MR_LP_ADV_NEXT_PAGE |
2221 MR_TOGGLE_RX |
2222 MR_NP_RX);
2223 if (ap->rxconfig & ANEG_CFG_FD)
2224 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2225 if (ap->rxconfig & ANEG_CFG_HD)
2226 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2227 if (ap->rxconfig & ANEG_CFG_PS1)
2228 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2229 if (ap->rxconfig & ANEG_CFG_PS2)
2230 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2231 if (ap->rxconfig & ANEG_CFG_RF1)
2232 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2233 if (ap->rxconfig & ANEG_CFG_RF2)
2234 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2235 if (ap->rxconfig & ANEG_CFG_NP)
2236 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2237
2238 ap->link_time = ap->cur_time;
2239
2240 ap->flags ^= (MR_TOGGLE_TX);
2241 if (ap->rxconfig & 0x0008)
2242 ap->flags |= MR_TOGGLE_RX;
2243 if (ap->rxconfig & ANEG_CFG_NP)
2244 ap->flags |= MR_NP_RX;
2245 ap->flags |= MR_PAGE_RX;
2246
2247 ap->state = ANEG_STATE_COMPLETE_ACK;
2248 ret = ANEG_TIMER_ENAB;
2249 break;
2250
2251 case ANEG_STATE_COMPLETE_ACK:
2252 if (ap->ability_match != 0 &&
2253 ap->rxconfig == 0) {
2254 ap->state = ANEG_STATE_AN_ENABLE;
2255 break;
2256 }
2257 delta = ap->cur_time - ap->link_time;
2258 if (delta > ANEG_STATE_SETTLE_TIME) {
2259 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2260 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2261 } else {
2262 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2263 !(ap->flags & MR_NP_RX)) {
2264 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2265 } else {
2266 ret = ANEG_FAILED;
2267 }
2268 }
2269 }
2270 break;
2271
2272 case ANEG_STATE_IDLE_DETECT_INIT:
2273 ap->link_time = ap->cur_time;
2274 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2275 tw32_f(MAC_MODE, tp->mac_mode);
2276 udelay(40);
2277
2278 ap->state = ANEG_STATE_IDLE_DETECT;
2279 ret = ANEG_TIMER_ENAB;
2280 break;
2281
2282 case ANEG_STATE_IDLE_DETECT:
2283 if (ap->ability_match != 0 &&
2284 ap->rxconfig == 0) {
2285 ap->state = ANEG_STATE_AN_ENABLE;
2286 break;
2287 }
2288 delta = ap->cur_time - ap->link_time;
2289 if (delta > ANEG_STATE_SETTLE_TIME) {
2290 /* XXX another gem from the Broadcom driver :( */
2291 ap->state = ANEG_STATE_LINK_OK;
2292 }
2293 break;
2294
2295 case ANEG_STATE_LINK_OK:
2296 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2297 ret = ANEG_DONE;
2298 break;
2299
2300 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2301 /* ??? unimplemented */
2302 break;
2303
2304 case ANEG_STATE_NEXT_PAGE_WAIT:
2305 /* ??? unimplemented */
2306 break;
2307
2308 default:
2309 ret = ANEG_FAILED;
2310 break;
2311 };
2312
2313 return ret;
2314 }
2315
2316 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2317 {
2318 int res = 0;
2319 struct tg3_fiber_aneginfo aninfo;
2320 int status = ANEG_FAILED;
2321 unsigned int tick;
2322 u32 tmp;
2323
2324 tw32_f(MAC_TX_AUTO_NEG, 0);
2325
2326 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2327 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2328 udelay(40);
2329
2330 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2331 udelay(40);
2332
2333 memset(&aninfo, 0, sizeof(aninfo));
2334 aninfo.flags |= MR_AN_ENABLE;
2335 aninfo.state = ANEG_STATE_UNKNOWN;
2336 aninfo.cur_time = 0;
2337 tick = 0;
2338 while (++tick < 195000) {
2339 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2340 if (status == ANEG_DONE || status == ANEG_FAILED)
2341 break;
2342
2343 udelay(1);
2344 }
2345
2346 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2347 tw32_f(MAC_MODE, tp->mac_mode);
2348 udelay(40);
2349
2350 *flags = aninfo.flags;
2351
2352 if (status == ANEG_DONE &&
2353 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2354 MR_LP_ADV_FULL_DUPLEX)))
2355 res = 1;
2356
2357 return res;
2358 }
2359
2360 static void tg3_init_bcm8002(struct tg3 *tp)
2361 {
2362 u32 mac_status = tr32(MAC_STATUS);
2363 int i;
2364
2365 /* Reset when initting first time or we have a link. */
2366 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2367 !(mac_status & MAC_STATUS_PCS_SYNCED))
2368 return;
2369
2370 /* Set PLL lock range. */
2371 tg3_writephy(tp, 0x16, 0x8007);
2372
2373 /* SW reset */
2374 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2375
2376 /* Wait for reset to complete. */
2377 /* XXX schedule_timeout() ... */
2378 for (i = 0; i < 500; i++)
2379 udelay(10);
2380
2381 /* Config mode; select PMA/Ch 1 regs. */
2382 tg3_writephy(tp, 0x10, 0x8411);
2383
2384 /* Enable auto-lock and comdet, select txclk for tx. */
2385 tg3_writephy(tp, 0x11, 0x0a10);
2386
2387 tg3_writephy(tp, 0x18, 0x00a0);
2388 tg3_writephy(tp, 0x16, 0x41ff);
2389
2390 /* Assert and deassert POR. */
2391 tg3_writephy(tp, 0x13, 0x0400);
2392 udelay(40);
2393 tg3_writephy(tp, 0x13, 0x0000);
2394
2395 tg3_writephy(tp, 0x11, 0x0a50);
2396 udelay(40);
2397 tg3_writephy(tp, 0x11, 0x0a10);
2398
2399 /* Wait for signal to stabilize */
2400 /* XXX schedule_timeout() ... */
2401 for (i = 0; i < 15000; i++)
2402 udelay(10);
2403
2404 /* Deselect the channel register so we can read the PHYID
2405 * later.
2406 */
2407 tg3_writephy(tp, 0x10, 0x8011);
2408 }
2409
2410 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2411 {
2412 u32 sg_dig_ctrl, sg_dig_status;
2413 u32 serdes_cfg, expected_sg_dig_ctrl;
2414 int workaround, port_a;
2415 int current_link_up;
2416
2417 serdes_cfg = 0;
2418 expected_sg_dig_ctrl = 0;
2419 workaround = 0;
2420 port_a = 1;
2421 current_link_up = 0;
2422
2423 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2424 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2425 workaround = 1;
2426 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2427 port_a = 0;
2428
2429 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2430 /* preserve bits 20-23 for voltage regulator */
2431 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2432 }
2433
2434 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2435
2436 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2437 if (sg_dig_ctrl & (1 << 31)) {
2438 if (workaround) {
2439 u32 val = serdes_cfg;
2440
2441 if (port_a)
2442 val |= 0xc010000;
2443 else
2444 val |= 0x4010000;
2445 tw32_f(MAC_SERDES_CFG, val);
2446 }
2447 tw32_f(SG_DIG_CTRL, 0x01388400);
2448 }
2449 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2450 tg3_setup_flow_control(tp, 0, 0);
2451 current_link_up = 1;
2452 }
2453 goto out;
2454 }
2455
2456 /* Want auto-negotiation. */
2457 expected_sg_dig_ctrl = 0x81388400;
2458
2459 /* Pause capability */
2460 expected_sg_dig_ctrl |= (1 << 11);
2461
2462 /* Asymettric pause */
2463 expected_sg_dig_ctrl |= (1 << 12);
2464
2465 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2466 if (workaround)
2467 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2468 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2469 udelay(5);
2470 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2471
2472 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2473 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2474 MAC_STATUS_SIGNAL_DET)) {
2475 int i;
2476
2477 /* Giver time to negotiate (~200ms) */
2478 for (i = 0; i < 40000; i++) {
2479 sg_dig_status = tr32(SG_DIG_STATUS);
2480 if (sg_dig_status & (0x3))
2481 break;
2482 udelay(5);
2483 }
2484 mac_status = tr32(MAC_STATUS);
2485
2486 if ((sg_dig_status & (1 << 1)) &&
2487 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2488 u32 local_adv, remote_adv;
2489
2490 local_adv = ADVERTISE_PAUSE_CAP;
2491 remote_adv = 0;
2492 if (sg_dig_status & (1 << 19))
2493 remote_adv |= LPA_PAUSE_CAP;
2494 if (sg_dig_status & (1 << 20))
2495 remote_adv |= LPA_PAUSE_ASYM;
2496
2497 tg3_setup_flow_control(tp, local_adv, remote_adv);
2498 current_link_up = 1;
2499 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2500 } else if (!(sg_dig_status & (1 << 1))) {
2501 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2502 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2503 else {
2504 if (workaround) {
2505 u32 val = serdes_cfg;
2506
2507 if (port_a)
2508 val |= 0xc010000;
2509 else
2510 val |= 0x4010000;
2511
2512 tw32_f(MAC_SERDES_CFG, val);
2513 }
2514
2515 tw32_f(SG_DIG_CTRL, 0x01388400);
2516 udelay(40);
2517
2518 /* Link parallel detection - link is up */
2519 /* only if we have PCS_SYNC and not */
2520 /* receiving config code words */
2521 mac_status = tr32(MAC_STATUS);
2522 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2523 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2524 tg3_setup_flow_control(tp, 0, 0);
2525 current_link_up = 1;
2526 }
2527 }
2528 }
2529 }
2530
2531 out:
2532 return current_link_up;
2533 }
2534
2535 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2536 {
2537 int current_link_up = 0;
2538
2539 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2540 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2541 goto out;
2542 }
2543
2544 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2545 u32 flags;
2546 int i;
2547
2548 if (fiber_autoneg(tp, &flags)) {
2549 u32 local_adv, remote_adv;
2550
2551 local_adv = ADVERTISE_PAUSE_CAP;
2552 remote_adv = 0;
2553 if (flags & MR_LP_ADV_SYM_PAUSE)
2554 remote_adv |= LPA_PAUSE_CAP;
2555 if (flags & MR_LP_ADV_ASYM_PAUSE)
2556 remote_adv |= LPA_PAUSE_ASYM;
2557
2558 tg3_setup_flow_control(tp, local_adv, remote_adv);
2559
2560 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2561 current_link_up = 1;
2562 }
2563 for (i = 0; i < 30; i++) {
2564 udelay(20);
2565 tw32_f(MAC_STATUS,
2566 (MAC_STATUS_SYNC_CHANGED |
2567 MAC_STATUS_CFG_CHANGED));
2568 udelay(40);
2569 if ((tr32(MAC_STATUS) &
2570 (MAC_STATUS_SYNC_CHANGED |
2571 MAC_STATUS_CFG_CHANGED)) == 0)
2572 break;
2573 }
2574
2575 mac_status = tr32(MAC_STATUS);
2576 if (current_link_up == 0 &&
2577 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2578 !(mac_status & MAC_STATUS_RCVD_CFG))
2579 current_link_up = 1;
2580 } else {
2581 /* Forcing 1000FD link up. */
2582 current_link_up = 1;
2583 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2584
2585 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2586 udelay(40);
2587 }
2588
2589 out:
2590 return current_link_up;
2591 }
2592
2593 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2594 {
2595 u32 orig_pause_cfg;
2596 u16 orig_active_speed;
2597 u8 orig_active_duplex;
2598 u32 mac_status;
2599 int current_link_up;
2600 int i;
2601
2602 orig_pause_cfg =
2603 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2604 TG3_FLAG_TX_PAUSE));
2605 orig_active_speed = tp->link_config.active_speed;
2606 orig_active_duplex = tp->link_config.active_duplex;
2607
2608 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2609 netif_carrier_ok(tp->dev) &&
2610 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2611 mac_status = tr32(MAC_STATUS);
2612 mac_status &= (MAC_STATUS_PCS_SYNCED |
2613 MAC_STATUS_SIGNAL_DET |
2614 MAC_STATUS_CFG_CHANGED |
2615 MAC_STATUS_RCVD_CFG);
2616 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2617 MAC_STATUS_SIGNAL_DET)) {
2618 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2619 MAC_STATUS_CFG_CHANGED));
2620 return 0;
2621 }
2622 }
2623
2624 tw32_f(MAC_TX_AUTO_NEG, 0);
2625
2626 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2627 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2628 tw32_f(MAC_MODE, tp->mac_mode);
2629 udelay(40);
2630
2631 if (tp->phy_id == PHY_ID_BCM8002)
2632 tg3_init_bcm8002(tp);
2633
2634 /* Enable link change event even when serdes polling. */
2635 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2636 udelay(40);
2637
2638 current_link_up = 0;
2639 mac_status = tr32(MAC_STATUS);
2640
2641 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2642 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2643 else
2644 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2645
2646 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2647 tw32_f(MAC_MODE, tp->mac_mode);
2648 udelay(40);
2649
2650 tp->hw_status->status =
2651 (SD_STATUS_UPDATED |
2652 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2653
2654 for (i = 0; i < 100; i++) {
2655 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2656 MAC_STATUS_CFG_CHANGED));
2657 udelay(5);
2658 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2659 MAC_STATUS_CFG_CHANGED)) == 0)
2660 break;
2661 }
2662
2663 mac_status = tr32(MAC_STATUS);
2664 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2665 current_link_up = 0;
2666 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2667 tw32_f(MAC_MODE, (tp->mac_mode |
2668 MAC_MODE_SEND_CONFIGS));
2669 udelay(1);
2670 tw32_f(MAC_MODE, tp->mac_mode);
2671 }
2672 }
2673
2674 if (current_link_up == 1) {
2675 tp->link_config.active_speed = SPEED_1000;
2676 tp->link_config.active_duplex = DUPLEX_FULL;
2677 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2678 LED_CTRL_LNKLED_OVERRIDE |
2679 LED_CTRL_1000MBPS_ON));
2680 } else {
2681 tp->link_config.active_speed = SPEED_INVALID;
2682 tp->link_config.active_duplex = DUPLEX_INVALID;
2683 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2684 LED_CTRL_LNKLED_OVERRIDE |
2685 LED_CTRL_TRAFFIC_OVERRIDE));
2686 }
2687
2688 if (current_link_up != netif_carrier_ok(tp->dev)) {
2689 if (current_link_up)
2690 netif_carrier_on(tp->dev);
2691 else
2692 netif_carrier_off(tp->dev);
2693 tg3_link_report(tp);
2694 } else {
2695 u32 now_pause_cfg =
2696 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2697 TG3_FLAG_TX_PAUSE);
2698 if (orig_pause_cfg != now_pause_cfg ||
2699 orig_active_speed != tp->link_config.active_speed ||
2700 orig_active_duplex != tp->link_config.active_duplex)
2701 tg3_link_report(tp);
2702 }
2703
2704 return 0;
2705 }
2706
2707 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2708 {
2709 int current_link_up, err = 0;
2710 u32 bmsr, bmcr;
2711 u16 current_speed;
2712 u8 current_duplex;
2713
2714 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2715 tw32_f(MAC_MODE, tp->mac_mode);
2716 udelay(40);
2717
2718 tw32(MAC_EVENT, 0);
2719
2720 tw32_f(MAC_STATUS,
2721 (MAC_STATUS_SYNC_CHANGED |
2722 MAC_STATUS_CFG_CHANGED |
2723 MAC_STATUS_MI_COMPLETION |
2724 MAC_STATUS_LNKSTATE_CHANGED));
2725 udelay(40);
2726
2727 if (force_reset)
2728 tg3_phy_reset(tp);
2729
2730 current_link_up = 0;
2731 current_speed = SPEED_INVALID;
2732 current_duplex = DUPLEX_INVALID;
2733
2734 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2735 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2736 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2737 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2738 bmsr |= BMSR_LSTATUS;
2739 else
2740 bmsr &= ~BMSR_LSTATUS;
2741 }
2742
2743 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2744
2745 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2746 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2747 /* do nothing, just check for link up at the end */
2748 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2749 u32 adv, new_adv;
2750
2751 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2752 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2753 ADVERTISE_1000XPAUSE |
2754 ADVERTISE_1000XPSE_ASYM |
2755 ADVERTISE_SLCT);
2756
2757 /* Always advertise symmetric PAUSE just like copper */
2758 new_adv |= ADVERTISE_1000XPAUSE;
2759
2760 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2761 new_adv |= ADVERTISE_1000XHALF;
2762 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2763 new_adv |= ADVERTISE_1000XFULL;
2764
2765 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2766 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2767 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2768 tg3_writephy(tp, MII_BMCR, bmcr);
2769
2770 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2771 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2772 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2773
2774 return err;
2775 }
2776 } else {
2777 u32 new_bmcr;
2778
2779 bmcr &= ~BMCR_SPEED1000;
2780 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2781
2782 if (tp->link_config.duplex == DUPLEX_FULL)
2783 new_bmcr |= BMCR_FULLDPLX;
2784
2785 if (new_bmcr != bmcr) {
2786 /* BMCR_SPEED1000 is a reserved bit that needs
2787 * to be set on write.
2788 */
2789 new_bmcr |= BMCR_SPEED1000;
2790
2791 /* Force a linkdown */
2792 if (netif_carrier_ok(tp->dev)) {
2793 u32 adv;
2794
2795 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2796 adv &= ~(ADVERTISE_1000XFULL |
2797 ADVERTISE_1000XHALF |
2798 ADVERTISE_SLCT);
2799 tg3_writephy(tp, MII_ADVERTISE, adv);
2800 tg3_writephy(tp, MII_BMCR, bmcr |
2801 BMCR_ANRESTART |
2802 BMCR_ANENABLE);
2803 udelay(10);
2804 netif_carrier_off(tp->dev);
2805 }
2806 tg3_writephy(tp, MII_BMCR, new_bmcr);
2807 bmcr = new_bmcr;
2808 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2809 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2810 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2811 ASIC_REV_5714) {
2812 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2813 bmsr |= BMSR_LSTATUS;
2814 else
2815 bmsr &= ~BMSR_LSTATUS;
2816 }
2817 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2818 }
2819 }
2820
2821 if (bmsr & BMSR_LSTATUS) {
2822 current_speed = SPEED_1000;
2823 current_link_up = 1;
2824 if (bmcr & BMCR_FULLDPLX)
2825 current_duplex = DUPLEX_FULL;
2826 else
2827 current_duplex = DUPLEX_HALF;
2828
2829 if (bmcr & BMCR_ANENABLE) {
2830 u32 local_adv, remote_adv, common;
2831
2832 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2833 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2834 common = local_adv & remote_adv;
2835 if (common & (ADVERTISE_1000XHALF |
2836 ADVERTISE_1000XFULL)) {
2837 if (common & ADVERTISE_1000XFULL)
2838 current_duplex = DUPLEX_FULL;
2839 else
2840 current_duplex = DUPLEX_HALF;
2841
2842 tg3_setup_flow_control(tp, local_adv,
2843 remote_adv);
2844 }
2845 else
2846 current_link_up = 0;
2847 }
2848 }
2849
2850 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2851 if (tp->link_config.active_duplex == DUPLEX_HALF)
2852 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2853
2854 tw32_f(MAC_MODE, tp->mac_mode);
2855 udelay(40);
2856
2857 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2858
2859 tp->link_config.active_speed = current_speed;
2860 tp->link_config.active_duplex = current_duplex;
2861
2862 if (current_link_up != netif_carrier_ok(tp->dev)) {
2863 if (current_link_up)
2864 netif_carrier_on(tp->dev);
2865 else {
2866 netif_carrier_off(tp->dev);
2867 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2868 }
2869 tg3_link_report(tp);
2870 }
2871 return err;
2872 }
2873
2874 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2875 {
2876 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2877 /* Give autoneg time to complete. */
2878 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2879 return;
2880 }
2881 if (!netif_carrier_ok(tp->dev) &&
2882 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2883 u32 bmcr;
2884
2885 tg3_readphy(tp, MII_BMCR, &bmcr);
2886 if (bmcr & BMCR_ANENABLE) {
2887 u32 phy1, phy2;
2888
2889 /* Select shadow register 0x1f */
2890 tg3_writephy(tp, 0x1c, 0x7c00);
2891 tg3_readphy(tp, 0x1c, &phy1);
2892
2893 /* Select expansion interrupt status register */
2894 tg3_writephy(tp, 0x17, 0x0f01);
2895 tg3_readphy(tp, 0x15, &phy2);
2896 tg3_readphy(tp, 0x15, &phy2);
2897
2898 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2899 /* We have signal detect and not receiving
2900 * config code words, link is up by parallel
2901 * detection.
2902 */
2903
2904 bmcr &= ~BMCR_ANENABLE;
2905 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2906 tg3_writephy(tp, MII_BMCR, bmcr);
2907 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2908 }
2909 }
2910 }
2911 else if (netif_carrier_ok(tp->dev) &&
2912 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2913 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2914 u32 phy2;
2915
2916 /* Select expansion interrupt status register */
2917 tg3_writephy(tp, 0x17, 0x0f01);
2918 tg3_readphy(tp, 0x15, &phy2);
2919 if (phy2 & 0x20) {
2920 u32 bmcr;
2921
2922 /* Config code words received, turn on autoneg. */
2923 tg3_readphy(tp, MII_BMCR, &bmcr);
2924 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2925
2926 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2927
2928 }
2929 }
2930 }
2931
2932 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2933 {
2934 int err;
2935
2936 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2937 err = tg3_setup_fiber_phy(tp, force_reset);
2938 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2939 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2940 } else {
2941 err = tg3_setup_copper_phy(tp, force_reset);
2942 }
2943
2944 if (tp->link_config.active_speed == SPEED_1000 &&
2945 tp->link_config.active_duplex == DUPLEX_HALF)
2946 tw32(MAC_TX_LENGTHS,
2947 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2948 (6 << TX_LENGTHS_IPG_SHIFT) |
2949 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2950 else
2951 tw32(MAC_TX_LENGTHS,
2952 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2953 (6 << TX_LENGTHS_IPG_SHIFT) |
2954 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2955
2956 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2957 if (netif_carrier_ok(tp->dev)) {
2958 tw32(HOSTCC_STAT_COAL_TICKS,
2959 tp->coal.stats_block_coalesce_usecs);
2960 } else {
2961 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2962 }
2963 }
2964
2965 return err;
2966 }
2967
2968 /* Tigon3 never reports partial packet sends. So we do not
2969 * need special logic to handle SKBs that have not had all
2970 * of their frags sent yet, like SunGEM does.
2971 */
2972 static void tg3_tx(struct tg3 *tp)
2973 {
2974 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2975 u32 sw_idx = tp->tx_cons;
2976
2977 while (sw_idx != hw_idx) {
2978 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2979 struct sk_buff *skb = ri->skb;
2980 int i;
2981
2982 BUG_ON(skb == NULL);
2983 pci_unmap_single(tp->pdev,
2984 pci_unmap_addr(ri, mapping),
2985 skb_headlen(skb),
2986 PCI_DMA_TODEVICE);
2987
2988 ri->skb = NULL;
2989
2990 sw_idx = NEXT_TX(sw_idx);
2991
2992 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2993 BUG_ON(sw_idx == hw_idx);
2994
2995 ri = &tp->tx_buffers[sw_idx];
2996 BUG_ON(ri->skb != NULL);
2997
2998 pci_unmap_page(tp->pdev,
2999 pci_unmap_addr(ri, mapping),
3000 skb_shinfo(skb)->frags[i].size,
3001 PCI_DMA_TODEVICE);
3002
3003 sw_idx = NEXT_TX(sw_idx);
3004 }
3005
3006 dev_kfree_skb(skb);
3007 }
3008
3009 tp->tx_cons = sw_idx;
3010
3011 if (unlikely(netif_queue_stopped(tp->dev))) {
3012 spin_lock(&tp->tx_lock);
3013 if (netif_queue_stopped(tp->dev) &&
3014 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
3015 netif_wake_queue(tp->dev);
3016 spin_unlock(&tp->tx_lock);
3017 }
3018 }
3019
3020 /* Returns size of skb allocated or < 0 on error.
3021 *
3022 * We only need to fill in the address because the other members
3023 * of the RX descriptor are invariant, see tg3_init_rings.
3024 *
3025 * Note the purposeful assymetry of cpu vs. chip accesses. For
3026 * posting buffers we only dirty the first cache line of the RX
3027 * descriptor (containing the address). Whereas for the RX status
3028 * buffers the cpu only reads the last cacheline of the RX descriptor
3029 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3030 */
3031 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3032 int src_idx, u32 dest_idx_unmasked)
3033 {
3034 struct tg3_rx_buffer_desc *desc;
3035 struct ring_info *map, *src_map;
3036 struct sk_buff *skb;
3037 dma_addr_t mapping;
3038 int skb_size, dest_idx;
3039
3040 src_map = NULL;
3041 switch (opaque_key) {
3042 case RXD_OPAQUE_RING_STD:
3043 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3044 desc = &tp->rx_std[dest_idx];
3045 map = &tp->rx_std_buffers[dest_idx];
3046 if (src_idx >= 0)
3047 src_map = &tp->rx_std_buffers[src_idx];
3048 skb_size = tp->rx_pkt_buf_sz;
3049 break;
3050
3051 case RXD_OPAQUE_RING_JUMBO:
3052 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3053 desc = &tp->rx_jumbo[dest_idx];
3054 map = &tp->rx_jumbo_buffers[dest_idx];
3055 if (src_idx >= 0)
3056 src_map = &tp->rx_jumbo_buffers[src_idx];
3057 skb_size = RX_JUMBO_PKT_BUF_SZ;
3058 break;
3059
3060 default:
3061 return -EINVAL;
3062 };
3063
3064 /* Do not overwrite any of the map or rp information
3065 * until we are sure we can commit to a new buffer.
3066 *
3067 * Callers depend upon this behavior and assume that
3068 * we leave everything unchanged if we fail.
3069 */
3070 skb = dev_alloc_skb(skb_size);
3071 if (skb == NULL)
3072 return -ENOMEM;
3073
3074 skb->dev = tp->dev;
3075 skb_reserve(skb, tp->rx_offset);
3076
3077 mapping = pci_map_single(tp->pdev, skb->data,
3078 skb_size - tp->rx_offset,
3079 PCI_DMA_FROMDEVICE);
3080
3081 map->skb = skb;
3082 pci_unmap_addr_set(map, mapping, mapping);
3083
3084 if (src_map != NULL)
3085 src_map->skb = NULL;
3086
3087 desc->addr_hi = ((u64)mapping >> 32);
3088 desc->addr_lo = ((u64)mapping & 0xffffffff);
3089
3090 return skb_size;
3091 }
3092
3093 /* We only need to move over in the address because the other
3094 * members of the RX descriptor are invariant. See notes above
3095 * tg3_alloc_rx_skb for full details.
3096 */
3097 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3098 int src_idx, u32 dest_idx_unmasked)
3099 {
3100 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3101 struct ring_info *src_map, *dest_map;
3102 int dest_idx;
3103
3104 switch (opaque_key) {
3105 case RXD_OPAQUE_RING_STD:
3106 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3107 dest_desc = &tp->rx_std[dest_idx];
3108 dest_map = &tp->rx_std_buffers[dest_idx];
3109 src_desc = &tp->rx_std[src_idx];
3110 src_map = &tp->rx_std_buffers[src_idx];
3111 break;
3112
3113 case RXD_OPAQUE_RING_JUMBO:
3114 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3115 dest_desc = &tp->rx_jumbo[dest_idx];
3116 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3117 src_desc = &tp->rx_jumbo[src_idx];
3118 src_map = &tp->rx_jumbo_buffers[src_idx];
3119 break;
3120
3121 default:
3122 return;
3123 };
3124
3125 dest_map->skb = src_map->skb;
3126 pci_unmap_addr_set(dest_map, mapping,
3127 pci_unmap_addr(src_map, mapping));
3128 dest_desc->addr_hi = src_desc->addr_hi;
3129 dest_desc->addr_lo = src_desc->addr_lo;
3130
3131 src_map->skb = NULL;
3132 }
3133
3134 #if TG3_VLAN_TAG_USED
3135 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3136 {
3137 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3138 }
3139 #endif
3140
3141 /* The RX ring scheme is composed of multiple rings which post fresh
3142 * buffers to the chip, and one special ring the chip uses to report
3143 * status back to the host.
3144 *
3145 * The special ring reports the status of received packets to the
3146 * host. The chip does not write into the original descriptor the
3147 * RX buffer was obtained from. The chip simply takes the original
3148 * descriptor as provided by the host, updates the status and length
3149 * field, then writes this into the next status ring entry.
3150 *
3151 * Each ring the host uses to post buffers to the chip is described
3152 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3153 * it is first placed into the on-chip ram. When the packet's length
3154 * is known, it walks down the TG3_BDINFO entries to select the ring.
3155 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3156 * which is within the range of the new packet's length is chosen.
3157 *
3158 * The "separate ring for rx status" scheme may sound queer, but it makes
3159 * sense from a cache coherency perspective. If only the host writes
3160 * to the buffer post rings, and only the chip writes to the rx status
3161 * rings, then cache lines never move beyond shared-modified state.
3162 * If both the host and chip were to write into the same ring, cache line
3163 * eviction could occur since both entities want it in an exclusive state.
3164 */
3165 static int tg3_rx(struct tg3 *tp, int budget)
3166 {
3167 u32 work_mask;
3168 u32 sw_idx = tp->rx_rcb_ptr;
3169 u16 hw_idx;
3170 int received;
3171
3172 hw_idx = tp->hw_status->idx[0].rx_producer;
3173 /*
3174 * We need to order the read of hw_idx and the read of
3175 * the opaque cookie.
3176 */
3177 rmb();
3178 work_mask = 0;
3179 received = 0;
3180 while (sw_idx != hw_idx && budget > 0) {
3181 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3182 unsigned int len;
3183 struct sk_buff *skb;
3184 dma_addr_t dma_addr;
3185 u32 opaque_key, desc_idx, *post_ptr;
3186
3187 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3188 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3189 if (opaque_key == RXD_OPAQUE_RING_STD) {
3190 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3191 mapping);
3192 skb = tp->rx_std_buffers[desc_idx].skb;
3193 post_ptr = &tp->rx_std_ptr;
3194 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3195 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3196 mapping);
3197 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3198 post_ptr = &tp->rx_jumbo_ptr;
3199 }
3200 else {
3201 goto next_pkt_nopost;
3202 }
3203
3204 work_mask |= opaque_key;
3205
3206 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3207 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3208 drop_it:
3209 tg3_recycle_rx(tp, opaque_key,
3210 desc_idx, *post_ptr);
3211 drop_it_no_recycle:
3212 /* Other statistics kept track of by card. */
3213 tp->net_stats.rx_dropped++;
3214 goto next_pkt;
3215 }
3216
3217 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3218
3219 if (len > RX_COPY_THRESHOLD
3220 && tp->rx_offset == 2
3221 /* rx_offset != 2 iff this is a 5701 card running
3222 * in PCI-X mode [see tg3_get_invariants()] */
3223 ) {
3224 int skb_size;
3225
3226 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3227 desc_idx, *post_ptr);
3228 if (skb_size < 0)
3229 goto drop_it;
3230
3231 pci_unmap_single(tp->pdev, dma_addr,
3232 skb_size - tp->rx_offset,
3233 PCI_DMA_FROMDEVICE);
3234
3235 skb_put(skb, len);
3236 } else {
3237 struct sk_buff *copy_skb;
3238
3239 tg3_recycle_rx(tp, opaque_key,
3240 desc_idx, *post_ptr);
3241
3242 copy_skb = dev_alloc_skb(len + 2);
3243 if (copy_skb == NULL)
3244 goto drop_it_no_recycle;
3245
3246 copy_skb->dev = tp->dev;
3247 skb_reserve(copy_skb, 2);
3248 skb_put(copy_skb, len);
3249 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3250 memcpy(copy_skb->data, skb->data, len);
3251 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3252
3253 /* We'll reuse the original ring buffer. */
3254 skb = copy_skb;
3255 }
3256
3257 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3258 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3259 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3260 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3261 skb->ip_summed = CHECKSUM_UNNECESSARY;
3262 else
3263 skb->ip_summed = CHECKSUM_NONE;
3264
3265 skb->protocol = eth_type_trans(skb, tp->dev);
3266 #if TG3_VLAN_TAG_USED
3267 if (tp->vlgrp != NULL &&
3268 desc->type_flags & RXD_FLAG_VLAN) {
3269 tg3_vlan_rx(tp, skb,
3270 desc->err_vlan & RXD_VLAN_MASK);
3271 } else
3272 #endif
3273 netif_receive_skb(skb);
3274
3275 tp->dev->last_rx = jiffies;
3276 received++;
3277 budget--;
3278
3279 next_pkt:
3280 (*post_ptr)++;
3281 next_pkt_nopost:
3282 sw_idx++;
3283 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3284
3285 /* Refresh hw_idx to see if there is new work */
3286 if (sw_idx == hw_idx) {
3287 hw_idx = tp->hw_status->idx[0].rx_producer;
3288 rmb();
3289 }
3290 }
3291
3292 /* ACK the status ring. */
3293 tp->rx_rcb_ptr = sw_idx;
3294 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3295
3296 /* Refill RX ring(s). */
3297 if (work_mask & RXD_OPAQUE_RING_STD) {
3298 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3299 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3300 sw_idx);
3301 }
3302 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3303 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3304 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3305 sw_idx);
3306 }
3307 mmiowb();
3308
3309 return received;
3310 }
3311
3312 static int tg3_poll(struct net_device *netdev, int *budget)
3313 {
3314 struct tg3 *tp = netdev_priv(netdev);
3315 struct tg3_hw_status *sblk = tp->hw_status;
3316 int done;
3317
3318 /* handle link change and other phy events */
3319 if (!(tp->tg3_flags &
3320 (TG3_FLAG_USE_LINKCHG_REG |
3321 TG3_FLAG_POLL_SERDES))) {
3322 if (sblk->status & SD_STATUS_LINK_CHG) {
3323 sblk->status = SD_STATUS_UPDATED |
3324 (sblk->status & ~SD_STATUS_LINK_CHG);
3325 spin_lock(&tp->lock);
3326 tg3_setup_phy(tp, 0);
3327 spin_unlock(&tp->lock);
3328 }
3329 }
3330
3331 /* run TX completion thread */
3332 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3333 tg3_tx(tp);
3334 }
3335
3336 /* run RX thread, within the bounds set by NAPI.
3337 * All RX "locking" is done by ensuring outside
3338 * code synchronizes with dev->poll()
3339 */
3340 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3341 int orig_budget = *budget;
3342 int work_done;
3343
3344 if (orig_budget > netdev->quota)
3345 orig_budget = netdev->quota;
3346
3347 work_done = tg3_rx(tp, orig_budget);
3348
3349 *budget -= work_done;
3350 netdev->quota -= work_done;
3351 }
3352
3353 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3354 tp->last_tag = sblk->status_tag;
3355 rmb();
3356 } else
3357 sblk->status &= ~SD_STATUS_UPDATED;
3358
3359 /* if no more work, tell net stack and NIC we're done */
3360 done = !tg3_has_work(tp);
3361 if (done) {
3362 netif_rx_complete(netdev);
3363 tg3_restart_ints(tp);
3364 }
3365
3366 return (done ? 0 : 1);
3367 }
3368
3369 static void tg3_irq_quiesce(struct tg3 *tp)
3370 {
3371 BUG_ON(tp->irq_sync);
3372
3373 tp->irq_sync = 1;
3374 smp_mb();
3375
3376 synchronize_irq(tp->pdev->irq);
3377 }
3378
3379 static inline int tg3_irq_sync(struct tg3 *tp)
3380 {
3381 return tp->irq_sync;
3382 }
3383
3384 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3385 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3386 * with as well. Most of the time, this is not necessary except when
3387 * shutting down the device.
3388 */
3389 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3390 {
3391 if (irq_sync)
3392 tg3_irq_quiesce(tp);
3393 spin_lock_bh(&tp->lock);
3394 spin_lock(&tp->tx_lock);
3395 }
3396
3397 static inline void tg3_full_unlock(struct tg3 *tp)
3398 {
3399 spin_unlock(&tp->tx_lock);
3400 spin_unlock_bh(&tp->lock);
3401 }
3402
3403 /* One-shot MSI handler - Chip automatically disables interrupt
3404 * after sending MSI so driver doesn't have to do it.
3405 */
3406 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id, struct pt_regs *regs)
3407 {
3408 struct net_device *dev = dev_id;
3409 struct tg3 *tp = netdev_priv(dev);
3410
3411 prefetch(tp->hw_status);
3412 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3413
3414 if (likely(!tg3_irq_sync(tp)))
3415 netif_rx_schedule(dev); /* schedule NAPI poll */
3416
3417 return IRQ_HANDLED;
3418 }
3419
3420 /* MSI ISR - No need to check for interrupt sharing and no need to
3421 * flush status block and interrupt mailbox. PCI ordering rules
3422 * guarantee that MSI will arrive after the status block.
3423 */
3424 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3425 {
3426 struct net_device *dev = dev_id;
3427 struct tg3 *tp = netdev_priv(dev);
3428
3429 prefetch(tp->hw_status);
3430 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3431 /*
3432 * Writing any value to intr-mbox-0 clears PCI INTA# and
3433 * chip-internal interrupt pending events.
3434 * Writing non-zero to intr-mbox-0 additional tells the
3435 * NIC to stop sending us irqs, engaging "in-intr-handler"
3436 * event coalescing.
3437 */
3438 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3439 if (likely(!tg3_irq_sync(tp)))
3440 netif_rx_schedule(dev); /* schedule NAPI poll */
3441
3442 return IRQ_RETVAL(1);
3443 }
3444
3445 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3446 {
3447 struct net_device *dev = dev_id;
3448 struct tg3 *tp = netdev_priv(dev);
3449 struct tg3_hw_status *sblk = tp->hw_status;
3450 unsigned int handled = 1;
3451
3452 /* In INTx mode, it is possible for the interrupt to arrive at
3453 * the CPU before the status block posted prior to the interrupt.
3454 * Reading the PCI State register will confirm whether the
3455 * interrupt is ours and will flush the status block.
3456 */
3457 if ((sblk->status & SD_STATUS_UPDATED) ||
3458 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3459 /*
3460 * Writing any value to intr-mbox-0 clears PCI INTA# and
3461 * chip-internal interrupt pending events.
3462 * Writing non-zero to intr-mbox-0 additional tells the
3463 * NIC to stop sending us irqs, engaging "in-intr-handler"
3464 * event coalescing.
3465 */
3466 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3467 0x00000001);
3468 if (tg3_irq_sync(tp))
3469 goto out;
3470 sblk->status &= ~SD_STATUS_UPDATED;
3471 if (likely(tg3_has_work(tp))) {
3472 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3473 netif_rx_schedule(dev); /* schedule NAPI poll */
3474 } else {
3475 /* No work, shared interrupt perhaps? re-enable
3476 * interrupts, and flush that PCI write
3477 */
3478 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3479 0x00000000);
3480 }
3481 } else { /* shared interrupt */
3482 handled = 0;
3483 }
3484 out:
3485 return IRQ_RETVAL(handled);
3486 }
3487
3488 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3489 {
3490 struct net_device *dev = dev_id;
3491 struct tg3 *tp = netdev_priv(dev);
3492 struct tg3_hw_status *sblk = tp->hw_status;
3493 unsigned int handled = 1;
3494
3495 /* In INTx mode, it is possible for the interrupt to arrive at
3496 * the CPU before the status block posted prior to the interrupt.
3497 * Reading the PCI State register will confirm whether the
3498 * interrupt is ours and will flush the status block.
3499 */
3500 if ((sblk->status_tag != tp->last_tag) ||
3501 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3502 /*
3503 * writing any value to intr-mbox-0 clears PCI INTA# and
3504 * chip-internal interrupt pending events.
3505 * writing non-zero to intr-mbox-0 additional tells the
3506 * NIC to stop sending us irqs, engaging "in-intr-handler"
3507 * event coalescing.
3508 */
3509 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3510 0x00000001);
3511 if (tg3_irq_sync(tp))
3512 goto out;
3513 if (netif_rx_schedule_prep(dev)) {
3514 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3515 /* Update last_tag to mark that this status has been
3516 * seen. Because interrupt may be shared, we may be
3517 * racing with tg3_poll(), so only update last_tag
3518 * if tg3_poll() is not scheduled.
3519 */
3520 tp->last_tag = sblk->status_tag;
3521 __netif_rx_schedule(dev);
3522 }
3523 } else { /* shared interrupt */
3524 handled = 0;
3525 }
3526 out:
3527 return IRQ_RETVAL(handled);
3528 }
3529
3530 /* ISR for interrupt test */
3531 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3532 struct pt_regs *regs)
3533 {
3534 struct net_device *dev = dev_id;
3535 struct tg3 *tp = netdev_priv(dev);
3536 struct tg3_hw_status *sblk = tp->hw_status;
3537
3538 if ((sblk->status & SD_STATUS_UPDATED) ||
3539 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3540 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3541 0x00000001);
3542 return IRQ_RETVAL(1);
3543 }
3544 return IRQ_RETVAL(0);
3545 }
3546
3547 static int tg3_init_hw(struct tg3 *, int);
3548 static int tg3_halt(struct tg3 *, int, int);
3549
3550 #ifdef CONFIG_NET_POLL_CONTROLLER
3551 static void tg3_poll_controller(struct net_device *dev)
3552 {
3553 struct tg3 *tp = netdev_priv(dev);
3554
3555 tg3_interrupt(tp->pdev->irq, dev, NULL);
3556 }
3557 #endif
3558
3559 static void tg3_reset_task(void *_data)
3560 {
3561 struct tg3 *tp = _data;
3562 unsigned int restart_timer;
3563
3564 tg3_full_lock(tp, 0);
3565 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3566
3567 if (!netif_running(tp->dev)) {
3568 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3569 tg3_full_unlock(tp);
3570 return;
3571 }
3572
3573 tg3_full_unlock(tp);
3574
3575 tg3_netif_stop(tp);
3576
3577 tg3_full_lock(tp, 1);
3578
3579 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3580 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3581
3582 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3583 tg3_init_hw(tp, 1);
3584
3585 tg3_netif_start(tp);
3586
3587 if (restart_timer)
3588 mod_timer(&tp->timer, jiffies + 1);
3589
3590 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3591
3592 tg3_full_unlock(tp);
3593 }
3594
3595 static void tg3_tx_timeout(struct net_device *dev)
3596 {
3597 struct tg3 *tp = netdev_priv(dev);
3598
3599 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3600 dev->name);
3601
3602 schedule_work(&tp->reset_task);
3603 }
3604
3605 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3606 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3607 {
3608 u32 base = (u32) mapping & 0xffffffff;
3609
3610 return ((base > 0xffffdcc0) &&
3611 (base + len + 8 < base));
3612 }
3613
3614 /* Test for DMA addresses > 40-bit */
3615 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3616 int len)
3617 {
3618 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3619 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3620 return (((u64) mapping + len) > DMA_40BIT_MASK);
3621 return 0;
3622 #else
3623 return 0;
3624 #endif
3625 }
3626
3627 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3628
3629 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3630 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3631 u32 last_plus_one, u32 *start,
3632 u32 base_flags, u32 mss)
3633 {
3634 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3635 dma_addr_t new_addr = 0;
3636 u32 entry = *start;
3637 int i, ret = 0;
3638
3639 if (!new_skb) {
3640 ret = -1;
3641 } else {
3642 /* New SKB is guaranteed to be linear. */
3643 entry = *start;
3644 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3645 PCI_DMA_TODEVICE);
3646 /* Make sure new skb does not cross any 4G boundaries.
3647 * Drop the packet if it does.
3648 */
3649 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3650 ret = -1;
3651 dev_kfree_skb(new_skb);
3652 new_skb = NULL;
3653 } else {
3654 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3655 base_flags, 1 | (mss << 1));
3656 *start = NEXT_TX(entry);
3657 }
3658 }
3659
3660 /* Now clean up the sw ring entries. */
3661 i = 0;
3662 while (entry != last_plus_one) {
3663 int len;
3664
3665 if (i == 0)
3666 len = skb_headlen(skb);
3667 else
3668 len = skb_shinfo(skb)->frags[i-1].size;
3669 pci_unmap_single(tp->pdev,
3670 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3671 len, PCI_DMA_TODEVICE);
3672 if (i == 0) {
3673 tp->tx_buffers[entry].skb = new_skb;
3674 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3675 } else {
3676 tp->tx_buffers[entry].skb = NULL;
3677 }
3678 entry = NEXT_TX(entry);
3679 i++;
3680 }
3681
3682 dev_kfree_skb(skb);
3683
3684 return ret;
3685 }
3686
3687 static void tg3_set_txd(struct tg3 *tp, int entry,
3688 dma_addr_t mapping, int len, u32 flags,
3689 u32 mss_and_is_end)
3690 {
3691 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3692 int is_end = (mss_and_is_end & 0x1);
3693 u32 mss = (mss_and_is_end >> 1);
3694 u32 vlan_tag = 0;
3695
3696 if (is_end)
3697 flags |= TXD_FLAG_END;
3698 if (flags & TXD_FLAG_VLAN) {
3699 vlan_tag = flags >> 16;
3700 flags &= 0xffff;
3701 }
3702 vlan_tag |= (mss << TXD_MSS_SHIFT);
3703
3704 txd->addr_hi = ((u64) mapping >> 32);
3705 txd->addr_lo = ((u64) mapping & 0xffffffff);
3706 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3707 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3708 }
3709
3710 /* hard_start_xmit for devices that don't have any bugs and
3711 * support TG3_FLG2_HW_TSO_2 only.
3712 */
3713 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3714 {
3715 struct tg3 *tp = netdev_priv(dev);
3716 dma_addr_t mapping;
3717 u32 len, entry, base_flags, mss;
3718
3719 len = skb_headlen(skb);
3720
3721 /* No BH disabling for tx_lock here. We are running in BH disabled
3722 * context and TX reclaim runs via tp->poll inside of a software
3723 * interrupt. Furthermore, IRQ processing runs lockless so we have
3724 * no IRQ context deadlocks to worry about either. Rejoice!
3725 */
3726 if (!spin_trylock(&tp->tx_lock))
3727 return NETDEV_TX_LOCKED;
3728
3729 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3730 if (!netif_queue_stopped(dev)) {
3731 netif_stop_queue(dev);
3732
3733 /* This is a hard error, log it. */
3734 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3735 "queue awake!\n", dev->name);
3736 }
3737 spin_unlock(&tp->tx_lock);
3738 return NETDEV_TX_BUSY;
3739 }
3740
3741 entry = tp->tx_prod;
3742 base_flags = 0;
3743 #if TG3_TSO_SUPPORT != 0
3744 mss = 0;
3745 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3746 (mss = skb_shinfo(skb)->tso_size) != 0) {
3747 int tcp_opt_len, ip_tcp_len;
3748
3749 if (skb_header_cloned(skb) &&
3750 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3751 dev_kfree_skb(skb);
3752 goto out_unlock;
3753 }
3754
3755 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3756 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3757
3758 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3759 TXD_FLAG_CPU_POST_DMA);
3760
3761 skb->nh.iph->check = 0;
3762 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3763
3764 skb->h.th->check = 0;
3765
3766 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3767 }
3768 else if (skb->ip_summed == CHECKSUM_HW)
3769 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3770 #else
3771 mss = 0;
3772 if (skb->ip_summed == CHECKSUM_HW)
3773 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3774 #endif
3775 #if TG3_VLAN_TAG_USED
3776 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3777 base_flags |= (TXD_FLAG_VLAN |
3778 (vlan_tx_tag_get(skb) << 16));
3779 #endif
3780
3781 /* Queue skb data, a.k.a. the main skb fragment. */
3782 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3783
3784 tp->tx_buffers[entry].skb = skb;
3785 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3786
3787 tg3_set_txd(tp, entry, mapping, len, base_flags,
3788 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3789
3790 entry = NEXT_TX(entry);
3791
3792 /* Now loop through additional data fragments, and queue them. */
3793 if (skb_shinfo(skb)->nr_frags > 0) {
3794 unsigned int i, last;
3795
3796 last = skb_shinfo(skb)->nr_frags - 1;
3797 for (i = 0; i <= last; i++) {
3798 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3799
3800 len = frag->size;
3801 mapping = pci_map_page(tp->pdev,
3802 frag->page,
3803 frag->page_offset,
3804 len, PCI_DMA_TODEVICE);
3805
3806 tp->tx_buffers[entry].skb = NULL;
3807 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3808
3809 tg3_set_txd(tp, entry, mapping, len,
3810 base_flags, (i == last) | (mss << 1));
3811
3812 entry = NEXT_TX(entry);
3813 }
3814 }
3815
3816 /* Packets are ready, update Tx producer idx local and on card. */
3817 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3818
3819 tp->tx_prod = entry;
3820 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
3821 netif_stop_queue(dev);
3822 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3823 netif_wake_queue(tp->dev);
3824 }
3825
3826 out_unlock:
3827 mmiowb();
3828 spin_unlock(&tp->tx_lock);
3829
3830 dev->trans_start = jiffies;
3831
3832 return NETDEV_TX_OK;
3833 }
3834
3835 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3836 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3837 */
3838 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3839 {
3840 struct tg3 *tp = netdev_priv(dev);
3841 dma_addr_t mapping;
3842 u32 len, entry, base_flags, mss;
3843 int would_hit_hwbug;
3844
3845 len = skb_headlen(skb);
3846
3847 /* No BH disabling for tx_lock here. We are running in BH disabled
3848 * context and TX reclaim runs via tp->poll inside of a software
3849 * interrupt. Furthermore, IRQ processing runs lockless so we have
3850 * no IRQ context deadlocks to worry about either. Rejoice!
3851 */
3852 if (!spin_trylock(&tp->tx_lock))
3853 return NETDEV_TX_LOCKED;
3854
3855 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3856 if (!netif_queue_stopped(dev)) {
3857 netif_stop_queue(dev);
3858
3859 /* This is a hard error, log it. */
3860 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3861 "queue awake!\n", dev->name);
3862 }
3863 spin_unlock(&tp->tx_lock);
3864 return NETDEV_TX_BUSY;
3865 }
3866
3867 entry = tp->tx_prod;
3868 base_flags = 0;
3869 if (skb->ip_summed == CHECKSUM_HW)
3870 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3871 #if TG3_TSO_SUPPORT != 0
3872 mss = 0;
3873 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3874 (mss = skb_shinfo(skb)->tso_size) != 0) {
3875 int tcp_opt_len, ip_tcp_len;
3876
3877 if (skb_header_cloned(skb) &&
3878 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3879 dev_kfree_skb(skb);
3880 goto out_unlock;
3881 }
3882
3883 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3884 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3885
3886 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3887 TXD_FLAG_CPU_POST_DMA);
3888
3889 skb->nh.iph->check = 0;
3890 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3891 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3892 skb->h.th->check = 0;
3893 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3894 }
3895 else {
3896 skb->h.th->check =
3897 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3898 skb->nh.iph->daddr,
3899 0, IPPROTO_TCP, 0);
3900 }
3901
3902 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3903 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3904 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3905 int tsflags;
3906
3907 tsflags = ((skb->nh.iph->ihl - 5) +
3908 (tcp_opt_len >> 2));
3909 mss |= (tsflags << 11);
3910 }
3911 } else {
3912 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3913 int tsflags;
3914
3915 tsflags = ((skb->nh.iph->ihl - 5) +
3916 (tcp_opt_len >> 2));
3917 base_flags |= tsflags << 12;
3918 }
3919 }
3920 }
3921 #else
3922 mss = 0;
3923 #endif
3924 #if TG3_VLAN_TAG_USED
3925 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3926 base_flags |= (TXD_FLAG_VLAN |
3927 (vlan_tx_tag_get(skb) << 16));
3928 #endif
3929
3930 /* Queue skb data, a.k.a. the main skb fragment. */
3931 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3932
3933 tp->tx_buffers[entry].skb = skb;
3934 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3935
3936 would_hit_hwbug = 0;
3937
3938 if (tg3_4g_overflow_test(mapping, len))
3939 would_hit_hwbug = 1;
3940
3941 tg3_set_txd(tp, entry, mapping, len, base_flags,
3942 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3943
3944 entry = NEXT_TX(entry);
3945
3946 /* Now loop through additional data fragments, and queue them. */
3947 if (skb_shinfo(skb)->nr_frags > 0) {
3948 unsigned int i, last;
3949
3950 last = skb_shinfo(skb)->nr_frags - 1;
3951 for (i = 0; i <= last; i++) {
3952 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3953
3954 len = frag->size;
3955 mapping = pci_map_page(tp->pdev,
3956 frag->page,
3957 frag->page_offset,
3958 len, PCI_DMA_TODEVICE);
3959
3960 tp->tx_buffers[entry].skb = NULL;
3961 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3962
3963 if (tg3_4g_overflow_test(mapping, len))
3964 would_hit_hwbug = 1;
3965
3966 if (tg3_40bit_overflow_test(tp, mapping, len))
3967 would_hit_hwbug = 1;
3968
3969 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3970 tg3_set_txd(tp, entry, mapping, len,
3971 base_flags, (i == last)|(mss << 1));
3972 else
3973 tg3_set_txd(tp, entry, mapping, len,
3974 base_flags, (i == last));
3975
3976 entry = NEXT_TX(entry);
3977 }
3978 }
3979
3980 if (would_hit_hwbug) {
3981 u32 last_plus_one = entry;
3982 u32 start;
3983
3984 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3985 start &= (TG3_TX_RING_SIZE - 1);
3986
3987 /* If the workaround fails due to memory/mapping
3988 * failure, silently drop this packet.
3989 */
3990 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
3991 &start, base_flags, mss))
3992 goto out_unlock;
3993
3994 entry = start;
3995 }
3996
3997 /* Packets are ready, update Tx producer idx local and on card. */
3998 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3999
4000 tp->tx_prod = entry;
4001 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
4002 netif_stop_queue(dev);
4003 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
4004 netif_wake_queue(tp->dev);
4005 }
4006
4007 out_unlock:
4008 mmiowb();
4009 spin_unlock(&tp->tx_lock);
4010
4011 dev->trans_start = jiffies;
4012
4013 return NETDEV_TX_OK;
4014 }
4015
4016 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4017 int new_mtu)
4018 {
4019 dev->mtu = new_mtu;
4020
4021 if (new_mtu > ETH_DATA_LEN) {
4022 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4023 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4024 ethtool_op_set_tso(dev, 0);
4025 }
4026 else
4027 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4028 } else {
4029 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4030 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4031 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4032 }
4033 }
4034
4035 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4036 {
4037 struct tg3 *tp = netdev_priv(dev);
4038
4039 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4040 return -EINVAL;
4041
4042 if (!netif_running(dev)) {
4043 /* We'll just catch it later when the
4044 * device is up'd.
4045 */
4046 tg3_set_mtu(dev, tp, new_mtu);
4047 return 0;
4048 }
4049
4050 tg3_netif_stop(tp);
4051
4052 tg3_full_lock(tp, 1);
4053
4054 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4055
4056 tg3_set_mtu(dev, tp, new_mtu);
4057
4058 tg3_init_hw(tp, 0);
4059
4060 tg3_netif_start(tp);
4061
4062 tg3_full_unlock(tp);
4063
4064 return 0;
4065 }
4066
4067 /* Free up pending packets in all rx/tx rings.
4068 *
4069 * The chip has been shut down and the driver detached from
4070 * the networking, so no interrupts or new tx packets will
4071 * end up in the driver. tp->{tx,}lock is not held and we are not
4072 * in an interrupt context and thus may sleep.
4073 */
4074 static void tg3_free_rings(struct tg3 *tp)
4075 {
4076 struct ring_info *rxp;
4077 int i;
4078
4079 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4080 rxp = &tp->rx_std_buffers[i];
4081
4082 if (rxp->skb == NULL)
4083 continue;
4084 pci_unmap_single(tp->pdev,
4085 pci_unmap_addr(rxp, mapping),
4086 tp->rx_pkt_buf_sz - tp->rx_offset,
4087 PCI_DMA_FROMDEVICE);
4088 dev_kfree_skb_any(rxp->skb);
4089 rxp->skb = NULL;
4090 }
4091
4092 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4093 rxp = &tp->rx_jumbo_buffers[i];
4094
4095 if (rxp->skb == NULL)
4096 continue;
4097 pci_unmap_single(tp->pdev,
4098 pci_unmap_addr(rxp, mapping),
4099 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4100 PCI_DMA_FROMDEVICE);
4101 dev_kfree_skb_any(rxp->skb);
4102 rxp->skb = NULL;
4103 }
4104
4105 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4106 struct tx_ring_info *txp;
4107 struct sk_buff *skb;
4108 int j;
4109
4110 txp = &tp->tx_buffers[i];
4111 skb = txp->skb;
4112
4113 if (skb == NULL) {
4114 i++;
4115 continue;
4116 }
4117
4118 pci_unmap_single(tp->pdev,
4119 pci_unmap_addr(txp, mapping),
4120 skb_headlen(skb),
4121 PCI_DMA_TODEVICE);
4122 txp->skb = NULL;
4123
4124 i++;
4125
4126 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4127 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4128 pci_unmap_page(tp->pdev,
4129 pci_unmap_addr(txp, mapping),
4130 skb_shinfo(skb)->frags[j].size,
4131 PCI_DMA_TODEVICE);
4132 i++;
4133 }
4134
4135 dev_kfree_skb_any(skb);
4136 }
4137 }
4138
4139 /* Initialize tx/rx rings for packet processing.
4140 *
4141 * The chip has been shut down and the driver detached from
4142 * the networking, so no interrupts or new tx packets will
4143 * end up in the driver. tp->{tx,}lock are held and thus
4144 * we may not sleep.
4145 */
4146 static void tg3_init_rings(struct tg3 *tp)
4147 {
4148 u32 i;
4149
4150 /* Free up all the SKBs. */
4151 tg3_free_rings(tp);
4152
4153 /* Zero out all descriptors. */
4154 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4155 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4156 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4157 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4158
4159 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4160 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4161 (tp->dev->mtu > ETH_DATA_LEN))
4162 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4163
4164 /* Initialize invariants of the rings, we only set this
4165 * stuff once. This works because the card does not
4166 * write into the rx buffer posting rings.
4167 */
4168 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4169 struct tg3_rx_buffer_desc *rxd;
4170
4171 rxd = &tp->rx_std[i];
4172 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4173 << RXD_LEN_SHIFT;
4174 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4175 rxd->opaque = (RXD_OPAQUE_RING_STD |
4176 (i << RXD_OPAQUE_INDEX_SHIFT));
4177 }
4178
4179 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4180 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4181 struct tg3_rx_buffer_desc *rxd;
4182
4183 rxd = &tp->rx_jumbo[i];
4184 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4185 << RXD_LEN_SHIFT;
4186 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4187 RXD_FLAG_JUMBO;
4188 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4189 (i << RXD_OPAQUE_INDEX_SHIFT));
4190 }
4191 }
4192
4193 /* Now allocate fresh SKBs for each rx ring. */
4194 for (i = 0; i < tp->rx_pending; i++) {
4195 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
4196 -1, i) < 0)
4197 break;
4198 }
4199
4200 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4201 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4202 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4203 -1, i) < 0)
4204 break;
4205 }
4206 }
4207 }
4208
4209 /*
4210 * Must not be invoked with interrupt sources disabled and
4211 * the hardware shutdown down.
4212 */
4213 static void tg3_free_consistent(struct tg3 *tp)
4214 {
4215 kfree(tp->rx_std_buffers);
4216 tp->rx_std_buffers = NULL;
4217 if (tp->rx_std) {
4218 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4219 tp->rx_std, tp->rx_std_mapping);
4220 tp->rx_std = NULL;
4221 }
4222 if (tp->rx_jumbo) {
4223 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4224 tp->rx_jumbo, tp->rx_jumbo_mapping);
4225 tp->rx_jumbo = NULL;
4226 }
4227 if (tp->rx_rcb) {
4228 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4229 tp->rx_rcb, tp->rx_rcb_mapping);
4230 tp->rx_rcb = NULL;
4231 }
4232 if (tp->tx_ring) {
4233 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4234 tp->tx_ring, tp->tx_desc_mapping);
4235 tp->tx_ring = NULL;
4236 }
4237 if (tp->hw_status) {
4238 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4239 tp->hw_status, tp->status_mapping);
4240 tp->hw_status = NULL;
4241 }
4242 if (tp->hw_stats) {
4243 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4244 tp->hw_stats, tp->stats_mapping);
4245 tp->hw_stats = NULL;
4246 }
4247 }
4248
4249 /*
4250 * Must not be invoked with interrupt sources disabled and
4251 * the hardware shutdown down. Can sleep.
4252 */
4253 static int tg3_alloc_consistent(struct tg3 *tp)
4254 {
4255 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4256 (TG3_RX_RING_SIZE +
4257 TG3_RX_JUMBO_RING_SIZE)) +
4258 (sizeof(struct tx_ring_info) *
4259 TG3_TX_RING_SIZE),
4260 GFP_KERNEL);
4261 if (!tp->rx_std_buffers)
4262 return -ENOMEM;
4263
4264 memset(tp->rx_std_buffers, 0,
4265 (sizeof(struct ring_info) *
4266 (TG3_RX_RING_SIZE +
4267 TG3_RX_JUMBO_RING_SIZE)) +
4268 (sizeof(struct tx_ring_info) *
4269 TG3_TX_RING_SIZE));
4270
4271 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4272 tp->tx_buffers = (struct tx_ring_info *)
4273 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4274
4275 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4276 &tp->rx_std_mapping);
4277 if (!tp->rx_std)
4278 goto err_out;
4279
4280 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4281 &tp->rx_jumbo_mapping);
4282
4283 if (!tp->rx_jumbo)
4284 goto err_out;
4285
4286 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4287 &tp->rx_rcb_mapping);
4288 if (!tp->rx_rcb)
4289 goto err_out;
4290
4291 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4292 &tp->tx_desc_mapping);
4293 if (!tp->tx_ring)
4294 goto err_out;
4295
4296 tp->hw_status = pci_alloc_consistent(tp->pdev,
4297 TG3_HW_STATUS_SIZE,
4298 &tp->status_mapping);
4299 if (!tp->hw_status)
4300 goto err_out;
4301
4302 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4303 sizeof(struct tg3_hw_stats),
4304 &tp->stats_mapping);
4305 if (!tp->hw_stats)
4306 goto err_out;
4307
4308 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4309 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4310
4311 return 0;
4312
4313 err_out:
4314 tg3_free_consistent(tp);
4315 return -ENOMEM;
4316 }
4317
4318 #define MAX_WAIT_CNT 1000
4319
4320 /* To stop a block, clear the enable bit and poll till it
4321 * clears. tp->lock is held.
4322 */
4323 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4324 {
4325 unsigned int i;
4326 u32 val;
4327
4328 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4329 switch (ofs) {
4330 case RCVLSC_MODE:
4331 case DMAC_MODE:
4332 case MBFREE_MODE:
4333 case BUFMGR_MODE:
4334 case MEMARB_MODE:
4335 /* We can't enable/disable these bits of the
4336 * 5705/5750, just say success.
4337 */
4338 return 0;
4339
4340 default:
4341 break;
4342 };
4343 }
4344
4345 val = tr32(ofs);
4346 val &= ~enable_bit;
4347 tw32_f(ofs, val);
4348
4349 for (i = 0; i < MAX_WAIT_CNT; i++) {
4350 udelay(100);
4351 val = tr32(ofs);
4352 if ((val & enable_bit) == 0)
4353 break;
4354 }
4355
4356 if (i == MAX_WAIT_CNT && !silent) {
4357 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4358 "ofs=%lx enable_bit=%x\n",
4359 ofs, enable_bit);
4360 return -ENODEV;
4361 }
4362
4363 return 0;
4364 }
4365
4366 /* tp->lock is held. */
4367 static int tg3_abort_hw(struct tg3 *tp, int silent)
4368 {
4369 int i, err;
4370
4371 tg3_disable_ints(tp);
4372
4373 tp->rx_mode &= ~RX_MODE_ENABLE;
4374 tw32_f(MAC_RX_MODE, tp->rx_mode);
4375 udelay(10);
4376
4377 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4378 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4379 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4380 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4381 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4382 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4383
4384 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4385 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4386 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4387 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4388 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4389 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4390 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4391
4392 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4393 tw32_f(MAC_MODE, tp->mac_mode);
4394 udelay(40);
4395
4396 tp->tx_mode &= ~TX_MODE_ENABLE;
4397 tw32_f(MAC_TX_MODE, tp->tx_mode);
4398
4399 for (i = 0; i < MAX_WAIT_CNT; i++) {
4400 udelay(100);
4401 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4402 break;
4403 }
4404 if (i >= MAX_WAIT_CNT) {
4405 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4406 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4407 tp->dev->name, tr32(MAC_TX_MODE));
4408 err |= -ENODEV;
4409 }
4410
4411 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4412 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4413 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4414
4415 tw32(FTQ_RESET, 0xffffffff);
4416 tw32(FTQ_RESET, 0x00000000);
4417
4418 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4419 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4420
4421 if (tp->hw_status)
4422 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4423 if (tp->hw_stats)
4424 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4425
4426 return err;
4427 }
4428
4429 /* tp->lock is held. */
4430 static int tg3_nvram_lock(struct tg3 *tp)
4431 {
4432 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4433 int i;
4434
4435 if (tp->nvram_lock_cnt == 0) {
4436 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4437 for (i = 0; i < 8000; i++) {
4438 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4439 break;
4440 udelay(20);
4441 }
4442 if (i == 8000) {
4443 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4444 return -ENODEV;
4445 }
4446 }
4447 tp->nvram_lock_cnt++;
4448 }
4449 return 0;
4450 }
4451
4452 /* tp->lock is held. */
4453 static void tg3_nvram_unlock(struct tg3 *tp)
4454 {
4455 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4456 if (tp->nvram_lock_cnt > 0)
4457 tp->nvram_lock_cnt--;
4458 if (tp->nvram_lock_cnt == 0)
4459 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4460 }
4461 }
4462
4463 /* tp->lock is held. */
4464 static void tg3_enable_nvram_access(struct tg3 *tp)
4465 {
4466 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4467 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4468 u32 nvaccess = tr32(NVRAM_ACCESS);
4469
4470 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4471 }
4472 }
4473
4474 /* tp->lock is held. */
4475 static void tg3_disable_nvram_access(struct tg3 *tp)
4476 {
4477 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4478 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4479 u32 nvaccess = tr32(NVRAM_ACCESS);
4480
4481 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4482 }
4483 }
4484
4485 /* tp->lock is held. */
4486 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4487 {
4488 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4489 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4490
4491 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4492 switch (kind) {
4493 case RESET_KIND_INIT:
4494 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4495 DRV_STATE_START);
4496 break;
4497
4498 case RESET_KIND_SHUTDOWN:
4499 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4500 DRV_STATE_UNLOAD);
4501 break;
4502
4503 case RESET_KIND_SUSPEND:
4504 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4505 DRV_STATE_SUSPEND);
4506 break;
4507
4508 default:
4509 break;
4510 };
4511 }
4512 }
4513
4514 /* tp->lock is held. */
4515 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4516 {
4517 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4518 switch (kind) {
4519 case RESET_KIND_INIT:
4520 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4521 DRV_STATE_START_DONE);
4522 break;
4523
4524 case RESET_KIND_SHUTDOWN:
4525 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4526 DRV_STATE_UNLOAD_DONE);
4527 break;
4528
4529 default:
4530 break;
4531 };
4532 }
4533 }
4534
4535 /* tp->lock is held. */
4536 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4537 {
4538 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4539 switch (kind) {
4540 case RESET_KIND_INIT:
4541 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4542 DRV_STATE_START);
4543 break;
4544
4545 case RESET_KIND_SHUTDOWN:
4546 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4547 DRV_STATE_UNLOAD);
4548 break;
4549
4550 case RESET_KIND_SUSPEND:
4551 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4552 DRV_STATE_SUSPEND);
4553 break;
4554
4555 default:
4556 break;
4557 };
4558 }
4559 }
4560
4561 static void tg3_stop_fw(struct tg3 *);
4562
4563 /* tp->lock is held. */
4564 static int tg3_chip_reset(struct tg3 *tp)
4565 {
4566 u32 val;
4567 void (*write_op)(struct tg3 *, u32, u32);
4568 int i;
4569
4570 tg3_nvram_lock(tp);
4571
4572 /* No matching tg3_nvram_unlock() after this because
4573 * chip reset below will undo the nvram lock.
4574 */
4575 tp->nvram_lock_cnt = 0;
4576
4577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4580 tw32(GRC_FASTBOOT_PC, 0);
4581
4582 /*
4583 * We must avoid the readl() that normally takes place.
4584 * It locks machines, causes machine checks, and other
4585 * fun things. So, temporarily disable the 5701
4586 * hardware workaround, while we do the reset.
4587 */
4588 write_op = tp->write32;
4589 if (write_op == tg3_write_flush_reg32)
4590 tp->write32 = tg3_write32;
4591
4592 /* do the reset */
4593 val = GRC_MISC_CFG_CORECLK_RESET;
4594
4595 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4596 if (tr32(0x7e2c) == 0x60) {
4597 tw32(0x7e2c, 0x20);
4598 }
4599 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4600 tw32(GRC_MISC_CFG, (1 << 29));
4601 val |= (1 << 29);
4602 }
4603 }
4604
4605 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4606 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4607 tw32(GRC_MISC_CFG, val);
4608
4609 /* restore 5701 hardware bug workaround write method */
4610 tp->write32 = write_op;
4611
4612 /* Unfortunately, we have to delay before the PCI read back.
4613 * Some 575X chips even will not respond to a PCI cfg access
4614 * when the reset command is given to the chip.
4615 *
4616 * How do these hardware designers expect things to work
4617 * properly if the PCI write is posted for a long period
4618 * of time? It is always necessary to have some method by
4619 * which a register read back can occur to push the write
4620 * out which does the reset.
4621 *
4622 * For most tg3 variants the trick below was working.
4623 * Ho hum...
4624 */
4625 udelay(120);
4626
4627 /* Flush PCI posted writes. The normal MMIO registers
4628 * are inaccessible at this time so this is the only
4629 * way to make this reliably (actually, this is no longer
4630 * the case, see above). I tried to use indirect
4631 * register read/write but this upset some 5701 variants.
4632 */
4633 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4634
4635 udelay(120);
4636
4637 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4638 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4639 int i;
4640 u32 cfg_val;
4641
4642 /* Wait for link training to complete. */
4643 for (i = 0; i < 5000; i++)
4644 udelay(100);
4645
4646 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4647 pci_write_config_dword(tp->pdev, 0xc4,
4648 cfg_val | (1 << 15));
4649 }
4650 /* Set PCIE max payload size and clear error status. */
4651 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4652 }
4653
4654 /* Re-enable indirect register accesses. */
4655 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4656 tp->misc_host_ctrl);
4657
4658 /* Set MAX PCI retry to zero. */
4659 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4660 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4661 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4662 val |= PCISTATE_RETRY_SAME_DMA;
4663 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4664
4665 pci_restore_state(tp->pdev);
4666
4667 /* Make sure PCI-X relaxed ordering bit is clear. */
4668 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4669 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4670 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4671
4672 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4673 u32 val;
4674
4675 /* Chip reset on 5780 will reset MSI enable bit,
4676 * so need to restore it.
4677 */
4678 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4679 u16 ctrl;
4680
4681 pci_read_config_word(tp->pdev,
4682 tp->msi_cap + PCI_MSI_FLAGS,
4683 &ctrl);
4684 pci_write_config_word(tp->pdev,
4685 tp->msi_cap + PCI_MSI_FLAGS,
4686 ctrl | PCI_MSI_FLAGS_ENABLE);
4687 val = tr32(MSGINT_MODE);
4688 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4689 }
4690
4691 val = tr32(MEMARB_MODE);
4692 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4693
4694 } else
4695 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4696
4697 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4698 tg3_stop_fw(tp);
4699 tw32(0x5000, 0x400);
4700 }
4701
4702 tw32(GRC_MODE, tp->grc_mode);
4703
4704 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4705 u32 val = tr32(0xc4);
4706
4707 tw32(0xc4, val | (1 << 15));
4708 }
4709
4710 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4711 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4712 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4713 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4714 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4715 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4716 }
4717
4718 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4719 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4720 tw32_f(MAC_MODE, tp->mac_mode);
4721 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4722 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4723 tw32_f(MAC_MODE, tp->mac_mode);
4724 } else
4725 tw32_f(MAC_MODE, 0);
4726 udelay(40);
4727
4728 /* Wait for firmware initialization to complete. */
4729 for (i = 0; i < 100000; i++) {
4730 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4731 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4732 break;
4733 udelay(10);
4734 }
4735
4736 /* Chip might not be fitted with firmare. Some Sun onboard
4737 * parts are configured like that. So don't signal the timeout
4738 * of the above loop as an error, but do report the lack of
4739 * running firmware once.
4740 */
4741 if (i >= 100000 &&
4742 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4743 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4744
4745 printk(KERN_INFO PFX "%s: No firmware running.\n",
4746 tp->dev->name);
4747 }
4748
4749 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4750 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4751 u32 val = tr32(0x7c00);
4752
4753 tw32(0x7c00, val | (1 << 25));
4754 }
4755
4756 /* Reprobe ASF enable state. */
4757 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4758 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4759 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4760 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4761 u32 nic_cfg;
4762
4763 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4764 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4765 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4766 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4767 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4768 }
4769 }
4770
4771 return 0;
4772 }
4773
4774 /* tp->lock is held. */
4775 static void tg3_stop_fw(struct tg3 *tp)
4776 {
4777 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4778 u32 val;
4779 int i;
4780
4781 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4782 val = tr32(GRC_RX_CPU_EVENT);
4783 val |= (1 << 14);
4784 tw32(GRC_RX_CPU_EVENT, val);
4785
4786 /* Wait for RX cpu to ACK the event. */
4787 for (i = 0; i < 100; i++) {
4788 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4789 break;
4790 udelay(1);
4791 }
4792 }
4793 }
4794
4795 /* tp->lock is held. */
4796 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4797 {
4798 int err;
4799
4800 tg3_stop_fw(tp);
4801
4802 tg3_write_sig_pre_reset(tp, kind);
4803
4804 tg3_abort_hw(tp, silent);
4805 err = tg3_chip_reset(tp);
4806
4807 tg3_write_sig_legacy(tp, kind);
4808 tg3_write_sig_post_reset(tp, kind);
4809
4810 if (err)
4811 return err;
4812
4813 return 0;
4814 }
4815
4816 #define TG3_FW_RELEASE_MAJOR 0x0
4817 #define TG3_FW_RELASE_MINOR 0x0
4818 #define TG3_FW_RELEASE_FIX 0x0
4819 #define TG3_FW_START_ADDR 0x08000000
4820 #define TG3_FW_TEXT_ADDR 0x08000000
4821 #define TG3_FW_TEXT_LEN 0x9c0
4822 #define TG3_FW_RODATA_ADDR 0x080009c0
4823 #define TG3_FW_RODATA_LEN 0x60
4824 #define TG3_FW_DATA_ADDR 0x08000a40
4825 #define TG3_FW_DATA_LEN 0x20
4826 #define TG3_FW_SBSS_ADDR 0x08000a60
4827 #define TG3_FW_SBSS_LEN 0xc
4828 #define TG3_FW_BSS_ADDR 0x08000a70
4829 #define TG3_FW_BSS_LEN 0x10
4830
4831 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4832 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4833 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4834 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4835 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4836 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4837 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4838 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4839 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4840 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4841 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4842 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4843 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4844 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4845 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4846 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4847 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4848 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4849 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4850 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4851 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4852 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4853 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4854 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4855 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4856 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4857 0, 0, 0, 0, 0, 0,
4858 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4859 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4860 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4861 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4862 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4863 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4864 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4865 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4866 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4867 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4868 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4869 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4870 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4871 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4872 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4873 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4874 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4875 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4876 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4877 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4878 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4879 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4880 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4881 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4882 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4883 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4884 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4885 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4886 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4887 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4888 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4889 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4890 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4891 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4892 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4893 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4894 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4895 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4896 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4897 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4898 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4899 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4900 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4901 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4902 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4903 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4904 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4905 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4906 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4907 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4908 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4909 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4910 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4911 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4912 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4913 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4914 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4915 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4916 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4917 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4918 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4919 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4920 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4921 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4922 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4923 };
4924
4925 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4926 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4927 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4928 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4929 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4930 0x00000000
4931 };
4932
4933 #if 0 /* All zeros, don't eat up space with it. */
4934 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4935 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4936 0x00000000, 0x00000000, 0x00000000, 0x00000000
4937 };
4938 #endif
4939
4940 #define RX_CPU_SCRATCH_BASE 0x30000
4941 #define RX_CPU_SCRATCH_SIZE 0x04000
4942 #define TX_CPU_SCRATCH_BASE 0x34000
4943 #define TX_CPU_SCRATCH_SIZE 0x04000
4944
4945 /* tp->lock is held. */
4946 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4947 {
4948 int i;
4949
4950 BUG_ON(offset == TX_CPU_BASE &&
4951 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
4952
4953 if (offset == RX_CPU_BASE) {
4954 for (i = 0; i < 10000; i++) {
4955 tw32(offset + CPU_STATE, 0xffffffff);
4956 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4957 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4958 break;
4959 }
4960
4961 tw32(offset + CPU_STATE, 0xffffffff);
4962 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4963 udelay(10);
4964 } else {
4965 for (i = 0; i < 10000; i++) {
4966 tw32(offset + CPU_STATE, 0xffffffff);
4967 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4968 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4969 break;
4970 }
4971 }
4972
4973 if (i >= 10000) {
4974 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4975 "and %s CPU\n",
4976 tp->dev->name,
4977 (offset == RX_CPU_BASE ? "RX" : "TX"));
4978 return -ENODEV;
4979 }
4980
4981 /* Clear firmware's nvram arbitration. */
4982 if (tp->tg3_flags & TG3_FLAG_NVRAM)
4983 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
4984 return 0;
4985 }
4986
4987 struct fw_info {
4988 unsigned int text_base;
4989 unsigned int text_len;
4990 u32 *text_data;
4991 unsigned int rodata_base;
4992 unsigned int rodata_len;
4993 u32 *rodata_data;
4994 unsigned int data_base;
4995 unsigned int data_len;
4996 u32 *data_data;
4997 };
4998
4999 /* tp->lock is held. */
5000 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5001 int cpu_scratch_size, struct fw_info *info)
5002 {
5003 int err, lock_err, i;
5004 void (*write_op)(struct tg3 *, u32, u32);
5005
5006 if (cpu_base == TX_CPU_BASE &&
5007 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5008 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5009 "TX cpu firmware on %s which is 5705.\n",
5010 tp->dev->name);
5011 return -EINVAL;
5012 }
5013
5014 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5015 write_op = tg3_write_mem;
5016 else
5017 write_op = tg3_write_indirect_reg32;
5018
5019 /* It is possible that bootcode is still loading at this point.
5020 * Get the nvram lock first before halting the cpu.
5021 */
5022 lock_err = tg3_nvram_lock(tp);
5023 err = tg3_halt_cpu(tp, cpu_base);
5024 if (!lock_err)
5025 tg3_nvram_unlock(tp);
5026 if (err)
5027 goto out;
5028
5029 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5030 write_op(tp, cpu_scratch_base + i, 0);
5031 tw32(cpu_base + CPU_STATE, 0xffffffff);
5032 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5033 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5034 write_op(tp, (cpu_scratch_base +
5035 (info->text_base & 0xffff) +
5036 (i * sizeof(u32))),
5037 (info->text_data ?
5038 info->text_data[i] : 0));
5039 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5040 write_op(tp, (cpu_scratch_base +
5041 (info->rodata_base & 0xffff) +
5042 (i * sizeof(u32))),
5043 (info->rodata_data ?
5044 info->rodata_data[i] : 0));
5045 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5046 write_op(tp, (cpu_scratch_base +
5047 (info->data_base & 0xffff) +
5048 (i * sizeof(u32))),
5049 (info->data_data ?
5050 info->data_data[i] : 0));
5051
5052 err = 0;
5053
5054 out:
5055 return err;
5056 }
5057
5058 /* tp->lock is held. */
5059 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5060 {
5061 struct fw_info info;
5062 int err, i;
5063
5064 info.text_base = TG3_FW_TEXT_ADDR;
5065 info.text_len = TG3_FW_TEXT_LEN;
5066 info.text_data = &tg3FwText[0];
5067 info.rodata_base = TG3_FW_RODATA_ADDR;
5068 info.rodata_len = TG3_FW_RODATA_LEN;
5069 info.rodata_data = &tg3FwRodata[0];
5070 info.data_base = TG3_FW_DATA_ADDR;
5071 info.data_len = TG3_FW_DATA_LEN;
5072 info.data_data = NULL;
5073
5074 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5075 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5076 &info);
5077 if (err)
5078 return err;
5079
5080 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5081 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5082 &info);
5083 if (err)
5084 return err;
5085
5086 /* Now startup only the RX cpu. */
5087 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5088 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5089
5090 for (i = 0; i < 5; i++) {
5091 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5092 break;
5093 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5094 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5095 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5096 udelay(1000);
5097 }
5098 if (i >= 5) {
5099 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5100 "to set RX CPU PC, is %08x should be %08x\n",
5101 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5102 TG3_FW_TEXT_ADDR);
5103 return -ENODEV;
5104 }
5105 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5106 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5107
5108 return 0;
5109 }
5110
5111 #if TG3_TSO_SUPPORT != 0
5112
5113 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5114 #define TG3_TSO_FW_RELASE_MINOR 0x6
5115 #define TG3_TSO_FW_RELEASE_FIX 0x0
5116 #define TG3_TSO_FW_START_ADDR 0x08000000
5117 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5118 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5119 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5120 #define TG3_TSO_FW_RODATA_LEN 0x60
5121 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5122 #define TG3_TSO_FW_DATA_LEN 0x30
5123 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5124 #define TG3_TSO_FW_SBSS_LEN 0x2c
5125 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5126 #define TG3_TSO_FW_BSS_LEN 0x894
5127
5128 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5129 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5130 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5131 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5132 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5133 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5134 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5135 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5136 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5137 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5138 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5139 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5140 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5141 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5142 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5143 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5144 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5145 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5146 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5147 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5148 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5149 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5150 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5151 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5152 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5153 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5154 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5155 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5156 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5157 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5158 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5159 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5160 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5161 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5162 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5163 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5164 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5165 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5166 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5167 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5168 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5169 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5170 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5171 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5172 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5173 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5174 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5175 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5176 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5177 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5178 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5179 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5180 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5181 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5182 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5183 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5184 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5185 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5186 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5187 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5188 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5189 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5190 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5191 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5192 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5193 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5194 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5195 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5196 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5197 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5198 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5199 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5200 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5201 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5202 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5203 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5204 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5205 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5206 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5207 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5208 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5209 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5210 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5211 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5212 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5213 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5214 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5215 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5216 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5217 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5218 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5219 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5220 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5221 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5222 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5223 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5224 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5225 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5226 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5227 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5228 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5229 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5230 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5231 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5232 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5233 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5234 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5235 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5236 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5237 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5238 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5239 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5240 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5241 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5242 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5243 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5244 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5245 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5246 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5247 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5248 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5249 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5250 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5251 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5252 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5253 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5254 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5255 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5256 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5257 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5258 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5259 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5260 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5261 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5262 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5263 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5264 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5265 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5266 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5267 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5268 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5269 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5270 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5271 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5272 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5273 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5274 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5275 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5276 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5277 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5278 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5279 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5280 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5281 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5282 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5283 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5284 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5285 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5286 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5287 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5288 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5289 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5290 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5291 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5292 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5293 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5294 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5295 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5296 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5297 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5298 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5299 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5300 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5301 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5302 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5303 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5304 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5305 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5306 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5307 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5308 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5309 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5310 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5311 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5312 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5313 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5314 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5315 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5316 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5317 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5318 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5319 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5320 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5321 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5322 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5323 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5324 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5325 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5326 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5327 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5328 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5329 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5330 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5331 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5332 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5333 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5334 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5335 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5336 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5337 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5338 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5339 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5340 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5341 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5342 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5343 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5344 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5345 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5346 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5347 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5348 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5349 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5350 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5351 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5352 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5353 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5354 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5355 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5356 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5357 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5358 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5359 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5360 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5361 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5362 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5363 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5364 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5365 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5366 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5367 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5368 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5369 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5370 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5371 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5372 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5373 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5374 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5375 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5376 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5377 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5378 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5379 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5380 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5381 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5382 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5383 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5384 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5385 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5386 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5387 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5388 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5389 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5390 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5391 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5392 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5393 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5394 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5395 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5396 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5397 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5398 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5399 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5400 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5401 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5402 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5403 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5404 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5405 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5406 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5407 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5408 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5409 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5410 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5411 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5412 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5413 };
5414
5415 static u32 tg3TsoFwRodata[] = {
5416 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5417 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5418 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5419 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5420 0x00000000,
5421 };
5422
5423 static u32 tg3TsoFwData[] = {
5424 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5425 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5426 0x00000000,
5427 };
5428
5429 /* 5705 needs a special version of the TSO firmware. */
5430 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5431 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5432 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5433 #define TG3_TSO5_FW_START_ADDR 0x00010000
5434 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5435 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5436 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5437 #define TG3_TSO5_FW_RODATA_LEN 0x50
5438 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5439 #define TG3_TSO5_FW_DATA_LEN 0x20
5440 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5441 #define TG3_TSO5_FW_SBSS_LEN 0x28
5442 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5443 #define TG3_TSO5_FW_BSS_LEN 0x88
5444
5445 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5446 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5447 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5448 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5449 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5450 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5451 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5452 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5453 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5454 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5455 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5456 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5457 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5458 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5459 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5460 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5461 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5462 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5463 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5464 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5465 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5466 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5467 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5468 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5469 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5470 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5471 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5472 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5473 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5474 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5475 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5476 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5477 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5478 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5479 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5480 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5481 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5482 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5483 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5484 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5485 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5486 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5487 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5488 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5489 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5490 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5491 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5492 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5493 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5494 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5495 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5496 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5497 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5498 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5499 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5500 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5501 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5502 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5503 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5504 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5505 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5506 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5507 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5508 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5509 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5510 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5511 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5512 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5513 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5514 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5515 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5516 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5517 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5518 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5519 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5520 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5521 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5522 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5523 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5524 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5525 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5526 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5527 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5528 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5529 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5530 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5531 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5532 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5533 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5534 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5535 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5536 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5537 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5538 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5539 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5540 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5541 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5542 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5543 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5544 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5545 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5546 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5547 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5548 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5549 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5550 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5551 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5552 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5553 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5554 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5555 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5556 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5557 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5558 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5559 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5560 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5561 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5562 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5563 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5564 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5565 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5566 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5567 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5568 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5569 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5570 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5571 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5572 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5573 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5574 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5575 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5576 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5577 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5578 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5579 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5580 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5581 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5582 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5583 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5584 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5585 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5586 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5587 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5588 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5589 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5590 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5591 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5592 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5593 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5594 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5595 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5596 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5597 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5598 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5599 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5600 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5601 0x00000000, 0x00000000, 0x00000000,
5602 };
5603
5604 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5605 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5606 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5607 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5608 0x00000000, 0x00000000, 0x00000000,
5609 };
5610
5611 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5612 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5613 0x00000000, 0x00000000, 0x00000000,
5614 };
5615
5616 /* tp->lock is held. */
5617 static int tg3_load_tso_firmware(struct tg3 *tp)
5618 {
5619 struct fw_info info;
5620 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5621 int err, i;
5622
5623 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5624 return 0;
5625
5626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5627 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5628 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5629 info.text_data = &tg3Tso5FwText[0];
5630 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5631 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5632 info.rodata_data = &tg3Tso5FwRodata[0];
5633 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5634 info.data_len = TG3_TSO5_FW_DATA_LEN;
5635 info.data_data = &tg3Tso5FwData[0];
5636 cpu_base = RX_CPU_BASE;
5637 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5638 cpu_scratch_size = (info.text_len +
5639 info.rodata_len +
5640 info.data_len +
5641 TG3_TSO5_FW_SBSS_LEN +
5642 TG3_TSO5_FW_BSS_LEN);
5643 } else {
5644 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5645 info.text_len = TG3_TSO_FW_TEXT_LEN;
5646 info.text_data = &tg3TsoFwText[0];
5647 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5648 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5649 info.rodata_data = &tg3TsoFwRodata[0];
5650 info.data_base = TG3_TSO_FW_DATA_ADDR;
5651 info.data_len = TG3_TSO_FW_DATA_LEN;
5652 info.data_data = &tg3TsoFwData[0];
5653 cpu_base = TX_CPU_BASE;
5654 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5655 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5656 }
5657
5658 err = tg3_load_firmware_cpu(tp, cpu_base,
5659 cpu_scratch_base, cpu_scratch_size,
5660 &info);
5661 if (err)
5662 return err;
5663
5664 /* Now startup the cpu. */
5665 tw32(cpu_base + CPU_STATE, 0xffffffff);
5666 tw32_f(cpu_base + CPU_PC, info.text_base);
5667
5668 for (i = 0; i < 5; i++) {
5669 if (tr32(cpu_base + CPU_PC) == info.text_base)
5670 break;
5671 tw32(cpu_base + CPU_STATE, 0xffffffff);
5672 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5673 tw32_f(cpu_base + CPU_PC, info.text_base);
5674 udelay(1000);
5675 }
5676 if (i >= 5) {
5677 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5678 "to set CPU PC, is %08x should be %08x\n",
5679 tp->dev->name, tr32(cpu_base + CPU_PC),
5680 info.text_base);
5681 return -ENODEV;
5682 }
5683 tw32(cpu_base + CPU_STATE, 0xffffffff);
5684 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5685 return 0;
5686 }
5687
5688 #endif /* TG3_TSO_SUPPORT != 0 */
5689
5690 /* tp->lock is held. */
5691 static void __tg3_set_mac_addr(struct tg3 *tp)
5692 {
5693 u32 addr_high, addr_low;
5694 int i;
5695
5696 addr_high = ((tp->dev->dev_addr[0] << 8) |
5697 tp->dev->dev_addr[1]);
5698 addr_low = ((tp->dev->dev_addr[2] << 24) |
5699 (tp->dev->dev_addr[3] << 16) |
5700 (tp->dev->dev_addr[4] << 8) |
5701 (tp->dev->dev_addr[5] << 0));
5702 for (i = 0; i < 4; i++) {
5703 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5704 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5705 }
5706
5707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5709 for (i = 0; i < 12; i++) {
5710 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5711 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5712 }
5713 }
5714
5715 addr_high = (tp->dev->dev_addr[0] +
5716 tp->dev->dev_addr[1] +
5717 tp->dev->dev_addr[2] +
5718 tp->dev->dev_addr[3] +
5719 tp->dev->dev_addr[4] +
5720 tp->dev->dev_addr[5]) &
5721 TX_BACKOFF_SEED_MASK;
5722 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5723 }
5724
5725 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5726 {
5727 struct tg3 *tp = netdev_priv(dev);
5728 struct sockaddr *addr = p;
5729
5730 if (!is_valid_ether_addr(addr->sa_data))
5731 return -EINVAL;
5732
5733 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5734
5735 if (!netif_running(dev))
5736 return 0;
5737
5738 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5739 /* Reset chip so that ASF can re-init any MAC addresses it
5740 * needs.
5741 */
5742 tg3_netif_stop(tp);
5743 tg3_full_lock(tp, 1);
5744
5745 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5746 tg3_init_hw(tp, 0);
5747
5748 tg3_netif_start(tp);
5749 tg3_full_unlock(tp);
5750 } else {
5751 spin_lock_bh(&tp->lock);
5752 __tg3_set_mac_addr(tp);
5753 spin_unlock_bh(&tp->lock);
5754 }
5755
5756 return 0;
5757 }
5758
5759 /* tp->lock is held. */
5760 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5761 dma_addr_t mapping, u32 maxlen_flags,
5762 u32 nic_addr)
5763 {
5764 tg3_write_mem(tp,
5765 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5766 ((u64) mapping >> 32));
5767 tg3_write_mem(tp,
5768 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5769 ((u64) mapping & 0xffffffff));
5770 tg3_write_mem(tp,
5771 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5772 maxlen_flags);
5773
5774 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5775 tg3_write_mem(tp,
5776 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5777 nic_addr);
5778 }
5779
5780 static void __tg3_set_rx_mode(struct net_device *);
5781 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5782 {
5783 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5784 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5785 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5786 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5787 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5788 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5789 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5790 }
5791 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5792 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5793 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5794 u32 val = ec->stats_block_coalesce_usecs;
5795
5796 if (!netif_carrier_ok(tp->dev))
5797 val = 0;
5798
5799 tw32(HOSTCC_STAT_COAL_TICKS, val);
5800 }
5801 }
5802
5803 /* tp->lock is held. */
5804 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
5805 {
5806 u32 val, rdmac_mode;
5807 int i, err, limit;
5808
5809 tg3_disable_ints(tp);
5810
5811 tg3_stop_fw(tp);
5812
5813 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5814
5815 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5816 tg3_abort_hw(tp, 1);
5817 }
5818
5819 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && reset_phy)
5820 tg3_phy_reset(tp);
5821
5822 err = tg3_chip_reset(tp);
5823 if (err)
5824 return err;
5825
5826 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5827
5828 /* This works around an issue with Athlon chipsets on
5829 * B3 tigon3 silicon. This bit has no effect on any
5830 * other revision. But do not set this on PCI Express
5831 * chips.
5832 */
5833 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5834 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5835 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5836
5837 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5838 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5839 val = tr32(TG3PCI_PCISTATE);
5840 val |= PCISTATE_RETRY_SAME_DMA;
5841 tw32(TG3PCI_PCISTATE, val);
5842 }
5843
5844 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5845 /* Enable some hw fixes. */
5846 val = tr32(TG3PCI_MSI_DATA);
5847 val |= (1 << 26) | (1 << 28) | (1 << 29);
5848 tw32(TG3PCI_MSI_DATA, val);
5849 }
5850
5851 /* Descriptor ring init may make accesses to the
5852 * NIC SRAM area to setup the TX descriptors, so we
5853 * can only do this after the hardware has been
5854 * successfully reset.
5855 */
5856 tg3_init_rings(tp);
5857
5858 /* This value is determined during the probe time DMA
5859 * engine test, tg3_test_dma.
5860 */
5861 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5862
5863 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5864 GRC_MODE_4X_NIC_SEND_RINGS |
5865 GRC_MODE_NO_TX_PHDR_CSUM |
5866 GRC_MODE_NO_RX_PHDR_CSUM);
5867 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5868
5869 /* Pseudo-header checksum is done by hardware logic and not
5870 * the offload processers, so make the chip do the pseudo-
5871 * header checksums on receive. For transmit it is more
5872 * convenient to do the pseudo-header checksum in software
5873 * as Linux does that on transmit for us in all cases.
5874 */
5875 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5876
5877 tw32(GRC_MODE,
5878 tp->grc_mode |
5879 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5880
5881 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5882 val = tr32(GRC_MISC_CFG);
5883 val &= ~0xff;
5884 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5885 tw32(GRC_MISC_CFG, val);
5886
5887 /* Initialize MBUF/DESC pool. */
5888 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5889 /* Do nothing. */
5890 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5891 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5893 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5894 else
5895 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5896 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5897 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5898 }
5899 #if TG3_TSO_SUPPORT != 0
5900 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5901 int fw_len;
5902
5903 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5904 TG3_TSO5_FW_RODATA_LEN +
5905 TG3_TSO5_FW_DATA_LEN +
5906 TG3_TSO5_FW_SBSS_LEN +
5907 TG3_TSO5_FW_BSS_LEN);
5908 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5909 tw32(BUFMGR_MB_POOL_ADDR,
5910 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5911 tw32(BUFMGR_MB_POOL_SIZE,
5912 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5913 }
5914 #endif
5915
5916 if (tp->dev->mtu <= ETH_DATA_LEN) {
5917 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5918 tp->bufmgr_config.mbuf_read_dma_low_water);
5919 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5920 tp->bufmgr_config.mbuf_mac_rx_low_water);
5921 tw32(BUFMGR_MB_HIGH_WATER,
5922 tp->bufmgr_config.mbuf_high_water);
5923 } else {
5924 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5925 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5926 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5927 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5928 tw32(BUFMGR_MB_HIGH_WATER,
5929 tp->bufmgr_config.mbuf_high_water_jumbo);
5930 }
5931 tw32(BUFMGR_DMA_LOW_WATER,
5932 tp->bufmgr_config.dma_low_water);
5933 tw32(BUFMGR_DMA_HIGH_WATER,
5934 tp->bufmgr_config.dma_high_water);
5935
5936 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5937 for (i = 0; i < 2000; i++) {
5938 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5939 break;
5940 udelay(10);
5941 }
5942 if (i >= 2000) {
5943 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5944 tp->dev->name);
5945 return -ENODEV;
5946 }
5947
5948 /* Setup replenish threshold. */
5949 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5950
5951 /* Initialize TG3_BDINFO's at:
5952 * RCVDBDI_STD_BD: standard eth size rx ring
5953 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5954 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5955 *
5956 * like so:
5957 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5958 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5959 * ring attribute flags
5960 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5961 *
5962 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5963 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5964 *
5965 * The size of each ring is fixed in the firmware, but the location is
5966 * configurable.
5967 */
5968 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5969 ((u64) tp->rx_std_mapping >> 32));
5970 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5971 ((u64) tp->rx_std_mapping & 0xffffffff));
5972 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5973 NIC_SRAM_RX_BUFFER_DESC);
5974
5975 /* Don't even try to program the JUMBO/MINI buffer descriptor
5976 * configs on 5705.
5977 */
5978 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5979 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5980 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5981 } else {
5982 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5983 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5984
5985 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5986 BDINFO_FLAGS_DISABLED);
5987
5988 /* Setup replenish threshold. */
5989 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5990
5991 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5992 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5993 ((u64) tp->rx_jumbo_mapping >> 32));
5994 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5995 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5996 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5997 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5998 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5999 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6000 } else {
6001 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6002 BDINFO_FLAGS_DISABLED);
6003 }
6004
6005 }
6006
6007 /* There is only one send ring on 5705/5750, no need to explicitly
6008 * disable the others.
6009 */
6010 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6011 /* Clear out send RCB ring in SRAM. */
6012 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6013 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6014 BDINFO_FLAGS_DISABLED);
6015 }
6016
6017 tp->tx_prod = 0;
6018 tp->tx_cons = 0;
6019 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6020 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6021
6022 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6023 tp->tx_desc_mapping,
6024 (TG3_TX_RING_SIZE <<
6025 BDINFO_FLAGS_MAXLEN_SHIFT),
6026 NIC_SRAM_TX_BUFFER_DESC);
6027
6028 /* There is only one receive return ring on 5705/5750, no need
6029 * to explicitly disable the others.
6030 */
6031 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6032 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6033 i += TG3_BDINFO_SIZE) {
6034 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6035 BDINFO_FLAGS_DISABLED);
6036 }
6037 }
6038
6039 tp->rx_rcb_ptr = 0;
6040 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6041
6042 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6043 tp->rx_rcb_mapping,
6044 (TG3_RX_RCB_RING_SIZE(tp) <<
6045 BDINFO_FLAGS_MAXLEN_SHIFT),
6046 0);
6047
6048 tp->rx_std_ptr = tp->rx_pending;
6049 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6050 tp->rx_std_ptr);
6051
6052 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6053 tp->rx_jumbo_pending : 0;
6054 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6055 tp->rx_jumbo_ptr);
6056
6057 /* Initialize MAC address and backoff seed. */
6058 __tg3_set_mac_addr(tp);
6059
6060 /* MTU + ethernet header + FCS + optional VLAN tag */
6061 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6062
6063 /* The slot time is changed by tg3_setup_phy if we
6064 * run at gigabit with half duplex.
6065 */
6066 tw32(MAC_TX_LENGTHS,
6067 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6068 (6 << TX_LENGTHS_IPG_SHIFT) |
6069 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6070
6071 /* Receive rules. */
6072 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6073 tw32(RCVLPC_CONFIG, 0x0181);
6074
6075 /* Calculate RDMAC_MODE setting early, we need it to determine
6076 * the RCVLPC_STATE_ENABLE mask.
6077 */
6078 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6079 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6080 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6081 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6082 RDMAC_MODE_LNGREAD_ENAB);
6083 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6084 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6085
6086 /* If statement applies to 5705 and 5750 PCI devices only */
6087 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6088 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6089 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6090 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6091 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6092 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6093 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6094 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6095 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6096 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6097 }
6098 }
6099
6100 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6101 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6102
6103 #if TG3_TSO_SUPPORT != 0
6104 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6105 rdmac_mode |= (1 << 27);
6106 #endif
6107
6108 /* Receive/send statistics. */
6109 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6110 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6111 val = tr32(RCVLPC_STATS_ENABLE);
6112 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6113 tw32(RCVLPC_STATS_ENABLE, val);
6114 } else {
6115 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6116 }
6117 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6118 tw32(SNDDATAI_STATSENAB, 0xffffff);
6119 tw32(SNDDATAI_STATSCTRL,
6120 (SNDDATAI_SCTRL_ENABLE |
6121 SNDDATAI_SCTRL_FASTUPD));
6122
6123 /* Setup host coalescing engine. */
6124 tw32(HOSTCC_MODE, 0);
6125 for (i = 0; i < 2000; i++) {
6126 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6127 break;
6128 udelay(10);
6129 }
6130
6131 __tg3_set_coalesce(tp, &tp->coal);
6132
6133 /* set status block DMA address */
6134 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6135 ((u64) tp->status_mapping >> 32));
6136 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6137 ((u64) tp->status_mapping & 0xffffffff));
6138
6139 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6140 /* Status/statistics block address. See tg3_timer,
6141 * the tg3_periodic_fetch_stats call there, and
6142 * tg3_get_stats to see how this works for 5705/5750 chips.
6143 */
6144 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6145 ((u64) tp->stats_mapping >> 32));
6146 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6147 ((u64) tp->stats_mapping & 0xffffffff));
6148 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6149 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6150 }
6151
6152 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6153
6154 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6155 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6156 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6157 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6158
6159 /* Clear statistics/status block in chip, and status block in ram. */
6160 for (i = NIC_SRAM_STATS_BLK;
6161 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6162 i += sizeof(u32)) {
6163 tg3_write_mem(tp, i, 0);
6164 udelay(40);
6165 }
6166 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6167
6168 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6169 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6170 /* reset to prevent losing 1st rx packet intermittently */
6171 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6172 udelay(10);
6173 }
6174
6175 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6176 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6177 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6178 udelay(40);
6179
6180 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6181 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
6182 * register to preserve the GPIO settings for LOMs. The GPIOs,
6183 * whether used as inputs or outputs, are set by boot code after
6184 * reset.
6185 */
6186 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
6187 u32 gpio_mask;
6188
6189 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
6190 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
6191
6192 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6193 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6194 GRC_LCLCTRL_GPIO_OUTPUT3;
6195
6196 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6197 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6198
6199 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6200
6201 /* GPIO1 must be driven high for eeprom write protect */
6202 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6203 GRC_LCLCTRL_GPIO_OUTPUT1);
6204 }
6205 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6206 udelay(100);
6207
6208 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6209 tp->last_tag = 0;
6210
6211 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6212 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6213 udelay(40);
6214 }
6215
6216 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6217 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6218 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6219 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6220 WDMAC_MODE_LNGREAD_ENAB);
6221
6222 /* If statement applies to 5705 and 5750 PCI devices only */
6223 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6224 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6226 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6227 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6228 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6229 /* nothing */
6230 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6231 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6232 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6233 val |= WDMAC_MODE_RX_ACCEL;
6234 }
6235 }
6236
6237 /* Enable host coalescing bug fix */
6238 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6239 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6240 val |= (1 << 29);
6241
6242 tw32_f(WDMAC_MODE, val);
6243 udelay(40);
6244
6245 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6246 val = tr32(TG3PCI_X_CAPS);
6247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6248 val &= ~PCIX_CAPS_BURST_MASK;
6249 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6250 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6251 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6252 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6253 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6254 val |= (tp->split_mode_max_reqs <<
6255 PCIX_CAPS_SPLIT_SHIFT);
6256 }
6257 tw32(TG3PCI_X_CAPS, val);
6258 }
6259
6260 tw32_f(RDMAC_MODE, rdmac_mode);
6261 udelay(40);
6262
6263 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6264 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6265 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6266 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6267 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6268 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6269 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6270 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6271 #if TG3_TSO_SUPPORT != 0
6272 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6273 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6274 #endif
6275 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6276 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6277
6278 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6279 err = tg3_load_5701_a0_firmware_fix(tp);
6280 if (err)
6281 return err;
6282 }
6283
6284 #if TG3_TSO_SUPPORT != 0
6285 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6286 err = tg3_load_tso_firmware(tp);
6287 if (err)
6288 return err;
6289 }
6290 #endif
6291
6292 tp->tx_mode = TX_MODE_ENABLE;
6293 tw32_f(MAC_TX_MODE, tp->tx_mode);
6294 udelay(100);
6295
6296 tp->rx_mode = RX_MODE_ENABLE;
6297 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6298 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6299
6300 tw32_f(MAC_RX_MODE, tp->rx_mode);
6301 udelay(10);
6302
6303 if (tp->link_config.phy_is_low_power) {
6304 tp->link_config.phy_is_low_power = 0;
6305 tp->link_config.speed = tp->link_config.orig_speed;
6306 tp->link_config.duplex = tp->link_config.orig_duplex;
6307 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6308 }
6309
6310 tp->mi_mode = MAC_MI_MODE_BASE;
6311 tw32_f(MAC_MI_MODE, tp->mi_mode);
6312 udelay(80);
6313
6314 tw32(MAC_LED_CTRL, tp->led_ctrl);
6315
6316 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6317 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6318 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6319 udelay(10);
6320 }
6321 tw32_f(MAC_RX_MODE, tp->rx_mode);
6322 udelay(10);
6323
6324 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6325 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6326 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6327 /* Set drive transmission level to 1.2V */
6328 /* only if the signal pre-emphasis bit is not set */
6329 val = tr32(MAC_SERDES_CFG);
6330 val &= 0xfffff000;
6331 val |= 0x880;
6332 tw32(MAC_SERDES_CFG, val);
6333 }
6334 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6335 tw32(MAC_SERDES_CFG, 0x616000);
6336 }
6337
6338 /* Prevent chip from dropping frames when flow control
6339 * is enabled.
6340 */
6341 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6342
6343 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6344 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6345 /* Use hardware link auto-negotiation */
6346 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6347 }
6348
6349 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6350 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6351 u32 tmp;
6352
6353 tmp = tr32(SERDES_RX_CTRL);
6354 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6355 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6356 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6357 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6358 }
6359
6360 err = tg3_setup_phy(tp, reset_phy);
6361 if (err)
6362 return err;
6363
6364 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6365 u32 tmp;
6366
6367 /* Clear CRC stats. */
6368 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6369 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6370 tg3_readphy(tp, 0x14, &tmp);
6371 }
6372 }
6373
6374 __tg3_set_rx_mode(tp->dev);
6375
6376 /* Initialize receive rules. */
6377 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6378 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6379 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6380 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6381
6382 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6383 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6384 limit = 8;
6385 else
6386 limit = 16;
6387 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6388 limit -= 4;
6389 switch (limit) {
6390 case 16:
6391 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6392 case 15:
6393 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6394 case 14:
6395 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6396 case 13:
6397 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6398 case 12:
6399 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6400 case 11:
6401 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6402 case 10:
6403 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6404 case 9:
6405 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6406 case 8:
6407 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6408 case 7:
6409 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6410 case 6:
6411 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6412 case 5:
6413 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6414 case 4:
6415 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6416 case 3:
6417 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6418 case 2:
6419 case 1:
6420
6421 default:
6422 break;
6423 };
6424
6425 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6426
6427 return 0;
6428 }
6429
6430 /* Called at device open time to get the chip ready for
6431 * packet processing. Invoked with tp->lock held.
6432 */
6433 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6434 {
6435 int err;
6436
6437 /* Force the chip into D0. */
6438 err = tg3_set_power_state(tp, PCI_D0);
6439 if (err)
6440 goto out;
6441
6442 tg3_switch_clocks(tp);
6443
6444 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6445
6446 err = tg3_reset_hw(tp, reset_phy);
6447
6448 out:
6449 return err;
6450 }
6451
6452 #define TG3_STAT_ADD32(PSTAT, REG) \
6453 do { u32 __val = tr32(REG); \
6454 (PSTAT)->low += __val; \
6455 if ((PSTAT)->low < __val) \
6456 (PSTAT)->high += 1; \
6457 } while (0)
6458
6459 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6460 {
6461 struct tg3_hw_stats *sp = tp->hw_stats;
6462
6463 if (!netif_carrier_ok(tp->dev))
6464 return;
6465
6466 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6467 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6468 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6469 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6470 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6471 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6472 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6473 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6474 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6475 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6476 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6477 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6478 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6479
6480 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6481 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6482 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6483 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6484 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6485 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6486 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6487 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6488 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6489 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6490 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6491 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6492 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6493 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6494
6495 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6496 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6497 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6498 }
6499
6500 static void tg3_timer(unsigned long __opaque)
6501 {
6502 struct tg3 *tp = (struct tg3 *) __opaque;
6503
6504 if (tp->irq_sync)
6505 goto restart_timer;
6506
6507 spin_lock(&tp->lock);
6508
6509 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6510 /* All of this garbage is because when using non-tagged
6511 * IRQ status the mailbox/status_block protocol the chip
6512 * uses with the cpu is race prone.
6513 */
6514 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6515 tw32(GRC_LOCAL_CTRL,
6516 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6517 } else {
6518 tw32(HOSTCC_MODE, tp->coalesce_mode |
6519 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6520 }
6521
6522 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6523 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6524 spin_unlock(&tp->lock);
6525 schedule_work(&tp->reset_task);
6526 return;
6527 }
6528 }
6529
6530 /* This part only runs once per second. */
6531 if (!--tp->timer_counter) {
6532 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6533 tg3_periodic_fetch_stats(tp);
6534
6535 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6536 u32 mac_stat;
6537 int phy_event;
6538
6539 mac_stat = tr32(MAC_STATUS);
6540
6541 phy_event = 0;
6542 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6543 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6544 phy_event = 1;
6545 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6546 phy_event = 1;
6547
6548 if (phy_event)
6549 tg3_setup_phy(tp, 0);
6550 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6551 u32 mac_stat = tr32(MAC_STATUS);
6552 int need_setup = 0;
6553
6554 if (netif_carrier_ok(tp->dev) &&
6555 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6556 need_setup = 1;
6557 }
6558 if (! netif_carrier_ok(tp->dev) &&
6559 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6560 MAC_STATUS_SIGNAL_DET))) {
6561 need_setup = 1;
6562 }
6563 if (need_setup) {
6564 tw32_f(MAC_MODE,
6565 (tp->mac_mode &
6566 ~MAC_MODE_PORT_MODE_MASK));
6567 udelay(40);
6568 tw32_f(MAC_MODE, tp->mac_mode);
6569 udelay(40);
6570 tg3_setup_phy(tp, 0);
6571 }
6572 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6573 tg3_serdes_parallel_detect(tp);
6574
6575 tp->timer_counter = tp->timer_multiplier;
6576 }
6577
6578 /* Heartbeat is only sent once every 2 seconds. */
6579 if (!--tp->asf_counter) {
6580 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6581 u32 val;
6582
6583 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6584 FWCMD_NICDRV_ALIVE2);
6585 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6586 /* 5 seconds timeout */
6587 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6588 val = tr32(GRC_RX_CPU_EVENT);
6589 val |= (1 << 14);
6590 tw32(GRC_RX_CPU_EVENT, val);
6591 }
6592 tp->asf_counter = tp->asf_multiplier;
6593 }
6594
6595 spin_unlock(&tp->lock);
6596
6597 restart_timer:
6598 tp->timer.expires = jiffies + tp->timer_offset;
6599 add_timer(&tp->timer);
6600 }
6601
6602 static int tg3_request_irq(struct tg3 *tp)
6603 {
6604 irqreturn_t (*fn)(int, void *, struct pt_regs *);
6605 unsigned long flags;
6606 struct net_device *dev = tp->dev;
6607
6608 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6609 fn = tg3_msi;
6610 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6611 fn = tg3_msi_1shot;
6612 flags = SA_SAMPLE_RANDOM;
6613 } else {
6614 fn = tg3_interrupt;
6615 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6616 fn = tg3_interrupt_tagged;
6617 flags = SA_SHIRQ | SA_SAMPLE_RANDOM;
6618 }
6619 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6620 }
6621
6622 static int tg3_test_interrupt(struct tg3 *tp)
6623 {
6624 struct net_device *dev = tp->dev;
6625 int err, i;
6626 u32 int_mbox = 0;
6627
6628 if (!netif_running(dev))
6629 return -ENODEV;
6630
6631 tg3_disable_ints(tp);
6632
6633 free_irq(tp->pdev->irq, dev);
6634
6635 err = request_irq(tp->pdev->irq, tg3_test_isr,
6636 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6637 if (err)
6638 return err;
6639
6640 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6641 tg3_enable_ints(tp);
6642
6643 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6644 HOSTCC_MODE_NOW);
6645
6646 for (i = 0; i < 5; i++) {
6647 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6648 TG3_64BIT_REG_LOW);
6649 if (int_mbox != 0)
6650 break;
6651 msleep(10);
6652 }
6653
6654 tg3_disable_ints(tp);
6655
6656 free_irq(tp->pdev->irq, dev);
6657
6658 err = tg3_request_irq(tp);
6659
6660 if (err)
6661 return err;
6662
6663 if (int_mbox != 0)
6664 return 0;
6665
6666 return -EIO;
6667 }
6668
6669 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6670 * successfully restored
6671 */
6672 static int tg3_test_msi(struct tg3 *tp)
6673 {
6674 struct net_device *dev = tp->dev;
6675 int err;
6676 u16 pci_cmd;
6677
6678 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6679 return 0;
6680
6681 /* Turn off SERR reporting in case MSI terminates with Master
6682 * Abort.
6683 */
6684 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6685 pci_write_config_word(tp->pdev, PCI_COMMAND,
6686 pci_cmd & ~PCI_COMMAND_SERR);
6687
6688 err = tg3_test_interrupt(tp);
6689
6690 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6691
6692 if (!err)
6693 return 0;
6694
6695 /* other failures */
6696 if (err != -EIO)
6697 return err;
6698
6699 /* MSI test failed, go back to INTx mode */
6700 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6701 "switching to INTx mode. Please report this failure to "
6702 "the PCI maintainer and include system chipset information.\n",
6703 tp->dev->name);
6704
6705 free_irq(tp->pdev->irq, dev);
6706 pci_disable_msi(tp->pdev);
6707
6708 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6709
6710 err = tg3_request_irq(tp);
6711 if (err)
6712 return err;
6713
6714 /* Need to reset the chip because the MSI cycle may have terminated
6715 * with Master Abort.
6716 */
6717 tg3_full_lock(tp, 1);
6718
6719 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6720 err = tg3_init_hw(tp, 1);
6721
6722 tg3_full_unlock(tp);
6723
6724 if (err)
6725 free_irq(tp->pdev->irq, dev);
6726
6727 return err;
6728 }
6729
6730 static int tg3_open(struct net_device *dev)
6731 {
6732 struct tg3 *tp = netdev_priv(dev);
6733 int err;
6734
6735 tg3_full_lock(tp, 0);
6736
6737 err = tg3_set_power_state(tp, PCI_D0);
6738 if (err)
6739 return err;
6740
6741 tg3_disable_ints(tp);
6742 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6743
6744 tg3_full_unlock(tp);
6745
6746 /* The placement of this call is tied
6747 * to the setup and use of Host TX descriptors.
6748 */
6749 err = tg3_alloc_consistent(tp);
6750 if (err)
6751 return err;
6752
6753 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6754 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6755 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
6756 !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
6757 (tp->pdev_peer == tp->pdev))) {
6758 /* All MSI supporting chips should support tagged
6759 * status. Assert that this is the case.
6760 */
6761 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6762 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6763 "Not using MSI.\n", tp->dev->name);
6764 } else if (pci_enable_msi(tp->pdev) == 0) {
6765 u32 msi_mode;
6766
6767 msi_mode = tr32(MSGINT_MODE);
6768 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6769 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6770 }
6771 }
6772 err = tg3_request_irq(tp);
6773
6774 if (err) {
6775 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6776 pci_disable_msi(tp->pdev);
6777 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6778 }
6779 tg3_free_consistent(tp);
6780 return err;
6781 }
6782
6783 tg3_full_lock(tp, 0);
6784
6785 err = tg3_init_hw(tp, 1);
6786 if (err) {
6787 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6788 tg3_free_rings(tp);
6789 } else {
6790 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6791 tp->timer_offset = HZ;
6792 else
6793 tp->timer_offset = HZ / 10;
6794
6795 BUG_ON(tp->timer_offset > HZ);
6796 tp->timer_counter = tp->timer_multiplier =
6797 (HZ / tp->timer_offset);
6798 tp->asf_counter = tp->asf_multiplier =
6799 ((HZ / tp->timer_offset) * 2);
6800
6801 init_timer(&tp->timer);
6802 tp->timer.expires = jiffies + tp->timer_offset;
6803 tp->timer.data = (unsigned long) tp;
6804 tp->timer.function = tg3_timer;
6805 }
6806
6807 tg3_full_unlock(tp);
6808
6809 if (err) {
6810 free_irq(tp->pdev->irq, dev);
6811 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6812 pci_disable_msi(tp->pdev);
6813 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6814 }
6815 tg3_free_consistent(tp);
6816 return err;
6817 }
6818
6819 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6820 err = tg3_test_msi(tp);
6821
6822 if (err) {
6823 tg3_full_lock(tp, 0);
6824
6825 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6826 pci_disable_msi(tp->pdev);
6827 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6828 }
6829 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6830 tg3_free_rings(tp);
6831 tg3_free_consistent(tp);
6832
6833 tg3_full_unlock(tp);
6834
6835 return err;
6836 }
6837
6838 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6839 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
6840 u32 val = tr32(0x7c04);
6841
6842 tw32(0x7c04, val | (1 << 29));
6843 }
6844 }
6845 }
6846
6847 tg3_full_lock(tp, 0);
6848
6849 add_timer(&tp->timer);
6850 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6851 tg3_enable_ints(tp);
6852
6853 tg3_full_unlock(tp);
6854
6855 netif_start_queue(dev);
6856
6857 return 0;
6858 }
6859
6860 #if 0
6861 /*static*/ void tg3_dump_state(struct tg3 *tp)
6862 {
6863 u32 val32, val32_2, val32_3, val32_4, val32_5;
6864 u16 val16;
6865 int i;
6866
6867 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6868 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6869 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6870 val16, val32);
6871
6872 /* MAC block */
6873 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6874 tr32(MAC_MODE), tr32(MAC_STATUS));
6875 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6876 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6877 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6878 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6879 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6880 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6881
6882 /* Send data initiator control block */
6883 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6884 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6885 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6886 tr32(SNDDATAI_STATSCTRL));
6887
6888 /* Send data completion control block */
6889 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6890
6891 /* Send BD ring selector block */
6892 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6893 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6894
6895 /* Send BD initiator control block */
6896 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6897 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6898
6899 /* Send BD completion control block */
6900 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6901
6902 /* Receive list placement control block */
6903 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6904 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6905 printk(" RCVLPC_STATSCTRL[%08x]\n",
6906 tr32(RCVLPC_STATSCTRL));
6907
6908 /* Receive data and receive BD initiator control block */
6909 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6910 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6911
6912 /* Receive data completion control block */
6913 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6914 tr32(RCVDCC_MODE));
6915
6916 /* Receive BD initiator control block */
6917 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6918 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6919
6920 /* Receive BD completion control block */
6921 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6922 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6923
6924 /* Receive list selector control block */
6925 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6926 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6927
6928 /* Mbuf cluster free block */
6929 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6930 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6931
6932 /* Host coalescing control block */
6933 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6934 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6935 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6936 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6937 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6938 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6939 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6940 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6941 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6942 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6943 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6944 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6945
6946 /* Memory arbiter control block */
6947 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6948 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6949
6950 /* Buffer manager control block */
6951 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6952 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6953 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6954 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6955 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6956 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6957 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6958 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6959
6960 /* Read DMA control block */
6961 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6962 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6963
6964 /* Write DMA control block */
6965 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6966 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6967
6968 /* DMA completion block */
6969 printk("DEBUG: DMAC_MODE[%08x]\n",
6970 tr32(DMAC_MODE));
6971
6972 /* GRC block */
6973 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6974 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6975 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6976 tr32(GRC_LOCAL_CTRL));
6977
6978 /* TG3_BDINFOs */
6979 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6980 tr32(RCVDBDI_JUMBO_BD + 0x0),
6981 tr32(RCVDBDI_JUMBO_BD + 0x4),
6982 tr32(RCVDBDI_JUMBO_BD + 0x8),
6983 tr32(RCVDBDI_JUMBO_BD + 0xc));
6984 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6985 tr32(RCVDBDI_STD_BD + 0x0),
6986 tr32(RCVDBDI_STD_BD + 0x4),
6987 tr32(RCVDBDI_STD_BD + 0x8),
6988 tr32(RCVDBDI_STD_BD + 0xc));
6989 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6990 tr32(RCVDBDI_MINI_BD + 0x0),
6991 tr32(RCVDBDI_MINI_BD + 0x4),
6992 tr32(RCVDBDI_MINI_BD + 0x8),
6993 tr32(RCVDBDI_MINI_BD + 0xc));
6994
6995 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6996 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6997 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6998 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6999 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7000 val32, val32_2, val32_3, val32_4);
7001
7002 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7003 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7004 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7005 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7006 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7007 val32, val32_2, val32_3, val32_4);
7008
7009 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7010 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7011 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7012 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7013 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7014 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7015 val32, val32_2, val32_3, val32_4, val32_5);
7016
7017 /* SW status block */
7018 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7019 tp->hw_status->status,
7020 tp->hw_status->status_tag,
7021 tp->hw_status->rx_jumbo_consumer,
7022 tp->hw_status->rx_consumer,
7023 tp->hw_status->rx_mini_consumer,
7024 tp->hw_status->idx[0].rx_producer,
7025 tp->hw_status->idx[0].tx_consumer);
7026
7027 /* SW statistics block */
7028 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7029 ((u32 *)tp->hw_stats)[0],
7030 ((u32 *)tp->hw_stats)[1],
7031 ((u32 *)tp->hw_stats)[2],
7032 ((u32 *)tp->hw_stats)[3]);
7033
7034 /* Mailboxes */
7035 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7036 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7037 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7038 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7039 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7040
7041 /* NIC side send descriptors. */
7042 for (i = 0; i < 6; i++) {
7043 unsigned long txd;
7044
7045 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7046 + (i * sizeof(struct tg3_tx_buffer_desc));
7047 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7048 i,
7049 readl(txd + 0x0), readl(txd + 0x4),
7050 readl(txd + 0x8), readl(txd + 0xc));
7051 }
7052
7053 /* NIC side RX descriptors. */
7054 for (i = 0; i < 6; i++) {
7055 unsigned long rxd;
7056
7057 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7058 + (i * sizeof(struct tg3_rx_buffer_desc));
7059 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7060 i,
7061 readl(rxd + 0x0), readl(rxd + 0x4),
7062 readl(rxd + 0x8), readl(rxd + 0xc));
7063 rxd += (4 * sizeof(u32));
7064 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7065 i,
7066 readl(rxd + 0x0), readl(rxd + 0x4),
7067 readl(rxd + 0x8), readl(rxd + 0xc));
7068 }
7069
7070 for (i = 0; i < 6; i++) {
7071 unsigned long rxd;
7072
7073 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7074 + (i * sizeof(struct tg3_rx_buffer_desc));
7075 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7076 i,
7077 readl(rxd + 0x0), readl(rxd + 0x4),
7078 readl(rxd + 0x8), readl(rxd + 0xc));
7079 rxd += (4 * sizeof(u32));
7080 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7081 i,
7082 readl(rxd + 0x0), readl(rxd + 0x4),
7083 readl(rxd + 0x8), readl(rxd + 0xc));
7084 }
7085 }
7086 #endif
7087
7088 static struct net_device_stats *tg3_get_stats(struct net_device *);
7089 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7090
7091 static int tg3_close(struct net_device *dev)
7092 {
7093 struct tg3 *tp = netdev_priv(dev);
7094
7095 /* Calling flush_scheduled_work() may deadlock because
7096 * linkwatch_event() may be on the workqueue and it will try to get
7097 * the rtnl_lock which we are holding.
7098 */
7099 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7100 msleep(1);
7101
7102 netif_stop_queue(dev);
7103
7104 del_timer_sync(&tp->timer);
7105
7106 tg3_full_lock(tp, 1);
7107 #if 0
7108 tg3_dump_state(tp);
7109 #endif
7110
7111 tg3_disable_ints(tp);
7112
7113 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7114 tg3_free_rings(tp);
7115 tp->tg3_flags &=
7116 ~(TG3_FLAG_INIT_COMPLETE |
7117 TG3_FLAG_GOT_SERDES_FLOWCTL);
7118
7119 tg3_full_unlock(tp);
7120
7121 free_irq(tp->pdev->irq, dev);
7122 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7123 pci_disable_msi(tp->pdev);
7124 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7125 }
7126
7127 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7128 sizeof(tp->net_stats_prev));
7129 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7130 sizeof(tp->estats_prev));
7131
7132 tg3_free_consistent(tp);
7133
7134 tg3_set_power_state(tp, PCI_D3hot);
7135
7136 netif_carrier_off(tp->dev);
7137
7138 return 0;
7139 }
7140
7141 static inline unsigned long get_stat64(tg3_stat64_t *val)
7142 {
7143 unsigned long ret;
7144
7145 #if (BITS_PER_LONG == 32)
7146 ret = val->low;
7147 #else
7148 ret = ((u64)val->high << 32) | ((u64)val->low);
7149 #endif
7150 return ret;
7151 }
7152
7153 static unsigned long calc_crc_errors(struct tg3 *tp)
7154 {
7155 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7156
7157 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7158 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7159 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7160 u32 val;
7161
7162 spin_lock_bh(&tp->lock);
7163 if (!tg3_readphy(tp, 0x1e, &val)) {
7164 tg3_writephy(tp, 0x1e, val | 0x8000);
7165 tg3_readphy(tp, 0x14, &val);
7166 } else
7167 val = 0;
7168 spin_unlock_bh(&tp->lock);
7169
7170 tp->phy_crc_errors += val;
7171
7172 return tp->phy_crc_errors;
7173 }
7174
7175 return get_stat64(&hw_stats->rx_fcs_errors);
7176 }
7177
7178 #define ESTAT_ADD(member) \
7179 estats->member = old_estats->member + \
7180 get_stat64(&hw_stats->member)
7181
7182 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7183 {
7184 struct tg3_ethtool_stats *estats = &tp->estats;
7185 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7186 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7187
7188 if (!hw_stats)
7189 return old_estats;
7190
7191 ESTAT_ADD(rx_octets);
7192 ESTAT_ADD(rx_fragments);
7193 ESTAT_ADD(rx_ucast_packets);
7194 ESTAT_ADD(rx_mcast_packets);
7195 ESTAT_ADD(rx_bcast_packets);
7196 ESTAT_ADD(rx_fcs_errors);
7197 ESTAT_ADD(rx_align_errors);
7198 ESTAT_ADD(rx_xon_pause_rcvd);
7199 ESTAT_ADD(rx_xoff_pause_rcvd);
7200 ESTAT_ADD(rx_mac_ctrl_rcvd);
7201 ESTAT_ADD(rx_xoff_entered);
7202 ESTAT_ADD(rx_frame_too_long_errors);
7203 ESTAT_ADD(rx_jabbers);
7204 ESTAT_ADD(rx_undersize_packets);
7205 ESTAT_ADD(rx_in_length_errors);
7206 ESTAT_ADD(rx_out_length_errors);
7207 ESTAT_ADD(rx_64_or_less_octet_packets);
7208 ESTAT_ADD(rx_65_to_127_octet_packets);
7209 ESTAT_ADD(rx_128_to_255_octet_packets);
7210 ESTAT_ADD(rx_256_to_511_octet_packets);
7211 ESTAT_ADD(rx_512_to_1023_octet_packets);
7212 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7213 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7214 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7215 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7216 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7217
7218 ESTAT_ADD(tx_octets);
7219 ESTAT_ADD(tx_collisions);
7220 ESTAT_ADD(tx_xon_sent);
7221 ESTAT_ADD(tx_xoff_sent);
7222 ESTAT_ADD(tx_flow_control);
7223 ESTAT_ADD(tx_mac_errors);
7224 ESTAT_ADD(tx_single_collisions);
7225 ESTAT_ADD(tx_mult_collisions);
7226 ESTAT_ADD(tx_deferred);
7227 ESTAT_ADD(tx_excessive_collisions);
7228 ESTAT_ADD(tx_late_collisions);
7229 ESTAT_ADD(tx_collide_2times);
7230 ESTAT_ADD(tx_collide_3times);
7231 ESTAT_ADD(tx_collide_4times);
7232 ESTAT_ADD(tx_collide_5times);
7233 ESTAT_ADD(tx_collide_6times);
7234 ESTAT_ADD(tx_collide_7times);
7235 ESTAT_ADD(tx_collide_8times);
7236 ESTAT_ADD(tx_collide_9times);
7237 ESTAT_ADD(tx_collide_10times);
7238 ESTAT_ADD(tx_collide_11times);
7239 ESTAT_ADD(tx_collide_12times);
7240 ESTAT_ADD(tx_collide_13times);
7241 ESTAT_ADD(tx_collide_14times);
7242 ESTAT_ADD(tx_collide_15times);
7243 ESTAT_ADD(tx_ucast_packets);
7244 ESTAT_ADD(tx_mcast_packets);
7245 ESTAT_ADD(tx_bcast_packets);
7246 ESTAT_ADD(tx_carrier_sense_errors);
7247 ESTAT_ADD(tx_discards);
7248 ESTAT_ADD(tx_errors);
7249
7250 ESTAT_ADD(dma_writeq_full);
7251 ESTAT_ADD(dma_write_prioq_full);
7252 ESTAT_ADD(rxbds_empty);
7253 ESTAT_ADD(rx_discards);
7254 ESTAT_ADD(rx_errors);
7255 ESTAT_ADD(rx_threshold_hit);
7256
7257 ESTAT_ADD(dma_readq_full);
7258 ESTAT_ADD(dma_read_prioq_full);
7259 ESTAT_ADD(tx_comp_queue_full);
7260
7261 ESTAT_ADD(ring_set_send_prod_index);
7262 ESTAT_ADD(ring_status_update);
7263 ESTAT_ADD(nic_irqs);
7264 ESTAT_ADD(nic_avoided_irqs);
7265 ESTAT_ADD(nic_tx_threshold_hit);
7266
7267 return estats;
7268 }
7269
7270 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7271 {
7272 struct tg3 *tp = netdev_priv(dev);
7273 struct net_device_stats *stats = &tp->net_stats;
7274 struct net_device_stats *old_stats = &tp->net_stats_prev;
7275 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7276
7277 if (!hw_stats)
7278 return old_stats;
7279
7280 stats->rx_packets = old_stats->rx_packets +
7281 get_stat64(&hw_stats->rx_ucast_packets) +
7282 get_stat64(&hw_stats->rx_mcast_packets) +
7283 get_stat64(&hw_stats->rx_bcast_packets);
7284
7285 stats->tx_packets = old_stats->tx_packets +
7286 get_stat64(&hw_stats->tx_ucast_packets) +
7287 get_stat64(&hw_stats->tx_mcast_packets) +
7288 get_stat64(&hw_stats->tx_bcast_packets);
7289
7290 stats->rx_bytes = old_stats->rx_bytes +
7291 get_stat64(&hw_stats->rx_octets);
7292 stats->tx_bytes = old_stats->tx_bytes +
7293 get_stat64(&hw_stats->tx_octets);
7294
7295 stats->rx_errors = old_stats->rx_errors +
7296 get_stat64(&hw_stats->rx_errors);
7297 stats->tx_errors = old_stats->tx_errors +
7298 get_stat64(&hw_stats->tx_errors) +
7299 get_stat64(&hw_stats->tx_mac_errors) +
7300 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7301 get_stat64(&hw_stats->tx_discards);
7302
7303 stats->multicast = old_stats->multicast +
7304 get_stat64(&hw_stats->rx_mcast_packets);
7305 stats->collisions = old_stats->collisions +
7306 get_stat64(&hw_stats->tx_collisions);
7307
7308 stats->rx_length_errors = old_stats->rx_length_errors +
7309 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7310 get_stat64(&hw_stats->rx_undersize_packets);
7311
7312 stats->rx_over_errors = old_stats->rx_over_errors +
7313 get_stat64(&hw_stats->rxbds_empty);
7314 stats->rx_frame_errors = old_stats->rx_frame_errors +
7315 get_stat64(&hw_stats->rx_align_errors);
7316 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7317 get_stat64(&hw_stats->tx_discards);
7318 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7319 get_stat64(&hw_stats->tx_carrier_sense_errors);
7320
7321 stats->rx_crc_errors = old_stats->rx_crc_errors +
7322 calc_crc_errors(tp);
7323
7324 stats->rx_missed_errors = old_stats->rx_missed_errors +
7325 get_stat64(&hw_stats->rx_discards);
7326
7327 return stats;
7328 }
7329
7330 static inline u32 calc_crc(unsigned char *buf, int len)
7331 {
7332 u32 reg;
7333 u32 tmp;
7334 int j, k;
7335
7336 reg = 0xffffffff;
7337
7338 for (j = 0; j < len; j++) {
7339 reg ^= buf[j];
7340
7341 for (k = 0; k < 8; k++) {
7342 tmp = reg & 0x01;
7343
7344 reg >>= 1;
7345
7346 if (tmp) {
7347 reg ^= 0xedb88320;
7348 }
7349 }
7350 }
7351
7352 return ~reg;
7353 }
7354
7355 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7356 {
7357 /* accept or reject all multicast frames */
7358 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7359 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7360 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7361 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7362 }
7363
7364 static void __tg3_set_rx_mode(struct net_device *dev)
7365 {
7366 struct tg3 *tp = netdev_priv(dev);
7367 u32 rx_mode;
7368
7369 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7370 RX_MODE_KEEP_VLAN_TAG);
7371
7372 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7373 * flag clear.
7374 */
7375 #if TG3_VLAN_TAG_USED
7376 if (!tp->vlgrp &&
7377 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7378 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7379 #else
7380 /* By definition, VLAN is disabled always in this
7381 * case.
7382 */
7383 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7384 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7385 #endif
7386
7387 if (dev->flags & IFF_PROMISC) {
7388 /* Promiscuous mode. */
7389 rx_mode |= RX_MODE_PROMISC;
7390 } else if (dev->flags & IFF_ALLMULTI) {
7391 /* Accept all multicast. */
7392 tg3_set_multi (tp, 1);
7393 } else if (dev->mc_count < 1) {
7394 /* Reject all multicast. */
7395 tg3_set_multi (tp, 0);
7396 } else {
7397 /* Accept one or more multicast(s). */
7398 struct dev_mc_list *mclist;
7399 unsigned int i;
7400 u32 mc_filter[4] = { 0, };
7401 u32 regidx;
7402 u32 bit;
7403 u32 crc;
7404
7405 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7406 i++, mclist = mclist->next) {
7407
7408 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7409 bit = ~crc & 0x7f;
7410 regidx = (bit & 0x60) >> 5;
7411 bit &= 0x1f;
7412 mc_filter[regidx] |= (1 << bit);
7413 }
7414
7415 tw32(MAC_HASH_REG_0, mc_filter[0]);
7416 tw32(MAC_HASH_REG_1, mc_filter[1]);
7417 tw32(MAC_HASH_REG_2, mc_filter[2]);
7418 tw32(MAC_HASH_REG_3, mc_filter[3]);
7419 }
7420
7421 if (rx_mode != tp->rx_mode) {
7422 tp->rx_mode = rx_mode;
7423 tw32_f(MAC_RX_MODE, rx_mode);
7424 udelay(10);
7425 }
7426 }
7427
7428 static void tg3_set_rx_mode(struct net_device *dev)
7429 {
7430 struct tg3 *tp = netdev_priv(dev);
7431
7432 if (!netif_running(dev))
7433 return;
7434
7435 tg3_full_lock(tp, 0);
7436 __tg3_set_rx_mode(dev);
7437 tg3_full_unlock(tp);
7438 }
7439
7440 #define TG3_REGDUMP_LEN (32 * 1024)
7441
7442 static int tg3_get_regs_len(struct net_device *dev)
7443 {
7444 return TG3_REGDUMP_LEN;
7445 }
7446
7447 static void tg3_get_regs(struct net_device *dev,
7448 struct ethtool_regs *regs, void *_p)
7449 {
7450 u32 *p = _p;
7451 struct tg3 *tp = netdev_priv(dev);
7452 u8 *orig_p = _p;
7453 int i;
7454
7455 regs->version = 0;
7456
7457 memset(p, 0, TG3_REGDUMP_LEN);
7458
7459 if (tp->link_config.phy_is_low_power)
7460 return;
7461
7462 tg3_full_lock(tp, 0);
7463
7464 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7465 #define GET_REG32_LOOP(base,len) \
7466 do { p = (u32 *)(orig_p + (base)); \
7467 for (i = 0; i < len; i += 4) \
7468 __GET_REG32((base) + i); \
7469 } while (0)
7470 #define GET_REG32_1(reg) \
7471 do { p = (u32 *)(orig_p + (reg)); \
7472 __GET_REG32((reg)); \
7473 } while (0)
7474
7475 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7476 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7477 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7478 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7479 GET_REG32_1(SNDDATAC_MODE);
7480 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7481 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7482 GET_REG32_1(SNDBDC_MODE);
7483 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7484 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7485 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7486 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7487 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7488 GET_REG32_1(RCVDCC_MODE);
7489 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7490 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7491 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7492 GET_REG32_1(MBFREE_MODE);
7493 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7494 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7495 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7496 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7497 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7498 GET_REG32_1(RX_CPU_MODE);
7499 GET_REG32_1(RX_CPU_STATE);
7500 GET_REG32_1(RX_CPU_PGMCTR);
7501 GET_REG32_1(RX_CPU_HWBKPT);
7502 GET_REG32_1(TX_CPU_MODE);
7503 GET_REG32_1(TX_CPU_STATE);
7504 GET_REG32_1(TX_CPU_PGMCTR);
7505 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7506 GET_REG32_LOOP(FTQ_RESET, 0x120);
7507 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7508 GET_REG32_1(DMAC_MODE);
7509 GET_REG32_LOOP(GRC_MODE, 0x4c);
7510 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7511 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7512
7513 #undef __GET_REG32
7514 #undef GET_REG32_LOOP
7515 #undef GET_REG32_1
7516
7517 tg3_full_unlock(tp);
7518 }
7519
7520 static int tg3_get_eeprom_len(struct net_device *dev)
7521 {
7522 struct tg3 *tp = netdev_priv(dev);
7523
7524 return tp->nvram_size;
7525 }
7526
7527 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7528 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7529
7530 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7531 {
7532 struct tg3 *tp = netdev_priv(dev);
7533 int ret;
7534 u8 *pd;
7535 u32 i, offset, len, val, b_offset, b_count;
7536
7537 if (tp->link_config.phy_is_low_power)
7538 return -EAGAIN;
7539
7540 offset = eeprom->offset;
7541 len = eeprom->len;
7542 eeprom->len = 0;
7543
7544 eeprom->magic = TG3_EEPROM_MAGIC;
7545
7546 if (offset & 3) {
7547 /* adjustments to start on required 4 byte boundary */
7548 b_offset = offset & 3;
7549 b_count = 4 - b_offset;
7550 if (b_count > len) {
7551 /* i.e. offset=1 len=2 */
7552 b_count = len;
7553 }
7554 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7555 if (ret)
7556 return ret;
7557 val = cpu_to_le32(val);
7558 memcpy(data, ((char*)&val) + b_offset, b_count);
7559 len -= b_count;
7560 offset += b_count;
7561 eeprom->len += b_count;
7562 }
7563
7564 /* read bytes upto the last 4 byte boundary */
7565 pd = &data[eeprom->len];
7566 for (i = 0; i < (len - (len & 3)); i += 4) {
7567 ret = tg3_nvram_read(tp, offset + i, &val);
7568 if (ret) {
7569 eeprom->len += i;
7570 return ret;
7571 }
7572 val = cpu_to_le32(val);
7573 memcpy(pd + i, &val, 4);
7574 }
7575 eeprom->len += i;
7576
7577 if (len & 3) {
7578 /* read last bytes not ending on 4 byte boundary */
7579 pd = &data[eeprom->len];
7580 b_count = len & 3;
7581 b_offset = offset + len - b_count;
7582 ret = tg3_nvram_read(tp, b_offset, &val);
7583 if (ret)
7584 return ret;
7585 val = cpu_to_le32(val);
7586 memcpy(pd, ((char*)&val), b_count);
7587 eeprom->len += b_count;
7588 }
7589 return 0;
7590 }
7591
7592 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7593
7594 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7595 {
7596 struct tg3 *tp = netdev_priv(dev);
7597 int ret;
7598 u32 offset, len, b_offset, odd_len, start, end;
7599 u8 *buf;
7600
7601 if (tp->link_config.phy_is_low_power)
7602 return -EAGAIN;
7603
7604 if (eeprom->magic != TG3_EEPROM_MAGIC)
7605 return -EINVAL;
7606
7607 offset = eeprom->offset;
7608 len = eeprom->len;
7609
7610 if ((b_offset = (offset & 3))) {
7611 /* adjustments to start on required 4 byte boundary */
7612 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7613 if (ret)
7614 return ret;
7615 start = cpu_to_le32(start);
7616 len += b_offset;
7617 offset &= ~3;
7618 if (len < 4)
7619 len = 4;
7620 }
7621
7622 odd_len = 0;
7623 if (len & 3) {
7624 /* adjustments to end on required 4 byte boundary */
7625 odd_len = 1;
7626 len = (len + 3) & ~3;
7627 ret = tg3_nvram_read(tp, offset+len-4, &end);
7628 if (ret)
7629 return ret;
7630 end = cpu_to_le32(end);
7631 }
7632
7633 buf = data;
7634 if (b_offset || odd_len) {
7635 buf = kmalloc(len, GFP_KERNEL);
7636 if (buf == 0)
7637 return -ENOMEM;
7638 if (b_offset)
7639 memcpy(buf, &start, 4);
7640 if (odd_len)
7641 memcpy(buf+len-4, &end, 4);
7642 memcpy(buf + b_offset, data, eeprom->len);
7643 }
7644
7645 ret = tg3_nvram_write_block(tp, offset, len, buf);
7646
7647 if (buf != data)
7648 kfree(buf);
7649
7650 return ret;
7651 }
7652
7653 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7654 {
7655 struct tg3 *tp = netdev_priv(dev);
7656
7657 cmd->supported = (SUPPORTED_Autoneg);
7658
7659 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7660 cmd->supported |= (SUPPORTED_1000baseT_Half |
7661 SUPPORTED_1000baseT_Full);
7662
7663 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7664 cmd->supported |= (SUPPORTED_100baseT_Half |
7665 SUPPORTED_100baseT_Full |
7666 SUPPORTED_10baseT_Half |
7667 SUPPORTED_10baseT_Full |
7668 SUPPORTED_MII);
7669 cmd->port = PORT_TP;
7670 } else {
7671 cmd->supported |= SUPPORTED_FIBRE;
7672 cmd->port = PORT_FIBRE;
7673 }
7674
7675 cmd->advertising = tp->link_config.advertising;
7676 if (netif_running(dev)) {
7677 cmd->speed = tp->link_config.active_speed;
7678 cmd->duplex = tp->link_config.active_duplex;
7679 }
7680 cmd->phy_address = PHY_ADDR;
7681 cmd->transceiver = 0;
7682 cmd->autoneg = tp->link_config.autoneg;
7683 cmd->maxtxpkt = 0;
7684 cmd->maxrxpkt = 0;
7685 return 0;
7686 }
7687
7688 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7689 {
7690 struct tg3 *tp = netdev_priv(dev);
7691
7692 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7693 /* These are the only valid advertisement bits allowed. */
7694 if (cmd->autoneg == AUTONEG_ENABLE &&
7695 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7696 ADVERTISED_1000baseT_Full |
7697 ADVERTISED_Autoneg |
7698 ADVERTISED_FIBRE)))
7699 return -EINVAL;
7700 /* Fiber can only do SPEED_1000. */
7701 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7702 (cmd->speed != SPEED_1000))
7703 return -EINVAL;
7704 /* Copper cannot force SPEED_1000. */
7705 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7706 (cmd->speed == SPEED_1000))
7707 return -EINVAL;
7708 else if ((cmd->speed == SPEED_1000) &&
7709 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7710 return -EINVAL;
7711
7712 tg3_full_lock(tp, 0);
7713
7714 tp->link_config.autoneg = cmd->autoneg;
7715 if (cmd->autoneg == AUTONEG_ENABLE) {
7716 tp->link_config.advertising = cmd->advertising;
7717 tp->link_config.speed = SPEED_INVALID;
7718 tp->link_config.duplex = DUPLEX_INVALID;
7719 } else {
7720 tp->link_config.advertising = 0;
7721 tp->link_config.speed = cmd->speed;
7722 tp->link_config.duplex = cmd->duplex;
7723 }
7724
7725 if (netif_running(dev))
7726 tg3_setup_phy(tp, 1);
7727
7728 tg3_full_unlock(tp);
7729
7730 return 0;
7731 }
7732
7733 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7734 {
7735 struct tg3 *tp = netdev_priv(dev);
7736
7737 strcpy(info->driver, DRV_MODULE_NAME);
7738 strcpy(info->version, DRV_MODULE_VERSION);
7739 strcpy(info->fw_version, tp->fw_ver);
7740 strcpy(info->bus_info, pci_name(tp->pdev));
7741 }
7742
7743 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7744 {
7745 struct tg3 *tp = netdev_priv(dev);
7746
7747 wol->supported = WAKE_MAGIC;
7748 wol->wolopts = 0;
7749 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7750 wol->wolopts = WAKE_MAGIC;
7751 memset(&wol->sopass, 0, sizeof(wol->sopass));
7752 }
7753
7754 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7755 {
7756 struct tg3 *tp = netdev_priv(dev);
7757
7758 if (wol->wolopts & ~WAKE_MAGIC)
7759 return -EINVAL;
7760 if ((wol->wolopts & WAKE_MAGIC) &&
7761 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7762 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7763 return -EINVAL;
7764
7765 spin_lock_bh(&tp->lock);
7766 if (wol->wolopts & WAKE_MAGIC)
7767 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7768 else
7769 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7770 spin_unlock_bh(&tp->lock);
7771
7772 return 0;
7773 }
7774
7775 static u32 tg3_get_msglevel(struct net_device *dev)
7776 {
7777 struct tg3 *tp = netdev_priv(dev);
7778 return tp->msg_enable;
7779 }
7780
7781 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7782 {
7783 struct tg3 *tp = netdev_priv(dev);
7784 tp->msg_enable = value;
7785 }
7786
7787 #if TG3_TSO_SUPPORT != 0
7788 static int tg3_set_tso(struct net_device *dev, u32 value)
7789 {
7790 struct tg3 *tp = netdev_priv(dev);
7791
7792 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7793 if (value)
7794 return -EINVAL;
7795 return 0;
7796 }
7797 return ethtool_op_set_tso(dev, value);
7798 }
7799 #endif
7800
7801 static int tg3_nway_reset(struct net_device *dev)
7802 {
7803 struct tg3 *tp = netdev_priv(dev);
7804 u32 bmcr;
7805 int r;
7806
7807 if (!netif_running(dev))
7808 return -EAGAIN;
7809
7810 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7811 return -EINVAL;
7812
7813 spin_lock_bh(&tp->lock);
7814 r = -EINVAL;
7815 tg3_readphy(tp, MII_BMCR, &bmcr);
7816 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7817 ((bmcr & BMCR_ANENABLE) ||
7818 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7819 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7820 BMCR_ANENABLE);
7821 r = 0;
7822 }
7823 spin_unlock_bh(&tp->lock);
7824
7825 return r;
7826 }
7827
7828 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7829 {
7830 struct tg3 *tp = netdev_priv(dev);
7831
7832 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7833 ering->rx_mini_max_pending = 0;
7834 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7835 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7836 else
7837 ering->rx_jumbo_max_pending = 0;
7838
7839 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
7840
7841 ering->rx_pending = tp->rx_pending;
7842 ering->rx_mini_pending = 0;
7843 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7844 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7845 else
7846 ering->rx_jumbo_pending = 0;
7847
7848 ering->tx_pending = tp->tx_pending;
7849 }
7850
7851 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7852 {
7853 struct tg3 *tp = netdev_priv(dev);
7854 int irq_sync = 0;
7855
7856 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7857 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7858 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7859 return -EINVAL;
7860
7861 if (netif_running(dev)) {
7862 tg3_netif_stop(tp);
7863 irq_sync = 1;
7864 }
7865
7866 tg3_full_lock(tp, irq_sync);
7867
7868 tp->rx_pending = ering->rx_pending;
7869
7870 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7871 tp->rx_pending > 63)
7872 tp->rx_pending = 63;
7873 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7874 tp->tx_pending = ering->tx_pending;
7875
7876 if (netif_running(dev)) {
7877 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7878 tg3_init_hw(tp, 1);
7879 tg3_netif_start(tp);
7880 }
7881
7882 tg3_full_unlock(tp);
7883
7884 return 0;
7885 }
7886
7887 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7888 {
7889 struct tg3 *tp = netdev_priv(dev);
7890
7891 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7892 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7893 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7894 }
7895
7896 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7897 {
7898 struct tg3 *tp = netdev_priv(dev);
7899 int irq_sync = 0;
7900
7901 if (netif_running(dev)) {
7902 tg3_netif_stop(tp);
7903 irq_sync = 1;
7904 }
7905
7906 tg3_full_lock(tp, irq_sync);
7907
7908 if (epause->autoneg)
7909 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7910 else
7911 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7912 if (epause->rx_pause)
7913 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7914 else
7915 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7916 if (epause->tx_pause)
7917 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7918 else
7919 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7920
7921 if (netif_running(dev)) {
7922 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7923 tg3_init_hw(tp, 1);
7924 tg3_netif_start(tp);
7925 }
7926
7927 tg3_full_unlock(tp);
7928
7929 return 0;
7930 }
7931
7932 static u32 tg3_get_rx_csum(struct net_device *dev)
7933 {
7934 struct tg3 *tp = netdev_priv(dev);
7935 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7936 }
7937
7938 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7939 {
7940 struct tg3 *tp = netdev_priv(dev);
7941
7942 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7943 if (data != 0)
7944 return -EINVAL;
7945 return 0;
7946 }
7947
7948 spin_lock_bh(&tp->lock);
7949 if (data)
7950 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7951 else
7952 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7953 spin_unlock_bh(&tp->lock);
7954
7955 return 0;
7956 }
7957
7958 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7959 {
7960 struct tg3 *tp = netdev_priv(dev);
7961
7962 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7963 if (data != 0)
7964 return -EINVAL;
7965 return 0;
7966 }
7967
7968 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
7970 ethtool_op_set_tx_hw_csum(dev, data);
7971 else
7972 ethtool_op_set_tx_csum(dev, data);
7973
7974 return 0;
7975 }
7976
7977 static int tg3_get_stats_count (struct net_device *dev)
7978 {
7979 return TG3_NUM_STATS;
7980 }
7981
7982 static int tg3_get_test_count (struct net_device *dev)
7983 {
7984 return TG3_NUM_TEST;
7985 }
7986
7987 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7988 {
7989 switch (stringset) {
7990 case ETH_SS_STATS:
7991 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7992 break;
7993 case ETH_SS_TEST:
7994 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7995 break;
7996 default:
7997 WARN_ON(1); /* we need a WARN() */
7998 break;
7999 }
8000 }
8001
8002 static int tg3_phys_id(struct net_device *dev, u32 data)
8003 {
8004 struct tg3 *tp = netdev_priv(dev);
8005 int i;
8006
8007 if (!netif_running(tp->dev))
8008 return -EAGAIN;
8009
8010 if (data == 0)
8011 data = 2;
8012
8013 for (i = 0; i < (data * 2); i++) {
8014 if ((i % 2) == 0)
8015 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8016 LED_CTRL_1000MBPS_ON |
8017 LED_CTRL_100MBPS_ON |
8018 LED_CTRL_10MBPS_ON |
8019 LED_CTRL_TRAFFIC_OVERRIDE |
8020 LED_CTRL_TRAFFIC_BLINK |
8021 LED_CTRL_TRAFFIC_LED);
8022
8023 else
8024 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8025 LED_CTRL_TRAFFIC_OVERRIDE);
8026
8027 if (msleep_interruptible(500))
8028 break;
8029 }
8030 tw32(MAC_LED_CTRL, tp->led_ctrl);
8031 return 0;
8032 }
8033
8034 static void tg3_get_ethtool_stats (struct net_device *dev,
8035 struct ethtool_stats *estats, u64 *tmp_stats)
8036 {
8037 struct tg3 *tp = netdev_priv(dev);
8038 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8039 }
8040
8041 #define NVRAM_TEST_SIZE 0x100
8042 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8043
8044 static int tg3_test_nvram(struct tg3 *tp)
8045 {
8046 u32 *buf, csum, magic;
8047 int i, j, err = 0, size;
8048
8049 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8050 return -EIO;
8051
8052 if (magic == TG3_EEPROM_MAGIC)
8053 size = NVRAM_TEST_SIZE;
8054 else if ((magic & 0xff000000) == 0xa5000000) {
8055 if ((magic & 0xe00000) == 0x200000)
8056 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8057 else
8058 return 0;
8059 } else
8060 return -EIO;
8061
8062 buf = kmalloc(size, GFP_KERNEL);
8063 if (buf == NULL)
8064 return -ENOMEM;
8065
8066 err = -EIO;
8067 for (i = 0, j = 0; i < size; i += 4, j++) {
8068 u32 val;
8069
8070 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8071 break;
8072 buf[j] = cpu_to_le32(val);
8073 }
8074 if (i < size)
8075 goto out;
8076
8077 /* Selfboot format */
8078 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC) {
8079 u8 *buf8 = (u8 *) buf, csum8 = 0;
8080
8081 for (i = 0; i < size; i++)
8082 csum8 += buf8[i];
8083
8084 if (csum8 == 0) {
8085 err = 0;
8086 goto out;
8087 }
8088
8089 err = -EIO;
8090 goto out;
8091 }
8092
8093 /* Bootstrap checksum at offset 0x10 */
8094 csum = calc_crc((unsigned char *) buf, 0x10);
8095 if(csum != cpu_to_le32(buf[0x10/4]))
8096 goto out;
8097
8098 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8099 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8100 if (csum != cpu_to_le32(buf[0xfc/4]))
8101 goto out;
8102
8103 err = 0;
8104
8105 out:
8106 kfree(buf);
8107 return err;
8108 }
8109
8110 #define TG3_SERDES_TIMEOUT_SEC 2
8111 #define TG3_COPPER_TIMEOUT_SEC 6
8112
8113 static int tg3_test_link(struct tg3 *tp)
8114 {
8115 int i, max;
8116
8117 if (!netif_running(tp->dev))
8118 return -ENODEV;
8119
8120 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8121 max = TG3_SERDES_TIMEOUT_SEC;
8122 else
8123 max = TG3_COPPER_TIMEOUT_SEC;
8124
8125 for (i = 0; i < max; i++) {
8126 if (netif_carrier_ok(tp->dev))
8127 return 0;
8128
8129 if (msleep_interruptible(1000))
8130 break;
8131 }
8132
8133 return -EIO;
8134 }
8135
8136 /* Only test the commonly used registers */
8137 static int tg3_test_registers(struct tg3 *tp)
8138 {
8139 int i, is_5705;
8140 u32 offset, read_mask, write_mask, val, save_val, read_val;
8141 static struct {
8142 u16 offset;
8143 u16 flags;
8144 #define TG3_FL_5705 0x1
8145 #define TG3_FL_NOT_5705 0x2
8146 #define TG3_FL_NOT_5788 0x4
8147 u32 read_mask;
8148 u32 write_mask;
8149 } reg_tbl[] = {
8150 /* MAC Control Registers */
8151 { MAC_MODE, TG3_FL_NOT_5705,
8152 0x00000000, 0x00ef6f8c },
8153 { MAC_MODE, TG3_FL_5705,
8154 0x00000000, 0x01ef6b8c },
8155 { MAC_STATUS, TG3_FL_NOT_5705,
8156 0x03800107, 0x00000000 },
8157 { MAC_STATUS, TG3_FL_5705,
8158 0x03800100, 0x00000000 },
8159 { MAC_ADDR_0_HIGH, 0x0000,
8160 0x00000000, 0x0000ffff },
8161 { MAC_ADDR_0_LOW, 0x0000,
8162 0x00000000, 0xffffffff },
8163 { MAC_RX_MTU_SIZE, 0x0000,
8164 0x00000000, 0x0000ffff },
8165 { MAC_TX_MODE, 0x0000,
8166 0x00000000, 0x00000070 },
8167 { MAC_TX_LENGTHS, 0x0000,
8168 0x00000000, 0x00003fff },
8169 { MAC_RX_MODE, TG3_FL_NOT_5705,
8170 0x00000000, 0x000007fc },
8171 { MAC_RX_MODE, TG3_FL_5705,
8172 0x00000000, 0x000007dc },
8173 { MAC_HASH_REG_0, 0x0000,
8174 0x00000000, 0xffffffff },
8175 { MAC_HASH_REG_1, 0x0000,
8176 0x00000000, 0xffffffff },
8177 { MAC_HASH_REG_2, 0x0000,
8178 0x00000000, 0xffffffff },
8179 { MAC_HASH_REG_3, 0x0000,
8180 0x00000000, 0xffffffff },
8181
8182 /* Receive Data and Receive BD Initiator Control Registers. */
8183 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8184 0x00000000, 0xffffffff },
8185 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8186 0x00000000, 0xffffffff },
8187 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8188 0x00000000, 0x00000003 },
8189 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8190 0x00000000, 0xffffffff },
8191 { RCVDBDI_STD_BD+0, 0x0000,
8192 0x00000000, 0xffffffff },
8193 { RCVDBDI_STD_BD+4, 0x0000,
8194 0x00000000, 0xffffffff },
8195 { RCVDBDI_STD_BD+8, 0x0000,
8196 0x00000000, 0xffff0002 },
8197 { RCVDBDI_STD_BD+0xc, 0x0000,
8198 0x00000000, 0xffffffff },
8199
8200 /* Receive BD Initiator Control Registers. */
8201 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8202 0x00000000, 0xffffffff },
8203 { RCVBDI_STD_THRESH, TG3_FL_5705,
8204 0x00000000, 0x000003ff },
8205 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8206 0x00000000, 0xffffffff },
8207
8208 /* Host Coalescing Control Registers. */
8209 { HOSTCC_MODE, TG3_FL_NOT_5705,
8210 0x00000000, 0x00000004 },
8211 { HOSTCC_MODE, TG3_FL_5705,
8212 0x00000000, 0x000000f6 },
8213 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8214 0x00000000, 0xffffffff },
8215 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8216 0x00000000, 0x000003ff },
8217 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8218 0x00000000, 0xffffffff },
8219 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8220 0x00000000, 0x000003ff },
8221 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8222 0x00000000, 0xffffffff },
8223 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8224 0x00000000, 0x000000ff },
8225 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8226 0x00000000, 0xffffffff },
8227 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8228 0x00000000, 0x000000ff },
8229 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8230 0x00000000, 0xffffffff },
8231 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8232 0x00000000, 0xffffffff },
8233 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8234 0x00000000, 0xffffffff },
8235 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8236 0x00000000, 0x000000ff },
8237 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8238 0x00000000, 0xffffffff },
8239 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8240 0x00000000, 0x000000ff },
8241 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8242 0x00000000, 0xffffffff },
8243 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8244 0x00000000, 0xffffffff },
8245 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8246 0x00000000, 0xffffffff },
8247 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8248 0x00000000, 0xffffffff },
8249 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8250 0x00000000, 0xffffffff },
8251 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8252 0xffffffff, 0x00000000 },
8253 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8254 0xffffffff, 0x00000000 },
8255
8256 /* Buffer Manager Control Registers. */
8257 { BUFMGR_MB_POOL_ADDR, 0x0000,
8258 0x00000000, 0x007fff80 },
8259 { BUFMGR_MB_POOL_SIZE, 0x0000,
8260 0x00000000, 0x007fffff },
8261 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8262 0x00000000, 0x0000003f },
8263 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8264 0x00000000, 0x000001ff },
8265 { BUFMGR_MB_HIGH_WATER, 0x0000,
8266 0x00000000, 0x000001ff },
8267 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8268 0xffffffff, 0x00000000 },
8269 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8270 0xffffffff, 0x00000000 },
8271
8272 /* Mailbox Registers */
8273 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8274 0x00000000, 0x000001ff },
8275 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8276 0x00000000, 0x000001ff },
8277 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8278 0x00000000, 0x000007ff },
8279 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8280 0x00000000, 0x000001ff },
8281
8282 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8283 };
8284
8285 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8286 is_5705 = 1;
8287 else
8288 is_5705 = 0;
8289
8290 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8291 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8292 continue;
8293
8294 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8295 continue;
8296
8297 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8298 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8299 continue;
8300
8301 offset = (u32) reg_tbl[i].offset;
8302 read_mask = reg_tbl[i].read_mask;
8303 write_mask = reg_tbl[i].write_mask;
8304
8305 /* Save the original register content */
8306 save_val = tr32(offset);
8307
8308 /* Determine the read-only value. */
8309 read_val = save_val & read_mask;
8310
8311 /* Write zero to the register, then make sure the read-only bits
8312 * are not changed and the read/write bits are all zeros.
8313 */
8314 tw32(offset, 0);
8315
8316 val = tr32(offset);
8317
8318 /* Test the read-only and read/write bits. */
8319 if (((val & read_mask) != read_val) || (val & write_mask))
8320 goto out;
8321
8322 /* Write ones to all the bits defined by RdMask and WrMask, then
8323 * make sure the read-only bits are not changed and the
8324 * read/write bits are all ones.
8325 */
8326 tw32(offset, read_mask | write_mask);
8327
8328 val = tr32(offset);
8329
8330 /* Test the read-only bits. */
8331 if ((val & read_mask) != read_val)
8332 goto out;
8333
8334 /* Test the read/write bits. */
8335 if ((val & write_mask) != write_mask)
8336 goto out;
8337
8338 tw32(offset, save_val);
8339 }
8340
8341 return 0;
8342
8343 out:
8344 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
8345 tw32(offset, save_val);
8346 return -EIO;
8347 }
8348
8349 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8350 {
8351 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8352 int i;
8353 u32 j;
8354
8355 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8356 for (j = 0; j < len; j += 4) {
8357 u32 val;
8358
8359 tg3_write_mem(tp, offset + j, test_pattern[i]);
8360 tg3_read_mem(tp, offset + j, &val);
8361 if (val != test_pattern[i])
8362 return -EIO;
8363 }
8364 }
8365 return 0;
8366 }
8367
8368 static int tg3_test_memory(struct tg3 *tp)
8369 {
8370 static struct mem_entry {
8371 u32 offset;
8372 u32 len;
8373 } mem_tbl_570x[] = {
8374 { 0x00000000, 0x00b50},
8375 { 0x00002000, 0x1c000},
8376 { 0xffffffff, 0x00000}
8377 }, mem_tbl_5705[] = {
8378 { 0x00000100, 0x0000c},
8379 { 0x00000200, 0x00008},
8380 { 0x00004000, 0x00800},
8381 { 0x00006000, 0x01000},
8382 { 0x00008000, 0x02000},
8383 { 0x00010000, 0x0e000},
8384 { 0xffffffff, 0x00000}
8385 }, mem_tbl_5755[] = {
8386 { 0x00000200, 0x00008},
8387 { 0x00004000, 0x00800},
8388 { 0x00006000, 0x00800},
8389 { 0x00008000, 0x02000},
8390 { 0x00010000, 0x0c000},
8391 { 0xffffffff, 0x00000}
8392 };
8393 struct mem_entry *mem_tbl;
8394 int err = 0;
8395 int i;
8396
8397 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8398 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8400 mem_tbl = mem_tbl_5755;
8401 else
8402 mem_tbl = mem_tbl_5705;
8403 } else
8404 mem_tbl = mem_tbl_570x;
8405
8406 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8407 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8408 mem_tbl[i].len)) != 0)
8409 break;
8410 }
8411
8412 return err;
8413 }
8414
8415 #define TG3_MAC_LOOPBACK 0
8416 #define TG3_PHY_LOOPBACK 1
8417
8418 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8419 {
8420 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8421 u32 desc_idx;
8422 struct sk_buff *skb, *rx_skb;
8423 u8 *tx_data;
8424 dma_addr_t map;
8425 int num_pkts, tx_len, rx_len, i, err;
8426 struct tg3_rx_buffer_desc *desc;
8427
8428 if (loopback_mode == TG3_MAC_LOOPBACK) {
8429 /* HW errata - mac loopback fails in some cases on 5780.
8430 * Normal traffic and PHY loopback are not affected by
8431 * errata.
8432 */
8433 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8434 return 0;
8435
8436 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8437 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8438 MAC_MODE_PORT_MODE_GMII;
8439 tw32(MAC_MODE, mac_mode);
8440 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8441 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8442 BMCR_SPEED1000);
8443 udelay(40);
8444 /* reset to prevent losing 1st rx packet intermittently */
8445 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8446 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8447 udelay(10);
8448 tw32_f(MAC_RX_MODE, tp->rx_mode);
8449 }
8450 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8451 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8452 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8453 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8454 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8455 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8456 }
8457 tw32(MAC_MODE, mac_mode);
8458 }
8459 else
8460 return -EINVAL;
8461
8462 err = -EIO;
8463
8464 tx_len = 1514;
8465 skb = dev_alloc_skb(tx_len);
8466 if (!skb)
8467 return -ENOMEM;
8468
8469 tx_data = skb_put(skb, tx_len);
8470 memcpy(tx_data, tp->dev->dev_addr, 6);
8471 memset(tx_data + 6, 0x0, 8);
8472
8473 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8474
8475 for (i = 14; i < tx_len; i++)
8476 tx_data[i] = (u8) (i & 0xff);
8477
8478 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8479
8480 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8481 HOSTCC_MODE_NOW);
8482
8483 udelay(10);
8484
8485 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8486
8487 num_pkts = 0;
8488
8489 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8490
8491 tp->tx_prod++;
8492 num_pkts++;
8493
8494 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8495 tp->tx_prod);
8496 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8497
8498 udelay(10);
8499
8500 for (i = 0; i < 10; i++) {
8501 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8502 HOSTCC_MODE_NOW);
8503
8504 udelay(10);
8505
8506 tx_idx = tp->hw_status->idx[0].tx_consumer;
8507 rx_idx = tp->hw_status->idx[0].rx_producer;
8508 if ((tx_idx == tp->tx_prod) &&
8509 (rx_idx == (rx_start_idx + num_pkts)))
8510 break;
8511 }
8512
8513 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8514 dev_kfree_skb(skb);
8515
8516 if (tx_idx != tp->tx_prod)
8517 goto out;
8518
8519 if (rx_idx != rx_start_idx + num_pkts)
8520 goto out;
8521
8522 desc = &tp->rx_rcb[rx_start_idx];
8523 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8524 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8525 if (opaque_key != RXD_OPAQUE_RING_STD)
8526 goto out;
8527
8528 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8529 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8530 goto out;
8531
8532 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8533 if (rx_len != tx_len)
8534 goto out;
8535
8536 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8537
8538 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8539 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8540
8541 for (i = 14; i < tx_len; i++) {
8542 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8543 goto out;
8544 }
8545 err = 0;
8546
8547 /* tg3_free_rings will unmap and free the rx_skb */
8548 out:
8549 return err;
8550 }
8551
8552 #define TG3_MAC_LOOPBACK_FAILED 1
8553 #define TG3_PHY_LOOPBACK_FAILED 2
8554 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8555 TG3_PHY_LOOPBACK_FAILED)
8556
8557 static int tg3_test_loopback(struct tg3 *tp)
8558 {
8559 int err = 0;
8560
8561 if (!netif_running(tp->dev))
8562 return TG3_LOOPBACK_FAILED;
8563
8564 tg3_reset_hw(tp, 1);
8565
8566 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8567 err |= TG3_MAC_LOOPBACK_FAILED;
8568 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8569 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8570 err |= TG3_PHY_LOOPBACK_FAILED;
8571 }
8572
8573 return err;
8574 }
8575
8576 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8577 u64 *data)
8578 {
8579 struct tg3 *tp = netdev_priv(dev);
8580
8581 if (tp->link_config.phy_is_low_power)
8582 tg3_set_power_state(tp, PCI_D0);
8583
8584 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8585
8586 if (tg3_test_nvram(tp) != 0) {
8587 etest->flags |= ETH_TEST_FL_FAILED;
8588 data[0] = 1;
8589 }
8590 if (tg3_test_link(tp) != 0) {
8591 etest->flags |= ETH_TEST_FL_FAILED;
8592 data[1] = 1;
8593 }
8594 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8595 int err, irq_sync = 0;
8596
8597 if (netif_running(dev)) {
8598 tg3_netif_stop(tp);
8599 irq_sync = 1;
8600 }
8601
8602 tg3_full_lock(tp, irq_sync);
8603
8604 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8605 err = tg3_nvram_lock(tp);
8606 tg3_halt_cpu(tp, RX_CPU_BASE);
8607 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8608 tg3_halt_cpu(tp, TX_CPU_BASE);
8609 if (!err)
8610 tg3_nvram_unlock(tp);
8611
8612 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8613 tg3_phy_reset(tp);
8614
8615 if (tg3_test_registers(tp) != 0) {
8616 etest->flags |= ETH_TEST_FL_FAILED;
8617 data[2] = 1;
8618 }
8619 if (tg3_test_memory(tp) != 0) {
8620 etest->flags |= ETH_TEST_FL_FAILED;
8621 data[3] = 1;
8622 }
8623 if ((data[4] = tg3_test_loopback(tp)) != 0)
8624 etest->flags |= ETH_TEST_FL_FAILED;
8625
8626 tg3_full_unlock(tp);
8627
8628 if (tg3_test_interrupt(tp) != 0) {
8629 etest->flags |= ETH_TEST_FL_FAILED;
8630 data[5] = 1;
8631 }
8632
8633 tg3_full_lock(tp, 0);
8634
8635 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8636 if (netif_running(dev)) {
8637 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8638 tg3_init_hw(tp, 1);
8639 tg3_netif_start(tp);
8640 }
8641
8642 tg3_full_unlock(tp);
8643 }
8644 if (tp->link_config.phy_is_low_power)
8645 tg3_set_power_state(tp, PCI_D3hot);
8646
8647 }
8648
8649 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8650 {
8651 struct mii_ioctl_data *data = if_mii(ifr);
8652 struct tg3 *tp = netdev_priv(dev);
8653 int err;
8654
8655 switch(cmd) {
8656 case SIOCGMIIPHY:
8657 data->phy_id = PHY_ADDR;
8658
8659 /* fallthru */
8660 case SIOCGMIIREG: {
8661 u32 mii_regval;
8662
8663 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8664 break; /* We have no PHY */
8665
8666 if (tp->link_config.phy_is_low_power)
8667 return -EAGAIN;
8668
8669 spin_lock_bh(&tp->lock);
8670 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8671 spin_unlock_bh(&tp->lock);
8672
8673 data->val_out = mii_regval;
8674
8675 return err;
8676 }
8677
8678 case SIOCSMIIREG:
8679 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8680 break; /* We have no PHY */
8681
8682 if (!capable(CAP_NET_ADMIN))
8683 return -EPERM;
8684
8685 if (tp->link_config.phy_is_low_power)
8686 return -EAGAIN;
8687
8688 spin_lock_bh(&tp->lock);
8689 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8690 spin_unlock_bh(&tp->lock);
8691
8692 return err;
8693
8694 default:
8695 /* do nothing */
8696 break;
8697 }
8698 return -EOPNOTSUPP;
8699 }
8700
8701 #if TG3_VLAN_TAG_USED
8702 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8703 {
8704 struct tg3 *tp = netdev_priv(dev);
8705
8706 tg3_full_lock(tp, 0);
8707
8708 tp->vlgrp = grp;
8709
8710 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8711 __tg3_set_rx_mode(dev);
8712
8713 tg3_full_unlock(tp);
8714 }
8715
8716 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8717 {
8718 struct tg3 *tp = netdev_priv(dev);
8719
8720 tg3_full_lock(tp, 0);
8721 if (tp->vlgrp)
8722 tp->vlgrp->vlan_devices[vid] = NULL;
8723 tg3_full_unlock(tp);
8724 }
8725 #endif
8726
8727 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8728 {
8729 struct tg3 *tp = netdev_priv(dev);
8730
8731 memcpy(ec, &tp->coal, sizeof(*ec));
8732 return 0;
8733 }
8734
8735 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8736 {
8737 struct tg3 *tp = netdev_priv(dev);
8738 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8739 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8740
8741 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8742 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8743 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8744 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8745 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8746 }
8747
8748 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8749 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8750 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8751 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8752 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8753 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8754 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8755 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8756 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8757 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8758 return -EINVAL;
8759
8760 /* No rx interrupts will be generated if both are zero */
8761 if ((ec->rx_coalesce_usecs == 0) &&
8762 (ec->rx_max_coalesced_frames == 0))
8763 return -EINVAL;
8764
8765 /* No tx interrupts will be generated if both are zero */
8766 if ((ec->tx_coalesce_usecs == 0) &&
8767 (ec->tx_max_coalesced_frames == 0))
8768 return -EINVAL;
8769
8770 /* Only copy relevant parameters, ignore all others. */
8771 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8772 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8773 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8774 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8775 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8776 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8777 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8778 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8779 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8780
8781 if (netif_running(dev)) {
8782 tg3_full_lock(tp, 0);
8783 __tg3_set_coalesce(tp, &tp->coal);
8784 tg3_full_unlock(tp);
8785 }
8786 return 0;
8787 }
8788
8789 static struct ethtool_ops tg3_ethtool_ops = {
8790 .get_settings = tg3_get_settings,
8791 .set_settings = tg3_set_settings,
8792 .get_drvinfo = tg3_get_drvinfo,
8793 .get_regs_len = tg3_get_regs_len,
8794 .get_regs = tg3_get_regs,
8795 .get_wol = tg3_get_wol,
8796 .set_wol = tg3_set_wol,
8797 .get_msglevel = tg3_get_msglevel,
8798 .set_msglevel = tg3_set_msglevel,
8799 .nway_reset = tg3_nway_reset,
8800 .get_link = ethtool_op_get_link,
8801 .get_eeprom_len = tg3_get_eeprom_len,
8802 .get_eeprom = tg3_get_eeprom,
8803 .set_eeprom = tg3_set_eeprom,
8804 .get_ringparam = tg3_get_ringparam,
8805 .set_ringparam = tg3_set_ringparam,
8806 .get_pauseparam = tg3_get_pauseparam,
8807 .set_pauseparam = tg3_set_pauseparam,
8808 .get_rx_csum = tg3_get_rx_csum,
8809 .set_rx_csum = tg3_set_rx_csum,
8810 .get_tx_csum = ethtool_op_get_tx_csum,
8811 .set_tx_csum = tg3_set_tx_csum,
8812 .get_sg = ethtool_op_get_sg,
8813 .set_sg = ethtool_op_set_sg,
8814 #if TG3_TSO_SUPPORT != 0
8815 .get_tso = ethtool_op_get_tso,
8816 .set_tso = tg3_set_tso,
8817 #endif
8818 .self_test_count = tg3_get_test_count,
8819 .self_test = tg3_self_test,
8820 .get_strings = tg3_get_strings,
8821 .phys_id = tg3_phys_id,
8822 .get_stats_count = tg3_get_stats_count,
8823 .get_ethtool_stats = tg3_get_ethtool_stats,
8824 .get_coalesce = tg3_get_coalesce,
8825 .set_coalesce = tg3_set_coalesce,
8826 .get_perm_addr = ethtool_op_get_perm_addr,
8827 };
8828
8829 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8830 {
8831 u32 cursize, val, magic;
8832
8833 tp->nvram_size = EEPROM_CHIP_SIZE;
8834
8835 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8836 return;
8837
8838 if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000))
8839 return;
8840
8841 /*
8842 * Size the chip by reading offsets at increasing powers of two.
8843 * When we encounter our validation signature, we know the addressing
8844 * has wrapped around, and thus have our chip size.
8845 */
8846 cursize = 0x10;
8847
8848 while (cursize < tp->nvram_size) {
8849 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
8850 return;
8851
8852 if (val == magic)
8853 break;
8854
8855 cursize <<= 1;
8856 }
8857
8858 tp->nvram_size = cursize;
8859 }
8860
8861 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8862 {
8863 u32 val;
8864
8865 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
8866 return;
8867
8868 /* Selfboot format */
8869 if (val != TG3_EEPROM_MAGIC) {
8870 tg3_get_eeprom_size(tp);
8871 return;
8872 }
8873
8874 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8875 if (val != 0) {
8876 tp->nvram_size = (val >> 16) * 1024;
8877 return;
8878 }
8879 }
8880 tp->nvram_size = 0x20000;
8881 }
8882
8883 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8884 {
8885 u32 nvcfg1;
8886
8887 nvcfg1 = tr32(NVRAM_CFG1);
8888 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8889 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8890 }
8891 else {
8892 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8893 tw32(NVRAM_CFG1, nvcfg1);
8894 }
8895
8896 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8897 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8898 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8899 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8900 tp->nvram_jedecnum = JEDEC_ATMEL;
8901 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8902 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8903 break;
8904 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8905 tp->nvram_jedecnum = JEDEC_ATMEL;
8906 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8907 break;
8908 case FLASH_VENDOR_ATMEL_EEPROM:
8909 tp->nvram_jedecnum = JEDEC_ATMEL;
8910 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8911 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8912 break;
8913 case FLASH_VENDOR_ST:
8914 tp->nvram_jedecnum = JEDEC_ST;
8915 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8916 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8917 break;
8918 case FLASH_VENDOR_SAIFUN:
8919 tp->nvram_jedecnum = JEDEC_SAIFUN;
8920 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8921 break;
8922 case FLASH_VENDOR_SST_SMALL:
8923 case FLASH_VENDOR_SST_LARGE:
8924 tp->nvram_jedecnum = JEDEC_SST;
8925 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8926 break;
8927 }
8928 }
8929 else {
8930 tp->nvram_jedecnum = JEDEC_ATMEL;
8931 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8932 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8933 }
8934 }
8935
8936 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8937 {
8938 u32 nvcfg1;
8939
8940 nvcfg1 = tr32(NVRAM_CFG1);
8941
8942 /* NVRAM protection for TPM */
8943 if (nvcfg1 & (1 << 27))
8944 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8945
8946 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8947 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8948 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8949 tp->nvram_jedecnum = JEDEC_ATMEL;
8950 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8951 break;
8952 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8953 tp->nvram_jedecnum = JEDEC_ATMEL;
8954 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8955 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8956 break;
8957 case FLASH_5752VENDOR_ST_M45PE10:
8958 case FLASH_5752VENDOR_ST_M45PE20:
8959 case FLASH_5752VENDOR_ST_M45PE40:
8960 tp->nvram_jedecnum = JEDEC_ST;
8961 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8962 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8963 break;
8964 }
8965
8966 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8967 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8968 case FLASH_5752PAGE_SIZE_256:
8969 tp->nvram_pagesize = 256;
8970 break;
8971 case FLASH_5752PAGE_SIZE_512:
8972 tp->nvram_pagesize = 512;
8973 break;
8974 case FLASH_5752PAGE_SIZE_1K:
8975 tp->nvram_pagesize = 1024;
8976 break;
8977 case FLASH_5752PAGE_SIZE_2K:
8978 tp->nvram_pagesize = 2048;
8979 break;
8980 case FLASH_5752PAGE_SIZE_4K:
8981 tp->nvram_pagesize = 4096;
8982 break;
8983 case FLASH_5752PAGE_SIZE_264:
8984 tp->nvram_pagesize = 264;
8985 break;
8986 }
8987 }
8988 else {
8989 /* For eeprom, set pagesize to maximum eeprom size */
8990 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8991
8992 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8993 tw32(NVRAM_CFG1, nvcfg1);
8994 }
8995 }
8996
8997 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
8998 {
8999 u32 nvcfg1;
9000
9001 nvcfg1 = tr32(NVRAM_CFG1);
9002
9003 /* NVRAM protection for TPM */
9004 if (nvcfg1 & (1 << 27))
9005 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9006
9007 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9008 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9009 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9010 tp->nvram_jedecnum = JEDEC_ATMEL;
9011 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9012 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9013
9014 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9015 tw32(NVRAM_CFG1, nvcfg1);
9016 break;
9017 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9018 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9019 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9020 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9021 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9022 tp->nvram_jedecnum = JEDEC_ATMEL;
9023 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9024 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9025 tp->nvram_pagesize = 264;
9026 break;
9027 case FLASH_5752VENDOR_ST_M45PE10:
9028 case FLASH_5752VENDOR_ST_M45PE20:
9029 case FLASH_5752VENDOR_ST_M45PE40:
9030 tp->nvram_jedecnum = JEDEC_ST;
9031 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9032 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9033 tp->nvram_pagesize = 256;
9034 break;
9035 }
9036 }
9037
9038 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9039 {
9040 u32 nvcfg1;
9041
9042 nvcfg1 = tr32(NVRAM_CFG1);
9043
9044 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9045 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9046 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9047 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9048 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9049 tp->nvram_jedecnum = JEDEC_ATMEL;
9050 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9051 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9052
9053 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9054 tw32(NVRAM_CFG1, nvcfg1);
9055 break;
9056 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9057 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9058 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9059 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9060 tp->nvram_jedecnum = JEDEC_ATMEL;
9061 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9062 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9063 tp->nvram_pagesize = 264;
9064 break;
9065 case FLASH_5752VENDOR_ST_M45PE10:
9066 case FLASH_5752VENDOR_ST_M45PE20:
9067 case FLASH_5752VENDOR_ST_M45PE40:
9068 tp->nvram_jedecnum = JEDEC_ST;
9069 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9070 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9071 tp->nvram_pagesize = 256;
9072 break;
9073 }
9074 }
9075
9076 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9077 static void __devinit tg3_nvram_init(struct tg3 *tp)
9078 {
9079 int j;
9080
9081 tw32_f(GRC_EEPROM_ADDR,
9082 (EEPROM_ADDR_FSM_RESET |
9083 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9084 EEPROM_ADDR_CLKPERD_SHIFT)));
9085
9086 /* XXX schedule_timeout() ... */
9087 for (j = 0; j < 100; j++)
9088 udelay(10);
9089
9090 /* Enable seeprom accesses. */
9091 tw32_f(GRC_LOCAL_CTRL,
9092 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9093 udelay(100);
9094
9095 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9096 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9097 tp->tg3_flags |= TG3_FLAG_NVRAM;
9098
9099 if (tg3_nvram_lock(tp)) {
9100 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9101 "tg3_nvram_init failed.\n", tp->dev->name);
9102 return;
9103 }
9104 tg3_enable_nvram_access(tp);
9105
9106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9107 tg3_get_5752_nvram_info(tp);
9108 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9109 tg3_get_5755_nvram_info(tp);
9110 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9111 tg3_get_5787_nvram_info(tp);
9112 else
9113 tg3_get_nvram_info(tp);
9114
9115 tg3_get_nvram_size(tp);
9116
9117 tg3_disable_nvram_access(tp);
9118 tg3_nvram_unlock(tp);
9119
9120 } else {
9121 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9122
9123 tg3_get_eeprom_size(tp);
9124 }
9125 }
9126
9127 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9128 u32 offset, u32 *val)
9129 {
9130 u32 tmp;
9131 int i;
9132
9133 if (offset > EEPROM_ADDR_ADDR_MASK ||
9134 (offset % 4) != 0)
9135 return -EINVAL;
9136
9137 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9138 EEPROM_ADDR_DEVID_MASK |
9139 EEPROM_ADDR_READ);
9140 tw32(GRC_EEPROM_ADDR,
9141 tmp |
9142 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9143 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9144 EEPROM_ADDR_ADDR_MASK) |
9145 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9146
9147 for (i = 0; i < 10000; i++) {
9148 tmp = tr32(GRC_EEPROM_ADDR);
9149
9150 if (tmp & EEPROM_ADDR_COMPLETE)
9151 break;
9152 udelay(100);
9153 }
9154 if (!(tmp & EEPROM_ADDR_COMPLETE))
9155 return -EBUSY;
9156
9157 *val = tr32(GRC_EEPROM_DATA);
9158 return 0;
9159 }
9160
9161 #define NVRAM_CMD_TIMEOUT 10000
9162
9163 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9164 {
9165 int i;
9166
9167 tw32(NVRAM_CMD, nvram_cmd);
9168 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9169 udelay(10);
9170 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9171 udelay(10);
9172 break;
9173 }
9174 }
9175 if (i == NVRAM_CMD_TIMEOUT) {
9176 return -EBUSY;
9177 }
9178 return 0;
9179 }
9180
9181 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9182 {
9183 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9184 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9185 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9186 (tp->nvram_jedecnum == JEDEC_ATMEL))
9187
9188 addr = ((addr / tp->nvram_pagesize) <<
9189 ATMEL_AT45DB0X1B_PAGE_POS) +
9190 (addr % tp->nvram_pagesize);
9191
9192 return addr;
9193 }
9194
9195 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9196 {
9197 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9198 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9199 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9200 (tp->nvram_jedecnum == JEDEC_ATMEL))
9201
9202 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9203 tp->nvram_pagesize) +
9204 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9205
9206 return addr;
9207 }
9208
9209 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9210 {
9211 int ret;
9212
9213 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9214 return tg3_nvram_read_using_eeprom(tp, offset, val);
9215
9216 offset = tg3_nvram_phys_addr(tp, offset);
9217
9218 if (offset > NVRAM_ADDR_MSK)
9219 return -EINVAL;
9220
9221 ret = tg3_nvram_lock(tp);
9222 if (ret)
9223 return ret;
9224
9225 tg3_enable_nvram_access(tp);
9226
9227 tw32(NVRAM_ADDR, offset);
9228 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9229 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9230
9231 if (ret == 0)
9232 *val = swab32(tr32(NVRAM_RDDATA));
9233
9234 tg3_disable_nvram_access(tp);
9235
9236 tg3_nvram_unlock(tp);
9237
9238 return ret;
9239 }
9240
9241 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9242 {
9243 int err;
9244 u32 tmp;
9245
9246 err = tg3_nvram_read(tp, offset, &tmp);
9247 *val = swab32(tmp);
9248 return err;
9249 }
9250
9251 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9252 u32 offset, u32 len, u8 *buf)
9253 {
9254 int i, j, rc = 0;
9255 u32 val;
9256
9257 for (i = 0; i < len; i += 4) {
9258 u32 addr, data;
9259
9260 addr = offset + i;
9261
9262 memcpy(&data, buf + i, 4);
9263
9264 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9265
9266 val = tr32(GRC_EEPROM_ADDR);
9267 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9268
9269 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9270 EEPROM_ADDR_READ);
9271 tw32(GRC_EEPROM_ADDR, val |
9272 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9273 (addr & EEPROM_ADDR_ADDR_MASK) |
9274 EEPROM_ADDR_START |
9275 EEPROM_ADDR_WRITE);
9276
9277 for (j = 0; j < 10000; j++) {
9278 val = tr32(GRC_EEPROM_ADDR);
9279
9280 if (val & EEPROM_ADDR_COMPLETE)
9281 break;
9282 udelay(100);
9283 }
9284 if (!(val & EEPROM_ADDR_COMPLETE)) {
9285 rc = -EBUSY;
9286 break;
9287 }
9288 }
9289
9290 return rc;
9291 }
9292
9293 /* offset and length are dword aligned */
9294 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9295 u8 *buf)
9296 {
9297 int ret = 0;
9298 u32 pagesize = tp->nvram_pagesize;
9299 u32 pagemask = pagesize - 1;
9300 u32 nvram_cmd;
9301 u8 *tmp;
9302
9303 tmp = kmalloc(pagesize, GFP_KERNEL);
9304 if (tmp == NULL)
9305 return -ENOMEM;
9306
9307 while (len) {
9308 int j;
9309 u32 phy_addr, page_off, size;
9310
9311 phy_addr = offset & ~pagemask;
9312
9313 for (j = 0; j < pagesize; j += 4) {
9314 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9315 (u32 *) (tmp + j))))
9316 break;
9317 }
9318 if (ret)
9319 break;
9320
9321 page_off = offset & pagemask;
9322 size = pagesize;
9323 if (len < size)
9324 size = len;
9325
9326 len -= size;
9327
9328 memcpy(tmp + page_off, buf, size);
9329
9330 offset = offset + (pagesize - page_off);
9331
9332 tg3_enable_nvram_access(tp);
9333
9334 /*
9335 * Before we can erase the flash page, we need
9336 * to issue a special "write enable" command.
9337 */
9338 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9339
9340 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9341 break;
9342
9343 /* Erase the target page */
9344 tw32(NVRAM_ADDR, phy_addr);
9345
9346 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9347 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9348
9349 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9350 break;
9351
9352 /* Issue another write enable to start the write. */
9353 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9354
9355 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9356 break;
9357
9358 for (j = 0; j < pagesize; j += 4) {
9359 u32 data;
9360
9361 data = *((u32 *) (tmp + j));
9362 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9363
9364 tw32(NVRAM_ADDR, phy_addr + j);
9365
9366 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9367 NVRAM_CMD_WR;
9368
9369 if (j == 0)
9370 nvram_cmd |= NVRAM_CMD_FIRST;
9371 else if (j == (pagesize - 4))
9372 nvram_cmd |= NVRAM_CMD_LAST;
9373
9374 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9375 break;
9376 }
9377 if (ret)
9378 break;
9379 }
9380
9381 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9382 tg3_nvram_exec_cmd(tp, nvram_cmd);
9383
9384 kfree(tmp);
9385
9386 return ret;
9387 }
9388
9389 /* offset and length are dword aligned */
9390 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9391 u8 *buf)
9392 {
9393 int i, ret = 0;
9394
9395 for (i = 0; i < len; i += 4, offset += 4) {
9396 u32 data, page_off, phy_addr, nvram_cmd;
9397
9398 memcpy(&data, buf + i, 4);
9399 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9400
9401 page_off = offset % tp->nvram_pagesize;
9402
9403 phy_addr = tg3_nvram_phys_addr(tp, offset);
9404
9405 tw32(NVRAM_ADDR, phy_addr);
9406
9407 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9408
9409 if ((page_off == 0) || (i == 0))
9410 nvram_cmd |= NVRAM_CMD_FIRST;
9411 if (page_off == (tp->nvram_pagesize - 4))
9412 nvram_cmd |= NVRAM_CMD_LAST;
9413
9414 if (i == (len - 4))
9415 nvram_cmd |= NVRAM_CMD_LAST;
9416
9417 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9418 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9419 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9420 (tp->nvram_jedecnum == JEDEC_ST) &&
9421 (nvram_cmd & NVRAM_CMD_FIRST)) {
9422
9423 if ((ret = tg3_nvram_exec_cmd(tp,
9424 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9425 NVRAM_CMD_DONE)))
9426
9427 break;
9428 }
9429 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9430 /* We always do complete word writes to eeprom. */
9431 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9432 }
9433
9434 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9435 break;
9436 }
9437 return ret;
9438 }
9439
9440 /* offset and length are dword aligned */
9441 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9442 {
9443 int ret;
9444
9445 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9446 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9447 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9448 udelay(40);
9449 }
9450
9451 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9452 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9453 }
9454 else {
9455 u32 grc_mode;
9456
9457 ret = tg3_nvram_lock(tp);
9458 if (ret)
9459 return ret;
9460
9461 tg3_enable_nvram_access(tp);
9462 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9463 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9464 tw32(NVRAM_WRITE1, 0x406);
9465
9466 grc_mode = tr32(GRC_MODE);
9467 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9468
9469 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9470 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9471
9472 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9473 buf);
9474 }
9475 else {
9476 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9477 buf);
9478 }
9479
9480 grc_mode = tr32(GRC_MODE);
9481 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9482
9483 tg3_disable_nvram_access(tp);
9484 tg3_nvram_unlock(tp);
9485 }
9486
9487 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9488 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9489 udelay(40);
9490 }
9491
9492 return ret;
9493 }
9494
9495 struct subsys_tbl_ent {
9496 u16 subsys_vendor, subsys_devid;
9497 u32 phy_id;
9498 };
9499
9500 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9501 /* Broadcom boards. */
9502 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9503 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9504 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9505 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9506 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9507 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9508 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9509 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9510 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9511 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9512 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9513
9514 /* 3com boards. */
9515 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9516 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9517 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9518 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9519 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9520
9521 /* DELL boards. */
9522 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9523 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9524 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9525 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9526
9527 /* Compaq boards. */
9528 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9529 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9530 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9531 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9532 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9533
9534 /* IBM boards. */
9535 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9536 };
9537
9538 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9539 {
9540 int i;
9541
9542 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9543 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9544 tp->pdev->subsystem_vendor) &&
9545 (subsys_id_to_phy_id[i].subsys_devid ==
9546 tp->pdev->subsystem_device))
9547 return &subsys_id_to_phy_id[i];
9548 }
9549 return NULL;
9550 }
9551
9552 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9553 {
9554 u32 val;
9555 u16 pmcsr;
9556
9557 /* On some early chips the SRAM cannot be accessed in D3hot state,
9558 * so need make sure we're in D0.
9559 */
9560 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9561 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9562 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9563 msleep(1);
9564
9565 /* Make sure register accesses (indirect or otherwise)
9566 * will function correctly.
9567 */
9568 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9569 tp->misc_host_ctrl);
9570
9571 /* The memory arbiter has to be enabled in order for SRAM accesses
9572 * to succeed. Normally on powerup the tg3 chip firmware will make
9573 * sure it is enabled, but other entities such as system netboot
9574 * code might disable it.
9575 */
9576 val = tr32(MEMARB_MODE);
9577 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9578
9579 tp->phy_id = PHY_ID_INVALID;
9580 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9581
9582 /* Assume an onboard device by default. */
9583 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9584
9585 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9586 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9587 u32 nic_cfg, led_cfg;
9588 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9589 int eeprom_phy_serdes = 0;
9590
9591 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9592 tp->nic_sram_data_cfg = nic_cfg;
9593
9594 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9595 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9596 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9597 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9598 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9599 (ver > 0) && (ver < 0x100))
9600 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9601
9602 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9603 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9604 eeprom_phy_serdes = 1;
9605
9606 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9607 if (nic_phy_id != 0) {
9608 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9609 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9610
9611 eeprom_phy_id = (id1 >> 16) << 10;
9612 eeprom_phy_id |= (id2 & 0xfc00) << 16;
9613 eeprom_phy_id |= (id2 & 0x03ff) << 0;
9614 } else
9615 eeprom_phy_id = 0;
9616
9617 tp->phy_id = eeprom_phy_id;
9618 if (eeprom_phy_serdes) {
9619 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
9620 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9621 else
9622 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9623 }
9624
9625 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9626 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9627 SHASTA_EXT_LED_MODE_MASK);
9628 else
9629 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9630
9631 switch (led_cfg) {
9632 default:
9633 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9634 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9635 break;
9636
9637 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9638 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9639 break;
9640
9641 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9642 tp->led_ctrl = LED_CTRL_MODE_MAC;
9643
9644 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9645 * read on some older 5700/5701 bootcode.
9646 */
9647 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9648 ASIC_REV_5700 ||
9649 GET_ASIC_REV(tp->pci_chip_rev_id) ==
9650 ASIC_REV_5701)
9651 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9652
9653 break;
9654
9655 case SHASTA_EXT_LED_SHARED:
9656 tp->led_ctrl = LED_CTRL_MODE_SHARED;
9657 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9658 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9659 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9660 LED_CTRL_MODE_PHY_2);
9661 break;
9662
9663 case SHASTA_EXT_LED_MAC:
9664 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9665 break;
9666
9667 case SHASTA_EXT_LED_COMBO:
9668 tp->led_ctrl = LED_CTRL_MODE_COMBO;
9669 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9670 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9671 LED_CTRL_MODE_PHY_2);
9672 break;
9673
9674 };
9675
9676 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9677 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9678 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9679 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9680
9681 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
9682 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9683 else
9684 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9685
9686 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9687 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9688 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9689 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9690 }
9691 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9692 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9693
9694 if (cfg2 & (1 << 17))
9695 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9696
9697 /* serdes signal pre-emphasis in register 0x590 set by */
9698 /* bootcode if bit 18 is set */
9699 if (cfg2 & (1 << 18))
9700 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9701 }
9702 }
9703
9704 static int __devinit tg3_phy_probe(struct tg3 *tp)
9705 {
9706 u32 hw_phy_id_1, hw_phy_id_2;
9707 u32 hw_phy_id, hw_phy_id_masked;
9708 int err;
9709
9710 /* Reading the PHY ID register can conflict with ASF
9711 * firwmare access to the PHY hardware.
9712 */
9713 err = 0;
9714 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9715 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9716 } else {
9717 /* Now read the physical PHY_ID from the chip and verify
9718 * that it is sane. If it doesn't look good, we fall back
9719 * to either the hard-coded table based PHY_ID and failing
9720 * that the value found in the eeprom area.
9721 */
9722 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9723 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9724
9725 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
9726 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9727 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
9728
9729 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9730 }
9731
9732 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9733 tp->phy_id = hw_phy_id;
9734 if (hw_phy_id_masked == PHY_ID_BCM8002)
9735 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9736 else
9737 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9738 } else {
9739 if (tp->phy_id != PHY_ID_INVALID) {
9740 /* Do nothing, phy ID already set up in
9741 * tg3_get_eeprom_hw_cfg().
9742 */
9743 } else {
9744 struct subsys_tbl_ent *p;
9745
9746 /* No eeprom signature? Try the hardcoded
9747 * subsys device table.
9748 */
9749 p = lookup_by_subsys(tp);
9750 if (!p)
9751 return -ENODEV;
9752
9753 tp->phy_id = p->phy_id;
9754 if (!tp->phy_id ||
9755 tp->phy_id == PHY_ID_BCM8002)
9756 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9757 }
9758 }
9759
9760 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9761 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9762 u32 bmsr, adv_reg, tg3_ctrl;
9763
9764 tg3_readphy(tp, MII_BMSR, &bmsr);
9765 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9766 (bmsr & BMSR_LSTATUS))
9767 goto skip_phy_reset;
9768
9769 err = tg3_phy_reset(tp);
9770 if (err)
9771 return err;
9772
9773 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9774 ADVERTISE_100HALF | ADVERTISE_100FULL |
9775 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9776 tg3_ctrl = 0;
9777 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9778 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9779 MII_TG3_CTRL_ADV_1000_FULL);
9780 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9781 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9782 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9783 MII_TG3_CTRL_ENABLE_AS_MASTER);
9784 }
9785
9786 if (!tg3_copper_is_advertising_all(tp)) {
9787 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9788
9789 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9790 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9791
9792 tg3_writephy(tp, MII_BMCR,
9793 BMCR_ANENABLE | BMCR_ANRESTART);
9794 }
9795 tg3_phy_set_wirespeed(tp);
9796
9797 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9798 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9799 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9800 }
9801
9802 skip_phy_reset:
9803 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9804 err = tg3_init_5401phy_dsp(tp);
9805 if (err)
9806 return err;
9807 }
9808
9809 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9810 err = tg3_init_5401phy_dsp(tp);
9811 }
9812
9813 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9814 tp->link_config.advertising =
9815 (ADVERTISED_1000baseT_Half |
9816 ADVERTISED_1000baseT_Full |
9817 ADVERTISED_Autoneg |
9818 ADVERTISED_FIBRE);
9819 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9820 tp->link_config.advertising &=
9821 ~(ADVERTISED_1000baseT_Half |
9822 ADVERTISED_1000baseT_Full);
9823
9824 return err;
9825 }
9826
9827 static void __devinit tg3_read_partno(struct tg3 *tp)
9828 {
9829 unsigned char vpd_data[256];
9830 int i;
9831 u32 magic;
9832
9833 if (tg3_nvram_read_swab(tp, 0x0, &magic))
9834 goto out_not_found;
9835
9836 if (magic == TG3_EEPROM_MAGIC) {
9837 for (i = 0; i < 256; i += 4) {
9838 u32 tmp;
9839
9840 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9841 goto out_not_found;
9842
9843 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
9844 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
9845 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9846 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9847 }
9848 } else {
9849 int vpd_cap;
9850
9851 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
9852 for (i = 0; i < 256; i += 4) {
9853 u32 tmp, j = 0;
9854 u16 tmp16;
9855
9856 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
9857 i);
9858 while (j++ < 100) {
9859 pci_read_config_word(tp->pdev, vpd_cap +
9860 PCI_VPD_ADDR, &tmp16);
9861 if (tmp16 & 0x8000)
9862 break;
9863 msleep(1);
9864 }
9865 if (!(tmp16 & 0x8000))
9866 goto out_not_found;
9867
9868 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
9869 &tmp);
9870 tmp = cpu_to_le32(tmp);
9871 memcpy(&vpd_data[i], &tmp, 4);
9872 }
9873 }
9874
9875 /* Now parse and find the part number. */
9876 for (i = 0; i < 256; ) {
9877 unsigned char val = vpd_data[i];
9878 int block_end;
9879
9880 if (val == 0x82 || val == 0x91) {
9881 i = (i + 3 +
9882 (vpd_data[i + 1] +
9883 (vpd_data[i + 2] << 8)));
9884 continue;
9885 }
9886
9887 if (val != 0x90)
9888 goto out_not_found;
9889
9890 block_end = (i + 3 +
9891 (vpd_data[i + 1] +
9892 (vpd_data[i + 2] << 8)));
9893 i += 3;
9894 while (i < block_end) {
9895 if (vpd_data[i + 0] == 'P' &&
9896 vpd_data[i + 1] == 'N') {
9897 int partno_len = vpd_data[i + 2];
9898
9899 if (partno_len > 24)
9900 goto out_not_found;
9901
9902 memcpy(tp->board_part_number,
9903 &vpd_data[i + 3],
9904 partno_len);
9905
9906 /* Success. */
9907 return;
9908 }
9909 }
9910
9911 /* Part number not found. */
9912 goto out_not_found;
9913 }
9914
9915 out_not_found:
9916 strcpy(tp->board_part_number, "none");
9917 }
9918
9919 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
9920 {
9921 u32 val, offset, start;
9922
9923 if (tg3_nvram_read_swab(tp, 0, &val))
9924 return;
9925
9926 if (val != TG3_EEPROM_MAGIC)
9927 return;
9928
9929 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
9930 tg3_nvram_read_swab(tp, 0x4, &start))
9931 return;
9932
9933 offset = tg3_nvram_logical_addr(tp, offset);
9934 if (tg3_nvram_read_swab(tp, offset, &val))
9935 return;
9936
9937 if ((val & 0xfc000000) == 0x0c000000) {
9938 u32 ver_offset, addr;
9939 int i;
9940
9941 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
9942 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
9943 return;
9944
9945 if (val != 0)
9946 return;
9947
9948 addr = offset + ver_offset - start;
9949 for (i = 0; i < 16; i += 4) {
9950 if (tg3_nvram_read(tp, addr + i, &val))
9951 return;
9952
9953 val = cpu_to_le32(val);
9954 memcpy(tp->fw_ver + i, &val, 4);
9955 }
9956 }
9957 }
9958
9959 static int __devinit tg3_get_invariants(struct tg3 *tp)
9960 {
9961 static struct pci_device_id write_reorder_chipsets[] = {
9962 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9963 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9964 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
9965 PCI_DEVICE_ID_VIA_8385_0) },
9966 { },
9967 };
9968 u32 misc_ctrl_reg;
9969 u32 cacheline_sz_reg;
9970 u32 pci_state_reg, grc_misc_cfg;
9971 u32 val;
9972 u16 pci_cmd;
9973 int err;
9974
9975 /* Force memory write invalidate off. If we leave it on,
9976 * then on 5700_BX chips we have to enable a workaround.
9977 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
9978 * to match the cacheline size. The Broadcom driver have this
9979 * workaround but turns MWI off all the times so never uses
9980 * it. This seems to suggest that the workaround is insufficient.
9981 */
9982 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9983 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
9984 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9985
9986 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
9987 * has the register indirect write enable bit set before
9988 * we try to access any of the MMIO registers. It is also
9989 * critical that the PCI-X hw workaround situation is decided
9990 * before that as well.
9991 */
9992 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9993 &misc_ctrl_reg);
9994
9995 tp->pci_chip_rev_id = (misc_ctrl_reg >>
9996 MISC_HOST_CTRL_CHIPREV_SHIFT);
9997
9998 /* Wrong chip ID in 5752 A0. This code can be removed later
9999 * as A0 is not in production.
10000 */
10001 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10002 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10003
10004 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10005 * we need to disable memory and use config. cycles
10006 * only to access all registers. The 5702/03 chips
10007 * can mistakenly decode the special cycles from the
10008 * ICH chipsets as memory write cycles, causing corruption
10009 * of register and memory space. Only certain ICH bridges
10010 * will drive special cycles with non-zero data during the
10011 * address phase which can fall within the 5703's address
10012 * range. This is not an ICH bug as the PCI spec allows
10013 * non-zero address during special cycles. However, only
10014 * these ICH bridges are known to drive non-zero addresses
10015 * during special cycles.
10016 *
10017 * Since special cycles do not cross PCI bridges, we only
10018 * enable this workaround if the 5703 is on the secondary
10019 * bus of these ICH bridges.
10020 */
10021 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10022 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10023 static struct tg3_dev_id {
10024 u32 vendor;
10025 u32 device;
10026 u32 rev;
10027 } ich_chipsets[] = {
10028 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10029 PCI_ANY_ID },
10030 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10031 PCI_ANY_ID },
10032 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10033 0xa },
10034 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10035 PCI_ANY_ID },
10036 { },
10037 };
10038 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10039 struct pci_dev *bridge = NULL;
10040
10041 while (pci_id->vendor != 0) {
10042 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10043 bridge);
10044 if (!bridge) {
10045 pci_id++;
10046 continue;
10047 }
10048 if (pci_id->rev != PCI_ANY_ID) {
10049 u8 rev;
10050
10051 pci_read_config_byte(bridge, PCI_REVISION_ID,
10052 &rev);
10053 if (rev > pci_id->rev)
10054 continue;
10055 }
10056 if (bridge->subordinate &&
10057 (bridge->subordinate->number ==
10058 tp->pdev->bus->number)) {
10059
10060 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10061 pci_dev_put(bridge);
10062 break;
10063 }
10064 }
10065 }
10066
10067 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10068 * DMA addresses > 40-bit. This bridge may have other additional
10069 * 57xx devices behind it in some 4-port NIC designs for example.
10070 * Any tg3 device found behind the bridge will also need the 40-bit
10071 * DMA workaround.
10072 */
10073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10074 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10075 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10076 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10077 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10078 }
10079 else {
10080 struct pci_dev *bridge = NULL;
10081
10082 do {
10083 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10084 PCI_DEVICE_ID_SERVERWORKS_EPB,
10085 bridge);
10086 if (bridge && bridge->subordinate &&
10087 (bridge->subordinate->number <=
10088 tp->pdev->bus->number) &&
10089 (bridge->subordinate->subordinate >=
10090 tp->pdev->bus->number)) {
10091 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10092 pci_dev_put(bridge);
10093 break;
10094 }
10095 } while (bridge);
10096 }
10097
10098 /* Initialize misc host control in PCI block. */
10099 tp->misc_host_ctrl |= (misc_ctrl_reg &
10100 MISC_HOST_CTRL_CHIPREV);
10101 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10102 tp->misc_host_ctrl);
10103
10104 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10105 &cacheline_sz_reg);
10106
10107 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10108 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10109 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10110 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10111
10112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10113 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10114 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10115 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10116 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10117 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10118
10119 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10120 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10121 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10122
10123 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10126 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10127 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10128 } else
10129 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1;
10130 }
10131
10132 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10133 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10134 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10135 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10136 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
10137 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10138
10139 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
10140 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10141
10142 /* If we have an AMD 762 or VIA K8T800 chipset, write
10143 * reordering to the mailbox registers done by the host
10144 * controller can cause major troubles. We read back from
10145 * every mailbox register write to force the writes to be
10146 * posted to the chip in order.
10147 */
10148 if (pci_dev_present(write_reorder_chipsets) &&
10149 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10150 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10151
10152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10153 tp->pci_lat_timer < 64) {
10154 tp->pci_lat_timer = 64;
10155
10156 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10157 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10158 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10159 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10160
10161 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10162 cacheline_sz_reg);
10163 }
10164
10165 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10166 &pci_state_reg);
10167
10168 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10169 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10170
10171 /* If this is a 5700 BX chipset, and we are in PCI-X
10172 * mode, enable register write workaround.
10173 *
10174 * The workaround is to use indirect register accesses
10175 * for all chip writes not to mailbox registers.
10176 */
10177 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10178 u32 pm_reg;
10179 u16 pci_cmd;
10180
10181 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10182
10183 /* The chip can have it's power management PCI config
10184 * space registers clobbered due to this bug.
10185 * So explicitly force the chip into D0 here.
10186 */
10187 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10188 &pm_reg);
10189 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10190 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10191 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10192 pm_reg);
10193
10194 /* Also, force SERR#/PERR# in PCI command. */
10195 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10196 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10197 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10198 }
10199 }
10200
10201 /* 5700 BX chips need to have their TX producer index mailboxes
10202 * written twice to workaround a bug.
10203 */
10204 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10205 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10206
10207 /* Back to back register writes can cause problems on this chip,
10208 * the workaround is to read back all reg writes except those to
10209 * mailbox regs. See tg3_write_indirect_reg32().
10210 *
10211 * PCI Express 5750_A0 rev chips need this workaround too.
10212 */
10213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10214 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10215 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10216 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10217
10218 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10219 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10220 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10221 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10222
10223 /* Chip-specific fixup from Broadcom driver */
10224 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10225 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10226 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10227 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10228 }
10229
10230 /* Default fast path register access methods */
10231 tp->read32 = tg3_read32;
10232 tp->write32 = tg3_write32;
10233 tp->read32_mbox = tg3_read32;
10234 tp->write32_mbox = tg3_write32;
10235 tp->write32_tx_mbox = tg3_write32;
10236 tp->write32_rx_mbox = tg3_write32;
10237
10238 /* Various workaround register access methods */
10239 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10240 tp->write32 = tg3_write_indirect_reg32;
10241 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10242 tp->write32 = tg3_write_flush_reg32;
10243
10244 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10245 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10246 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10247 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10248 tp->write32_rx_mbox = tg3_write_flush_reg32;
10249 }
10250
10251 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10252 tp->read32 = tg3_read_indirect_reg32;
10253 tp->write32 = tg3_write_indirect_reg32;
10254 tp->read32_mbox = tg3_read_indirect_mbox;
10255 tp->write32_mbox = tg3_write_indirect_mbox;
10256 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10257 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10258
10259 iounmap(tp->regs);
10260 tp->regs = NULL;
10261
10262 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10263 pci_cmd &= ~PCI_COMMAND_MEMORY;
10264 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10265 }
10266
10267 if (tp->write32 == tg3_write_indirect_reg32 ||
10268 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10269 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10271 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10272
10273 /* Get eeprom hw config before calling tg3_set_power_state().
10274 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10275 * determined before calling tg3_set_power_state() so that
10276 * we know whether or not to switch out of Vaux power.
10277 * When the flag is set, it means that GPIO1 is used for eeprom
10278 * write protect and also implies that it is a LOM where GPIOs
10279 * are not used to switch power.
10280 */
10281 tg3_get_eeprom_hw_cfg(tp);
10282
10283 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10284 * GPIO1 driven high will bring 5700's external PHY out of reset.
10285 * It is also used as eeprom write protect on LOMs.
10286 */
10287 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10288 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10289 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10290 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10291 GRC_LCLCTRL_GPIO_OUTPUT1);
10292 /* Unused GPIO3 must be driven as output on 5752 because there
10293 * are no pull-up resistors on unused GPIO pins.
10294 */
10295 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10296 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10297
10298 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10299 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10300
10301 /* Force the chip into D0. */
10302 err = tg3_set_power_state(tp, PCI_D0);
10303 if (err) {
10304 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10305 pci_name(tp->pdev));
10306 return err;
10307 }
10308
10309 /* 5700 B0 chips do not support checksumming correctly due
10310 * to hardware bugs.
10311 */
10312 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10313 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10314
10315 /* Derive initial jumbo mode from MTU assigned in
10316 * ether_setup() via the alloc_etherdev() call
10317 */
10318 if (tp->dev->mtu > ETH_DATA_LEN &&
10319 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10320 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10321
10322 /* Determine WakeOnLan speed to use. */
10323 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10324 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10325 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10326 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10327 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10328 } else {
10329 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10330 }
10331
10332 /* A few boards don't want Ethernet@WireSpeed phy feature */
10333 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10334 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10335 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10336 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10337 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10338 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10339
10340 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10341 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10342 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10343 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10344 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10345
10346 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10349 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10350 else
10351 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10352 }
10353
10354 tp->coalesce_mode = 0;
10355 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10356 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10357 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10358
10359 /* Initialize MAC MI mode, polling disabled. */
10360 tw32_f(MAC_MI_MODE, tp->mi_mode);
10361 udelay(80);
10362
10363 /* Initialize data/descriptor byte/word swapping. */
10364 val = tr32(GRC_MODE);
10365 val &= GRC_MODE_HOST_STACKUP;
10366 tw32(GRC_MODE, val | tp->grc_mode);
10367
10368 tg3_switch_clocks(tp);
10369
10370 /* Clear this out for sanity. */
10371 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10372
10373 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10374 &pci_state_reg);
10375 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10376 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10377 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10378
10379 if (chiprevid == CHIPREV_ID_5701_A0 ||
10380 chiprevid == CHIPREV_ID_5701_B0 ||
10381 chiprevid == CHIPREV_ID_5701_B2 ||
10382 chiprevid == CHIPREV_ID_5701_B5) {
10383 void __iomem *sram_base;
10384
10385 /* Write some dummy words into the SRAM status block
10386 * area, see if it reads back correctly. If the return
10387 * value is bad, force enable the PCIX workaround.
10388 */
10389 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10390
10391 writel(0x00000000, sram_base);
10392 writel(0x00000000, sram_base + 4);
10393 writel(0xffffffff, sram_base + 4);
10394 if (readl(sram_base) != 0x00000000)
10395 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10396 }
10397 }
10398
10399 udelay(50);
10400 tg3_nvram_init(tp);
10401
10402 grc_misc_cfg = tr32(GRC_MISC_CFG);
10403 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10404
10405 /* Broadcom's driver says that CIOBE multisplit has a bug */
10406 #if 0
10407 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10408 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10409 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10410 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10411 }
10412 #endif
10413 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10414 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10415 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10416 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10417
10418 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10419 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10420 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10421 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10422 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10423 HOSTCC_MODE_CLRTICK_TXBD);
10424
10425 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10426 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10427 tp->misc_host_ctrl);
10428 }
10429
10430 /* these are limited to 10/100 only */
10431 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10432 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10433 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10434 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10435 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10436 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10437 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10438 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10439 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10440 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
10441 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10442
10443 err = tg3_phy_probe(tp);
10444 if (err) {
10445 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10446 pci_name(tp->pdev), err);
10447 /* ... but do not return immediately ... */
10448 }
10449
10450 tg3_read_partno(tp);
10451 tg3_read_fw_ver(tp);
10452
10453 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10454 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10455 } else {
10456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10457 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10458 else
10459 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10460 }
10461
10462 /* 5700 {AX,BX} chips have a broken status block link
10463 * change bit implementation, so we must use the
10464 * status register in those cases.
10465 */
10466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10467 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10468 else
10469 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10470
10471 /* The led_ctrl is set during tg3_phy_probe, here we might
10472 * have to force the link status polling mechanism based
10473 * upon subsystem IDs.
10474 */
10475 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10476 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10477 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10478 TG3_FLAG_USE_LINKCHG_REG);
10479 }
10480
10481 /* For all SERDES we poll the MAC status register. */
10482 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10483 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10484 else
10485 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10486
10487 /* All chips before 5787 can get confused if TX buffers
10488 * straddle the 4GB address boundary in some cases.
10489 */
10490 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10491 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10492 tp->dev->hard_start_xmit = tg3_start_xmit;
10493 else
10494 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10495
10496 tp->rx_offset = 2;
10497 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10498 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10499 tp->rx_offset = 0;
10500
10501 /* By default, disable wake-on-lan. User can change this
10502 * using ETHTOOL_SWOL.
10503 */
10504 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10505
10506 return err;
10507 }
10508
10509 #ifdef CONFIG_SPARC64
10510 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10511 {
10512 struct net_device *dev = tp->dev;
10513 struct pci_dev *pdev = tp->pdev;
10514 struct pcidev_cookie *pcp = pdev->sysdata;
10515
10516 if (pcp != NULL) {
10517 int node = pcp->prom_node;
10518
10519 if (prom_getproplen(node, "local-mac-address") == 6) {
10520 prom_getproperty(node, "local-mac-address",
10521 dev->dev_addr, 6);
10522 memcpy(dev->perm_addr, dev->dev_addr, 6);
10523 return 0;
10524 }
10525 }
10526 return -ENODEV;
10527 }
10528
10529 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10530 {
10531 struct net_device *dev = tp->dev;
10532
10533 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10534 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10535 return 0;
10536 }
10537 #endif
10538
10539 static int __devinit tg3_get_device_address(struct tg3 *tp)
10540 {
10541 struct net_device *dev = tp->dev;
10542 u32 hi, lo, mac_offset;
10543 int addr_ok = 0;
10544
10545 #ifdef CONFIG_SPARC64
10546 if (!tg3_get_macaddr_sparc(tp))
10547 return 0;
10548 #endif
10549
10550 mac_offset = 0x7c;
10551 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10552 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10553 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10554 mac_offset = 0xcc;
10555 if (tg3_nvram_lock(tp))
10556 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
10557 else
10558 tg3_nvram_unlock(tp);
10559 }
10560
10561 /* First try to get it from MAC address mailbox. */
10562 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
10563 if ((hi >> 16) == 0x484b) {
10564 dev->dev_addr[0] = (hi >> 8) & 0xff;
10565 dev->dev_addr[1] = (hi >> 0) & 0xff;
10566
10567 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
10568 dev->dev_addr[2] = (lo >> 24) & 0xff;
10569 dev->dev_addr[3] = (lo >> 16) & 0xff;
10570 dev->dev_addr[4] = (lo >> 8) & 0xff;
10571 dev->dev_addr[5] = (lo >> 0) & 0xff;
10572
10573 /* Some old bootcode may report a 0 MAC address in SRAM */
10574 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
10575 }
10576 if (!addr_ok) {
10577 /* Next, try NVRAM. */
10578 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
10579 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
10580 dev->dev_addr[0] = ((hi >> 16) & 0xff);
10581 dev->dev_addr[1] = ((hi >> 24) & 0xff);
10582 dev->dev_addr[2] = ((lo >> 0) & 0xff);
10583 dev->dev_addr[3] = ((lo >> 8) & 0xff);
10584 dev->dev_addr[4] = ((lo >> 16) & 0xff);
10585 dev->dev_addr[5] = ((lo >> 24) & 0xff);
10586 }
10587 /* Finally just fetch it out of the MAC control regs. */
10588 else {
10589 hi = tr32(MAC_ADDR_0_HIGH);
10590 lo = tr32(MAC_ADDR_0_LOW);
10591
10592 dev->dev_addr[5] = lo & 0xff;
10593 dev->dev_addr[4] = (lo >> 8) & 0xff;
10594 dev->dev_addr[3] = (lo >> 16) & 0xff;
10595 dev->dev_addr[2] = (lo >> 24) & 0xff;
10596 dev->dev_addr[1] = hi & 0xff;
10597 dev->dev_addr[0] = (hi >> 8) & 0xff;
10598 }
10599 }
10600
10601 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
10602 #ifdef CONFIG_SPARC64
10603 if (!tg3_get_default_macaddr_sparc(tp))
10604 return 0;
10605 #endif
10606 return -EINVAL;
10607 }
10608 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
10609 return 0;
10610 }
10611
10612 #define BOUNDARY_SINGLE_CACHELINE 1
10613 #define BOUNDARY_MULTI_CACHELINE 2
10614
10615 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
10616 {
10617 int cacheline_size;
10618 u8 byte;
10619 int goal;
10620
10621 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
10622 if (byte == 0)
10623 cacheline_size = 1024;
10624 else
10625 cacheline_size = (int) byte * 4;
10626
10627 /* On 5703 and later chips, the boundary bits have no
10628 * effect.
10629 */
10630 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10631 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
10632 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10633 goto out;
10634
10635 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
10636 goal = BOUNDARY_MULTI_CACHELINE;
10637 #else
10638 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
10639 goal = BOUNDARY_SINGLE_CACHELINE;
10640 #else
10641 goal = 0;
10642 #endif
10643 #endif
10644
10645 if (!goal)
10646 goto out;
10647
10648 /* PCI controllers on most RISC systems tend to disconnect
10649 * when a device tries to burst across a cache-line boundary.
10650 * Therefore, letting tg3 do so just wastes PCI bandwidth.
10651 *
10652 * Unfortunately, for PCI-E there are only limited
10653 * write-side controls for this, and thus for reads
10654 * we will still get the disconnects. We'll also waste
10655 * these PCI cycles for both read and write for chips
10656 * other than 5700 and 5701 which do not implement the
10657 * boundary bits.
10658 */
10659 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10660 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10661 switch (cacheline_size) {
10662 case 16:
10663 case 32:
10664 case 64:
10665 case 128:
10666 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10667 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10668 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10669 } else {
10670 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10671 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10672 }
10673 break;
10674
10675 case 256:
10676 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10677 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10678 break;
10679
10680 default:
10681 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10682 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10683 break;
10684 };
10685 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10686 switch (cacheline_size) {
10687 case 16:
10688 case 32:
10689 case 64:
10690 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10691 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10692 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10693 break;
10694 }
10695 /* fallthrough */
10696 case 128:
10697 default:
10698 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10699 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10700 break;
10701 };
10702 } else {
10703 switch (cacheline_size) {
10704 case 16:
10705 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10706 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10707 DMA_RWCTRL_WRITE_BNDRY_16);
10708 break;
10709 }
10710 /* fallthrough */
10711 case 32:
10712 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10713 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10714 DMA_RWCTRL_WRITE_BNDRY_32);
10715 break;
10716 }
10717 /* fallthrough */
10718 case 64:
10719 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10720 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10721 DMA_RWCTRL_WRITE_BNDRY_64);
10722 break;
10723 }
10724 /* fallthrough */
10725 case 128:
10726 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10727 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10728 DMA_RWCTRL_WRITE_BNDRY_128);
10729 break;
10730 }
10731 /* fallthrough */
10732 case 256:
10733 val |= (DMA_RWCTRL_READ_BNDRY_256 |
10734 DMA_RWCTRL_WRITE_BNDRY_256);
10735 break;
10736 case 512:
10737 val |= (DMA_RWCTRL_READ_BNDRY_512 |
10738 DMA_RWCTRL_WRITE_BNDRY_512);
10739 break;
10740 case 1024:
10741 default:
10742 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10743 DMA_RWCTRL_WRITE_BNDRY_1024);
10744 break;
10745 };
10746 }
10747
10748 out:
10749 return val;
10750 }
10751
10752 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10753 {
10754 struct tg3_internal_buffer_desc test_desc;
10755 u32 sram_dma_descs;
10756 int i, ret;
10757
10758 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10759
10760 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10761 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10762 tw32(RDMAC_STATUS, 0);
10763 tw32(WDMAC_STATUS, 0);
10764
10765 tw32(BUFMGR_MODE, 0);
10766 tw32(FTQ_RESET, 0);
10767
10768 test_desc.addr_hi = ((u64) buf_dma) >> 32;
10769 test_desc.addr_lo = buf_dma & 0xffffffff;
10770 test_desc.nic_mbuf = 0x00002100;
10771 test_desc.len = size;
10772
10773 /*
10774 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10775 * the *second* time the tg3 driver was getting loaded after an
10776 * initial scan.
10777 *
10778 * Broadcom tells me:
10779 * ...the DMA engine is connected to the GRC block and a DMA
10780 * reset may affect the GRC block in some unpredictable way...
10781 * The behavior of resets to individual blocks has not been tested.
10782 *
10783 * Broadcom noted the GRC reset will also reset all sub-components.
10784 */
10785 if (to_device) {
10786 test_desc.cqid_sqid = (13 << 8) | 2;
10787
10788 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10789 udelay(40);
10790 } else {
10791 test_desc.cqid_sqid = (16 << 8) | 7;
10792
10793 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10794 udelay(40);
10795 }
10796 test_desc.flags = 0x00000005;
10797
10798 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10799 u32 val;
10800
10801 val = *(((u32 *)&test_desc) + i);
10802 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10803 sram_dma_descs + (i * sizeof(u32)));
10804 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10805 }
10806 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10807
10808 if (to_device) {
10809 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10810 } else {
10811 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10812 }
10813
10814 ret = -ENODEV;
10815 for (i = 0; i < 40; i++) {
10816 u32 val;
10817
10818 if (to_device)
10819 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10820 else
10821 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10822 if ((val & 0xffff) == sram_dma_descs) {
10823 ret = 0;
10824 break;
10825 }
10826
10827 udelay(100);
10828 }
10829
10830 return ret;
10831 }
10832
10833 #define TEST_BUFFER_SIZE 0x2000
10834
10835 static int __devinit tg3_test_dma(struct tg3 *tp)
10836 {
10837 dma_addr_t buf_dma;
10838 u32 *buf, saved_dma_rwctrl;
10839 int ret;
10840
10841 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10842 if (!buf) {
10843 ret = -ENOMEM;
10844 goto out_nofree;
10845 }
10846
10847 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10848 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10849
10850 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10851
10852 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10853 /* DMA read watermark not used on PCIE */
10854 tp->dma_rwctrl |= 0x00180000;
10855 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10858 tp->dma_rwctrl |= 0x003f0000;
10859 else
10860 tp->dma_rwctrl |= 0x003f000f;
10861 } else {
10862 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10863 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10864 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10865
10866 /* If the 5704 is behind the EPB bridge, we can
10867 * do the less restrictive ONE_DMA workaround for
10868 * better performance.
10869 */
10870 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
10871 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10872 tp->dma_rwctrl |= 0x8000;
10873 else if (ccval == 0x6 || ccval == 0x7)
10874 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10875
10876 /* Set bit 23 to enable PCIX hw bug fix */
10877 tp->dma_rwctrl |= 0x009f0000;
10878 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10879 /* 5780 always in PCIX mode */
10880 tp->dma_rwctrl |= 0x00144000;
10881 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10882 /* 5714 always in PCIX mode */
10883 tp->dma_rwctrl |= 0x00148000;
10884 } else {
10885 tp->dma_rwctrl |= 0x001b000f;
10886 }
10887 }
10888
10889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10891 tp->dma_rwctrl &= 0xfffffff0;
10892
10893 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10894 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10895 /* Remove this if it causes problems for some boards. */
10896 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10897
10898 /* On 5700/5701 chips, we need to set this bit.
10899 * Otherwise the chip will issue cacheline transactions
10900 * to streamable DMA memory with not all the byte
10901 * enables turned on. This is an error on several
10902 * RISC PCI controllers, in particular sparc64.
10903 *
10904 * On 5703/5704 chips, this bit has been reassigned
10905 * a different meaning. In particular, it is used
10906 * on those chips to enable a PCI-X workaround.
10907 */
10908 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10909 }
10910
10911 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10912
10913 #if 0
10914 /* Unneeded, already done by tg3_get_invariants. */
10915 tg3_switch_clocks(tp);
10916 #endif
10917
10918 ret = 0;
10919 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10920 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10921 goto out;
10922
10923 /* It is best to perform DMA test with maximum write burst size
10924 * to expose the 5700/5701 write DMA bug.
10925 */
10926 saved_dma_rwctrl = tp->dma_rwctrl;
10927 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10928 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10929
10930 while (1) {
10931 u32 *p = buf, i;
10932
10933 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10934 p[i] = i;
10935
10936 /* Send the buffer to the chip. */
10937 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10938 if (ret) {
10939 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10940 break;
10941 }
10942
10943 #if 0
10944 /* validate data reached card RAM correctly. */
10945 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10946 u32 val;
10947 tg3_read_mem(tp, 0x2100 + (i*4), &val);
10948 if (le32_to_cpu(val) != p[i]) {
10949 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
10950 /* ret = -ENODEV here? */
10951 }
10952 p[i] = 0;
10953 }
10954 #endif
10955 /* Now read it back. */
10956 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10957 if (ret) {
10958 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10959
10960 break;
10961 }
10962
10963 /* Verify it. */
10964 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10965 if (p[i] == i)
10966 continue;
10967
10968 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10969 DMA_RWCTRL_WRITE_BNDRY_16) {
10970 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10971 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10972 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10973 break;
10974 } else {
10975 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
10976 ret = -ENODEV;
10977 goto out;
10978 }
10979 }
10980
10981 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
10982 /* Success. */
10983 ret = 0;
10984 break;
10985 }
10986 }
10987 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10988 DMA_RWCTRL_WRITE_BNDRY_16) {
10989 static struct pci_device_id dma_wait_state_chipsets[] = {
10990 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
10991 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
10992 { },
10993 };
10994
10995 /* DMA test passed without adjusting DMA boundary,
10996 * now look for chipsets that are known to expose the
10997 * DMA bug without failing the test.
10998 */
10999 if (pci_dev_present(dma_wait_state_chipsets)) {
11000 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11001 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11002 }
11003 else
11004 /* Safe to use the calculated DMA boundary. */
11005 tp->dma_rwctrl = saved_dma_rwctrl;
11006
11007 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11008 }
11009
11010 out:
11011 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11012 out_nofree:
11013 return ret;
11014 }
11015
11016 static void __devinit tg3_init_link_config(struct tg3 *tp)
11017 {
11018 tp->link_config.advertising =
11019 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11020 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11021 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11022 ADVERTISED_Autoneg | ADVERTISED_MII);
11023 tp->link_config.speed = SPEED_INVALID;
11024 tp->link_config.duplex = DUPLEX_INVALID;
11025 tp->link_config.autoneg = AUTONEG_ENABLE;
11026 tp->link_config.active_speed = SPEED_INVALID;
11027 tp->link_config.active_duplex = DUPLEX_INVALID;
11028 tp->link_config.phy_is_low_power = 0;
11029 tp->link_config.orig_speed = SPEED_INVALID;
11030 tp->link_config.orig_duplex = DUPLEX_INVALID;
11031 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11032 }
11033
11034 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11035 {
11036 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11037 tp->bufmgr_config.mbuf_read_dma_low_water =
11038 DEFAULT_MB_RDMA_LOW_WATER_5705;
11039 tp->bufmgr_config.mbuf_mac_rx_low_water =
11040 DEFAULT_MB_MACRX_LOW_WATER_5705;
11041 tp->bufmgr_config.mbuf_high_water =
11042 DEFAULT_MB_HIGH_WATER_5705;
11043
11044 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11045 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11046 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11047 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11048 tp->bufmgr_config.mbuf_high_water_jumbo =
11049 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11050 } else {
11051 tp->bufmgr_config.mbuf_read_dma_low_water =
11052 DEFAULT_MB_RDMA_LOW_WATER;
11053 tp->bufmgr_config.mbuf_mac_rx_low_water =
11054 DEFAULT_MB_MACRX_LOW_WATER;
11055 tp->bufmgr_config.mbuf_high_water =
11056 DEFAULT_MB_HIGH_WATER;
11057
11058 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11059 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11060 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11061 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11062 tp->bufmgr_config.mbuf_high_water_jumbo =
11063 DEFAULT_MB_HIGH_WATER_JUMBO;
11064 }
11065
11066 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11067 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11068 }
11069
11070 static char * __devinit tg3_phy_string(struct tg3 *tp)
11071 {
11072 switch (tp->phy_id & PHY_ID_MASK) {
11073 case PHY_ID_BCM5400: return "5400";
11074 case PHY_ID_BCM5401: return "5401";
11075 case PHY_ID_BCM5411: return "5411";
11076 case PHY_ID_BCM5701: return "5701";
11077 case PHY_ID_BCM5703: return "5703";
11078 case PHY_ID_BCM5704: return "5704";
11079 case PHY_ID_BCM5705: return "5705";
11080 case PHY_ID_BCM5750: return "5750";
11081 case PHY_ID_BCM5752: return "5752";
11082 case PHY_ID_BCM5714: return "5714";
11083 case PHY_ID_BCM5780: return "5780";
11084 case PHY_ID_BCM5755: return "5755";
11085 case PHY_ID_BCM5787: return "5787";
11086 case PHY_ID_BCM8002: return "8002/serdes";
11087 case 0: return "serdes";
11088 default: return "unknown";
11089 };
11090 }
11091
11092 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11093 {
11094 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11095 strcpy(str, "PCI Express");
11096 return str;
11097 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11098 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11099
11100 strcpy(str, "PCIX:");
11101
11102 if ((clock_ctrl == 7) ||
11103 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11104 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11105 strcat(str, "133MHz");
11106 else if (clock_ctrl == 0)
11107 strcat(str, "33MHz");
11108 else if (clock_ctrl == 2)
11109 strcat(str, "50MHz");
11110 else if (clock_ctrl == 4)
11111 strcat(str, "66MHz");
11112 else if (clock_ctrl == 6)
11113 strcat(str, "100MHz");
11114 } else {
11115 strcpy(str, "PCI:");
11116 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11117 strcat(str, "66MHz");
11118 else
11119 strcat(str, "33MHz");
11120 }
11121 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11122 strcat(str, ":32-bit");
11123 else
11124 strcat(str, ":64-bit");
11125 return str;
11126 }
11127
11128 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11129 {
11130 struct pci_dev *peer;
11131 unsigned int func, devnr = tp->pdev->devfn & ~7;
11132
11133 for (func = 0; func < 8; func++) {
11134 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11135 if (peer && peer != tp->pdev)
11136 break;
11137 pci_dev_put(peer);
11138 }
11139 /* 5704 can be configured in single-port mode, set peer to
11140 * tp->pdev in that case.
11141 */
11142 if (!peer) {
11143 peer = tp->pdev;
11144 return peer;
11145 }
11146
11147 /*
11148 * We don't need to keep the refcount elevated; there's no way
11149 * to remove one half of this device without removing the other
11150 */
11151 pci_dev_put(peer);
11152
11153 return peer;
11154 }
11155
11156 static void __devinit tg3_init_coal(struct tg3 *tp)
11157 {
11158 struct ethtool_coalesce *ec = &tp->coal;
11159
11160 memset(ec, 0, sizeof(*ec));
11161 ec->cmd = ETHTOOL_GCOALESCE;
11162 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11163 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11164 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11165 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11166 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11167 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11168 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11169 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11170 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11171
11172 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11173 HOSTCC_MODE_CLRTICK_TXBD)) {
11174 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11175 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11176 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11177 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11178 }
11179
11180 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11181 ec->rx_coalesce_usecs_irq = 0;
11182 ec->tx_coalesce_usecs_irq = 0;
11183 ec->stats_block_coalesce_usecs = 0;
11184 }
11185 }
11186
11187 static int __devinit tg3_init_one(struct pci_dev *pdev,
11188 const struct pci_device_id *ent)
11189 {
11190 static int tg3_version_printed = 0;
11191 unsigned long tg3reg_base, tg3reg_len;
11192 struct net_device *dev;
11193 struct tg3 *tp;
11194 int i, err, pm_cap;
11195 char str[40];
11196 u64 dma_mask, persist_dma_mask;
11197
11198 if (tg3_version_printed++ == 0)
11199 printk(KERN_INFO "%s", version);
11200
11201 err = pci_enable_device(pdev);
11202 if (err) {
11203 printk(KERN_ERR PFX "Cannot enable PCI device, "
11204 "aborting.\n");
11205 return err;
11206 }
11207
11208 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11209 printk(KERN_ERR PFX "Cannot find proper PCI device "
11210 "base address, aborting.\n");
11211 err = -ENODEV;
11212 goto err_out_disable_pdev;
11213 }
11214
11215 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11216 if (err) {
11217 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11218 "aborting.\n");
11219 goto err_out_disable_pdev;
11220 }
11221
11222 pci_set_master(pdev);
11223
11224 /* Find power-management capability. */
11225 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11226 if (pm_cap == 0) {
11227 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11228 "aborting.\n");
11229 err = -EIO;
11230 goto err_out_free_res;
11231 }
11232
11233 tg3reg_base = pci_resource_start(pdev, 0);
11234 tg3reg_len = pci_resource_len(pdev, 0);
11235
11236 dev = alloc_etherdev(sizeof(*tp));
11237 if (!dev) {
11238 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11239 err = -ENOMEM;
11240 goto err_out_free_res;
11241 }
11242
11243 SET_MODULE_OWNER(dev);
11244 SET_NETDEV_DEV(dev, &pdev->dev);
11245
11246 dev->features |= NETIF_F_LLTX;
11247 #if TG3_VLAN_TAG_USED
11248 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11249 dev->vlan_rx_register = tg3_vlan_rx_register;
11250 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11251 #endif
11252
11253 tp = netdev_priv(dev);
11254 tp->pdev = pdev;
11255 tp->dev = dev;
11256 tp->pm_cap = pm_cap;
11257 tp->mac_mode = TG3_DEF_MAC_MODE;
11258 tp->rx_mode = TG3_DEF_RX_MODE;
11259 tp->tx_mode = TG3_DEF_TX_MODE;
11260 tp->mi_mode = MAC_MI_MODE_BASE;
11261 if (tg3_debug > 0)
11262 tp->msg_enable = tg3_debug;
11263 else
11264 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11265
11266 /* The word/byte swap controls here control register access byte
11267 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11268 * setting below.
11269 */
11270 tp->misc_host_ctrl =
11271 MISC_HOST_CTRL_MASK_PCI_INT |
11272 MISC_HOST_CTRL_WORD_SWAP |
11273 MISC_HOST_CTRL_INDIR_ACCESS |
11274 MISC_HOST_CTRL_PCISTATE_RW;
11275
11276 /* The NONFRM (non-frame) byte/word swap controls take effect
11277 * on descriptor entries, anything which isn't packet data.
11278 *
11279 * The StrongARM chips on the board (one for tx, one for rx)
11280 * are running in big-endian mode.
11281 */
11282 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11283 GRC_MODE_WSWAP_NONFRM_DATA);
11284 #ifdef __BIG_ENDIAN
11285 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11286 #endif
11287 spin_lock_init(&tp->lock);
11288 spin_lock_init(&tp->tx_lock);
11289 spin_lock_init(&tp->indirect_lock);
11290 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
11291
11292 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11293 if (tp->regs == 0UL) {
11294 printk(KERN_ERR PFX "Cannot map device registers, "
11295 "aborting.\n");
11296 err = -ENOMEM;
11297 goto err_out_free_dev;
11298 }
11299
11300 tg3_init_link_config(tp);
11301
11302 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11303 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11304 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11305
11306 dev->open = tg3_open;
11307 dev->stop = tg3_close;
11308 dev->get_stats = tg3_get_stats;
11309 dev->set_multicast_list = tg3_set_rx_mode;
11310 dev->set_mac_address = tg3_set_mac_addr;
11311 dev->do_ioctl = tg3_ioctl;
11312 dev->tx_timeout = tg3_tx_timeout;
11313 dev->poll = tg3_poll;
11314 dev->ethtool_ops = &tg3_ethtool_ops;
11315 dev->weight = 64;
11316 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11317 dev->change_mtu = tg3_change_mtu;
11318 dev->irq = pdev->irq;
11319 #ifdef CONFIG_NET_POLL_CONTROLLER
11320 dev->poll_controller = tg3_poll_controller;
11321 #endif
11322
11323 err = tg3_get_invariants(tp);
11324 if (err) {
11325 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11326 "aborting.\n");
11327 goto err_out_iounmap;
11328 }
11329
11330 /* The EPB bridge inside 5714, 5715, and 5780 and any
11331 * device behind the EPB cannot support DMA addresses > 40-bit.
11332 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11333 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11334 * do DMA address check in tg3_start_xmit().
11335 */
11336 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11337 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11338 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11339 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11340 #ifdef CONFIG_HIGHMEM
11341 dma_mask = DMA_64BIT_MASK;
11342 #endif
11343 } else
11344 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11345
11346 /* Configure DMA attributes. */
11347 if (dma_mask > DMA_32BIT_MASK) {
11348 err = pci_set_dma_mask(pdev, dma_mask);
11349 if (!err) {
11350 dev->features |= NETIF_F_HIGHDMA;
11351 err = pci_set_consistent_dma_mask(pdev,
11352 persist_dma_mask);
11353 if (err < 0) {
11354 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11355 "DMA for consistent allocations\n");
11356 goto err_out_iounmap;
11357 }
11358 }
11359 }
11360 if (err || dma_mask == DMA_32BIT_MASK) {
11361 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11362 if (err) {
11363 printk(KERN_ERR PFX "No usable DMA configuration, "
11364 "aborting.\n");
11365 goto err_out_iounmap;
11366 }
11367 }
11368
11369 tg3_init_bufmgr_config(tp);
11370
11371 #if TG3_TSO_SUPPORT != 0
11372 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11373 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11374 }
11375 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11377 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11378 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11379 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11380 } else {
11381 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11382 }
11383
11384 /* TSO is on by default on chips that support hardware TSO.
11385 * Firmware TSO on older chips gives lower performance, so it
11386 * is off by default, but can be enabled using ethtool.
11387 */
11388 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
11389 dev->features |= NETIF_F_TSO;
11390
11391 #endif
11392
11393 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11394 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11395 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11396 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11397 tp->rx_pending = 63;
11398 }
11399
11400 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11401 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11402 tp->pdev_peer = tg3_find_peer(tp);
11403
11404 err = tg3_get_device_address(tp);
11405 if (err) {
11406 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11407 "aborting.\n");
11408 goto err_out_iounmap;
11409 }
11410
11411 /*
11412 * Reset chip in case UNDI or EFI driver did not shutdown
11413 * DMA self test will enable WDMAC and we'll see (spurious)
11414 * pending DMA on the PCI bus at that point.
11415 */
11416 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11417 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11418 pci_save_state(tp->pdev);
11419 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11420 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11421 }
11422
11423 err = tg3_test_dma(tp);
11424 if (err) {
11425 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11426 goto err_out_iounmap;
11427 }
11428
11429 /* Tigon3 can do ipv4 only... and some chips have buggy
11430 * checksumming.
11431 */
11432 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11433 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11434 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11435 dev->features |= NETIF_F_HW_CSUM;
11436 else
11437 dev->features |= NETIF_F_IP_CSUM;
11438 dev->features |= NETIF_F_SG;
11439 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11440 } else
11441 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11442
11443 /* flow control autonegotiation is default behavior */
11444 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11445
11446 tg3_init_coal(tp);
11447
11448 /* Now that we have fully setup the chip, save away a snapshot
11449 * of the PCI config space. We need to restore this after
11450 * GRC_MISC_CFG core clock resets and some resume events.
11451 */
11452 pci_save_state(tp->pdev);
11453
11454 err = register_netdev(dev);
11455 if (err) {
11456 printk(KERN_ERR PFX "Cannot register net device, "
11457 "aborting.\n");
11458 goto err_out_iounmap;
11459 }
11460
11461 pci_set_drvdata(pdev, dev);
11462
11463 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
11464 dev->name,
11465 tp->board_part_number,
11466 tp->pci_chip_rev_id,
11467 tg3_phy_string(tp),
11468 tg3_bus_string(tp, str),
11469 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
11470
11471 for (i = 0; i < 6; i++)
11472 printk("%2.2x%c", dev->dev_addr[i],
11473 i == 5 ? '\n' : ':');
11474
11475 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11476 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11477 "TSOcap[%d] \n",
11478 dev->name,
11479 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11480 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11481 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11482 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11483 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11484 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11485 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11486 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11487 dev->name, tp->dma_rwctrl,
11488 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11489 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11490
11491 netif_carrier_off(tp->dev);
11492
11493 return 0;
11494
11495 err_out_iounmap:
11496 if (tp->regs) {
11497 iounmap(tp->regs);
11498 tp->regs = NULL;
11499 }
11500
11501 err_out_free_dev:
11502 free_netdev(dev);
11503
11504 err_out_free_res:
11505 pci_release_regions(pdev);
11506
11507 err_out_disable_pdev:
11508 pci_disable_device(pdev);
11509 pci_set_drvdata(pdev, NULL);
11510 return err;
11511 }
11512
11513 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11514 {
11515 struct net_device *dev = pci_get_drvdata(pdev);
11516
11517 if (dev) {
11518 struct tg3 *tp = netdev_priv(dev);
11519
11520 flush_scheduled_work();
11521 unregister_netdev(dev);
11522 if (tp->regs) {
11523 iounmap(tp->regs);
11524 tp->regs = NULL;
11525 }
11526 free_netdev(dev);
11527 pci_release_regions(pdev);
11528 pci_disable_device(pdev);
11529 pci_set_drvdata(pdev, NULL);
11530 }
11531 }
11532
11533 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11534 {
11535 struct net_device *dev = pci_get_drvdata(pdev);
11536 struct tg3 *tp = netdev_priv(dev);
11537 int err;
11538
11539 if (!netif_running(dev))
11540 return 0;
11541
11542 flush_scheduled_work();
11543 tg3_netif_stop(tp);
11544
11545 del_timer_sync(&tp->timer);
11546
11547 tg3_full_lock(tp, 1);
11548 tg3_disable_ints(tp);
11549 tg3_full_unlock(tp);
11550
11551 netif_device_detach(dev);
11552
11553 tg3_full_lock(tp, 0);
11554 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11555 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
11556 tg3_full_unlock(tp);
11557
11558 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
11559 if (err) {
11560 tg3_full_lock(tp, 0);
11561
11562 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11563 tg3_init_hw(tp, 1);
11564
11565 tp->timer.expires = jiffies + tp->timer_offset;
11566 add_timer(&tp->timer);
11567
11568 netif_device_attach(dev);
11569 tg3_netif_start(tp);
11570
11571 tg3_full_unlock(tp);
11572 }
11573
11574 return err;
11575 }
11576
11577 static int tg3_resume(struct pci_dev *pdev)
11578 {
11579 struct net_device *dev = pci_get_drvdata(pdev);
11580 struct tg3 *tp = netdev_priv(dev);
11581 int err;
11582
11583 if (!netif_running(dev))
11584 return 0;
11585
11586 pci_restore_state(tp->pdev);
11587
11588 err = tg3_set_power_state(tp, PCI_D0);
11589 if (err)
11590 return err;
11591
11592 netif_device_attach(dev);
11593
11594 tg3_full_lock(tp, 0);
11595
11596 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11597 tg3_init_hw(tp, 1);
11598
11599 tp->timer.expires = jiffies + tp->timer_offset;
11600 add_timer(&tp->timer);
11601
11602 tg3_netif_start(tp);
11603
11604 tg3_full_unlock(tp);
11605
11606 return 0;
11607 }
11608
11609 static struct pci_driver tg3_driver = {
11610 .name = DRV_MODULE_NAME,
11611 .id_table = tg3_pci_tbl,
11612 .probe = tg3_init_one,
11613 .remove = __devexit_p(tg3_remove_one),
11614 .suspend = tg3_suspend,
11615 .resume = tg3_resume
11616 };
11617
11618 static int __init tg3_init(void)
11619 {
11620 return pci_module_init(&tg3_driver);
11621 }
11622
11623 static void __exit tg3_cleanup(void)
11624 {
11625 pci_unregister_driver(&tg3_driver);
11626 }
11627
11628 module_init(tg3_init);
11629 module_exit(tg3_cleanup);
Linux with added FPC-III support