drivers/net/wan/pc300.h

   1 /*
   2  * pc300.h      Cyclades-PC300(tm) Kernel API Definitions.
   3  *
   4  * Author:      Ivan Passos <ivan@cyclades.com>
   5  *
   6  * Copyright:   (c) 1999-2002 Cyclades Corp.
   7  *
   8  *      This program is free software; you can redistribute it and/or
   9  *      modify it under the terms of the GNU General Public License
  10  *      as published by the Free Software Foundation; either version
  11  *      2 of the License, or (at your option) any later version.
  12  *
  13  * $Log: pc300.h,v $
  14  * Revision 3.12  2002/03/07 14:17:09  henrique
  15  * License data fixed
  16  *
  17  * Revision 3.11  2002/01/28 21:09:39  daniela
  18  * Included ';' after pc300hw.bus.
  19  *
  20  * Revision 3.10  2002/01/17 17:58:52  ivan
  21  * Support for PC300-TE/M (PMC).
  22  *
  23  * Revision 3.9  2001/09/28 13:30:53  daniela
  24  * Renamed dma_start routine to rx_dma_start.
  25  *
  26  * Revision 3.8  2001/09/24 13:03:45  daniela
  27  * Fixed BOF interrupt treatment. Created dma_start routine.
  28  *
  29  * Revision 3.7  2001/08/10 17:19:58  daniela
  30  * Fixed IOCTLs defines.
  31  *
  32  * Revision 3.6  2001/07/18 19:24:42  daniela
  33  * Included kernel version.
  34  *
  35  * Revision 3.5  2001/07/05 18:38:08  daniela
  36  * DMA transmission bug fix.
  37  *
  38  * Revision 3.4  2001/06/26 17:10:40  daniela
  39  * New configuration parameters (line code, CRC calculation and clock).
  40  *
  41  * Revision 3.3  2001/06/22 13:13:02  regina
  42  * MLPPP implementation
  43  *
  44  * Revision 3.2  2001/06/18 17:56:09  daniela
  45  * Increased DEF_MTU and TX_QUEUE_LEN.
  46  *
  47  * Revision 3.1  2001/06/15 12:41:10  regina
  48  * upping major version number
  49  *
  50  * Revision 1.1.1.1  2001/06/13 20:25:06  daniela
  51  * PC300 initial CVS version (3.4.0-pre1)
  52  *
  53  * Revision 2.3 2001/03/05 daniela
  54  * Created struct pc300conf, to provide the hardware information to pc300util.
  55  * Inclusion of 'alloc_ramsize' field on structure 'pc300hw'.
  56  *
  57  * Revision 2.2 2000/12/22 daniela
  58  * Structures and defines to support pc300util: statistics, status,
  59  * loopback tests, trace.
  60  *
  61  * Revision 2.1 2000/09/28 ivan
  62  * Inclusion of 'iophys' and 'iosize' fields on structure 'pc300hw', to
  63  * allow release of I/O region at module unload.
  64  * Changed location of include files.
  65  *
  66  * Revision 2.0 2000/03/27 ivan
  67  * Added support for the PC300/TE cards.
  68  *
  69  * Revision 1.1 2000/01/31 ivan
  70  * Replaced 'pc300[drv|sca].h' former PC300 driver include files.
  71  *
  72  * Revision 1.0 1999/12/16 ivan
  73  * First official release.
  74  * Inclusion of 'nchan' field on structure 'pc300hw', to allow variable
  75  * number of ports per card.
  76  * Inclusion of 'if_ptr' field on structure 'pc300dev'.
  77  *
  78  * Revision 0.6 1999/11/17 ivan
  79  * Changed X.25-specific function names to comply with adopted convention.
  80  *
  81  * Revision 0.5 1999/11/16 Daniela Squassoni
  82  * X.25 support.
  83  *
  84  * Revision 0.4 1999/11/15 ivan
  85  * Inclusion of 'clock' field on structure 'pc300hw'.
  86  *
  87  * Revision 0.3 1999/11/10 ivan
  88  * IOCTL name changing.
  89  * Inclusion of driver function prototypes.
  90  *
  91  * Revision 0.2 1999/11/03 ivan
  92  * Inclusion of 'tx_skb' and union 'ifu' on structure 'pc300dev'.
  93  *
  94  * Revision 0.1 1999/01/15 ivan
  95  * Initial version.
  96  *
  97  */
  98
  99 #ifndef _PC300_H
 100 #define _PC300_H
 101
 102 #include <linux/hdlc.h>
 103 #include "hd64572.h"
 104 #include "pc300-falc-lh.h"
 105
 106 #ifndef CY_TYPES
 107 #define CY_TYPES
 108 typedef __u64   ucdouble;       /* 64 bits, unsigned */
 109 typedef __u32   uclong;         /* 32 bits, unsigned */
 110 typedef __u16   ucshort;        /* 16 bits, unsigned */
 111 typedef __u8    ucchar;         /* 8 bits, unsigned */
 112 #endif /* CY_TYPES */
 113
 114 #define PC300_PROTO_MLPPP 1
 115
 116 #define PC300_KERNEL    "2.4.x" /* Kernel supported by this driver */
 117
 118 #define PC300_DEVNAME   "hdlc"  /* Dev. name base (for hdlc0, hdlc1, etc.) */
 119 #define PC300_MAXINDEX  100     /* Max dev. name index (the '0' in hdlc0) */
 120
 121 #define PC300_MAXCARDS  4       /* Max number of cards per system */
 122 #define PC300_MAXCHAN   2       /* Number of channels per card */
 123
 124 #define PC300_PLX_WIN   0x80    /* PLX control window size (128b) */
 125 #define PC300_RAMSIZE   0x40000 /* RAM window size (256Kb) */
 126 #define PC300_SCASIZE   0x400   /* SCA window size (1Kb) */
 127 #define PC300_FALCSIZE  0x400   /* FALC window size (1Kb) */
 128
 129 #define PC300_OSC_CLOCK 24576000
 130 #define PC300_PCI_CLOCK 33000000
 131
 132 #define BD_DEF_LEN      0x0800  /* DMA buffer length (2KB) */
 133 #define DMA_TX_MEMSZ    0x8000  /* Total DMA Tx memory size (32KB/ch) */
 134 #define DMA_RX_MEMSZ    0x10000 /* Total DMA Rx memory size (64KB/ch) */
 135
 136 #define N_DMA_TX_BUF    (DMA_TX_MEMSZ / BD_DEF_LEN)     /* DMA Tx buffers */
 137 #define N_DMA_RX_BUF    (DMA_RX_MEMSZ / BD_DEF_LEN)     /* DMA Rx buffers */
 138
 139 /* DMA Buffer Offsets */
 140 #define DMA_TX_BASE     ((N_DMA_TX_BUF + N_DMA_RX_BUF) *        \
 141                          PC300_MAXCHAN * sizeof(pcsca_bd_t))
 142 #define DMA_RX_BASE     (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ)
 143
 144 /* DMA Descriptor Offsets */
 145 #define DMA_TX_BD_BASE  0x0000
 146 #define DMA_RX_BD_BASE  (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \
 147                                 BD_DEF_LEN) * sizeof(pcsca_bd_t)))
 148
 149 /* DMA Descriptor Macros */
 150 #define TX_BD_ADDR(chan, n)     (DMA_TX_BD_BASE + \
 151                                  ((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t))
 152 #define RX_BD_ADDR(chan, n)     (DMA_RX_BD_BASE + \
 153                                  ((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t))
 154
 155 /* Macro to access the FALC registers (TE only) */
 156 #define F_REG(reg, chan)        (0x200*(chan) + ((reg)<<2))
 157
 158 /***************************************
 159  * Memory access functions/macros      *
 160  * (required to support Alpha systems) *
 161  ***************************************/
 162 #ifdef __KERNEL__
 163 #define cpc_writeb(port,val)    {writeb((ucchar)(val),(port)); mb();}
 164 #define cpc_writew(port,val)    {writew((ushort)(val),(port)); mb();}
 165 #define cpc_writel(port,val)    {writel((uclong)(val),(port)); mb();}
 166
 167 #define cpc_readb(port)         readb(port)
 168 #define cpc_readw(port)         readw(port)
 169 #define cpc_readl(port)         readl(port)
 170
 171 #else /* __KERNEL__ */
 172 #define cpc_writeb(port,val)    (*(volatile ucchar *)(port) = (ucchar)(val))
 173 #define cpc_writew(port,val)    (*(volatile ucshort *)(port) = (ucshort)(val))
 174 #define cpc_writel(port,val)    (*(volatile uclong *)(port) = (uclong)(val))
 175
 176 #define cpc_readb(port)         (*(volatile ucchar *)(port))
 177 #define cpc_readw(port)         (*(volatile ucshort *)(port))
 178 #define cpc_readl(port)         (*(volatile uclong *)(port))
 179
 180 #endif /* __KERNEL__ */
 181
 182 /****** Data Structures *****************************************************/
 183
 184 /*
 185  *      RUNTIME_9050 - PLX PCI9050-1 local configuration and shared runtime
 186  *      registers. This structure can be used to access the 9050 registers
 187  *      (memory mapped).
 188  */
 189 struct RUNTIME_9050 {
 190         uclong  loc_addr_range[4];      /* 00-0Ch : Local Address Ranges */
 191         uclong  loc_rom_range;          /* 10h : Local ROM Range */
 192         uclong  loc_addr_base[4];       /* 14-20h : Local Address Base Addrs */
 193         uclong  loc_rom_base;           /* 24h : Local ROM Base */
 194         uclong  loc_bus_descr[4];       /* 28-34h : Local Bus Descriptors */
 195         uclong  rom_bus_descr;          /* 38h : ROM Bus Descriptor */
 196         uclong  cs_base[4];             /* 3C-48h : Chip Select Base Addrs */
 197         uclong  intr_ctrl_stat;         /* 4Ch : Interrupt Control/Status */
 198         uclong  init_ctrl;              /* 50h : EEPROM ctrl, Init Ctrl, etc */
 199 };
 200
 201 #define PLX_9050_LINT1_ENABLE   0x01
 202 #define PLX_9050_LINT1_POL      0x02
 203 #define PLX_9050_LINT1_STATUS   0x04
 204 #define PLX_9050_LINT2_ENABLE   0x08
 205 #define PLX_9050_LINT2_POL      0x10
 206 #define PLX_9050_LINT2_STATUS   0x20
 207 #define PLX_9050_INTR_ENABLE    0x40
 208 #define PLX_9050_SW_INTR        0x80
 209
 210 /* Masks to access the init_ctrl PLX register */
 211 #define PC300_CLKSEL_MASK               (0x00000004UL)
 212 #define PC300_CHMEDIA_MASK(chan)        (0x00000020UL<<(chan*3))
 213 #define PC300_CTYPE_MASK                (0x00000800UL)
 214
 215 /* CPLD Registers (base addr = falcbase, TE only) */
 216 /* CPLD v. 0 */
 217 #define CPLD_REG1       0x140   /* Chip resets, DCD/CTS status */
 218 #define CPLD_REG2       0x144   /* Clock enable , LED control */
 219 /* CPLD v. 2 or higher */
 220 #define CPLD_V2_REG1    0x100   /* Chip resets, DCD/CTS status */
 221 #define CPLD_V2_REG2    0x104   /* Clock enable , LED control */
 222 #define CPLD_ID_REG     0x108   /* CPLD version */
 223
 224 /* CPLD Register bit description: for the FALC bits, they should always be
 225    set based on the channel (use (bit<<(2*ch)) to access the correct bit for
 226    that channel) */
 227 #define CPLD_REG1_FALC_RESET    0x01
 228 #define CPLD_REG1_SCA_RESET     0x02
 229 #define CPLD_REG1_GLOBAL_CLK    0x08
 230 #define CPLD_REG1_FALC_DCD      0x10
 231 #define CPLD_REG1_FALC_CTS      0x20
 232
 233 #define CPLD_REG2_FALC_TX_CLK   0x01
 234 #define CPLD_REG2_FALC_RX_CLK   0x02
 235 #define CPLD_REG2_FALC_LED1     0x10
 236 #define CPLD_REG2_FALC_LED2     0x20
 237
 238 /* Structure with FALC-related fields (TE only) */
 239 #define PC300_FALC_MAXLOOP      0x0000ffff      /* for falc_issue_cmd() */
 240
 241 typedef struct falc {
 242         ucchar sync;            /* If true FALC is synchronized */
 243         ucchar active;          /* if TRUE then already active */
 244         ucchar loop_active;     /* if TRUE a line loopback UP was received */
 245         ucchar loop_gen;        /* if TRUE a line loopback UP was issued */
 246
 247         ucchar num_channels;
 248         ucchar offset;          /* 1 for T1, 0 for E1 */
 249         ucchar full_bandwidth;
 250
 251         ucchar xmb_cause;
 252         ucchar multiframe_mode;
 253
 254         /* Statistics */
 255         ucshort pden;   /* Pulse Density violation count */
 256         ucshort los;    /* Loss of Signal count */
 257         ucshort losr;   /* Loss of Signal recovery count */
 258         ucshort lfa;    /* Loss of frame alignment count */
 259         ucshort farec;  /* Frame Alignment Recovery count */
 260         ucshort lmfa;   /* Loss of multiframe alignment count */
 261         ucshort ais;    /* Remote Alarm indication Signal count */
 262         ucshort sec;    /* One-second timer */
 263         ucshort es;     /* Errored second */
 264         ucshort rai;    /* remote alarm received */
 265         ucshort bec;
 266         ucshort fec;
 267         ucshort cvc;
 268         ucshort cec;
 269         ucshort ebc;
 270
 271         /* Status */
 272         ucchar red_alarm;
 273         ucchar blue_alarm;
 274         ucchar loss_fa;
 275         ucchar yellow_alarm;
 276         ucchar loss_mfa;
 277         ucchar prbs;
 278 } falc_t;
 279
 280 typedef struct falc_status {
 281         ucchar sync;  /* If true FALC is synchronized */
 282         ucchar red_alarm;
 283         ucchar blue_alarm;
 284         ucchar loss_fa;
 285         ucchar yellow_alarm;
 286         ucchar loss_mfa;
 287         ucchar prbs;
 288 } falc_status_t;
 289
 290 typedef struct rsv_x21_status {
 291         ucchar dcd;
 292         ucchar dsr;
 293         ucchar cts;
 294         ucchar rts;
 295         ucchar dtr;
 296 } rsv_x21_status_t;
 297
 298 typedef struct pc300stats {
 299         int hw_type;
 300         uclong line_on;
 301         uclong line_off;
 302         struct net_device_stats gen_stats;
 303         falc_t te_stats;
 304 } pc300stats_t;
 305
 306 typedef struct pc300status {
 307         int hw_type;
 308         rsv_x21_status_t gen_status;
 309         falc_status_t te_status;
 310 } pc300status_t;
 311
 312 typedef struct pc300loopback {
 313         char loop_type;
 314         char loop_on;
 315 } pc300loopback_t;
 316
 317 typedef struct pc300patterntst {
 318         char patrntst_on;       /* 0 - off; 1 - on; 2 - read num_errors */
 319         ucshort num_errors;
 320 } pc300patterntst_t;
 321
 322 typedef struct pc300dev {
 323         void *if_ptr;           /* General purpose pointer */
 324         struct pc300ch *chan;
 325         ucchar trace_on;
 326         uclong line_on;         /* DCD(X.21, RSV) / sync(TE) change counters */
 327         uclong line_off;
 328 #ifdef __KERNEL__
 329         char name[16];
 330         struct net_device *dev;
 331
 332         void *private;
 333         struct sk_buff *tx_skb;
 334         union { /* This union has all the protocol-specific structures */
 335                 struct ppp_device pppdev;
 336         }ifu;
 337 #ifdef CONFIG_PC300_MLPPP
 338         void *cpc_tty;  /* information to PC300 TTY driver */
 339 #endif
 340 #endif /* __KERNEL__ */
 341 }pc300dev_t;
 342
 343 typedef struct pc300hw {
 344         int type;               /* RSV, X21, etc. */
 345         int bus;                /* Bus (PCI, PMC, etc.) */
 346         int nchan;              /* number of channels */
 347         int irq;                /* interrupt request level */
 348         uclong clock;           /* Board clock */
 349         ucchar cpld_id;         /* CPLD ID (TE only) */
 350         ucshort cpld_reg1;      /* CPLD reg 1 (TE only) */
 351         ucshort cpld_reg2;      /* CPLD reg 2 (TE only) */
 352         ucshort gpioc_reg;      /* PLX GPIOC reg */
 353         ucshort intctl_reg;     /* PLX Int Ctrl/Status reg */
 354         uclong iophys;          /* PLX registers I/O base */
 355         uclong iosize;          /* PLX registers I/O size */
 356         uclong plxphys;         /* PLX registers MMIO base (physical) */
 357         void __iomem * plxbase; /* PLX registers MMIO base (virtual) */
 358         uclong plxsize;         /* PLX registers MMIO size */
 359         uclong scaphys;         /* SCA registers MMIO base (physical) */
 360         void __iomem * scabase; /* SCA registers MMIO base (virtual) */
 361         uclong scasize;         /* SCA registers MMIO size */
 362         uclong ramphys;         /* On-board RAM MMIO base (physical) */
 363         void __iomem * rambase; /* On-board RAM MMIO base (virtual) */
 364         uclong alloc_ramsize;   /* RAM MMIO size allocated by the PCI bridge */
 365         uclong ramsize;         /* On-board RAM MMIO size */
 366         uclong falcphys;        /* FALC registers MMIO base (physical) */
 367         void __iomem * falcbase;/* FALC registers MMIO base (virtual) */
 368         uclong falcsize;        /* FALC registers MMIO size */
 369 } pc300hw_t;
 370
 371 typedef struct pc300chconf {
 372         sync_serial_settings    phys_settings;  /* Clock type/rate (in bps),
 373                                                    loopback mode */
 374         raw_hdlc_proto          proto_settings; /* Encoding, parity (CRC) */
 375         uclong media;           /* HW media (RS232, V.35, etc.) */
 376         uclong proto;           /* Protocol (PPP, X.25, etc.) */
 377         ucchar monitor;         /* Monitor mode (0 = off, !0 = on) */
 378
 379         /* TE-specific parameters */
 380         ucchar lcode;           /* Line Code (AMI, B8ZS, etc.) */
 381         ucchar fr_mode;         /* Frame Mode (ESF, D4, etc.) */
 382         ucchar lbo;             /* Line Build Out */
 383         ucchar rx_sens;         /* Rx Sensitivity (long- or short-haul) */
 384         uclong tslot_bitmap;    /* bit[i]=1  =>  timeslot _i_ is active */
 385 } pc300chconf_t;
 386
 387 typedef struct pc300ch {
 388         struct pc300 *card;
 389         int channel;
 390         pc300dev_t d;
 391         pc300chconf_t conf;
 392         ucchar tx_first_bd;     /* First TX DMA block descr. w/ data */
 393         ucchar tx_next_bd;      /* Next free TX DMA block descriptor */
 394         ucchar rx_first_bd;     /* First free RX DMA block descriptor */
 395         ucchar rx_last_bd;      /* Last free RX DMA block descriptor */
 396         ucchar nfree_tx_bd;     /* Number of free TX DMA block descriptors */
 397         falc_t falc;            /* FALC structure (TE only) */
 398 } pc300ch_t;
 399
 400 typedef struct pc300 {
 401         pc300hw_t hw;                   /* hardware config. */
 402         pc300ch_t chan[PC300_MAXCHAN];
 403 #ifdef __KERNEL__
 404         spinlock_t card_lock;
 405 #endif /* __KERNEL__ */
 406 } pc300_t;
 407
 408 typedef struct pc300conf {
 409         pc300hw_t hw;
 410         pc300chconf_t conf;
 411 } pc300conf_t;
 412
 413 /* DEV ioctl() commands */
 414 #define N_SPPP_IOCTLS   2
 415
 416 enum pc300_ioctl_cmds {
 417         SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS),
 418         SIOCGPC300CONF,
 419         SIOCSPC300CONF,
 420         SIOCGPC300STATUS,
 421         SIOCGPC300FALCSTATUS,
 422         SIOCGPC300UTILSTATS,
 423         SIOCGPC300UTILSTATUS,
 424         SIOCSPC300TRACE,
 425         SIOCSPC300LOOPBACK,
 426         SIOCSPC300PATTERNTEST,
 427 };
 428
 429 /* Loopback types - PC300/TE boards */
 430 enum pc300_loopback_cmds {
 431         PC300LOCLOOP = 1,
 432         PC300REMLOOP,
 433         PC300PAYLOADLOOP,
 434         PC300GENLOOPUP,
 435         PC300GENLOOPDOWN,
 436 };
 437
 438 /* Control Constant Definitions */
 439 #define PC300_RSV       0x01
 440 #define PC300_X21       0x02
 441 #define PC300_TE        0x03
 442
 443 #define PC300_PCI       0x00
 444 #define PC300_PMC       0x01
 445
 446 #define PC300_LC_AMI    0x01
 447 #define PC300_LC_B8ZS   0x02
 448 #define PC300_LC_NRZ    0x03
 449 #define PC300_LC_HDB3   0x04
 450
 451 /* Framing (T1) */
 452 #define PC300_FR_ESF            0x01
 453 #define PC300_FR_D4             0x02
 454 #define PC300_FR_ESF_JAPAN      0x03
 455
 456 /* Framing (E1) */
 457 #define PC300_FR_MF_CRC4        0x04
 458 #define PC300_FR_MF_NON_CRC4    0x05
 459 #define PC300_FR_UNFRAMED       0x06
 460
 461 #define PC300_LBO_0_DB          0x00
 462 #define PC300_LBO_7_5_DB        0x01
 463 #define PC300_LBO_15_DB         0x02
 464 #define PC300_LBO_22_5_DB       0x03
 465
 466 #define PC300_RX_SENS_SH        0x01
 467 #define PC300_RX_SENS_LH        0x02
 468
 469 #define PC300_TX_TIMEOUT        (2*HZ)
 470 #define PC300_TX_QUEUE_LEN      100
 471 #define PC300_DEF_MTU           1600
 472
 473 #ifdef __KERNEL__
 474 /* Function Prototypes */
 475 void tx_dma_start(pc300_t *, int);
 476 int cpc_open(struct net_device *dev);
 477 int cpc_set_media(hdlc_device *, int);
 478 #endif /* __KERNEL__ */
 479
 480 #endif  /* _PC300_H */
 481