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Linux 2.6.17.7
[linux/fpc-iii.git] / drivers / scsi / sata_mv.c
blobf16f92a6ec0fe468da2c87363227015e0f27a061
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37 #include <asm/io.h>
38
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.7"
41
42 enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
54 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
55 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
56 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
57 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
58
59 MV_SATAHC0_REG_BASE = 0x20000,
60 MV_FLASH_CTL = 0x1046c,
61 MV_GPIO_PORT_CTL = 0x104f0,
62 MV_RESET_CFG = 0x180d8,
63
64 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
65 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
66 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
67 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
68
69 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
70
71 MV_MAX_Q_DEPTH = 32,
72 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
73
74 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
75 * CRPB needs alignment on a 256B boundary. Size == 256B
76 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
77 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
78 */
79 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
80 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
81 MV_MAX_SG_CT = 176,
82 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
83 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
84
85 MV_PORTS_PER_HC = 4,
86 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
87 MV_PORT_HC_SHIFT = 2,
88 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
89 MV_PORT_MASK = 3,
90
91 /* Host Flags */
92 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
93 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
94 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
95 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
96 ATA_FLAG_NO_ATAPI),
97 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
98
99 CRQB_FLAG_READ = (1 << 0),
100 CRQB_TAG_SHIFT = 1,
101 CRQB_CMD_ADDR_SHIFT = 8,
102 CRQB_CMD_CS = (0x2 << 11),
103 CRQB_CMD_LAST = (1 << 15),
104
105 CRPB_FLAG_STATUS_SHIFT = 8,
106
107 EPRD_FLAG_END_OF_TBL = (1 << 31),
108
109 /* PCI interface registers */
110
111 PCI_COMMAND_OFS = 0xc00,
112
113 PCI_MAIN_CMD_STS_OFS = 0xd30,
114 STOP_PCI_MASTER = (1 << 2),
115 PCI_MASTER_EMPTY = (1 << 3),
116 GLOB_SFT_RST = (1 << 4),
117
118 MV_PCI_MODE = 0xd00,
119 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
120 MV_PCI_DISC_TIMER = 0xd04,
121 MV_PCI_MSI_TRIGGER = 0xc38,
122 MV_PCI_SERR_MASK = 0xc28,
123 MV_PCI_XBAR_TMOUT = 0x1d04,
124 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
125 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
126 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
127 MV_PCI_ERR_COMMAND = 0x1d50,
128
129 PCI_IRQ_CAUSE_OFS = 0x1d58,
130 PCI_IRQ_MASK_OFS = 0x1d5c,
131 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
132
133 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
134 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
135 PORT0_ERR = (1 << 0), /* shift by port # */
136 PORT0_DONE = (1 << 1), /* shift by port # */
137 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
138 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
139 PCI_ERR = (1 << 18),
140 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
141 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
142 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
143 GPIO_INT = (1 << 22),
144 SELF_INT = (1 << 23),
145 TWSI_INT = (1 << 24),
146 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
147 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
148 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
149 HC_MAIN_RSVD),
150
151 /* SATAHC registers */
152 HC_CFG_OFS = 0,
153
154 HC_IRQ_CAUSE_OFS = 0x14,
155 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
156 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
157 DEV_IRQ = (1 << 8), /* shift by port # */
158
159 /* Shadow block registers */
160 SHD_BLK_OFS = 0x100,
161 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
162
163 /* SATA registers */
164 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
165 SATA_ACTIVE_OFS = 0x350,
166 PHY_MODE3 = 0x310,
167 PHY_MODE4 = 0x314,
168 PHY_MODE2 = 0x330,
169 MV5_PHY_MODE = 0x74,
170 MV5_LT_MODE = 0x30,
171 MV5_PHY_CTL = 0x0C,
172 SATA_INTERFACE_CTL = 0x050,
173
174 MV_M2_PREAMP_MASK = 0x7e0,
175
176 /* Port registers */
177 EDMA_CFG_OFS = 0,
178 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
179 EDMA_CFG_NCQ = (1 << 5),
180 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
181 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
182 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
183
184 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
185 EDMA_ERR_IRQ_MASK_OFS = 0xc,
186 EDMA_ERR_D_PAR = (1 << 0),
187 EDMA_ERR_PRD_PAR = (1 << 1),
188 EDMA_ERR_DEV = (1 << 2),
189 EDMA_ERR_DEV_DCON = (1 << 3),
190 EDMA_ERR_DEV_CON = (1 << 4),
191 EDMA_ERR_SERR = (1 << 5),
192 EDMA_ERR_SELF_DIS = (1 << 7),
193 EDMA_ERR_BIST_ASYNC = (1 << 8),
194 EDMA_ERR_CRBQ_PAR = (1 << 9),
195 EDMA_ERR_CRPB_PAR = (1 << 10),
196 EDMA_ERR_INTRL_PAR = (1 << 11),
197 EDMA_ERR_IORDY = (1 << 12),
198 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
199 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
200 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
201 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
202 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
203 EDMA_ERR_TRANS_PROTO = (1 << 31),
204 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
205 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
206 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
207 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
208 EDMA_ERR_LNK_DATA_RX |
209 EDMA_ERR_LNK_DATA_TX |
210 EDMA_ERR_TRANS_PROTO),
211
212 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
213 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
214
215 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
216 EDMA_REQ_Q_PTR_SHIFT = 5,
217
218 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
219 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
220 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
221 EDMA_RSP_Q_PTR_SHIFT = 3,
222
223 EDMA_CMD_OFS = 0x28,
224 EDMA_EN = (1 << 0),
225 EDMA_DS = (1 << 1),
226 ATA_RST = (1 << 2),
227
228 EDMA_IORDY_TMOUT = 0x34,
229 EDMA_ARB_CFG = 0x38,
230
231 /* Host private flags (hp_flags) */
232 MV_HP_FLAG_MSI = (1 << 0),
233 MV_HP_ERRATA_50XXB0 = (1 << 1),
234 MV_HP_ERRATA_50XXB2 = (1 << 2),
235 MV_HP_ERRATA_60X1B2 = (1 << 3),
236 MV_HP_ERRATA_60X1C0 = (1 << 4),
237 MV_HP_ERRATA_XX42A0 = (1 << 5),
238 MV_HP_50XX = (1 << 6),
239 MV_HP_GEN_IIE = (1 << 7),
240
241 /* Port private flags (pp_flags) */
242 MV_PP_FLAG_EDMA_EN = (1 << 0),
243 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
244 };
245
246 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
247 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
248 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
249 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
250 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
251
252 enum {
253 /* Our DMA boundary is determined by an ePRD being unable to handle
254 * anything larger than 64KB
255 */
256 MV_DMA_BOUNDARY = 0xffffU,
257
258 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
259
260 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
261 };
262
263 enum chip_type {
264 chip_504x,
265 chip_508x,
266 chip_5080,
267 chip_604x,
268 chip_608x,
269 chip_6042,
270 chip_7042,
271 };
272
273 /* Command ReQuest Block: 32B */
274 struct mv_crqb {
275 u32 sg_addr;
276 u32 sg_addr_hi;
277 u16 ctrl_flags;
278 u16 ata_cmd[11];
279 };
280
281 struct mv_crqb_iie {
282 u32 addr;
283 u32 addr_hi;
284 u32 flags;
285 u32 len;
286 u32 ata_cmd[4];
287 };
288
289 /* Command ResPonse Block: 8B */
290 struct mv_crpb {
291 u16 id;
292 u16 flags;
293 u32 tmstmp;
294 };
295
296 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
297 struct mv_sg {
298 u32 addr;
299 u32 flags_size;
300 u32 addr_hi;
301 u32 reserved;
302 };
303
304 struct mv_port_priv {
305 struct mv_crqb *crqb;
306 dma_addr_t crqb_dma;
307 struct mv_crpb *crpb;
308 dma_addr_t crpb_dma;
309 struct mv_sg *sg_tbl;
310 dma_addr_t sg_tbl_dma;
311 u32 pp_flags;
312 };
313
314 struct mv_port_signal {
315 u32 amps;
316 u32 pre;
317 };
318
319 struct mv_host_priv;
320 struct mv_hw_ops {
321 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
322 unsigned int port);
323 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
324 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
325 void __iomem *mmio);
326 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
327 unsigned int n_hc);
328 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
329 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
330 };
331
332 struct mv_host_priv {
333 u32 hp_flags;
334 struct mv_port_signal signal[8];
335 const struct mv_hw_ops *ops;
336 };
337
338 static void mv_irq_clear(struct ata_port *ap);
339 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
340 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
341 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
342 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
343 static void mv_phy_reset(struct ata_port *ap);
344 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
345 static void mv_host_stop(struct ata_host_set *host_set);
346 static int mv_port_start(struct ata_port *ap);
347 static void mv_port_stop(struct ata_port *ap);
348 static void mv_qc_prep(struct ata_queued_cmd *qc);
349 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
350 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
351 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
352 struct pt_regs *regs);
353 static void mv_eng_timeout(struct ata_port *ap);
354 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
355
356 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
357 unsigned int port);
358 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
359 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
360 void __iomem *mmio);
361 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
362 unsigned int n_hc);
363 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
364 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
365
366 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
367 unsigned int port);
368 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
369 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
370 void __iomem *mmio);
371 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
372 unsigned int n_hc);
373 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
374 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
375 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
376 unsigned int port_no);
377 static void mv_stop_and_reset(struct ata_port *ap);
378
379 static struct scsi_host_template mv_sht = {
380 .module = THIS_MODULE,
381 .name = DRV_NAME,
382 .ioctl = ata_scsi_ioctl,
383 .queuecommand = ata_scsi_queuecmd,
384 .can_queue = MV_USE_Q_DEPTH,
385 .this_id = ATA_SHT_THIS_ID,
386 .sg_tablesize = MV_MAX_SG_CT / 2,
387 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
388 .emulated = ATA_SHT_EMULATED,
389 .use_clustering = ATA_SHT_USE_CLUSTERING,
390 .proc_name = DRV_NAME,
391 .dma_boundary = MV_DMA_BOUNDARY,
392 .slave_configure = ata_scsi_slave_config,
393 .bios_param = ata_std_bios_param,
394 };
395
396 static const struct ata_port_operations mv5_ops = {
397 .port_disable = ata_port_disable,
398
399 .tf_load = ata_tf_load,
400 .tf_read = ata_tf_read,
401 .check_status = ata_check_status,
402 .exec_command = ata_exec_command,
403 .dev_select = ata_std_dev_select,
404
405 .phy_reset = mv_phy_reset,
406
407 .qc_prep = mv_qc_prep,
408 .qc_issue = mv_qc_issue,
409
410 .eng_timeout = mv_eng_timeout,
411
412 .irq_handler = mv_interrupt,
413 .irq_clear = mv_irq_clear,
414
415 .scr_read = mv5_scr_read,
416 .scr_write = mv5_scr_write,
417
418 .port_start = mv_port_start,
419 .port_stop = mv_port_stop,
420 .host_stop = mv_host_stop,
421 };
422
423 static const struct ata_port_operations mv6_ops = {
424 .port_disable = ata_port_disable,
425
426 .tf_load = ata_tf_load,
427 .tf_read = ata_tf_read,
428 .check_status = ata_check_status,
429 .exec_command = ata_exec_command,
430 .dev_select = ata_std_dev_select,
431
432 .phy_reset = mv_phy_reset,
433
434 .qc_prep = mv_qc_prep,
435 .qc_issue = mv_qc_issue,
436
437 .eng_timeout = mv_eng_timeout,
438
439 .irq_handler = mv_interrupt,
440 .irq_clear = mv_irq_clear,
441
442 .scr_read = mv_scr_read,
443 .scr_write = mv_scr_write,
444
445 .port_start = mv_port_start,
446 .port_stop = mv_port_stop,
447 .host_stop = mv_host_stop,
448 };
449
450 static const struct ata_port_operations mv_iie_ops = {
451 .port_disable = ata_port_disable,
452
453 .tf_load = ata_tf_load,
454 .tf_read = ata_tf_read,
455 .check_status = ata_check_status,
456 .exec_command = ata_exec_command,
457 .dev_select = ata_std_dev_select,
458
459 .phy_reset = mv_phy_reset,
460
461 .qc_prep = mv_qc_prep_iie,
462 .qc_issue = mv_qc_issue,
463
464 .eng_timeout = mv_eng_timeout,
465
466 .irq_handler = mv_interrupt,
467 .irq_clear = mv_irq_clear,
468
469 .scr_read = mv_scr_read,
470 .scr_write = mv_scr_write,
471
472 .port_start = mv_port_start,
473 .port_stop = mv_port_stop,
474 .host_stop = mv_host_stop,
475 };
476
477 static const struct ata_port_info mv_port_info[] = {
478 { /* chip_504x */
479 .sht = &mv_sht,
480 .host_flags = MV_COMMON_FLAGS,
481 .pio_mask = 0x1f, /* pio0-4 */
482 .udma_mask = 0x7f, /* udma0-6 */
483 .port_ops = &mv5_ops,
484 },
485 { /* chip_508x */
486 .sht = &mv_sht,
487 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
488 .pio_mask = 0x1f, /* pio0-4 */
489 .udma_mask = 0x7f, /* udma0-6 */
490 .port_ops = &mv5_ops,
491 },
492 { /* chip_5080 */
493 .sht = &mv_sht,
494 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
495 .pio_mask = 0x1f, /* pio0-4 */
496 .udma_mask = 0x7f, /* udma0-6 */
497 .port_ops = &mv5_ops,
498 },
499 { /* chip_604x */
500 .sht = &mv_sht,
501 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
502 .pio_mask = 0x1f, /* pio0-4 */
503 .udma_mask = 0x7f, /* udma0-6 */
504 .port_ops = &mv6_ops,
505 },
506 { /* chip_608x */
507 .sht = &mv_sht,
508 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
509 MV_FLAG_DUAL_HC),
510 .pio_mask = 0x1f, /* pio0-4 */
511 .udma_mask = 0x7f, /* udma0-6 */
512 .port_ops = &mv6_ops,
513 },
514 { /* chip_6042 */
515 .sht = &mv_sht,
516 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
517 .pio_mask = 0x1f, /* pio0-4 */
518 .udma_mask = 0x7f, /* udma0-6 */
519 .port_ops = &mv_iie_ops,
520 },
521 { /* chip_7042 */
522 .sht = &mv_sht,
523 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
524 MV_FLAG_DUAL_HC),
525 .pio_mask = 0x1f, /* pio0-4 */
526 .udma_mask = 0x7f, /* udma0-6 */
527 .port_ops = &mv_iie_ops,
528 },
529 };
530
531 static const struct pci_device_id mv_pci_tbl[] = {
532 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
533 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
534 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
535 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
536
537 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
538 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
539 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6042), 0, 0, chip_6042},
540 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
541 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
542
543 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
544 {} /* terminate list */
545 };
546
547 static struct pci_driver mv_pci_driver = {
548 .name = DRV_NAME,
549 .id_table = mv_pci_tbl,
550 .probe = mv_init_one,
551 .remove = ata_pci_remove_one,
552 };
553
554 static const struct mv_hw_ops mv5xxx_ops = {
555 .phy_errata = mv5_phy_errata,
556 .enable_leds = mv5_enable_leds,
557 .read_preamp = mv5_read_preamp,
558 .reset_hc = mv5_reset_hc,
559 .reset_flash = mv5_reset_flash,
560 .reset_bus = mv5_reset_bus,
561 };
562
563 static const struct mv_hw_ops mv6xxx_ops = {
564 .phy_errata = mv6_phy_errata,
565 .enable_leds = mv6_enable_leds,
566 .read_preamp = mv6_read_preamp,
567 .reset_hc = mv6_reset_hc,
568 .reset_flash = mv6_reset_flash,
569 .reset_bus = mv_reset_pci_bus,
570 };
571
572 /*
573 * module options
574 */
575 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
576
577
578 /*
579 * Functions
580 */
581
582 static inline void writelfl(unsigned long data, void __iomem *addr)
583 {
584 writel(data, addr);
585 (void) readl(addr); /* flush to avoid PCI posted write */
586 }
587
588 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
589 {
590 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
591 }
592
593 static inline unsigned int mv_hc_from_port(unsigned int port)
594 {
595 return port >> MV_PORT_HC_SHIFT;
596 }
597
598 static inline unsigned int mv_hardport_from_port(unsigned int port)
599 {
600 return port & MV_PORT_MASK;
601 }
602
603 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
604 unsigned int port)
605 {
606 return mv_hc_base(base, mv_hc_from_port(port));
607 }
608
609 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
610 {
611 return mv_hc_base_from_port(base, port) +
612 MV_SATAHC_ARBTR_REG_SZ +
613 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
614 }
615
616 static inline void __iomem *mv_ap_base(struct ata_port *ap)
617 {
618 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
619 }
620
621 static inline int mv_get_hc_count(unsigned long host_flags)
622 {
623 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
624 }
625
626 static void mv_irq_clear(struct ata_port *ap)
627 {
628 }
629
630 /**
631 * mv_start_dma - Enable eDMA engine
632 * @base: port base address
633 * @pp: port private data
634 *
635 * Verify the local cache of the eDMA state is accurate with a
636 * WARN_ON.
637 *
638 * LOCKING:
639 * Inherited from caller.
640 */
641 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
642 {
643 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
644 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
645 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
646 }
647 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
648 }
649
650 /**
651 * mv_stop_dma - Disable eDMA engine
652 * @ap: ATA channel to manipulate
653 *
654 * Verify the local cache of the eDMA state is accurate with a
655 * WARN_ON.
656 *
657 * LOCKING:
658 * Inherited from caller.
659 */
660 static void mv_stop_dma(struct ata_port *ap)
661 {
662 void __iomem *port_mmio = mv_ap_base(ap);
663 struct mv_port_priv *pp = ap->private_data;
664 u32 reg;
665 int i;
666
667 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
668 /* Disable EDMA if active. The disable bit auto clears.
669 */
670 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
671 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
672 } else {
673 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
674 }
675
676 /* now properly wait for the eDMA to stop */
677 for (i = 1000; i > 0; i--) {
678 reg = readl(port_mmio + EDMA_CMD_OFS);
679 if (!(EDMA_EN & reg)) {
680 break;
681 }
682 udelay(100);
683 }
684
685 if (EDMA_EN & reg) {
686 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
687 /* FIXME: Consider doing a reset here to recover */
688 }
689 }
690
691 #ifdef ATA_DEBUG
692 static void mv_dump_mem(void __iomem *start, unsigned bytes)
693 {
694 int b, w;
695 for (b = 0; b < bytes; ) {
696 DPRINTK("%p: ", start + b);
697 for (w = 0; b < bytes && w < 4; w++) {
698 printk("%08x ",readl(start + b));
699 b += sizeof(u32);
700 }
701 printk("\n");
702 }
703 }
704 #endif
705
706 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
707 {
708 #ifdef ATA_DEBUG
709 int b, w;
710 u32 dw;
711 for (b = 0; b < bytes; ) {
712 DPRINTK("%02x: ", b);
713 for (w = 0; b < bytes && w < 4; w++) {
714 (void) pci_read_config_dword(pdev,b,&dw);
715 printk("%08x ",dw);
716 b += sizeof(u32);
717 }
718 printk("\n");
719 }
720 #endif
721 }
722 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
723 struct pci_dev *pdev)
724 {
725 #ifdef ATA_DEBUG
726 void __iomem *hc_base = mv_hc_base(mmio_base,
727 port >> MV_PORT_HC_SHIFT);
728 void __iomem *port_base;
729 int start_port, num_ports, p, start_hc, num_hcs, hc;
730
731 if (0 > port) {
732 start_hc = start_port = 0;
733 num_ports = 8; /* shld be benign for 4 port devs */
734 num_hcs = 2;
735 } else {
736 start_hc = port >> MV_PORT_HC_SHIFT;
737 start_port = port;
738 num_ports = num_hcs = 1;
739 }
740 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
741 num_ports > 1 ? num_ports - 1 : start_port);
742
743 if (NULL != pdev) {
744 DPRINTK("PCI config space regs:\n");
745 mv_dump_pci_cfg(pdev, 0x68);
746 }
747 DPRINTK("PCI regs:\n");
748 mv_dump_mem(mmio_base+0xc00, 0x3c);
749 mv_dump_mem(mmio_base+0xd00, 0x34);
750 mv_dump_mem(mmio_base+0xf00, 0x4);
751 mv_dump_mem(mmio_base+0x1d00, 0x6c);
752 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
753 hc_base = mv_hc_base(mmio_base, hc);
754 DPRINTK("HC regs (HC %i):\n", hc);
755 mv_dump_mem(hc_base, 0x1c);
756 }
757 for (p = start_port; p < start_port + num_ports; p++) {
758 port_base = mv_port_base(mmio_base, p);
759 DPRINTK("EDMA regs (port %i):\n",p);
760 mv_dump_mem(port_base, 0x54);
761 DPRINTK("SATA regs (port %i):\n",p);
762 mv_dump_mem(port_base+0x300, 0x60);
763 }
764 #endif
765 }
766
767 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
768 {
769 unsigned int ofs;
770
771 switch (sc_reg_in) {
772 case SCR_STATUS:
773 case SCR_CONTROL:
774 case SCR_ERROR:
775 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
776 break;
777 case SCR_ACTIVE:
778 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
779 break;
780 default:
781 ofs = 0xffffffffU;
782 break;
783 }
784 return ofs;
785 }
786
787 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
788 {
789 unsigned int ofs = mv_scr_offset(sc_reg_in);
790
791 if (0xffffffffU != ofs) {
792 return readl(mv_ap_base(ap) + ofs);
793 } else {
794 return (u32) ofs;
795 }
796 }
797
798 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
799 {
800 unsigned int ofs = mv_scr_offset(sc_reg_in);
801
802 if (0xffffffffU != ofs) {
803 writelfl(val, mv_ap_base(ap) + ofs);
804 }
805 }
806
807 /**
808 * mv_host_stop - Host specific cleanup/stop routine.
809 * @host_set: host data structure
810 *
811 * Disable ints, cleanup host memory, call general purpose
812 * host_stop.
813 *
814 * LOCKING:
815 * Inherited from caller.
816 */
817 static void mv_host_stop(struct ata_host_set *host_set)
818 {
819 struct mv_host_priv *hpriv = host_set->private_data;
820 struct pci_dev *pdev = to_pci_dev(host_set->dev);
821
822 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
823 pci_disable_msi(pdev);
824 } else {
825 pci_intx(pdev, 0);
826 }
827 kfree(hpriv);
828 ata_host_stop(host_set);
829 }
830
831 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
832 {
833 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
834 }
835
836 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
837 {
838 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
839
840 /* set up non-NCQ EDMA configuration */
841 cfg &= ~0x1f; /* clear queue depth */
842 cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */
843 cfg &= ~(1 << 9); /* disable equeue */
844
845 if (IS_GEN_I(hpriv))
846 cfg |= (1 << 8); /* enab config burst size mask */
847
848 else if (IS_GEN_II(hpriv))
849 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
850
851 else if (IS_GEN_IIE(hpriv)) {
852 cfg |= (1 << 23); /* dis RX PM port mask */
853 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
854 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
855 cfg |= (1 << 18); /* enab early completion */
856 cfg |= (1 << 17); /* enab host q cache */
857 cfg |= (1 << 22); /* enab cutthrough */
858 }
859
860 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
861 }
862
863 /**
864 * mv_port_start - Port specific init/start routine.
865 * @ap: ATA channel to manipulate
866 *
867 * Allocate and point to DMA memory, init port private memory,
868 * zero indices.
869 *
870 * LOCKING:
871 * Inherited from caller.
872 */
873 static int mv_port_start(struct ata_port *ap)
874 {
875 struct device *dev = ap->host_set->dev;
876 struct mv_host_priv *hpriv = ap->host_set->private_data;
877 struct mv_port_priv *pp;
878 void __iomem *port_mmio = mv_ap_base(ap);
879 void *mem;
880 dma_addr_t mem_dma;
881 int rc = -ENOMEM;
882
883 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
884 if (!pp)
885 goto err_out;
886 memset(pp, 0, sizeof(*pp));
887
888 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
889 GFP_KERNEL);
890 if (!mem)
891 goto err_out_pp;
892 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
893
894 rc = ata_pad_alloc(ap, dev);
895 if (rc)
896 goto err_out_priv;
897
898 /* First item in chunk of DMA memory:
899 * 32-slot command request table (CRQB), 32 bytes each in size
900 */
901 pp->crqb = mem;
902 pp->crqb_dma = mem_dma;
903 mem += MV_CRQB_Q_SZ;
904 mem_dma += MV_CRQB_Q_SZ;
905
906 /* Second item:
907 * 32-slot command response table (CRPB), 8 bytes each in size
908 */
909 pp->crpb = mem;
910 pp->crpb_dma = mem_dma;
911 mem += MV_CRPB_Q_SZ;
912 mem_dma += MV_CRPB_Q_SZ;
913
914 /* Third item:
915 * Table of scatter-gather descriptors (ePRD), 16 bytes each
916 */
917 pp->sg_tbl = mem;
918 pp->sg_tbl_dma = mem_dma;
919
920 mv_edma_cfg(hpriv, port_mmio);
921
922 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
923 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
924 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
925
926 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
927 writelfl(pp->crqb_dma & 0xffffffff,
928 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
929 else
930 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
931
932 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
933
934 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
935 writelfl(pp->crpb_dma & 0xffffffff,
936 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
937 else
938 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
939
940 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
941 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
942
943 /* Don't turn on EDMA here...do it before DMA commands only. Else
944 * we'll be unable to send non-data, PIO, etc due to restricted access
945 * to shadow regs.
946 */
947 ap->private_data = pp;
948 return 0;
949
950 err_out_priv:
951 mv_priv_free(pp, dev);
952 err_out_pp:
953 kfree(pp);
954 err_out:
955 return rc;
956 }
957
958 /**
959 * mv_port_stop - Port specific cleanup/stop routine.
960 * @ap: ATA channel to manipulate
961 *
962 * Stop DMA, cleanup port memory.
963 *
964 * LOCKING:
965 * This routine uses the host_set lock to protect the DMA stop.
966 */
967 static void mv_port_stop(struct ata_port *ap)
968 {
969 struct device *dev = ap->host_set->dev;
970 struct mv_port_priv *pp = ap->private_data;
971 unsigned long flags;
972
973 spin_lock_irqsave(&ap->host_set->lock, flags);
974 mv_stop_dma(ap);
975 spin_unlock_irqrestore(&ap->host_set->lock, flags);
976
977 ap->private_data = NULL;
978 ata_pad_free(ap, dev);
979 mv_priv_free(pp, dev);
980 kfree(pp);
981 }
982
983 /**
984 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
985 * @qc: queued command whose SG list to source from
986 *
987 * Populate the SG list and mark the last entry.
988 *
989 * LOCKING:
990 * Inherited from caller.
991 */
992 static void mv_fill_sg(struct ata_queued_cmd *qc)
993 {
994 struct mv_port_priv *pp = qc->ap->private_data;
995 unsigned int i = 0;
996 struct scatterlist *sg;
997
998 ata_for_each_sg(sg, qc) {
999 dma_addr_t addr;
1000 u32 sg_len, len, offset;
1001
1002 addr = sg_dma_address(sg);
1003 sg_len = sg_dma_len(sg);
1004
1005 while (sg_len) {
1006 offset = addr & MV_DMA_BOUNDARY;
1007 len = sg_len;
1008 if ((offset + sg_len) > 0x10000)
1009 len = 0x10000 - offset;
1010
1011 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
1012 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1013 pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
1014
1015 sg_len -= len;
1016 addr += len;
1017
1018 if (!sg_len && ata_sg_is_last(sg, qc))
1019 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1020
1021 i++;
1022 }
1023 }
1024 }
1025
1026 static inline unsigned mv_inc_q_index(unsigned index)
1027 {
1028 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
1029 }
1030
1031 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
1032 {
1033 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1034 (last ? CRQB_CMD_LAST : 0);
1035 *cmdw = cpu_to_le16(tmp);
1036 }
1037
1038 /**
1039 * mv_qc_prep - Host specific command preparation.
1040 * @qc: queued command to prepare
1041 *
1042 * This routine simply redirects to the general purpose routine
1043 * if command is not DMA. Else, it handles prep of the CRQB
1044 * (command request block), does some sanity checking, and calls
1045 * the SG load routine.
1046 *
1047 * LOCKING:
1048 * Inherited from caller.
1049 */
1050 static void mv_qc_prep(struct ata_queued_cmd *qc)
1051 {
1052 struct ata_port *ap = qc->ap;
1053 struct mv_port_priv *pp = ap->private_data;
1054 u16 *cw;
1055 struct ata_taskfile *tf;
1056 u16 flags = 0;
1057 unsigned in_index;
1058
1059 if (ATA_PROT_DMA != qc->tf.protocol)
1060 return;
1061
1062 /* Fill in command request block
1063 */
1064 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1065 flags |= CRQB_FLAG_READ;
1066 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1067 flags |= qc->tag << CRQB_TAG_SHIFT;
1068
1069 /* get current queue index from hardware */
1070 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1071 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1072
1073 pp->crqb[in_index].sg_addr =
1074 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1075 pp->crqb[in_index].sg_addr_hi =
1076 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1077 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1078
1079 cw = &pp->crqb[in_index].ata_cmd[0];
1080 tf = &qc->tf;
1081
1082 /* Sadly, the CRQB cannot accomodate all registers--there are
1083 * only 11 bytes...so we must pick and choose required
1084 * registers based on the command. So, we drop feature and
1085 * hob_feature for [RW] DMA commands, but they are needed for
1086 * NCQ. NCQ will drop hob_nsect.
1087 */
1088 switch (tf->command) {
1089 case ATA_CMD_READ:
1090 case ATA_CMD_READ_EXT:
1091 case ATA_CMD_WRITE:
1092 case ATA_CMD_WRITE_EXT:
1093 case ATA_CMD_WRITE_FUA_EXT:
1094 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1095 break;
1096 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1097 case ATA_CMD_FPDMA_READ:
1098 case ATA_CMD_FPDMA_WRITE:
1099 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1100 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1101 break;
1102 #endif /* FIXME: remove this line when NCQ added */
1103 default:
1104 /* The only other commands EDMA supports in non-queued and
1105 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1106 * of which are defined/used by Linux. If we get here, this
1107 * driver needs work.
1108 *
1109 * FIXME: modify libata to give qc_prep a return value and
1110 * return error here.
1111 */
1112 BUG_ON(tf->command);
1113 break;
1114 }
1115 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1116 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1117 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1118 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1119 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1120 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1121 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1122 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1123 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1124
1125 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1126 return;
1127 mv_fill_sg(qc);
1128 }
1129
1130 /**
1131 * mv_qc_prep_iie - Host specific command preparation.
1132 * @qc: queued command to prepare
1133 *
1134 * This routine simply redirects to the general purpose routine
1135 * if command is not DMA. Else, it handles prep of the CRQB
1136 * (command request block), does some sanity checking, and calls
1137 * the SG load routine.
1138 *
1139 * LOCKING:
1140 * Inherited from caller.
1141 */
1142 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1143 {
1144 struct ata_port *ap = qc->ap;
1145 struct mv_port_priv *pp = ap->private_data;
1146 struct mv_crqb_iie *crqb;
1147 struct ata_taskfile *tf;
1148 unsigned in_index;
1149 u32 flags = 0;
1150
1151 if (ATA_PROT_DMA != qc->tf.protocol)
1152 return;
1153
1154 /* Fill in Gen IIE command request block
1155 */
1156 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1157 flags |= CRQB_FLAG_READ;
1158
1159 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1160 flags |= qc->tag << CRQB_TAG_SHIFT;
1161
1162 /* get current queue index from hardware */
1163 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1164 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1165
1166 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1167 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1168 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1169 crqb->flags = cpu_to_le32(flags);
1170
1171 tf = &qc->tf;
1172 crqb->ata_cmd[0] = cpu_to_le32(
1173 (tf->command << 16) |
1174 (tf->feature << 24)
1175 );
1176 crqb->ata_cmd[1] = cpu_to_le32(
1177 (tf->lbal << 0) |
1178 (tf->lbam << 8) |
1179 (tf->lbah << 16) |
1180 (tf->device << 24)
1181 );
1182 crqb->ata_cmd[2] = cpu_to_le32(
1183 (tf->hob_lbal << 0) |
1184 (tf->hob_lbam << 8) |
1185 (tf->hob_lbah << 16) |
1186 (tf->hob_feature << 24)
1187 );
1188 crqb->ata_cmd[3] = cpu_to_le32(
1189 (tf->nsect << 0) |
1190 (tf->hob_nsect << 8)
1191 );
1192
1193 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1194 return;
1195 mv_fill_sg(qc);
1196 }
1197
1198 /**
1199 * mv_qc_issue - Initiate a command to the host
1200 * @qc: queued command to start
1201 *
1202 * This routine simply redirects to the general purpose routine
1203 * if command is not DMA. Else, it sanity checks our local
1204 * caches of the request producer/consumer indices then enables
1205 * DMA and bumps the request producer index.
1206 *
1207 * LOCKING:
1208 * Inherited from caller.
1209 */
1210 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1211 {
1212 void __iomem *port_mmio = mv_ap_base(qc->ap);
1213 struct mv_port_priv *pp = qc->ap->private_data;
1214 unsigned in_index;
1215 u32 in_ptr;
1216
1217 if (ATA_PROT_DMA != qc->tf.protocol) {
1218 /* We're about to send a non-EDMA capable command to the
1219 * port. Turn off EDMA so there won't be problems accessing
1220 * shadow block, etc registers.
1221 */
1222 mv_stop_dma(qc->ap);
1223 return ata_qc_issue_prot(qc);
1224 }
1225
1226 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1227 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1228
1229 /* until we do queuing, the queue should be empty at this point */
1230 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1231 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1232
1233 in_index = mv_inc_q_index(in_index); /* now incr producer index */
1234
1235 mv_start_dma(port_mmio, pp);
1236
1237 /* and write the request in pointer to kick the EDMA to life */
1238 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1239 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
1240 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1241
1242 return 0;
1243 }
1244
1245 /**
1246 * mv_get_crpb_status - get status from most recently completed cmd
1247 * @ap: ATA channel to manipulate
1248 *
1249 * This routine is for use when the port is in DMA mode, when it
1250 * will be using the CRPB (command response block) method of
1251 * returning command completion information. We check indices
1252 * are good, grab status, and bump the response consumer index to
1253 * prove that we're up to date.
1254 *
1255 * LOCKING:
1256 * Inherited from caller.
1257 */
1258 static u8 mv_get_crpb_status(struct ata_port *ap)
1259 {
1260 void __iomem *port_mmio = mv_ap_base(ap);
1261 struct mv_port_priv *pp = ap->private_data;
1262 unsigned out_index;
1263 u32 out_ptr;
1264 u8 ata_status;
1265
1266 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1267 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1268
1269 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1270 >> CRPB_FLAG_STATUS_SHIFT;
1271
1272 /* increment our consumer index... */
1273 out_index = mv_inc_q_index(out_index);
1274
1275 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1276 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1277 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1278
1279 /* write out our inc'd consumer index so EDMA knows we're caught up */
1280 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1281 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
1282 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1283
1284 /* Return ATA status register for completed CRPB */
1285 return ata_status;
1286 }
1287
1288 /**
1289 * mv_err_intr - Handle error interrupts on the port
1290 * @ap: ATA channel to manipulate
1291 * @reset_allowed: bool: 0 == don't trigger from reset here
1292 *
1293 * In most cases, just clear the interrupt and move on. However,
1294 * some cases require an eDMA reset, which is done right before
1295 * the COMRESET in mv_phy_reset(). The SERR case requires a
1296 * clear of pending errors in the SATA SERROR register. Finally,
1297 * if the port disabled DMA, update our cached copy to match.
1298 *
1299 * LOCKING:
1300 * Inherited from caller.
1301 */
1302 static void mv_err_intr(struct ata_port *ap, int reset_allowed)
1303 {
1304 void __iomem *port_mmio = mv_ap_base(ap);
1305 u32 edma_err_cause, serr = 0;
1306
1307 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1308
1309 if (EDMA_ERR_SERR & edma_err_cause) {
1310 serr = scr_read(ap, SCR_ERROR);
1311 scr_write_flush(ap, SCR_ERROR, serr);
1312 }
1313 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1314 struct mv_port_priv *pp = ap->private_data;
1315 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1316 }
1317 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1318 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1319
1320 /* Clear EDMA now that SERR cleanup done */
1321 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1322
1323 /* check for fatal here and recover if needed */
1324 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
1325 mv_stop_and_reset(ap);
1326 }
1327
1328 /**
1329 * mv_host_intr - Handle all interrupts on the given host controller
1330 * @host_set: host specific structure
1331 * @relevant: port error bits relevant to this host controller
1332 * @hc: which host controller we're to look at
1333 *
1334 * Read then write clear the HC interrupt status then walk each
1335 * port connected to the HC and see if it needs servicing. Port
1336 * success ints are reported in the HC interrupt status reg, the
1337 * port error ints are reported in the higher level main
1338 * interrupt status register and thus are passed in via the
1339 * 'relevant' argument.
1340 *
1341 * LOCKING:
1342 * Inherited from caller.
1343 */
1344 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1345 unsigned int hc)
1346 {
1347 void __iomem *mmio = host_set->mmio_base;
1348 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1349 struct ata_queued_cmd *qc;
1350 u32 hc_irq_cause;
1351 int shift, port, port0, hard_port, handled;
1352 unsigned int err_mask;
1353
1354 if (hc == 0) {
1355 port0 = 0;
1356 } else {
1357 port0 = MV_PORTS_PER_HC;
1358 }
1359
1360 /* we'll need the HC success int register in most cases */
1361 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1362 if (hc_irq_cause) {
1363 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1364 }
1365
1366 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1367 hc,relevant,hc_irq_cause);
1368
1369 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1370 u8 ata_status = 0;
1371 struct ata_port *ap = host_set->ports[port];
1372 struct mv_port_priv *pp = ap->private_data;
1373
1374 hard_port = mv_hardport_from_port(port); /* range 0..3 */
1375 handled = 0; /* ensure ata_status is set if handled++ */
1376
1377 /* Note that DEV_IRQ might happen spuriously during EDMA,
1378 * and should be ignored in such cases.
1379 * The cause of this is still under investigation.
1380 */
1381 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1382 /* EDMA: check for response queue interrupt */
1383 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1384 ata_status = mv_get_crpb_status(ap);
1385 handled = 1;
1386 }
1387 } else {
1388 /* PIO: check for device (drive) interrupt */
1389 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1390 ata_status = readb((void __iomem *)
1391 ap->ioaddr.status_addr);
1392 handled = 1;
1393 /* ignore spurious intr if drive still BUSY */
1394 if (ata_status & ATA_BUSY) {
1395 ata_status = 0;
1396 handled = 0;
1397 }
1398 }
1399 }
1400
1401 if (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))
1402 continue;
1403
1404 err_mask = ac_err_mask(ata_status);
1405
1406 shift = port << 1; /* (port * 2) */
1407 if (port >= MV_PORTS_PER_HC) {
1408 shift++; /* skip bit 8 in the HC Main IRQ reg */
1409 }
1410 if ((PORT0_ERR << shift) & relevant) {
1411 mv_err_intr(ap, 1);
1412 err_mask |= AC_ERR_OTHER;
1413 handled = 1;
1414 }
1415
1416 if (handled) {
1417 qc = ata_qc_from_tag(ap, ap->active_tag);
1418 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
1419 VPRINTK("port %u IRQ found for qc, "
1420 "ata_status 0x%x\n", port,ata_status);
1421 /* mark qc status appropriately */
1422 if (!(qc->tf.ctl & ATA_NIEN)) {
1423 qc->err_mask |= err_mask;
1424 ata_qc_complete(qc);
1425 }
1426 }
1427 }
1428 }
1429 VPRINTK("EXIT\n");
1430 }
1431
1432 /**
1433 * mv_interrupt -
1434 * @irq: unused
1435 * @dev_instance: private data; in this case the host structure
1436 * @regs: unused
1437 *
1438 * Read the read only register to determine if any host
1439 * controllers have pending interrupts. If so, call lower level
1440 * routine to handle. Also check for PCI errors which are only
1441 * reported here.
1442 *
1443 * LOCKING:
1444 * This routine holds the host_set lock while processing pending
1445 * interrupts.
1446 */
1447 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1448 struct pt_regs *regs)
1449 {
1450 struct ata_host_set *host_set = dev_instance;
1451 unsigned int hc, handled = 0, n_hcs;
1452 void __iomem *mmio = host_set->mmio_base;
1453 struct mv_host_priv *hpriv;
1454 u32 irq_stat;
1455
1456 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1457
1458 /* check the cases where we either have nothing pending or have read
1459 * a bogus register value which can indicate HW removal or PCI fault
1460 */
1461 if (!irq_stat || (0xffffffffU == irq_stat)) {
1462 return IRQ_NONE;
1463 }
1464
1465 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1466 spin_lock(&host_set->lock);
1467
1468 for (hc = 0; hc < n_hcs; hc++) {
1469 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1470 if (relevant) {
1471 mv_host_intr(host_set, relevant, hc);
1472 handled++;
1473 }
1474 }
1475
1476 hpriv = host_set->private_data;
1477 if (IS_60XX(hpriv)) {
1478 /* deal with the interrupt coalescing bits */
1479 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1480 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1481 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1482 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1483 }
1484 }
1485
1486 if (PCI_ERR & irq_stat) {
1487 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1488 readl(mmio + PCI_IRQ_CAUSE_OFS));
1489
1490 DPRINTK("All regs @ PCI error\n");
1491 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1492
1493 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1494 handled++;
1495 }
1496 spin_unlock(&host_set->lock);
1497
1498 return IRQ_RETVAL(handled);
1499 }
1500
1501 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1502 {
1503 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1504 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1505
1506 return hc_mmio + ofs;
1507 }
1508
1509 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1510 {
1511 unsigned int ofs;
1512
1513 switch (sc_reg_in) {
1514 case SCR_STATUS:
1515 case SCR_ERROR:
1516 case SCR_CONTROL:
1517 ofs = sc_reg_in * sizeof(u32);
1518 break;
1519 default:
1520 ofs = 0xffffffffU;
1521 break;
1522 }
1523 return ofs;
1524 }
1525
1526 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1527 {
1528 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1529 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1530
1531 if (ofs != 0xffffffffU)
1532 return readl(mmio + ofs);
1533 else
1534 return (u32) ofs;
1535 }
1536
1537 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1538 {
1539 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1540 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1541
1542 if (ofs != 0xffffffffU)
1543 writelfl(val, mmio + ofs);
1544 }
1545
1546 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1547 {
1548 u8 rev_id;
1549 int early_5080;
1550
1551 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1552
1553 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1554
1555 if (!early_5080) {
1556 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1557 tmp |= (1 << 0);
1558 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1559 }
1560
1561 mv_reset_pci_bus(pdev, mmio);
1562 }
1563
1564 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1565 {
1566 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1567 }
1568
1569 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1570 void __iomem *mmio)
1571 {
1572 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1573 u32 tmp;
1574
1575 tmp = readl(phy_mmio + MV5_PHY_MODE);
1576
1577 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1578 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1579 }
1580
1581 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1582 {
1583 u32 tmp;
1584
1585 writel(0, mmio + MV_GPIO_PORT_CTL);
1586
1587 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1588
1589 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1590 tmp |= ~(1 << 0);
1591 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1592 }
1593
1594 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1595 unsigned int port)
1596 {
1597 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1598 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1599 u32 tmp;
1600 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1601
1602 if (fix_apm_sq) {
1603 tmp = readl(phy_mmio + MV5_LT_MODE);
1604 tmp |= (1 << 19);
1605 writel(tmp, phy_mmio + MV5_LT_MODE);
1606
1607 tmp = readl(phy_mmio + MV5_PHY_CTL);
1608 tmp &= ~0x3;
1609 tmp |= 0x1;
1610 writel(tmp, phy_mmio + MV5_PHY_CTL);
1611 }
1612
1613 tmp = readl(phy_mmio + MV5_PHY_MODE);
1614 tmp &= ~mask;
1615 tmp |= hpriv->signal[port].pre;
1616 tmp |= hpriv->signal[port].amps;
1617 writel(tmp, phy_mmio + MV5_PHY_MODE);
1618 }
1619
1620
1621 #undef ZERO
1622 #define ZERO(reg) writel(0, port_mmio + (reg))
1623 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1624 unsigned int port)
1625 {
1626 void __iomem *port_mmio = mv_port_base(mmio, port);
1627
1628 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1629
1630 mv_channel_reset(hpriv, mmio, port);
1631
1632 ZERO(0x028); /* command */
1633 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1634 ZERO(0x004); /* timer */
1635 ZERO(0x008); /* irq err cause */
1636 ZERO(0x00c); /* irq err mask */
1637 ZERO(0x010); /* rq bah */
1638 ZERO(0x014); /* rq inp */
1639 ZERO(0x018); /* rq outp */
1640 ZERO(0x01c); /* respq bah */
1641 ZERO(0x024); /* respq outp */
1642 ZERO(0x020); /* respq inp */
1643 ZERO(0x02c); /* test control */
1644 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1645 }
1646 #undef ZERO
1647
1648 #define ZERO(reg) writel(0, hc_mmio + (reg))
1649 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1650 unsigned int hc)
1651 {
1652 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1653 u32 tmp;
1654
1655 ZERO(0x00c);
1656 ZERO(0x010);
1657 ZERO(0x014);
1658 ZERO(0x018);
1659
1660 tmp = readl(hc_mmio + 0x20);
1661 tmp &= 0x1c1c1c1c;
1662 tmp |= 0x03030303;
1663 writel(tmp, hc_mmio + 0x20);
1664 }
1665 #undef ZERO
1666
1667 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1668 unsigned int n_hc)
1669 {
1670 unsigned int hc, port;
1671
1672 for (hc = 0; hc < n_hc; hc++) {
1673 for (port = 0; port < MV_PORTS_PER_HC; port++)
1674 mv5_reset_hc_port(hpriv, mmio,
1675 (hc * MV_PORTS_PER_HC) + port);
1676
1677 mv5_reset_one_hc(hpriv, mmio, hc);
1678 }
1679
1680 return 0;
1681 }
1682
1683 #undef ZERO
1684 #define ZERO(reg) writel(0, mmio + (reg))
1685 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1686 {
1687 u32 tmp;
1688
1689 tmp = readl(mmio + MV_PCI_MODE);
1690 tmp &= 0xff00ffff;
1691 writel(tmp, mmio + MV_PCI_MODE);
1692
1693 ZERO(MV_PCI_DISC_TIMER);
1694 ZERO(MV_PCI_MSI_TRIGGER);
1695 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1696 ZERO(HC_MAIN_IRQ_MASK_OFS);
1697 ZERO(MV_PCI_SERR_MASK);
1698 ZERO(PCI_IRQ_CAUSE_OFS);
1699 ZERO(PCI_IRQ_MASK_OFS);
1700 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1701 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1702 ZERO(MV_PCI_ERR_ATTRIBUTE);
1703 ZERO(MV_PCI_ERR_COMMAND);
1704 }
1705 #undef ZERO
1706
1707 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1708 {
1709 u32 tmp;
1710
1711 mv5_reset_flash(hpriv, mmio);
1712
1713 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1714 tmp &= 0x3;
1715 tmp |= (1 << 5) | (1 << 6);
1716 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1717 }
1718
1719 /**
1720 * mv6_reset_hc - Perform the 6xxx global soft reset
1721 * @mmio: base address of the HBA
1722 *
1723 * This routine only applies to 6xxx parts.
1724 *
1725 * LOCKING:
1726 * Inherited from caller.
1727 */
1728 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1729 unsigned int n_hc)
1730 {
1731 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1732 int i, rc = 0;
1733 u32 t;
1734
1735 /* Following procedure defined in PCI "main command and status
1736 * register" table.
1737 */
1738 t = readl(reg);
1739 writel(t | STOP_PCI_MASTER, reg);
1740
1741 for (i = 0; i < 1000; i++) {
1742 udelay(1);
1743 t = readl(reg);
1744 if (PCI_MASTER_EMPTY & t) {
1745 break;
1746 }
1747 }
1748 if (!(PCI_MASTER_EMPTY & t)) {
1749 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1750 rc = 1;
1751 goto done;
1752 }
1753
1754 /* set reset */
1755 i = 5;
1756 do {
1757 writel(t | GLOB_SFT_RST, reg);
1758 t = readl(reg);
1759 udelay(1);
1760 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1761
1762 if (!(GLOB_SFT_RST & t)) {
1763 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1764 rc = 1;
1765 goto done;
1766 }
1767
1768 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1769 i = 5;
1770 do {
1771 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1772 t = readl(reg);
1773 udelay(1);
1774 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1775
1776 if (GLOB_SFT_RST & t) {
1777 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1778 rc = 1;
1779 }
1780 done:
1781 return rc;
1782 }
1783
1784 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1785 void __iomem *mmio)
1786 {
1787 void __iomem *port_mmio;
1788 u32 tmp;
1789
1790 tmp = readl(mmio + MV_RESET_CFG);
1791 if ((tmp & (1 << 0)) == 0) {
1792 hpriv->signal[idx].amps = 0x7 << 8;
1793 hpriv->signal[idx].pre = 0x1 << 5;
1794 return;
1795 }
1796
1797 port_mmio = mv_port_base(mmio, idx);
1798 tmp = readl(port_mmio + PHY_MODE2);
1799
1800 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1801 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1802 }
1803
1804 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1805 {
1806 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1807 }
1808
1809 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1810 unsigned int port)
1811 {
1812 void __iomem *port_mmio = mv_port_base(mmio, port);
1813
1814 u32 hp_flags = hpriv->hp_flags;
1815 int fix_phy_mode2 =
1816 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1817 int fix_phy_mode4 =
1818 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1819 u32 m2, tmp;
1820
1821 if (fix_phy_mode2) {
1822 m2 = readl(port_mmio + PHY_MODE2);
1823 m2 &= ~(1 << 16);
1824 m2 |= (1 << 31);
1825 writel(m2, port_mmio + PHY_MODE2);
1826
1827 udelay(200);
1828
1829 m2 = readl(port_mmio + PHY_MODE2);
1830 m2 &= ~((1 << 16) | (1 << 31));
1831 writel(m2, port_mmio + PHY_MODE2);
1832
1833 udelay(200);
1834 }
1835
1836 /* who knows what this magic does */
1837 tmp = readl(port_mmio + PHY_MODE3);
1838 tmp &= ~0x7F800000;
1839 tmp |= 0x2A800000;
1840 writel(tmp, port_mmio + PHY_MODE3);
1841
1842 if (fix_phy_mode4) {
1843 u32 m4;
1844
1845 m4 = readl(port_mmio + PHY_MODE4);
1846
1847 if (hp_flags & MV_HP_ERRATA_60X1B2)
1848 tmp = readl(port_mmio + 0x310);
1849
1850 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1851
1852 writel(m4, port_mmio + PHY_MODE4);
1853
1854 if (hp_flags & MV_HP_ERRATA_60X1B2)
1855 writel(tmp, port_mmio + 0x310);
1856 }
1857
1858 /* Revert values of pre-emphasis and signal amps to the saved ones */
1859 m2 = readl(port_mmio + PHY_MODE2);
1860
1861 m2 &= ~MV_M2_PREAMP_MASK;
1862 m2 |= hpriv->signal[port].amps;
1863 m2 |= hpriv->signal[port].pre;
1864 m2 &= ~(1 << 16);
1865
1866 /* according to mvSata 3.6.1, some IIE values are fixed */
1867 if (IS_GEN_IIE(hpriv)) {
1868 m2 &= ~0xC30FF01F;
1869 m2 |= 0x0000900F;
1870 }
1871
1872 writel(m2, port_mmio + PHY_MODE2);
1873 }
1874
1875 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1876 unsigned int port_no)
1877 {
1878 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1879
1880 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1881
1882 if (IS_60XX(hpriv)) {
1883 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1884 ifctl |= (1 << 7); /* enable gen2i speed */
1885 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
1886 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1887 }
1888
1889 udelay(25); /* allow reset propagation */
1890
1891 /* Spec never mentions clearing the bit. Marvell's driver does
1892 * clear the bit, however.
1893 */
1894 writelfl(0, port_mmio + EDMA_CMD_OFS);
1895
1896 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1897
1898 if (IS_50XX(hpriv))
1899 mdelay(1);
1900 }
1901
1902 static void mv_stop_and_reset(struct ata_port *ap)
1903 {
1904 struct mv_host_priv *hpriv = ap->host_set->private_data;
1905 void __iomem *mmio = ap->host_set->mmio_base;
1906
1907 mv_stop_dma(ap);
1908
1909 mv_channel_reset(hpriv, mmio, ap->port_no);
1910
1911 __mv_phy_reset(ap, 0);
1912 }
1913
1914 static inline void __msleep(unsigned int msec, int can_sleep)
1915 {
1916 if (can_sleep)
1917 msleep(msec);
1918 else
1919 mdelay(msec);
1920 }
1921
1922 /**
1923 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1924 * @ap: ATA channel to manipulate
1925 *
1926 * Part of this is taken from __sata_phy_reset and modified to
1927 * not sleep since this routine gets called from interrupt level.
1928 *
1929 * LOCKING:
1930 * Inherited from caller. This is coded to safe to call at
1931 * interrupt level, i.e. it does not sleep.
1932 */
1933 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1934 {
1935 struct mv_port_priv *pp = ap->private_data;
1936 struct mv_host_priv *hpriv = ap->host_set->private_data;
1937 void __iomem *port_mmio = mv_ap_base(ap);
1938 struct ata_taskfile tf;
1939 struct ata_device *dev = &ap->device[0];
1940 unsigned long timeout;
1941 int retry = 5;
1942 u32 sstatus;
1943
1944 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1945
1946 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1947 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1948 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1949
1950 /* Issue COMRESET via SControl */
1951 comreset_retry:
1952 scr_write_flush(ap, SCR_CONTROL, 0x301);
1953 __msleep(1, can_sleep);
1954
1955 scr_write_flush(ap, SCR_CONTROL, 0x300);
1956 __msleep(20, can_sleep);
1957
1958 timeout = jiffies + msecs_to_jiffies(200);
1959 do {
1960 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1961 if ((sstatus == 3) || (sstatus == 0))
1962 break;
1963
1964 __msleep(1, can_sleep);
1965 } while (time_before(jiffies, timeout));
1966
1967 /* work around errata */
1968 if (IS_60XX(hpriv) &&
1969 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1970 (retry-- > 0))
1971 goto comreset_retry;
1972
1973 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1974 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1975 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1976
1977 if (sata_dev_present(ap)) {
1978 ata_port_probe(ap);
1979 } else {
1980 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1981 ap->id, scr_read(ap, SCR_STATUS));
1982 ata_port_disable(ap);
1983 return;
1984 }
1985 ap->cbl = ATA_CBL_SATA;
1986
1987 /* even after SStatus reflects that device is ready,
1988 * it seems to take a while for link to be fully
1989 * established (and thus Status no longer 0x80/0x7F),
1990 * so we poll a bit for that, here.
1991 */
1992 retry = 20;
1993 while (1) {
1994 u8 drv_stat = ata_check_status(ap);
1995 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1996 break;
1997 __msleep(500, can_sleep);
1998 if (retry-- <= 0)
1999 break;
2000 }
2001
2002 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
2003 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
2004 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
2005 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
2006
2007 dev->class = ata_dev_classify(&tf);
2008 if (!ata_dev_present(dev)) {
2009 VPRINTK("Port disabled post-sig: No device present.\n");
2010 ata_port_disable(ap);
2011 }
2012
2013 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2014
2015 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2016
2017 VPRINTK("EXIT\n");
2018 }
2019
2020 static void mv_phy_reset(struct ata_port *ap)
2021 {
2022 __mv_phy_reset(ap, 1);
2023 }
2024
2025 /**
2026 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
2027 * @ap: ATA channel to manipulate
2028 *
2029 * Intent is to clear all pending error conditions, reset the
2030 * chip/bus, fail the command, and move on.
2031 *
2032 * LOCKING:
2033 * This routine holds the host_set lock while failing the command.
2034 */
2035 static void mv_eng_timeout(struct ata_port *ap)
2036 {
2037 struct ata_queued_cmd *qc;
2038 unsigned long flags;
2039
2040 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
2041 DPRINTK("All regs @ start of eng_timeout\n");
2042 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
2043 to_pci_dev(ap->host_set->dev));
2044
2045 qc = ata_qc_from_tag(ap, ap->active_tag);
2046 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2047 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
2048 &qc->scsicmd->cmnd);
2049
2050 spin_lock_irqsave(&ap->host_set->lock, flags);
2051 mv_err_intr(ap, 0);
2052 mv_stop_and_reset(ap);
2053 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2054
2055 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2056 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2057 qc->err_mask |= AC_ERR_TIMEOUT;
2058 ata_eh_qc_complete(qc);
2059 }
2060 }
2061
2062 /**
2063 * mv_port_init - Perform some early initialization on a single port.
2064 * @port: libata data structure storing shadow register addresses
2065 * @port_mmio: base address of the port
2066 *
2067 * Initialize shadow register mmio addresses, clear outstanding
2068 * interrupts on the port, and unmask interrupts for the future
2069 * start of the port.
2070 *
2071 * LOCKING:
2072 * Inherited from caller.
2073 */
2074 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2075 {
2076 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
2077 unsigned serr_ofs;
2078
2079 /* PIO related setup
2080 */
2081 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2082 port->error_addr =
2083 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2084 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2085 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2086 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2087 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2088 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2089 port->status_addr =
2090 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2091 /* special case: control/altstatus doesn't have ATA_REG_ address */
2092 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2093
2094 /* unused: */
2095 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
2096
2097 /* Clear any currently outstanding port interrupt conditions */
2098 serr_ofs = mv_scr_offset(SCR_ERROR);
2099 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2100 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2101
2102 /* unmask all EDMA error interrupts */
2103 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2104
2105 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2106 readl(port_mmio + EDMA_CFG_OFS),
2107 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2108 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2109 }
2110
2111 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2112 unsigned int board_idx)
2113 {
2114 u8 rev_id;
2115 u32 hp_flags = hpriv->hp_flags;
2116
2117 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2118
2119 switch(board_idx) {
2120 case chip_5080:
2121 hpriv->ops = &mv5xxx_ops;
2122 hp_flags |= MV_HP_50XX;
2123
2124 switch (rev_id) {
2125 case 0x1:
2126 hp_flags |= MV_HP_ERRATA_50XXB0;
2127 break;
2128 case 0x3:
2129 hp_flags |= MV_HP_ERRATA_50XXB2;
2130 break;
2131 default:
2132 dev_printk(KERN_WARNING, &pdev->dev,
2133 "Applying 50XXB2 workarounds to unknown rev\n");
2134 hp_flags |= MV_HP_ERRATA_50XXB2;
2135 break;
2136 }
2137 break;
2138
2139 case chip_504x:
2140 case chip_508x:
2141 hpriv->ops = &mv5xxx_ops;
2142 hp_flags |= MV_HP_50XX;
2143
2144 switch (rev_id) {
2145 case 0x0:
2146 hp_flags |= MV_HP_ERRATA_50XXB0;
2147 break;
2148 case 0x3:
2149 hp_flags |= MV_HP_ERRATA_50XXB2;
2150 break;
2151 default:
2152 dev_printk(KERN_WARNING, &pdev->dev,
2153 "Applying B2 workarounds to unknown rev\n");
2154 hp_flags |= MV_HP_ERRATA_50XXB2;
2155 break;
2156 }
2157 break;
2158
2159 case chip_604x:
2160 case chip_608x:
2161 hpriv->ops = &mv6xxx_ops;
2162
2163 switch (rev_id) {
2164 case 0x7:
2165 hp_flags |= MV_HP_ERRATA_60X1B2;
2166 break;
2167 case 0x9:
2168 hp_flags |= MV_HP_ERRATA_60X1C0;
2169 break;
2170 default:
2171 dev_printk(KERN_WARNING, &pdev->dev,
2172 "Applying B2 workarounds to unknown rev\n");
2173 hp_flags |= MV_HP_ERRATA_60X1B2;
2174 break;
2175 }
2176 break;
2177
2178 case chip_7042:
2179 case chip_6042:
2180 hpriv->ops = &mv6xxx_ops;
2181
2182 hp_flags |= MV_HP_GEN_IIE;
2183
2184 switch (rev_id) {
2185 case 0x0:
2186 hp_flags |= MV_HP_ERRATA_XX42A0;
2187 break;
2188 case 0x1:
2189 hp_flags |= MV_HP_ERRATA_60X1C0;
2190 break;
2191 default:
2192 dev_printk(KERN_WARNING, &pdev->dev,
2193 "Applying 60X1C0 workarounds to unknown rev\n");
2194 hp_flags |= MV_HP_ERRATA_60X1C0;
2195 break;
2196 }
2197 break;
2198
2199 default:
2200 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2201 return 1;
2202 }
2203
2204 hpriv->hp_flags = hp_flags;
2205
2206 return 0;
2207 }
2208
2209 /**
2210 * mv_init_host - Perform some early initialization of the host.
2211 * @pdev: host PCI device
2212 * @probe_ent: early data struct representing the host
2213 *
2214 * If possible, do an early global reset of the host. Then do
2215 * our port init and clear/unmask all/relevant host interrupts.
2216 *
2217 * LOCKING:
2218 * Inherited from caller.
2219 */
2220 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2221 unsigned int board_idx)
2222 {
2223 int rc = 0, n_hc, port, hc;
2224 void __iomem *mmio = probe_ent->mmio_base;
2225 struct mv_host_priv *hpriv = probe_ent->private_data;
2226
2227 /* global interrupt mask */
2228 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2229
2230 rc = mv_chip_id(pdev, hpriv, board_idx);
2231 if (rc)
2232 goto done;
2233
2234 n_hc = mv_get_hc_count(probe_ent->host_flags);
2235 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2236
2237 for (port = 0; port < probe_ent->n_ports; port++)
2238 hpriv->ops->read_preamp(hpriv, port, mmio);
2239
2240 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2241 if (rc)
2242 goto done;
2243
2244 hpriv->ops->reset_flash(hpriv, mmio);
2245 hpriv->ops->reset_bus(pdev, mmio);
2246 hpriv->ops->enable_leds(hpriv, mmio);
2247
2248 for (port = 0; port < probe_ent->n_ports; port++) {
2249 if (IS_60XX(hpriv)) {
2250 void __iomem *port_mmio = mv_port_base(mmio, port);
2251
2252 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2253 ifctl |= (1 << 7); /* enable gen2i speed */
2254 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2255 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2256 }
2257
2258 hpriv->ops->phy_errata(hpriv, mmio, port);
2259 }
2260
2261 for (port = 0; port < probe_ent->n_ports; port++) {
2262 void __iomem *port_mmio = mv_port_base(mmio, port);
2263 mv_port_init(&probe_ent->port[port], port_mmio);
2264 }
2265
2266 for (hc = 0; hc < n_hc; hc++) {
2267 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2268
2269 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2270 "(before clear)=0x%08x\n", hc,
2271 readl(hc_mmio + HC_CFG_OFS),
2272 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2273
2274 /* Clear any currently outstanding hc interrupt conditions */
2275 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2276 }
2277
2278 /* Clear any currently outstanding host interrupt conditions */
2279 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2280
2281 /* and unmask interrupt generation for host regs */
2282 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2283 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2284
2285 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2286 "PCI int cause/mask=0x%08x/0x%08x\n",
2287 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2288 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2289 readl(mmio + PCI_IRQ_CAUSE_OFS),
2290 readl(mmio + PCI_IRQ_MASK_OFS));
2291
2292 done:
2293 return rc;
2294 }
2295
2296 /**
2297 * mv_print_info - Dump key info to kernel log for perusal.
2298 * @probe_ent: early data struct representing the host
2299 *
2300 * FIXME: complete this.
2301 *
2302 * LOCKING:
2303 * Inherited from caller.
2304 */
2305 static void mv_print_info(struct ata_probe_ent *probe_ent)
2306 {
2307 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2308 struct mv_host_priv *hpriv = probe_ent->private_data;
2309 u8 rev_id, scc;
2310 const char *scc_s;
2311
2312 /* Use this to determine the HW stepping of the chip so we know
2313 * what errata to workaround
2314 */
2315 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2316
2317 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2318 if (scc == 0)
2319 scc_s = "SCSI";
2320 else if (scc == 0x01)
2321 scc_s = "RAID";
2322 else
2323 scc_s = "unknown";
2324
2325 dev_printk(KERN_INFO, &pdev->dev,
2326 "%u slots %u ports %s mode IRQ via %s\n",
2327 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2328 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2329 }
2330
2331 /**
2332 * mv_init_one - handle a positive probe of a Marvell host
2333 * @pdev: PCI device found
2334 * @ent: PCI device ID entry for the matched host
2335 *
2336 * LOCKING:
2337 * Inherited from caller.
2338 */
2339 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2340 {
2341 static int printed_version = 0;
2342 struct ata_probe_ent *probe_ent = NULL;
2343 struct mv_host_priv *hpriv;
2344 unsigned int board_idx = (unsigned int)ent->driver_data;
2345 void __iomem *mmio_base;
2346 int pci_dev_busy = 0, rc;
2347
2348 if (!printed_version++)
2349 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2350
2351 rc = pci_enable_device(pdev);
2352 if (rc) {
2353 return rc;
2354 }
2355 pci_set_master(pdev);
2356
2357 rc = pci_request_regions(pdev, DRV_NAME);
2358 if (rc) {
2359 pci_dev_busy = 1;
2360 goto err_out;
2361 }
2362
2363 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2364 if (probe_ent == NULL) {
2365 rc = -ENOMEM;
2366 goto err_out_regions;
2367 }
2368
2369 memset(probe_ent, 0, sizeof(*probe_ent));
2370 probe_ent->dev = pci_dev_to_dev(pdev);
2371 INIT_LIST_HEAD(&probe_ent->node);
2372
2373 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2374 if (mmio_base == NULL) {
2375 rc = -ENOMEM;
2376 goto err_out_free_ent;
2377 }
2378
2379 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2380 if (!hpriv) {
2381 rc = -ENOMEM;
2382 goto err_out_iounmap;
2383 }
2384 memset(hpriv, 0, sizeof(*hpriv));
2385
2386 probe_ent->sht = mv_port_info[board_idx].sht;
2387 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2388 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2389 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2390 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2391
2392 probe_ent->irq = pdev->irq;
2393 probe_ent->irq_flags = SA_SHIRQ;
2394 probe_ent->mmio_base = mmio_base;
2395 probe_ent->private_data = hpriv;
2396
2397 /* initialize adapter */
2398 rc = mv_init_host(pdev, probe_ent, board_idx);
2399 if (rc) {
2400 goto err_out_hpriv;
2401 }
2402
2403 /* Enable interrupts */
2404 if (msi && pci_enable_msi(pdev) == 0) {
2405 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2406 } else {
2407 pci_intx(pdev, 1);
2408 }
2409
2410 mv_dump_pci_cfg(pdev, 0x68);
2411 mv_print_info(probe_ent);
2412
2413 if (ata_device_add(probe_ent) == 0) {
2414 rc = -ENODEV; /* No devices discovered */
2415 goto err_out_dev_add;
2416 }
2417
2418 kfree(probe_ent);
2419 return 0;
2420
2421 err_out_dev_add:
2422 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2423 pci_disable_msi(pdev);
2424 } else {
2425 pci_intx(pdev, 0);
2426 }
2427 err_out_hpriv:
2428 kfree(hpriv);
2429 err_out_iounmap:
2430 pci_iounmap(pdev, mmio_base);
2431 err_out_free_ent:
2432 kfree(probe_ent);
2433 err_out_regions:
2434 pci_release_regions(pdev);
2435 err_out:
2436 if (!pci_dev_busy) {
2437 pci_disable_device(pdev);
2438 }
2439
2440 return rc;
2441 }
2442
2443 static int __init mv_init(void)
2444 {
2445 return pci_module_init(&mv_pci_driver);
2446 }
2447
2448 static void __exit mv_exit(void)
2449 {
2450 pci_unregister_driver(&mv_pci_driver);
2451 }
2452
2453 MODULE_AUTHOR("Brett Russ");
2454 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2455 MODULE_LICENSE("GPL");
2456 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2457 MODULE_VERSION(DRV_VERSION);
2458
2459 module_param(msi, int, 0444);
2460 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2461
2462 module_init(mv_init);
2463 module_exit(mv_exit);
Linux with added FPC-III support