2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2005 Alan Stern, stern@rowland.harvard.edu
19 static void uhci_free_pending_tds(struct uhci_hcd
*uhci
);
22 * Technically, updating td->status here is a race, but it's not really a
23 * problem. The worst that can happen is that we set the IOC bit again
24 * generating a spurious interrupt. We could fix this by creating another
25 * QH and leaving the IOC bit always set, but then we would have to play
26 * games with the FSBR code to make sure we get the correct order in all
27 * the cases. I don't think it's worth the effort
29 static void uhci_set_next_interrupt(struct uhci_hcd
*uhci
)
32 mod_timer(&uhci_to_hcd(uhci
)->rh_timer
, jiffies
);
33 uhci
->term_td
->status
|= cpu_to_le32(TD_CTRL_IOC
);
36 static inline void uhci_clear_next_interrupt(struct uhci_hcd
*uhci
)
38 uhci
->term_td
->status
&= ~cpu_to_le32(TD_CTRL_IOC
);
41 static struct uhci_td
*uhci_alloc_td(struct uhci_hcd
*uhci
)
43 dma_addr_t dma_handle
;
46 td
= dma_pool_alloc(uhci
->td_pool
, GFP_ATOMIC
, &dma_handle
);
50 td
->dma_handle
= dma_handle
;
53 INIT_LIST_HEAD(&td
->list
);
54 INIT_LIST_HEAD(&td
->remove_list
);
55 INIT_LIST_HEAD(&td
->fl_list
);
60 static void uhci_free_td(struct uhci_hcd
*uhci
, struct uhci_td
*td
)
62 if (!list_empty(&td
->list
))
63 dev_warn(uhci_dev(uhci
), "td %p still in list!\n", td
);
64 if (!list_empty(&td
->remove_list
))
65 dev_warn(uhci_dev(uhci
), "td %p still in remove_list!\n", td
);
66 if (!list_empty(&td
->fl_list
))
67 dev_warn(uhci_dev(uhci
), "td %p still in fl_list!\n", td
);
69 dma_pool_free(uhci
->td_pool
, td
, td
->dma_handle
);
72 static inline void uhci_fill_td(struct uhci_td
*td
, u32 status
,
73 u32 token
, u32 buffer
)
75 td
->status
= cpu_to_le32(status
);
76 td
->token
= cpu_to_le32(token
);
77 td
->buffer
= cpu_to_le32(buffer
);
81 * We insert Isochronous URBs directly into the frame list at the beginning
83 static inline void uhci_insert_td_in_frame_list(struct uhci_hcd
*uhci
,
84 struct uhci_td
*td
, unsigned framenum
)
86 framenum
&= (UHCI_NUMFRAMES
- 1);
90 /* Is there a TD already mapped there? */
91 if (uhci
->frame_cpu
[framenum
]) {
92 struct uhci_td
*ftd
, *ltd
;
94 ftd
= uhci
->frame_cpu
[framenum
];
95 ltd
= list_entry(ftd
->fl_list
.prev
, struct uhci_td
, fl_list
);
97 list_add_tail(&td
->fl_list
, &ftd
->fl_list
);
101 ltd
->link
= cpu_to_le32(td
->dma_handle
);
103 td
->link
= uhci
->frame
[framenum
];
105 uhci
->frame
[framenum
] = cpu_to_le32(td
->dma_handle
);
106 uhci
->frame_cpu
[framenum
] = td
;
110 static inline void uhci_remove_td_from_frame_list(struct uhci_hcd
*uhci
,
113 /* If it's not inserted, don't remove it */
114 if (td
->frame
== -1) {
115 WARN_ON(!list_empty(&td
->fl_list
));
119 if (uhci
->frame_cpu
[td
->frame
] == td
) {
120 if (list_empty(&td
->fl_list
)) {
121 uhci
->frame
[td
->frame
] = td
->link
;
122 uhci
->frame_cpu
[td
->frame
] = NULL
;
126 ntd
= list_entry(td
->fl_list
.next
, struct uhci_td
, fl_list
);
127 uhci
->frame
[td
->frame
] = cpu_to_le32(ntd
->dma_handle
);
128 uhci
->frame_cpu
[td
->frame
] = ntd
;
133 ptd
= list_entry(td
->fl_list
.prev
, struct uhci_td
, fl_list
);
134 ptd
->link
= td
->link
;
137 list_del_init(&td
->fl_list
);
142 * Remove all the TDs for an Isochronous URB from the frame list
144 static void uhci_unlink_isochronous_tds(struct uhci_hcd
*uhci
, struct urb
*urb
)
146 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
149 list_for_each_entry(td
, &urbp
->td_list
, list
)
150 uhci_remove_td_from_frame_list(uhci
, td
);
154 static struct uhci_qh
*uhci_alloc_qh(struct uhci_hcd
*uhci
,
155 struct usb_device
*udev
, struct usb_host_endpoint
*hep
)
157 dma_addr_t dma_handle
;
160 qh
= dma_pool_alloc(uhci
->qh_pool
, GFP_ATOMIC
, &dma_handle
);
164 qh
->dma_handle
= dma_handle
;
166 qh
->element
= UHCI_PTR_TERM
;
167 qh
->link
= UHCI_PTR_TERM
;
169 INIT_LIST_HEAD(&qh
->queue
);
170 INIT_LIST_HEAD(&qh
->node
);
172 if (udev
) { /* Normal QH */
173 qh
->dummy_td
= uhci_alloc_td(uhci
);
175 dma_pool_free(uhci
->qh_pool
, qh
, dma_handle
);
178 qh
->state
= QH_STATE_IDLE
;
183 } else { /* Skeleton QH */
184 qh
->state
= QH_STATE_ACTIVE
;
190 static void uhci_free_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
192 WARN_ON(qh
->state
!= QH_STATE_IDLE
&& qh
->udev
);
193 if (!list_empty(&qh
->queue
))
194 dev_warn(uhci_dev(uhci
), "qh %p list not empty!\n", qh
);
198 qh
->hep
->hcpriv
= NULL
;
199 uhci_free_td(uhci
, qh
->dummy_td
);
201 dma_pool_free(uhci
->qh_pool
, qh
, qh
->dma_handle
);
205 * When the currently executing URB is dequeued, save its current toggle value
207 static void uhci_save_toggle(struct uhci_qh
*qh
, struct urb
*urb
)
209 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
212 /* If the QH element pointer is UHCI_PTR_TERM then then currently
213 * executing URB has already been unlinked, so this one isn't it. */
214 if (qh_element(qh
) == UHCI_PTR_TERM
||
215 qh
->queue
.next
!= &urbp
->node
)
217 qh
->element
= UHCI_PTR_TERM
;
219 /* Only bulk and interrupt pipes have to worry about toggles */
220 if (!(usb_pipetype(urb
->pipe
) == PIPE_BULK
||
221 usb_pipetype(urb
->pipe
) == PIPE_INTERRUPT
))
224 /* Find the first active TD; that's the device's toggle state */
225 list_for_each_entry(td
, &urbp
->td_list
, list
) {
226 if (td_status(td
) & TD_CTRL_ACTIVE
) {
228 qh
->initial_toggle
= uhci_toggle(td_token(td
));
237 * Fix up the data toggles for URBs in a queue, when one of them
238 * terminates early (short transfer, error, or dequeued).
240 static void uhci_fixup_toggles(struct uhci_qh
*qh
, int skip_first
)
242 struct urb_priv
*urbp
= NULL
;
244 unsigned int toggle
= qh
->initial_toggle
;
247 /* Fixups for a short transfer start with the second URB in the
248 * queue (the short URB is the first). */
250 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
252 /* When starting with the first URB, if the QH element pointer is
253 * still valid then we know the URB's toggles are okay. */
254 else if (qh_element(qh
) != UHCI_PTR_TERM
)
257 /* Fix up the toggle for the URBs in the queue. Normally this
258 * loop won't run more than once: When an error or short transfer
259 * occurs, the queue usually gets emptied. */
260 urbp
= list_prepare_entry(urbp
, &qh
->queue
, node
);
261 list_for_each_entry_continue(urbp
, &qh
->queue
, node
) {
263 /* If the first TD has the right toggle value, we don't
264 * need to change any toggles in this URB */
265 td
= list_entry(urbp
->td_list
.next
, struct uhci_td
, list
);
266 if (toggle
> 1 || uhci_toggle(td_token(td
)) == toggle
) {
267 td
= list_entry(urbp
->td_list
.next
, struct uhci_td
,
269 toggle
= uhci_toggle(td_token(td
)) ^ 1;
271 /* Otherwise all the toggles in the URB have to be switched */
273 list_for_each_entry(td
, &urbp
->td_list
, list
) {
274 td
->token
^= __constant_cpu_to_le32(
282 pipe
= list_entry(qh
->queue
.next
, struct urb_priv
, node
)->urb
->pipe
;
283 usb_settoggle(qh
->udev
, usb_pipeendpoint(pipe
),
284 usb_pipeout(pipe
), toggle
);
289 * Put a QH on the schedule in both hardware and software
291 static void uhci_activate_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
295 WARN_ON(list_empty(&qh
->queue
));
297 /* Set the element pointer if it isn't set already.
298 * This isn't needed for Isochronous queues, but it doesn't hurt. */
299 if (qh_element(qh
) == UHCI_PTR_TERM
) {
300 struct urb_priv
*urbp
= list_entry(qh
->queue
.next
,
301 struct urb_priv
, node
);
302 struct uhci_td
*td
= list_entry(urbp
->td_list
.next
,
303 struct uhci_td
, list
);
305 qh
->element
= cpu_to_le32(td
->dma_handle
);
308 if (qh
->state
== QH_STATE_ACTIVE
)
310 qh
->state
= QH_STATE_ACTIVE
;
312 /* Move the QH from its old list to the end of the appropriate
314 if (qh
== uhci
->next_qh
)
315 uhci
->next_qh
= list_entry(qh
->node
.next
, struct uhci_qh
,
317 list_move_tail(&qh
->node
, &qh
->skel
->node
);
319 /* Link it into the schedule */
320 pqh
= list_entry(qh
->node
.prev
, struct uhci_qh
, node
);
321 qh
->link
= pqh
->link
;
323 pqh
->link
= UHCI_PTR_QH
| cpu_to_le32(qh
->dma_handle
);
327 * Take a QH off the hardware schedule
329 static void uhci_unlink_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
333 if (qh
->state
== QH_STATE_UNLINKING
)
335 WARN_ON(qh
->state
!= QH_STATE_ACTIVE
|| !qh
->udev
);
336 qh
->state
= QH_STATE_UNLINKING
;
338 /* Unlink the QH from the schedule and record when we did it */
339 pqh
= list_entry(qh
->node
.prev
, struct uhci_qh
, node
);
340 pqh
->link
= qh
->link
;
343 uhci_get_current_frame_number(uhci
);
344 qh
->unlink_frame
= uhci
->frame_number
;
346 /* Force an interrupt so we know when the QH is fully unlinked */
347 if (list_empty(&uhci
->skel_unlink_qh
->node
))
348 uhci_set_next_interrupt(uhci
);
350 /* Move the QH from its old list to the end of the unlinking list */
351 if (qh
== uhci
->next_qh
)
352 uhci
->next_qh
= list_entry(qh
->node
.next
, struct uhci_qh
,
354 list_move_tail(&qh
->node
, &uhci
->skel_unlink_qh
->node
);
358 * When we and the controller are through with a QH, it becomes IDLE.
359 * This happens when a QH has been off the schedule (on the unlinking
360 * list) for more than one frame, or when an error occurs while adding
361 * the first URB onto a new QH.
363 static void uhci_make_qh_idle(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
365 WARN_ON(qh
->state
== QH_STATE_ACTIVE
);
367 if (qh
== uhci
->next_qh
)
368 uhci
->next_qh
= list_entry(qh
->node
.next
, struct uhci_qh
,
370 list_move(&qh
->node
, &uhci
->idle_qh_list
);
371 qh
->state
= QH_STATE_IDLE
;
373 /* If anyone is waiting for a QH to become idle, wake them up */
374 if (uhci
->num_waiting
)
375 wake_up_all(&uhci
->waitqh
);
378 static inline struct urb_priv
*uhci_alloc_urb_priv(struct uhci_hcd
*uhci
,
381 struct urb_priv
*urbp
;
383 urbp
= kmem_cache_alloc(uhci_up_cachep
, SLAB_ATOMIC
);
387 memset((void *)urbp
, 0, sizeof(*urbp
));
392 INIT_LIST_HEAD(&urbp
->node
);
393 INIT_LIST_HEAD(&urbp
->td_list
);
398 static void uhci_add_td_to_urb(struct urb
*urb
, struct uhci_td
*td
)
400 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
402 list_add_tail(&td
->list
, &urbp
->td_list
);
405 static void uhci_remove_td_from_urb(struct uhci_td
*td
)
407 if (list_empty(&td
->list
))
410 list_del_init(&td
->list
);
413 static void uhci_free_urb_priv(struct uhci_hcd
*uhci
,
414 struct urb_priv
*urbp
)
416 struct uhci_td
*td
, *tmp
;
418 if (!list_empty(&urbp
->node
))
419 dev_warn(uhci_dev(uhci
), "urb %p still on QH's list!\n",
422 uhci_get_current_frame_number(uhci
);
423 if (uhci
->frame_number
+ uhci
->is_stopped
!= uhci
->td_remove_age
) {
424 uhci_free_pending_tds(uhci
);
425 uhci
->td_remove_age
= uhci
->frame_number
;
428 /* Check to see if the remove list is empty. Set the IOC bit */
429 /* to force an interrupt so we can remove the TDs. */
430 if (list_empty(&uhci
->td_remove_list
))
431 uhci_set_next_interrupt(uhci
);
433 list_for_each_entry_safe(td
, tmp
, &urbp
->td_list
, list
) {
434 uhci_remove_td_from_urb(td
);
435 list_add(&td
->remove_list
, &uhci
->td_remove_list
);
438 urbp
->urb
->hcpriv
= NULL
;
439 kmem_cache_free(uhci_up_cachep
, urbp
);
442 static void uhci_inc_fsbr(struct uhci_hcd
*uhci
, struct urb
*urb
)
444 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
446 if ((!(urb
->transfer_flags
& URB_NO_FSBR
)) && !urbp
->fsbr
) {
448 if (!uhci
->fsbr
++ && !uhci
->fsbrtimeout
)
449 uhci
->skel_term_qh
->link
= cpu_to_le32(uhci
->skel_fs_control_qh
->dma_handle
) | UHCI_PTR_QH
;
453 static void uhci_dec_fsbr(struct uhci_hcd
*uhci
, struct urb
*urb
)
455 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
457 if ((!(urb
->transfer_flags
& URB_NO_FSBR
)) && urbp
->fsbr
) {
460 uhci
->fsbrtimeout
= jiffies
+ FSBR_DELAY
;
465 * Map status to standard result codes
467 * <status> is (td_status(td) & 0xF60000), a.k.a.
468 * uhci_status_bits(td_status(td)).
469 * Note: <status> does not include the TD_CTRL_NAK bit.
470 * <dir_out> is True for output TDs and False for input TDs.
472 static int uhci_map_status(int status
, int dir_out
)
476 if (status
& TD_CTRL_BITSTUFF
) /* Bitstuff error */
478 if (status
& TD_CTRL_CRCTIMEO
) { /* CRC/Timeout */
484 if (status
& TD_CTRL_BABBLE
) /* Babble */
486 if (status
& TD_CTRL_DBUFERR
) /* Buffer error */
488 if (status
& TD_CTRL_STALLED
) /* Stalled */
490 WARN_ON(status
& TD_CTRL_ACTIVE
); /* Active */
497 static int uhci_submit_control(struct uhci_hcd
*uhci
, struct urb
*urb
,
501 unsigned long destination
, status
;
502 int maxsze
= le16_to_cpu(qh
->hep
->desc
.wMaxPacketSize
);
503 int len
= urb
->transfer_buffer_length
;
504 dma_addr_t data
= urb
->transfer_dma
;
507 /* The "pipe" thing contains the destination in bits 8--18 */
508 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | USB_PID_SETUP
;
510 /* 3 errors, dummy TD remains inactive */
511 status
= uhci_maxerr(3);
512 if (urb
->dev
->speed
== USB_SPEED_LOW
)
513 status
|= TD_CTRL_LS
;
516 * Build the TD for the control request setup packet
519 uhci_add_td_to_urb(urb
, td
);
520 uhci_fill_td(td
, status
, destination
| uhci_explen(8),
523 status
|= TD_CTRL_ACTIVE
;
526 * If direction is "send", change the packet ID from SETUP (0x2D)
527 * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
528 * set Short Packet Detect (SPD) for all data packets.
530 if (usb_pipeout(urb
->pipe
))
531 destination
^= (USB_PID_SETUP
^ USB_PID_OUT
);
533 destination
^= (USB_PID_SETUP
^ USB_PID_IN
);
534 status
|= TD_CTRL_SPD
;
541 int pktsze
= min(len
, maxsze
);
543 td
= uhci_alloc_td(uhci
);
546 *plink
= cpu_to_le32(td
->dma_handle
);
548 /* Alternate Data0/1 (start with Data1) */
549 destination
^= TD_TOKEN_TOGGLE
;
551 uhci_add_td_to_urb(urb
, td
);
552 uhci_fill_td(td
, status
, destination
| uhci_explen(pktsze
),
561 * Build the final TD for control status
563 td
= uhci_alloc_td(uhci
);
566 *plink
= cpu_to_le32(td
->dma_handle
);
569 * It's IN if the pipe is an output pipe or we're not expecting
572 destination
&= ~TD_TOKEN_PID_MASK
;
573 if (usb_pipeout(urb
->pipe
) || !urb
->transfer_buffer_length
)
574 destination
|= USB_PID_IN
;
576 destination
|= USB_PID_OUT
;
578 destination
|= TD_TOKEN_TOGGLE
; /* End in Data1 */
580 status
&= ~TD_CTRL_SPD
;
582 uhci_add_td_to_urb(urb
, td
);
583 uhci_fill_td(td
, status
| TD_CTRL_IOC
,
584 destination
| uhci_explen(0), 0);
588 * Build the new dummy TD and activate the old one
590 td
= uhci_alloc_td(uhci
);
593 *plink
= cpu_to_le32(td
->dma_handle
);
595 uhci_fill_td(td
, 0, USB_PID_OUT
| uhci_explen(0), 0);
597 qh
->dummy_td
->status
|= __constant_cpu_to_le32(TD_CTRL_ACTIVE
);
600 /* Low-speed transfers get a different queue, and won't hog the bus.
601 * Also, some devices enumerate better without FSBR; the easiest way
602 * to do that is to put URBs on the low-speed queue while the device
603 * isn't in the CONFIGURED state. */
604 if (urb
->dev
->speed
== USB_SPEED_LOW
||
605 urb
->dev
->state
!= USB_STATE_CONFIGURED
)
606 qh
->skel
= uhci
->skel_ls_control_qh
;
608 qh
->skel
= uhci
->skel_fs_control_qh
;
609 uhci_inc_fsbr(uhci
, urb
);
614 /* Remove the dummy TD from the td_list so it doesn't get freed */
615 uhci_remove_td_from_urb(qh
->dummy_td
);
620 * If control-IN transfer was short, the status packet wasn't sent.
621 * This routine changes the element pointer in the QH to point at the
622 * status TD. It's safe to do this even while the QH is live, because
623 * the hardware only updates the element pointer following a successful
624 * transfer. The inactive TD for the short packet won't cause an update,
625 * so the pointer won't get overwritten. The next time the controller
626 * sees this QH, it will send the status packet.
628 static int usb_control_retrigger_status(struct uhci_hcd
*uhci
, struct urb
*urb
)
630 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
633 urbp
->short_transfer
= 1;
635 td
= list_entry(urbp
->td_list
.prev
, struct uhci_td
, list
);
636 urbp
->qh
->element
= cpu_to_le32(td
->dma_handle
);
642 static int uhci_result_control(struct uhci_hcd
*uhci
, struct urb
*urb
)
644 struct list_head
*tmp
, *head
;
645 struct urb_priv
*urbp
= urb
->hcpriv
;
650 head
= &urbp
->td_list
;
651 if (urbp
->short_transfer
) {
656 urb
->actual_length
= 0;
659 td
= list_entry(tmp
, struct uhci_td
, list
);
661 /* The first TD is the SETUP stage, check the status, but skip */
663 status
= uhci_status_bits(td_status(td
));
664 if (status
& TD_CTRL_ACTIVE
)
670 /* The rest of the TDs (but the last) are data */
672 while (tmp
!= head
&& tmp
->next
!= head
) {
673 unsigned int ctrlstat
;
675 td
= list_entry(tmp
, struct uhci_td
, list
);
678 ctrlstat
= td_status(td
);
679 status
= uhci_status_bits(ctrlstat
);
680 if (status
& TD_CTRL_ACTIVE
)
683 urb
->actual_length
+= uhci_actual_length(ctrlstat
);
688 /* Check to see if we received a short packet */
689 if (uhci_actual_length(ctrlstat
) <
690 uhci_expected_length(td_token(td
))) {
691 if (urb
->transfer_flags
& URB_SHORT_NOT_OK
) {
696 return usb_control_retrigger_status(uhci
, urb
);
701 td
= list_entry(tmp
, struct uhci_td
, list
);
703 /* Control status stage */
704 status
= td_status(td
);
706 #ifdef I_HAVE_BUGGY_APC_BACKUPS
707 /* APC BackUPS Pro kludge */
708 /* It tries to send all of the descriptor instead of the amount */
710 if (status
& TD_CTRL_IOC
&& /* IOC is masked out by uhci_status_bits */
711 status
& TD_CTRL_ACTIVE
&&
712 status
& TD_CTRL_NAK
)
716 status
= uhci_status_bits(status
);
717 if (status
& TD_CTRL_ACTIVE
)
726 ret
= uhci_map_status(status
, uhci_packetout(td_token(td
)));
729 if ((debug
== 1 && ret
!= -EPIPE
) || debug
> 1) {
730 /* Some debugging code */
731 dev_dbg(uhci_dev(uhci
), "%s: failed with status %x\n",
732 __FUNCTION__
, status
);
735 /* Print the chain for debugging purposes */
736 uhci_show_qh(urbp
->qh
, errbuf
, ERRBUF_LEN
, 0);
741 /* Note that the queue has stopped */
742 urbp
->qh
->element
= UHCI_PTR_TERM
;
743 urbp
->qh
->is_stopped
= 1;
748 * Common submit for bulk and interrupt
750 static int uhci_submit_common(struct uhci_hcd
*uhci
, struct urb
*urb
,
754 unsigned long destination
, status
;
755 int maxsze
= le16_to_cpu(qh
->hep
->desc
.wMaxPacketSize
);
756 int len
= urb
->transfer_buffer_length
;
757 dma_addr_t data
= urb
->transfer_dma
;
764 /* The "pipe" thing contains the destination in bits 8--18 */
765 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | usb_packetid(urb
->pipe
);
766 toggle
= usb_gettoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
767 usb_pipeout(urb
->pipe
));
769 /* 3 errors, dummy TD remains inactive */
770 status
= uhci_maxerr(3);
771 if (urb
->dev
->speed
== USB_SPEED_LOW
)
772 status
|= TD_CTRL_LS
;
773 if (usb_pipein(urb
->pipe
))
774 status
|= TD_CTRL_SPD
;
781 do { /* Allow zero length packets */
784 if (len
<= pktsze
) { /* The last packet */
786 if (!(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
787 status
&= ~TD_CTRL_SPD
;
791 td
= uhci_alloc_td(uhci
);
794 *plink
= cpu_to_le32(td
->dma_handle
);
796 uhci_add_td_to_urb(urb
, td
);
797 uhci_fill_td(td
, status
,
798 destination
| uhci_explen(pktsze
) |
799 (toggle
<< TD_TOKEN_TOGGLE_SHIFT
),
802 status
|= TD_CTRL_ACTIVE
;
810 * URB_ZERO_PACKET means adding a 0-length packet, if direction
811 * is OUT and the transfer_length was an exact multiple of maxsze,
812 * hence (len = transfer_length - N * maxsze) == 0
813 * however, if transfer_length == 0, the zero packet was already
816 if ((urb
->transfer_flags
& URB_ZERO_PACKET
) &&
817 usb_pipeout(urb
->pipe
) && len
== 0 &&
818 urb
->transfer_buffer_length
> 0) {
819 td
= uhci_alloc_td(uhci
);
822 *plink
= cpu_to_le32(td
->dma_handle
);
824 uhci_add_td_to_urb(urb
, td
);
825 uhci_fill_td(td
, status
,
826 destination
| uhci_explen(0) |
827 (toggle
<< TD_TOKEN_TOGGLE_SHIFT
),
834 /* Set the interrupt-on-completion flag on the last packet.
835 * A more-or-less typical 4 KB URB (= size of one memory page)
836 * will require about 3 ms to transfer; that's a little on the
837 * fast side but not enough to justify delaying an interrupt
838 * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
840 td
->status
|= __constant_cpu_to_le32(TD_CTRL_IOC
);
843 * Build the new dummy TD and activate the old one
845 td
= uhci_alloc_td(uhci
);
848 *plink
= cpu_to_le32(td
->dma_handle
);
850 uhci_fill_td(td
, 0, USB_PID_OUT
| uhci_explen(0), 0);
852 qh
->dummy_td
->status
|= __constant_cpu_to_le32(TD_CTRL_ACTIVE
);
855 usb_settoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
856 usb_pipeout(urb
->pipe
), toggle
);
860 /* Remove the dummy TD from the td_list so it doesn't get freed */
861 uhci_remove_td_from_urb(qh
->dummy_td
);
866 * Common result for bulk and interrupt
868 static int uhci_result_common(struct uhci_hcd
*uhci
, struct urb
*urb
)
870 struct urb_priv
*urbp
= urb
->hcpriv
;
872 unsigned int status
= 0;
875 urb
->actual_length
= 0;
877 list_for_each_entry(td
, &urbp
->td_list
, list
) {
878 unsigned int ctrlstat
= td_status(td
);
880 status
= uhci_status_bits(ctrlstat
);
881 if (status
& TD_CTRL_ACTIVE
)
884 urb
->actual_length
+= uhci_actual_length(ctrlstat
);
889 if (uhci_actual_length(ctrlstat
) <
890 uhci_expected_length(td_token(td
))) {
891 if (urb
->transfer_flags
& URB_SHORT_NOT_OK
) {
897 * This URB stopped short of its end. We have to
898 * fix up the toggles of the following URBs on the
899 * queue and restart the queue.
901 * Do this only the first time we encounter the
904 if (!urbp
->short_transfer
) {
905 urbp
->short_transfer
= 1;
906 urbp
->qh
->initial_toggle
=
907 uhci_toggle(td_token(td
)) ^ 1;
908 uhci_fixup_toggles(urbp
->qh
, 1);
910 td
= list_entry(urbp
->td_list
.prev
,
911 struct uhci_td
, list
);
912 urbp
->qh
->element
= td
->link
;
921 ret
= uhci_map_status(status
, uhci_packetout(td_token(td
)));
923 if ((debug
== 1 && ret
!= -EPIPE
) || debug
> 1) {
924 /* Some debugging code */
925 dev_dbg(uhci_dev(uhci
), "%s: failed with status %x\n",
926 __FUNCTION__
, status
);
928 if (debug
> 1 && errbuf
) {
929 /* Print the chain for debugging purposes */
930 uhci_show_qh(urbp
->qh
, errbuf
, ERRBUF_LEN
, 0);
936 /* Note that the queue has stopped and save the next toggle value */
937 urbp
->qh
->element
= UHCI_PTR_TERM
;
938 urbp
->qh
->is_stopped
= 1;
939 urbp
->qh
->needs_fixup
= 1;
940 urbp
->qh
->initial_toggle
= uhci_toggle(td_token(td
)) ^
945 static inline int uhci_submit_bulk(struct uhci_hcd
*uhci
, struct urb
*urb
,
950 /* Can't have low-speed bulk transfers */
951 if (urb
->dev
->speed
== USB_SPEED_LOW
)
954 qh
->skel
= uhci
->skel_bulk_qh
;
955 ret
= uhci_submit_common(uhci
, urb
, qh
);
957 uhci_inc_fsbr(uhci
, urb
);
961 static inline int uhci_submit_interrupt(struct uhci_hcd
*uhci
, struct urb
*urb
,
964 /* USB 1.1 interrupt transfers only involve one packet per interval.
965 * Drivers can submit URBs of any length, but longer ones will need
966 * multiple intervals to complete.
968 qh
->skel
= uhci
->skelqh
[__interval_to_skel(urb
->interval
)];
969 return uhci_submit_common(uhci
, urb
, qh
);
973 * Isochronous transfers
975 static int uhci_submit_isochronous(struct uhci_hcd
*uhci
, struct urb
*urb
,
978 struct uhci_td
*td
= NULL
; /* Since urb->number_of_packets > 0 */
980 unsigned long destination
, status
;
981 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
983 if (urb
->number_of_packets
> 900) /* 900? Why? */
986 status
= TD_CTRL_ACTIVE
| TD_CTRL_IOS
;
987 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | usb_packetid(urb
->pipe
);
989 /* Figure out the starting frame number */
990 if (urb
->transfer_flags
& URB_ISO_ASAP
) {
991 if (list_empty(&qh
->queue
)) {
992 uhci_get_current_frame_number(uhci
);
993 urb
->start_frame
= (uhci
->frame_number
+ 10);
995 } else { /* Go right after the last one */
996 struct urb
*last_urb
;
998 last_urb
= list_entry(qh
->queue
.prev
,
999 struct urb_priv
, node
)->urb
;
1000 urb
->start_frame
= (last_urb
->start_frame
+
1001 last_urb
->number_of_packets
*
1002 last_urb
->interval
);
1005 /* FIXME: Sanity check */
1007 urb
->start_frame
&= (UHCI_NUMFRAMES
- 1);
1009 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
1010 td
= uhci_alloc_td(uhci
);
1014 uhci_add_td_to_urb(urb
, td
);
1015 uhci_fill_td(td
, status
, destination
|
1016 uhci_explen(urb
->iso_frame_desc
[i
].length
),
1018 urb
->iso_frame_desc
[i
].offset
);
1021 /* Set the interrupt-on-completion flag on the last packet. */
1022 td
->status
|= __constant_cpu_to_le32(TD_CTRL_IOC
);
1024 qh
->skel
= uhci
->skel_iso_qh
;
1026 /* Add the TDs to the frame list */
1027 frame
= urb
->start_frame
;
1028 list_for_each_entry(td
, &urbp
->td_list
, list
) {
1029 uhci_insert_td_in_frame_list(uhci
, td
, frame
);
1030 frame
+= urb
->interval
;
1036 static int uhci_result_isochronous(struct uhci_hcd
*uhci
, struct urb
*urb
)
1039 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
1043 urb
->actual_length
= urb
->error_count
= 0;
1046 list_for_each_entry(td
, &urbp
->td_list
, list
) {
1048 unsigned int ctrlstat
= td_status(td
);
1050 if (ctrlstat
& TD_CTRL_ACTIVE
)
1051 return -EINPROGRESS
;
1053 actlength
= uhci_actual_length(ctrlstat
);
1054 urb
->iso_frame_desc
[i
].actual_length
= actlength
;
1055 urb
->actual_length
+= actlength
;
1057 status
= uhci_map_status(uhci_status_bits(ctrlstat
),
1058 usb_pipeout(urb
->pipe
));
1059 urb
->iso_frame_desc
[i
].status
= status
;
1071 static int uhci_urb_enqueue(struct usb_hcd
*hcd
,
1072 struct usb_host_endpoint
*hep
,
1073 struct urb
*urb
, gfp_t mem_flags
)
1076 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1077 unsigned long flags
;
1078 struct urb_priv
*urbp
;
1082 spin_lock_irqsave(&uhci
->lock
, flags
);
1085 if (ret
!= -EINPROGRESS
) /* URB already unlinked! */
1089 urbp
= uhci_alloc_urb_priv(uhci
, urb
);
1094 qh
= (struct uhci_qh
*) hep
->hcpriv
;
1096 qh
= uhci_alloc_qh(uhci
, urb
->dev
, hep
);
1102 switch (usb_pipetype(urb
->pipe
)) {
1104 ret
= uhci_submit_control(uhci
, urb
, qh
);
1107 ret
= uhci_submit_bulk(uhci
, urb
, qh
);
1109 case PIPE_INTERRUPT
:
1110 if (list_empty(&qh
->queue
)) {
1111 bustime
= usb_check_bandwidth(urb
->dev
, urb
);
1115 ret
= uhci_submit_interrupt(uhci
, urb
, qh
);
1117 usb_claim_bandwidth(urb
->dev
, urb
, bustime
, 0);
1119 } else { /* inherit from parent */
1120 struct urb_priv
*eurbp
;
1122 eurbp
= list_entry(qh
->queue
.prev
, struct urb_priv
,
1124 urb
->bandwidth
= eurbp
->urb
->bandwidth
;
1125 ret
= uhci_submit_interrupt(uhci
, urb
, qh
);
1128 case PIPE_ISOCHRONOUS
:
1129 bustime
= usb_check_bandwidth(urb
->dev
, urb
);
1135 ret
= uhci_submit_isochronous(uhci
, urb
, qh
);
1137 usb_claim_bandwidth(urb
->dev
, urb
, bustime
, 1);
1141 goto err_submit_failed
;
1143 /* Add this URB to the QH */
1145 list_add_tail(&urbp
->node
, &qh
->queue
);
1147 /* If the new URB is the first and only one on this QH then either
1148 * the QH is new and idle or else it's unlinked and waiting to
1149 * become idle, so we can activate it right away. */
1150 if (qh
->queue
.next
== &urbp
->node
)
1151 uhci_activate_qh(uhci
, qh
);
1155 if (qh
->state
== QH_STATE_IDLE
)
1156 uhci_make_qh_idle(uhci
, qh
); /* Reclaim unused QH */
1159 uhci_free_urb_priv(uhci
, urbp
);
1162 spin_unlock_irqrestore(&uhci
->lock
, flags
);
1166 static int uhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
)
1168 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1169 unsigned long flags
;
1170 struct urb_priv
*urbp
;
1172 spin_lock_irqsave(&uhci
->lock
, flags
);
1174 if (!urbp
) /* URB was never linked! */
1177 /* Remove Isochronous TDs from the frame list ASAP */
1178 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
1179 uhci_unlink_isochronous_tds(uhci
, urb
);
1180 uhci_unlink_qh(uhci
, urbp
->qh
);
1183 spin_unlock_irqrestore(&uhci
->lock
, flags
);
1188 * Finish unlinking an URB and give it back
1190 static void uhci_giveback_urb(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
,
1191 struct urb
*urb
, struct pt_regs
*regs
)
1192 __releases(uhci
->lock
)
1193 __acquires(uhci
->lock
)
1195 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
1197 /* Isochronous TDs get unlinked directly from the frame list */
1198 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
1199 uhci_unlink_isochronous_tds(uhci
, urb
);
1201 /* If the URB isn't first on its queue, adjust the link pointer
1202 * of the last TD in the previous URB. */
1203 else if (qh
->queue
.next
!= &urbp
->node
) {
1204 struct urb_priv
*purbp
;
1205 struct uhci_td
*ptd
, *ltd
;
1207 purbp
= list_entry(urbp
->node
.prev
, struct urb_priv
, node
);
1208 ptd
= list_entry(purbp
->td_list
.prev
, struct uhci_td
,
1210 ltd
= list_entry(urbp
->td_list
.prev
, struct uhci_td
,
1212 ptd
->link
= ltd
->link
;
1215 /* Take the URB off the QH's queue. If the queue is now empty,
1216 * this is a perfect time for a toggle fixup. */
1217 list_del_init(&urbp
->node
);
1218 if (list_empty(&qh
->queue
) && qh
->needs_fixup
) {
1219 usb_settoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
1220 usb_pipeout(urb
->pipe
), qh
->initial_toggle
);
1221 qh
->needs_fixup
= 0;
1224 uhci_dec_fsbr(uhci
, urb
); /* Safe since it checks */
1225 uhci_free_urb_priv(uhci
, urbp
);
1227 switch (usb_pipetype(urb
->pipe
)) {
1228 case PIPE_ISOCHRONOUS
:
1229 /* Release bandwidth for Interrupt or Isoc. transfers */
1231 usb_release_bandwidth(urb
->dev
, urb
, 1);
1233 case PIPE_INTERRUPT
:
1234 /* Release bandwidth for Interrupt or Isoc. transfers */
1235 /* Make sure we don't release if we have a queued URB */
1236 if (list_empty(&qh
->queue
) && urb
->bandwidth
)
1237 usb_release_bandwidth(urb
->dev
, urb
, 0);
1239 /* bandwidth was passed on to queued URB, */
1240 /* so don't let usb_unlink_urb() release it */
1245 spin_unlock(&uhci
->lock
);
1246 usb_hcd_giveback_urb(uhci_to_hcd(uhci
), urb
, regs
);
1247 spin_lock(&uhci
->lock
);
1249 /* If the queue is now empty, we can unlink the QH and give up its
1250 * reserved bandwidth. */
1251 if (list_empty(&qh
->queue
)) {
1252 uhci_unlink_qh(uhci
, qh
);
1254 /* Bandwidth stuff not yet implemented */
1259 * Scan the URBs in a QH's queue
1261 #define QH_FINISHED_UNLINKING(qh) \
1262 (qh->state == QH_STATE_UNLINKING && \
1263 uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
1265 static void uhci_scan_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
,
1266 struct pt_regs
*regs
)
1268 struct urb_priv
*urbp
;
1272 while (!list_empty(&qh
->queue
)) {
1273 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
1276 switch (usb_pipetype(urb
->pipe
)) {
1278 status
= uhci_result_control(uhci
, urb
);
1280 case PIPE_ISOCHRONOUS
:
1281 status
= uhci_result_isochronous(uhci
, urb
);
1283 default: /* PIPE_BULK or PIPE_INTERRUPT */
1284 status
= uhci_result_common(uhci
, urb
);
1287 if (status
== -EINPROGRESS
)
1290 spin_lock(&urb
->lock
);
1291 if (urb
->status
== -EINPROGRESS
) /* Not dequeued */
1292 urb
->status
= status
;
1294 status
= -ECONNRESET
;
1295 spin_unlock(&urb
->lock
);
1297 /* Dequeued but completed URBs can't be given back unless
1298 * the QH is stopped or has finished unlinking. */
1299 if (status
== -ECONNRESET
&&
1300 !(qh
->is_stopped
|| QH_FINISHED_UNLINKING(qh
)))
1303 uhci_giveback_urb(uhci
, qh
, urb
, regs
);
1308 /* If the QH is neither stopped nor finished unlinking (normal case),
1309 * our work here is done. */
1311 if (!(qh
->is_stopped
|| QH_FINISHED_UNLINKING(qh
)))
1314 /* Otherwise give back each of the dequeued URBs */
1315 list_for_each_entry(urbp
, &qh
->queue
, node
) {
1317 if (urb
->status
!= -EINPROGRESS
) {
1318 uhci_save_toggle(qh
, urb
);
1319 uhci_giveback_urb(uhci
, qh
, urb
, regs
);
1325 /* There are no more dequeued URBs. If there are still URBs on the
1326 * queue, the QH can now be re-activated. */
1327 if (!list_empty(&qh
->queue
)) {
1328 if (qh
->needs_fixup
)
1329 uhci_fixup_toggles(qh
, 0);
1330 uhci_activate_qh(uhci
, qh
);
1333 /* The queue is empty. The QH can become idle if it is fully
1335 else if (QH_FINISHED_UNLINKING(qh
))
1336 uhci_make_qh_idle(uhci
, qh
);
1339 static void uhci_free_pending_tds(struct uhci_hcd
*uhci
)
1341 struct uhci_td
*td
, *tmp
;
1343 list_for_each_entry_safe(td
, tmp
, &uhci
->td_remove_list
, remove_list
) {
1344 list_del_init(&td
->remove_list
);
1346 uhci_free_td(uhci
, td
);
1351 * Process events in the schedule, but only in one thread at a time
1353 static void uhci_scan_schedule(struct uhci_hcd
*uhci
, struct pt_regs
*regs
)
1358 /* Don't allow re-entrant calls */
1359 if (uhci
->scan_in_progress
) {
1360 uhci
->need_rescan
= 1;
1363 uhci
->scan_in_progress
= 1;
1365 uhci
->need_rescan
= 0;
1367 uhci_clear_next_interrupt(uhci
);
1368 uhci_get_current_frame_number(uhci
);
1370 if (uhci
->frame_number
+ uhci
->is_stopped
!= uhci
->td_remove_age
)
1371 uhci_free_pending_tds(uhci
);
1373 /* Go through all the QH queues and process the URBs in each one */
1374 for (i
= 0; i
< UHCI_NUM_SKELQH
- 1; ++i
) {
1375 uhci
->next_qh
= list_entry(uhci
->skelqh
[i
]->node
.next
,
1376 struct uhci_qh
, node
);
1377 while ((qh
= uhci
->next_qh
) != uhci
->skelqh
[i
]) {
1378 uhci
->next_qh
= list_entry(qh
->node
.next
,
1379 struct uhci_qh
, node
);
1380 uhci_scan_qh(uhci
, qh
, regs
);
1384 if (uhci
->need_rescan
)
1386 uhci
->scan_in_progress
= 0;
1388 /* If the controller is stopped, we can finish these off right now */
1389 if (uhci
->is_stopped
)
1390 uhci_free_pending_tds(uhci
);
1392 if (list_empty(&uhci
->td_remove_list
) &&
1393 list_empty(&uhci
->skel_unlink_qh
->node
))
1394 uhci_clear_next_interrupt(uhci
);
1396 uhci_set_next_interrupt(uhci
);
1399 static void check_fsbr(struct uhci_hcd
*uhci
)
1401 /* For now, don't scan URBs for FSBR timeouts.
1402 * Add it back in later... */
1404 /* Really disable FSBR */
1405 if (!uhci
->fsbr
&& uhci
->fsbrtimeout
&& time_after_eq(jiffies
, uhci
->fsbrtimeout
)) {
1406 uhci
->fsbrtimeout
= 0;
1407 uhci
->skel_term_qh
->link
= UHCI_PTR_TERM
;