drivers/video/cg6.c

   1 /* cg6.c: CGSIX (GX, GXplus, TGX) frame buffer driver
   2  *
   3  * Copyright (C) 2003 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
   5  * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
   6  * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
   7  *
   8  * Driver layout based loosely on tgafb.c, see that file for credits.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/errno.h>
  14 #include <linux/string.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/fb.h>
  19 #include <linux/mm.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/sbus.h>
  23 #include <asm/oplib.h>
  24 #include <asm/fbio.h>
  25
  26 #include "sbuslib.h"
  27
  28 /*
  29  * Local functions.
  30  */
  31
  32 static int cg6_setcolreg(unsigned, unsigned, unsigned, unsigned,
  33                          unsigned, struct fb_info *);
  34 static int cg6_blank(int, struct fb_info *);
  35
  36 static void cg6_imageblit(struct fb_info *, const struct fb_image *);
  37 static void cg6_fillrect(struct fb_info *, const struct fb_fillrect *);
  38 static int cg6_sync(struct fb_info *);
  39 static int cg6_mmap(struct fb_info *, struct vm_area_struct *);
  40 static int cg6_ioctl(struct fb_info *, unsigned int, unsigned long);
  41
  42 /*
  43  *  Frame buffer operations
  44  */
  45
  46 static struct fb_ops cg6_ops = {
  47         .owner                  = THIS_MODULE,
  48         .fb_setcolreg           = cg6_setcolreg,
  49         .fb_blank               = cg6_blank,
  50         .fb_fillrect            = cg6_fillrect,
  51         .fb_copyarea            = cfb_copyarea,
  52         .fb_imageblit           = cg6_imageblit,
  53         .fb_sync                = cg6_sync,
  54         .fb_mmap                = cg6_mmap,
  55         .fb_ioctl               = cg6_ioctl,
  56 #ifdef CONFIG_COMPAT
  57         .fb_compat_ioctl        = sbusfb_compat_ioctl,
  58 #endif
  59 };
  60
  61 /* Offset of interesting structures in the OBIO space */
  62 /*
  63  * Brooktree is the video dac and is funny to program on the cg6.
  64  * (it's even funnier on the cg3)
  65  * The FBC could be the frame buffer control
  66  * The FHC could is the frame buffer hardware control.
  67  */
  68 #define CG6_ROM_OFFSET       0x0UL
  69 #define CG6_BROOKTREE_OFFSET 0x200000UL
  70 #define CG6_DHC_OFFSET       0x240000UL
  71 #define CG6_ALT_OFFSET       0x280000UL
  72 #define CG6_FHC_OFFSET       0x300000UL
  73 #define CG6_THC_OFFSET       0x301000UL
  74 #define CG6_FBC_OFFSET       0x700000UL
  75 #define CG6_TEC_OFFSET       0x701000UL
  76 #define CG6_RAM_OFFSET       0x800000UL
  77
  78 /* FHC definitions */
  79 #define CG6_FHC_FBID_SHIFT           24
  80 #define CG6_FHC_FBID_MASK            255
  81 #define CG6_FHC_REV_SHIFT            20
  82 #define CG6_FHC_REV_MASK             15
  83 #define CG6_FHC_FROP_DISABLE         (1 << 19)
  84 #define CG6_FHC_ROW_DISABLE          (1 << 18)
  85 #define CG6_FHC_SRC_DISABLE          (1 << 17)
  86 #define CG6_FHC_DST_DISABLE          (1 << 16)
  87 #define CG6_FHC_RESET                (1 << 15)
  88 #define CG6_FHC_LITTLE_ENDIAN        (1 << 13)
  89 #define CG6_FHC_RES_MASK             (3 << 11)
  90 #define CG6_FHC_1024                 (0 << 11)
  91 #define CG6_FHC_1152                 (1 << 11)
  92 #define CG6_FHC_1280                 (2 << 11)
  93 #define CG6_FHC_1600                 (3 << 11)
  94 #define CG6_FHC_CPU_MASK             (3 << 9)
  95 #define CG6_FHC_CPU_SPARC            (0 << 9)
  96 #define CG6_FHC_CPU_68020            (1 << 9)
  97 #define CG6_FHC_CPU_386              (2 << 9)
  98 #define CG6_FHC_TEST                 (1 << 8)
  99 #define CG6_FHC_TEST_X_SHIFT         4
 100 #define CG6_FHC_TEST_X_MASK          15
 101 #define CG6_FHC_TEST_Y_SHIFT         0
 102 #define CG6_FHC_TEST_Y_MASK          15
 103
 104 /* FBC mode definitions */
 105 #define CG6_FBC_BLIT_IGNORE             0x00000000
 106 #define CG6_FBC_BLIT_NOSRC              0x00100000
 107 #define CG6_FBC_BLIT_SRC                0x00200000
 108 #define CG6_FBC_BLIT_ILLEGAL            0x00300000
 109 #define CG6_FBC_BLIT_MASK               0x00300000
 110
 111 #define CG6_FBC_VBLANK                  0x00080000
 112
 113 #define CG6_FBC_MODE_IGNORE             0x00000000
 114 #define CG6_FBC_MODE_COLOR8             0x00020000
 115 #define CG6_FBC_MODE_COLOR1             0x00040000
 116 #define CG6_FBC_MODE_HRMONO             0x00060000
 117 #define CG6_FBC_MODE_MASK               0x00060000
 118
 119 #define CG6_FBC_DRAW_IGNORE             0x00000000
 120 #define CG6_FBC_DRAW_RENDER             0x00008000
 121 #define CG6_FBC_DRAW_PICK               0x00010000
 122 #define CG6_FBC_DRAW_ILLEGAL            0x00018000
 123 #define CG6_FBC_DRAW_MASK               0x00018000
 124
 125 #define CG6_FBC_BWRITE0_IGNORE          0x00000000
 126 #define CG6_FBC_BWRITE0_ENABLE          0x00002000
 127 #define CG6_FBC_BWRITE0_DISABLE         0x00004000
 128 #define CG6_FBC_BWRITE0_ILLEGAL         0x00006000
 129 #define CG6_FBC_BWRITE0_MASK            0x00006000
 130
 131 #define CG6_FBC_BWRITE1_IGNORE          0x00000000
 132 #define CG6_FBC_BWRITE1_ENABLE          0x00000800
 133 #define CG6_FBC_BWRITE1_DISABLE         0x00001000
 134 #define CG6_FBC_BWRITE1_ILLEGAL         0x00001800
 135 #define CG6_FBC_BWRITE1_MASK            0x00001800
 136
 137 #define CG6_FBC_BREAD_IGNORE            0x00000000
 138 #define CG6_FBC_BREAD_0                 0x00000200
 139 #define CG6_FBC_BREAD_1                 0x00000400
 140 #define CG6_FBC_BREAD_ILLEGAL           0x00000600
 141 #define CG6_FBC_BREAD_MASK              0x00000600
 142
 143 #define CG6_FBC_BDISP_IGNORE            0x00000000
 144 #define CG6_FBC_BDISP_0                 0x00000080
 145 #define CG6_FBC_BDISP_1                 0x00000100
 146 #define CG6_FBC_BDISP_ILLEGAL           0x00000180
 147 #define CG6_FBC_BDISP_MASK              0x00000180
 148
 149 #define CG6_FBC_INDEX_MOD               0x00000040
 150 #define CG6_FBC_INDEX_MASK              0x00000030
 151
 152 /* THC definitions */
 153 #define CG6_THC_MISC_REV_SHIFT       16
 154 #define CG6_THC_MISC_REV_MASK        15
 155 #define CG6_THC_MISC_RESET           (1 << 12)
 156 #define CG6_THC_MISC_VIDEO           (1 << 10)
 157 #define CG6_THC_MISC_SYNC            (1 << 9)
 158 #define CG6_THC_MISC_VSYNC           (1 << 8)
 159 #define CG6_THC_MISC_SYNC_ENAB       (1 << 7)
 160 #define CG6_THC_MISC_CURS_RES        (1 << 6)
 161 #define CG6_THC_MISC_INT_ENAB        (1 << 5)
 162 #define CG6_THC_MISC_INT             (1 << 4)
 163 #define CG6_THC_MISC_INIT            0x9f
 164
 165 /* The contents are unknown */
 166 struct cg6_tec {
 167         volatile int tec_matrix;
 168         volatile int tec_clip;
 169         volatile int tec_vdc;
 170 };
 171
 172 struct cg6_thc {
 173         uint thc_pad0[512];
 174         volatile uint thc_hs;           /* hsync timing */
 175         volatile uint thc_hsdvs;
 176         volatile uint thc_hd;
 177         volatile uint thc_vs;           /* vsync timing */
 178         volatile uint thc_vd;
 179         volatile uint thc_refresh;
 180         volatile uint thc_misc;
 181         uint thc_pad1[56];
 182         volatile uint thc_cursxy;       /* cursor x,y position (16 bits each) */
 183         volatile uint thc_cursmask[32]; /* cursor mask bits */
 184         volatile uint thc_cursbits[32]; /* what to show where mask enabled */
 185 };
 186
 187 struct cg6_fbc {
 188         u32             xxx0[1];
 189         volatile u32    mode;
 190         volatile u32    clip;
 191         u32             xxx1[1];
 192         volatile u32    s;
 193         volatile u32    draw;
 194         volatile u32    blit;
 195         volatile u32    font;
 196         u32             xxx2[24];
 197         volatile u32    x0, y0, z0, color0;
 198         volatile u32    x1, y1, z1, color1;
 199         volatile u32    x2, y2, z2, color2;
 200         volatile u32    x3, y3, z3, color3;
 201         volatile u32    offx, offy;
 202         u32             xxx3[2];
 203         volatile u32    incx, incy;
 204         u32             xxx4[2];
 205         volatile u32    clipminx, clipminy;
 206         u32             xxx5[2];
 207         volatile u32    clipmaxx, clipmaxy;
 208         u32             xxx6[2];
 209         volatile u32    fg;
 210         volatile u32    bg;
 211         volatile u32    alu;
 212         volatile u32    pm;
 213         volatile u32    pixelm;
 214         u32             xxx7[2];
 215         volatile u32    patalign;
 216         volatile u32    pattern[8];
 217         u32             xxx8[432];
 218         volatile u32    apointx, apointy, apointz;
 219         u32             xxx9[1];
 220         volatile u32    rpointx, rpointy, rpointz;
 221         u32             xxx10[5];
 222         volatile u32    pointr, pointg, pointb, pointa;
 223         volatile u32    alinex, aliney, alinez;
 224         u32             xxx11[1];
 225         volatile u32    rlinex, rliney, rlinez;
 226         u32             xxx12[5];
 227         volatile u32    liner, lineg, lineb, linea;
 228         volatile u32    atrix, atriy, atriz;
 229         u32             xxx13[1];
 230         volatile u32    rtrix, rtriy, rtriz;
 231         u32             xxx14[5];
 232         volatile u32    trir, trig, trib, tria;
 233         volatile u32    aquadx, aquady, aquadz;
 234         u32             xxx15[1];
 235         volatile u32    rquadx, rquady, rquadz;
 236         u32             xxx16[5];
 237         volatile u32    quadr, quadg, quadb, quada;
 238         volatile u32    arectx, arecty, arectz;
 239         u32             xxx17[1];
 240         volatile u32    rrectx, rrecty, rrectz;
 241         u32             xxx18[5];
 242         volatile u32    rectr, rectg, rectb, recta;
 243 };
 244
 245 struct bt_regs {
 246         volatile u32 addr;
 247         volatile u32 color_map;
 248         volatile u32 control;
 249         volatile u32 cursor;
 250 };
 251
 252 struct cg6_par {
 253         spinlock_t              lock;
 254         struct bt_regs          __iomem *bt;
 255         struct cg6_fbc          __iomem *fbc;
 256         struct cg6_thc          __iomem *thc;
 257         struct cg6_tec          __iomem *tec;
 258         volatile u32            __iomem *fhc;
 259
 260         u32                     flags;
 261 #define CG6_FLAG_BLANKED        0x00000001
 262
 263         unsigned long           physbase;
 264         unsigned long           fbsize;
 265
 266         struct sbus_dev         *sdev;
 267 };
 268
 269 static int cg6_sync(struct fb_info *info)
 270 {
 271         struct cg6_par *par = (struct cg6_par *) info->par;
 272         struct cg6_fbc __iomem *fbc = par->fbc;
 273         int limit = 10000;
 274
 275         do {
 276                 if (!(sbus_readl(&fbc->s) & 0x10000000))
 277                         break;
 278                 udelay(10);
 279         } while (--limit > 0);
 280
 281         return 0;
 282 }
 283
 284 /**
 285  *      cg6_fillrect - REQUIRED function. Can use generic routines if
 286  *                     non acclerated hardware and packed pixel based.
 287  *                     Draws a rectangle on the screen.
 288  *
 289  *      @info: frame buffer structure that represents a single frame buffer
 290  *      @rect: structure defining the rectagle and operation.
 291  */
 292 static void cg6_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 293 {
 294         struct cg6_par *par = (struct cg6_par *) info->par;
 295         struct cg6_fbc __iomem *fbc = par->fbc;
 296         unsigned long flags;
 297         s32 val;
 298
 299         /* XXX doesn't handle ROP_XOR */
 300
 301         spin_lock_irqsave(&par->lock, flags);
 302         cg6_sync(info);
 303         sbus_writel(rect->color, &fbc->fg);
 304         sbus_writel(~(u32)0, &fbc->pixelm);
 305         sbus_writel(0xea80ff00, &fbc->alu);
 306         sbus_writel(0, &fbc->s);
 307         sbus_writel(0, &fbc->clip);
 308         sbus_writel(~(u32)0, &fbc->pm);
 309         sbus_writel(rect->dy, &fbc->arecty);
 310         sbus_writel(rect->dx, &fbc->arectx);
 311         sbus_writel(rect->dy + rect->height, &fbc->arecty);
 312         sbus_writel(rect->dx + rect->width, &fbc->arectx);
 313         do {
 314                 val = sbus_readl(&fbc->draw);
 315         } while (val < 0 && (val & 0x20000000));
 316         spin_unlock_irqrestore(&par->lock, flags);
 317 }
 318
 319 /**
 320  *      cg6_imageblit - REQUIRED function. Can use generic routines if
 321  *                      non acclerated hardware and packed pixel based.
 322  *                      Copies a image from system memory to the screen.
 323  *
 324  *      @info: frame buffer structure that represents a single frame buffer
 325  *      @image: structure defining the image.
 326  */
 327 static void cg6_imageblit(struct fb_info *info, const struct fb_image *image)
 328 {
 329         struct cg6_par *par = (struct cg6_par *) info->par;
 330         struct cg6_fbc __iomem *fbc = par->fbc;
 331         const u8 *data = image->data;
 332         unsigned long flags;
 333         u32 x, y;
 334         int i, width;
 335
 336         if (image->depth > 1) {
 337                 cfb_imageblit(info, image);
 338                 return;
 339         }
 340
 341         spin_lock_irqsave(&par->lock, flags);
 342
 343         cg6_sync(info);
 344
 345         sbus_writel(image->fg_color, &fbc->fg);
 346         sbus_writel(image->bg_color, &fbc->bg);
 347         sbus_writel(0x140000, &fbc->mode);
 348         sbus_writel(0xe880fc30, &fbc->alu);
 349         sbus_writel(~(u32)0, &fbc->pixelm);
 350         sbus_writel(0, &fbc->s);
 351         sbus_writel(0, &fbc->clip);
 352         sbus_writel(0xff, &fbc->pm);
 353         sbus_writel(32, &fbc->incx);
 354         sbus_writel(0, &fbc->incy);
 355
 356         x = image->dx;
 357         y = image->dy;
 358         for (i = 0; i < image->height; i++) {
 359                 width = image->width;
 360
 361                 while (width >= 32) {
 362                         u32 val;
 363
 364                         sbus_writel(y, &fbc->y0);
 365                         sbus_writel(x, &fbc->x0);
 366                         sbus_writel(x + 32 - 1, &fbc->x1);
 367
 368                         val = ((u32)data[0] << 24) |
 369                               ((u32)data[1] << 16) |
 370                               ((u32)data[2] <<  8) |
 371                               ((u32)data[3] <<  0);
 372                         sbus_writel(val, &fbc->font);
 373
 374                         data += 4;
 375                         x += 32;
 376                         width -= 32;
 377                 }
 378                 if (width) {
 379                         u32 val;
 380
 381                         sbus_writel(y, &fbc->y0);
 382                         sbus_writel(x, &fbc->x0);
 383                         sbus_writel(x + width - 1, &fbc->x1);
 384                         if (width <= 8) {
 385                                 val = (u32) data[0] << 24;
 386                                 data += 1;
 387                         } else if (width <= 16) {
 388                                 val = ((u32) data[0] << 24) |
 389                                       ((u32) data[1] << 16);
 390                                 data += 2;
 391                         } else {
 392                                 val = ((u32) data[0] << 24) |
 393                                       ((u32) data[1] << 16) |
 394                                       ((u32) data[2] <<  8);
 395                                 data += 3;
 396                         }
 397                         sbus_writel(val, &fbc->font);
 398                 }
 399
 400                 y += 1;
 401                 x = image->dx;
 402         }
 403
 404         spin_unlock_irqrestore(&par->lock, flags);
 405 }
 406
 407 /**
 408  *      cg6_setcolreg - Optional function. Sets a color register.
 409  *      @regno: boolean, 0 copy local, 1 get_user() function
 410  *      @red: frame buffer colormap structure
 411  *      @green: The green value which can be up to 16 bits wide
 412  *      @blue:  The blue value which can be up to 16 bits wide.
 413  *      @transp: If supported the alpha value which can be up to 16 bits wide.
 414  *      @info: frame buffer info structure
 415  */
 416 static int cg6_setcolreg(unsigned regno,
 417                          unsigned red, unsigned green, unsigned blue,
 418                          unsigned transp, struct fb_info *info)
 419 {
 420         struct cg6_par *par = (struct cg6_par *) info->par;
 421         struct bt_regs __iomem *bt = par->bt;
 422         unsigned long flags;
 423
 424         if (regno >= 256)
 425                 return 1;
 426
 427         red >>= 8;
 428         green >>= 8;
 429         blue >>= 8;
 430
 431         spin_lock_irqsave(&par->lock, flags);
 432
 433         sbus_writel((u32)regno << 24, &bt->addr);
 434         sbus_writel((u32)red << 24, &bt->color_map);
 435         sbus_writel((u32)green << 24, &bt->color_map);
 436         sbus_writel((u32)blue << 24, &bt->color_map);
 437
 438         spin_unlock_irqrestore(&par->lock, flags);
 439
 440         return 0;
 441 }
 442
 443 /**
 444  *      cg6_blank - Optional function.  Blanks the display.
 445  *      @blank_mode: the blank mode we want.
 446  *      @info: frame buffer structure that represents a single frame buffer
 447  */
 448 static int
 449 cg6_blank(int blank, struct fb_info *info)
 450 {
 451         struct cg6_par *par = (struct cg6_par *) info->par;
 452         struct cg6_thc __iomem *thc = par->thc;
 453         unsigned long flags;
 454         u32 val;
 455
 456         spin_lock_irqsave(&par->lock, flags);
 457
 458         switch (blank) {
 459         case FB_BLANK_UNBLANK: /* Unblanking */
 460                 val = sbus_readl(&thc->thc_misc);
 461                 val |= CG6_THC_MISC_VIDEO;
 462                 sbus_writel(val, &thc->thc_misc);
 463                 par->flags &= ~CG6_FLAG_BLANKED;
 464                 break;
 465
 466         case FB_BLANK_NORMAL: /* Normal blanking */
 467         case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
 468         case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
 469         case FB_BLANK_POWERDOWN: /* Poweroff */
 470                 val = sbus_readl(&thc->thc_misc);
 471                 val &= ~CG6_THC_MISC_VIDEO;
 472                 sbus_writel(val, &thc->thc_misc);
 473                 par->flags |= CG6_FLAG_BLANKED;
 474                 break;
 475         }
 476
 477         spin_unlock_irqrestore(&par->lock, flags);
 478
 479         return 0;
 480 }
 481
 482 static struct sbus_mmap_map cg6_mmap_map[] = {
 483         {
 484                 .voff   = CG6_FBC,
 485                 .poff   = CG6_FBC_OFFSET,
 486                 .size   = PAGE_SIZE
 487         },
 488         {
 489                 .voff   = CG6_TEC,
 490                 .poff   = CG6_TEC_OFFSET,
 491                 .size   = PAGE_SIZE
 492         },
 493         {
 494                 .voff   = CG6_BTREGS,
 495                 .poff   = CG6_BROOKTREE_OFFSET,
 496                 .size   = PAGE_SIZE
 497         },
 498         {
 499                 .voff   = CG6_FHC,
 500                 .poff   = CG6_FHC_OFFSET,
 501                 .size   = PAGE_SIZE
 502         },
 503         {
 504                 .voff   = CG6_THC,
 505                 .poff   = CG6_THC_OFFSET,
 506                 .size   = PAGE_SIZE
 507         },
 508         {
 509                 .voff   = CG6_ROM,
 510                 .poff   = CG6_ROM_OFFSET,
 511                 .size   = 0x10000
 512         },
 513         {
 514                 .voff   = CG6_RAM,
 515                 .poff   = CG6_RAM_OFFSET,
 516                 .size   = SBUS_MMAP_FBSIZE(1)
 517         },
 518         {
 519                 .voff   = CG6_DHC,
 520                 .poff   = CG6_DHC_OFFSET,
 521                 .size   = 0x40000
 522         },
 523         { .size = 0 }
 524 };
 525
 526 static int cg6_mmap(struct fb_info *info, struct vm_area_struct *vma)
 527 {
 528         struct cg6_par *par = (struct cg6_par *)info->par;
 529
 530         return sbusfb_mmap_helper(cg6_mmap_map,
 531                                   par->physbase, par->fbsize,
 532                                   par->sdev->reg_addrs[0].which_io,
 533                                   vma);
 534 }
 535
 536 static int cg6_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
 537 {
 538         struct cg6_par *par = (struct cg6_par *) info->par;
 539
 540         return sbusfb_ioctl_helper(cmd, arg, info,
 541                                    FBTYPE_SUNFAST_COLOR, 8, par->fbsize);
 542 }
 543
 544 /*
 545  *  Initialisation
 546  */
 547
 548 static void
 549 cg6_init_fix(struct fb_info *info, int linebytes)
 550 {
 551         struct cg6_par *par = (struct cg6_par *)info->par;
 552         const char *cg6_cpu_name, *cg6_card_name;
 553         u32 conf;
 554
 555         conf = sbus_readl(par->fhc);
 556         switch(conf & CG6_FHC_CPU_MASK) {
 557         case CG6_FHC_CPU_SPARC:
 558                 cg6_cpu_name = "sparc";
 559                 break;
 560         case CG6_FHC_CPU_68020:
 561                 cg6_cpu_name = "68020";
 562                 break;
 563         default:
 564                 cg6_cpu_name = "i386";
 565                 break;
 566         };
 567         if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) {
 568                 if (par->fbsize <= 0x100000) {
 569                         cg6_card_name = "TGX";
 570                 } else {
 571                         cg6_card_name = "TGX+";
 572                 }
 573         } else {
 574                 if (par->fbsize <= 0x100000) {
 575                         cg6_card_name = "GX";
 576                 } else {
 577                         cg6_card_name = "GX+";
 578                 }
 579         }
 580
 581         sprintf(info->fix.id, "%s %s", cg6_card_name, cg6_cpu_name);
 582         info->fix.id[sizeof(info->fix.id)-1] = 0;
 583
 584         info->fix.type = FB_TYPE_PACKED_PIXELS;
 585         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 586
 587         info->fix.line_length = linebytes;
 588
 589         info->fix.accel = FB_ACCEL_SUN_CGSIX;
 590 }
 591
 592 /* Initialize Brooktree DAC */
 593 static void cg6_bt_init(struct cg6_par *par)
 594 {
 595         struct bt_regs __iomem *bt = par->bt;
 596
 597         sbus_writel(0x04 << 24, &bt->addr);         /* color planes */
 598         sbus_writel(0xff << 24, &bt->control);
 599         sbus_writel(0x05 << 24, &bt->addr);
 600         sbus_writel(0x00 << 24, &bt->control);
 601         sbus_writel(0x06 << 24, &bt->addr);         /* overlay plane */
 602         sbus_writel(0x73 << 24, &bt->control);
 603         sbus_writel(0x07 << 24, &bt->addr);
 604         sbus_writel(0x00 << 24, &bt->control);
 605 }
 606
 607 static void cg6_chip_init(struct fb_info *info)
 608 {
 609         struct cg6_par *par = (struct cg6_par *) info->par;
 610         struct cg6_tec __iomem *tec = par->tec;
 611         struct cg6_fbc __iomem *fbc = par->fbc;
 612         u32 rev, conf, mode;
 613         int i;
 614
 615         /* Turn off stuff in the Transform Engine. */
 616         sbus_writel(0, &tec->tec_matrix);
 617         sbus_writel(0, &tec->tec_clip);
 618         sbus_writel(0, &tec->tec_vdc);
 619
 620         /* Take care of bugs in old revisions. */
 621         rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK;
 622         if (rev < 5) {
 623                 conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) |
 624                         CG6_FHC_CPU_68020 | CG6_FHC_TEST |
 625                         (11 << CG6_FHC_TEST_X_SHIFT) |
 626                         (11 << CG6_FHC_TEST_Y_SHIFT);
 627                 if (rev < 2)
 628                         conf |= CG6_FHC_DST_DISABLE;
 629                 sbus_writel(conf, par->fhc);
 630         }
 631
 632         /* Set things in the FBC. Bad things appear to happen if we do
 633          * back to back store/loads on the mode register, so copy it
 634          * out instead. */
 635         mode = sbus_readl(&fbc->mode);
 636         do {
 637                 i = sbus_readl(&fbc->s);
 638         } while (i & 0x10000000);
 639         mode &= ~(CG6_FBC_BLIT_MASK | CG6_FBC_MODE_MASK |
 640                        CG6_FBC_DRAW_MASK | CG6_FBC_BWRITE0_MASK |
 641                        CG6_FBC_BWRITE1_MASK | CG6_FBC_BREAD_MASK |
 642                        CG6_FBC_BDISP_MASK);
 643         mode |= (CG6_FBC_BLIT_SRC | CG6_FBC_MODE_COLOR8 |
 644                       CG6_FBC_DRAW_RENDER | CG6_FBC_BWRITE0_ENABLE |
 645                       CG6_FBC_BWRITE1_DISABLE | CG6_FBC_BREAD_0 |
 646                       CG6_FBC_BDISP_0);
 647         sbus_writel(mode, &fbc->mode);
 648
 649         sbus_writel(0, &fbc->clip);
 650         sbus_writel(0, &fbc->offx);
 651         sbus_writel(0, &fbc->offy);
 652         sbus_writel(0, &fbc->clipminx);
 653         sbus_writel(0, &fbc->clipminy);
 654         sbus_writel(info->var.xres - 1, &fbc->clipmaxx);
 655         sbus_writel(info->var.yres - 1, &fbc->clipmaxy);
 656 }
 657
 658 struct all_info {
 659         struct fb_info info;
 660         struct cg6_par par;
 661         struct list_head list;
 662 };
 663 static LIST_HEAD(cg6_list);
 664
 665 static void cg6_init_one(struct sbus_dev *sdev)
 666 {
 667         struct all_info *all;
 668         int linebytes;
 669
 670         all = kmalloc(sizeof(*all), GFP_KERNEL);
 671         if (!all) {
 672                 printk(KERN_ERR "cg6: Cannot allocate memory.\n");
 673                 return;
 674         }
 675         memset(all, 0, sizeof(*all));
 676
 677         INIT_LIST_HEAD(&all->list);
 678
 679         spin_lock_init(&all->par.lock);
 680         all->par.sdev = sdev;
 681
 682         all->par.physbase = sdev->reg_addrs[0].phys_addr;
 683
 684         sbusfb_fill_var(&all->info.var, sdev->prom_node, 8);
 685         all->info.var.red.length = 8;
 686         all->info.var.green.length = 8;
 687         all->info.var.blue.length = 8;
 688
 689         linebytes = prom_getintdefault(sdev->prom_node, "linebytes",
 690                                        all->info.var.xres);
 691         all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
 692         if (prom_getbool(sdev->prom_node, "dblbuf"))
 693                 all->par.fbsize *= 4;
 694
 695         all->par.fbc = sbus_ioremap(&sdev->resource[0], CG6_FBC_OFFSET,
 696                              4096, "cgsix fbc");
 697         all->par.tec = sbus_ioremap(&sdev->resource[0], CG6_TEC_OFFSET,
 698                              sizeof(struct cg6_tec), "cgsix tec");
 699         all->par.thc = sbus_ioremap(&sdev->resource[0], CG6_THC_OFFSET,
 700                              sizeof(struct cg6_thc), "cgsix thc");
 701         all->par.bt = sbus_ioremap(&sdev->resource[0], CG6_BROOKTREE_OFFSET,
 702                              sizeof(struct bt_regs), "cgsix dac");
 703         all->par.fhc = sbus_ioremap(&sdev->resource[0], CG6_FHC_OFFSET,
 704                              sizeof(u32), "cgsix fhc");
 705
 706         all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_IMAGEBLIT |
 707                           FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
 708         all->info.fbops = &cg6_ops;
 709 #ifdef CONFIG_SPARC32
 710         all->info.screen_base = (char __iomem *)
 711                 prom_getintdefault(sdev->prom_node, "address", 0);
 712 #endif
 713         if (!all->info.screen_base)
 714                 all->info.screen_base =
 715                         sbus_ioremap(&sdev->resource[0], CG6_RAM_OFFSET,
 716                                      all->par.fbsize, "cgsix ram");
 717         all->info.par = &all->par;
 718
 719         all->info.var.accel_flags = FB_ACCELF_TEXT;
 720
 721         cg6_bt_init(&all->par);
 722         cg6_chip_init(&all->info);
 723         cg6_blank(0, &all->info);
 724
 725         if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
 726                 printk(KERN_ERR "cg6: Could not allocate color map.\n");
 727                 kfree(all);
 728                 return;
 729         }
 730
 731         fb_set_cmap(&all->info.cmap, &all->info);
 732         cg6_init_fix(&all->info, linebytes);
 733
 734         if (register_framebuffer(&all->info) < 0) {
 735                 printk(KERN_ERR "cg6: Could not register framebuffer.\n");
 736                 fb_dealloc_cmap(&all->info.cmap);
 737                 kfree(all);
 738                 return;
 739         }
 740
 741         list_add(&all->list, &cg6_list);
 742
 743         printk("cg6: CGsix [%s] at %lx:%lx\n",
 744                all->info.fix.id,
 745                (long) sdev->reg_addrs[0].which_io,
 746                (long) sdev->reg_addrs[0].phys_addr);
 747 }
 748
 749 int __init cg6_init(void)
 750 {
 751         struct sbus_bus *sbus;
 752         struct sbus_dev *sdev;
 753
 754         if (fb_get_options("cg6fb", NULL))
 755                 return -ENODEV;
 756
 757         for_all_sbusdev(sdev, sbus) {
 758                 if (!strcmp(sdev->prom_name, "cgsix") ||
 759                     !strcmp(sdev->prom_name, "cgthree+"))
 760                         cg6_init_one(sdev);
 761         }
 762
 763         return 0;
 764 }
 765
 766 void __exit cg6_exit(void)
 767 {
 768         struct list_head *pos, *tmp;
 769
 770         list_for_each_safe(pos, tmp, &cg6_list) {
 771                 struct all_info *all = list_entry(pos, typeof(*all), list);
 772
 773                 unregister_framebuffer(&all->info);
 774                 fb_dealloc_cmap(&all->info.cmap);
 775                 kfree(all);
 776         }
 777 }
 778
 779 int __init
 780 cg6_setup(char *arg)
 781 {
 782         /* No cmdline options yet... */
 783         return 0;
 784 }
 785
 786 module_init(cg6_init);
 787
 788 #ifdef MODULE
 789 module_exit(cg6_exit);
 790 #endif
 791
 792 MODULE_DESCRIPTION("framebuffer driver for CGsix chipsets");
 793 MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
 794 MODULE_LICENSE("GPL");