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Linux 2.6.17.7
[linux/fpc-iii.git] / drivers / video / matrox / matroxfb_misc.c
blob263d801ef78fd00898d0447205236c39b03c604f
1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
4 *
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 * Portions Copyright (c) 2001 Matrox Graphics Inc.
8 *
9 * Version: 1.65 2002/08/14
10 *
11 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
12 *
13 * Contributors: "menion?" <menion@mindless.com>
14 * Betatesting, fixes, ideas
15 *
16 * "Kurt Garloff" <garloff@suse.de>
17 * Betatesting, fixes, ideas, videomodes, videomodes timmings
18 *
19 * "Tom Rini" <trini@kernel.crashing.org>
20 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
21 *
22 * "Bibek Sahu" <scorpio@dodds.net>
23 * Access device through readb|w|l and write b|w|l
24 * Extensive debugging stuff
25 *
26 * "Daniel Haun" <haund@usa.net>
27 * Testing, hardware cursor fixes
28 *
29 * "Scott Wood" <sawst46+@pitt.edu>
30 * Fixes
31 *
32 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
33 * Betatesting
34 *
35 * "Kelly French" <targon@hazmat.com>
36 * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
37 * Betatesting, bug reporting
38 *
39 * "Pablo Bianucci" <pbian@pccp.com.ar>
40 * Fixes, ideas, betatesting
41 *
42 * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
43 * Fixes, enhandcements, ideas, betatesting
44 *
45 * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
46 * PPC betatesting, PPC support, backward compatibility
47 *
48 * "Paul Womar" <Paul@pwomar.demon.co.uk>
49 * "Owen Waller" <O.Waller@ee.qub.ac.uk>
50 * PPC betatesting
51 *
52 * "Thomas Pornin" <pornin@bolet.ens.fr>
53 * Alpha betatesting
54 *
55 * "Pieter van Leuven" <pvl@iae.nl>
56 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
57 * G100 testing
58 *
59 * "H. Peter Arvin" <hpa@transmeta.com>
60 * Ideas
61 *
62 * "Cort Dougan" <cort@cs.nmt.edu>
63 * CHRP fixes and PReP cleanup
64 *
65 * "Mark Vojkovich" <mvojkovi@ucsd.edu>
66 * G400 support
67 *
68 * "David C. Hansen" <haveblue@us.ibm.com>
69 * Fixes
70 *
71 * "Ian Romanick" <idr@us.ibm.com>
72 * Find PInS data in BIOS on PowerPC systems.
73 *
74 * (following author is not in any relation with this code, but his code
75 * is included in this driver)
76 *
77 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
78 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
79 *
80 * (following author is not in any relation with this code, but his ideas
81 * were used when writting this driver)
82 *
83 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
84 *
85 */
86
87 #include <linux/config.h>
88
89 #include "matroxfb_misc.h"
90 #include <linux/interrupt.h>
91 #include <linux/matroxfb.h>
92
93 void matroxfb_DAC_out(CPMINFO int reg, int val) {
94 DBG_REG(__FUNCTION__)
95 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
96 mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
97 }
98
99 int matroxfb_DAC_in(CPMINFO int reg) {
100 DBG_REG(__FUNCTION__)
101 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
102 return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
103 }
104
105 void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) {
106 unsigned int pixclock = var->pixclock;
107
108 DBG(__FUNCTION__)
109
110 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
111 mt->pixclock = 1000000000 / pixclock;
112 if (mt->pixclock < 1) mt->pixclock = 1;
113 mt->mnp = -1;
114 mt->dblscan = var->vmode & FB_VMODE_DOUBLE;
115 mt->interlaced = var->vmode & FB_VMODE_INTERLACED;
116 mt->HDisplay = var->xres;
117 mt->HSyncStart = mt->HDisplay + var->right_margin;
118 mt->HSyncEnd = mt->HSyncStart + var->hsync_len;
119 mt->HTotal = mt->HSyncEnd + var->left_margin;
120 mt->VDisplay = var->yres;
121 mt->VSyncStart = mt->VDisplay + var->lower_margin;
122 mt->VSyncEnd = mt->VSyncStart + var->vsync_len;
123 mt->VTotal = mt->VSyncEnd + var->upper_margin;
124 mt->sync = var->sync;
125 }
126
127 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
128 unsigned int* in, unsigned int* feed, unsigned int* post) {
129 unsigned int bestdiff = ~0;
130 unsigned int bestvco = 0;
131 unsigned int fxtal = pll->ref_freq;
132 unsigned int fwant;
133 unsigned int p;
134
135 DBG(__FUNCTION__)
136
137 fwant = freq;
138
139 #ifdef DEBUG
140 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
141 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
142 printk(KERN_ERR "freq: %d\n", freq);
143 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
144 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
145 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
146 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
147 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
148 printk(KERN_ERR "fmax: %d\n", fmax);
149 #endif
150 for (p = 1; p <= pll->post_shift_max; p++) {
151 if (fwant * 2 > fmax)
152 break;
153 fwant *= 2;
154 }
155 if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
156 if (fwant > fmax) fwant = fmax;
157 for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) {
158 unsigned int m;
159
160 if (fwant < pll->vco_freq_min) break;
161 for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
162 unsigned int diff, fvco;
163 unsigned int n;
164
165 n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1;
166 if (n > pll->feed_div_max)
167 break;
168 if (n < pll->feed_div_min)
169 n = pll->feed_div_min;
170 fvco = (fxtal * (n + 1)) / (m + 1);
171 if (fvco < fwant)
172 diff = fwant - fvco;
173 else
174 diff = fvco - fwant;
175 if (diff < bestdiff) {
176 bestdiff = diff;
177 *post = p;
178 *in = m;
179 *feed = n;
180 bestvco = fvco;
181 }
182 }
183 }
184 dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant);
185 return bestvco;
186 }
187
188 int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
189 unsigned int hd, hs, he, hbe, ht;
190 unsigned int vd, vs, ve, vt, lc;
191 unsigned int wd;
192 unsigned int divider;
193 int i;
194 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
195
196 DBG(__FUNCTION__)
197
198 hw->SEQ[0] = 0x00;
199 hw->SEQ[1] = 0x01; /* or 0x09 */
200 hw->SEQ[2] = 0x0F; /* bitplanes */
201 hw->SEQ[3] = 0x00;
202 hw->SEQ[4] = 0x0E;
203 /* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */
204 if (m->dblscan) {
205 m->VTotal <<= 1;
206 m->VDisplay <<= 1;
207 m->VSyncStart <<= 1;
208 m->VSyncEnd <<= 1;
209 }
210 if (m->interlaced) {
211 m->VTotal >>= 1;
212 m->VDisplay >>= 1;
213 m->VSyncStart >>= 1;
214 m->VSyncEnd >>= 1;
215 }
216
217 /* GCTL is ignored when not using 0xA0000 aperture */
218 hw->GCTL[0] = 0x00;
219 hw->GCTL[1] = 0x00;
220 hw->GCTL[2] = 0x00;
221 hw->GCTL[3] = 0x00;
222 hw->GCTL[4] = 0x00;
223 hw->GCTL[5] = 0x40;
224 hw->GCTL[6] = 0x05;
225 hw->GCTL[7] = 0x0F;
226 hw->GCTL[8] = 0xFF;
227
228 /* Whole ATTR is ignored in PowerGraphics mode */
229 for (i = 0; i < 16; i++)
230 hw->ATTR[i] = i;
231 hw->ATTR[16] = 0x41;
232 hw->ATTR[17] = 0xFF;
233 hw->ATTR[18] = 0x0F;
234 hw->ATTR[19] = 0x00;
235 hw->ATTR[20] = 0x00;
236
237 hd = m->HDisplay >> 3;
238 hs = m->HSyncStart >> 3;
239 he = m->HSyncEnd >> 3;
240 ht = m->HTotal >> 3;
241 /* standard timmings are in 8pixels, but for interleaved we cannot */
242 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
243 /* using 16 or more pixels per unit can save us */
244 divider = ACCESS_FBINFO(curr.final_bppShift);
245 while (divider & 3) {
246 hd >>= 1;
247 hs >>= 1;
248 he >>= 1;
249 ht >>= 1;
250 divider <<= 1;
251 }
252 divider = divider / 4;
253 /* divider can be from 1 to 8 */
254 while (divider > 8) {
255 hd <<= 1;
256 hs <<= 1;
257 he <<= 1;
258 ht <<= 1;
259 divider >>= 1;
260 }
261 hd = hd - 1;
262 hs = hs - 1;
263 he = he - 1;
264 ht = ht - 1;
265 vd = m->VDisplay - 1;
266 vs = m->VSyncStart - 1;
267 ve = m->VSyncEnd - 1;
268 vt = m->VTotal - 2;
269 lc = vd;
270 /* G200 cannot work with (ht & 7) == 6 */
271 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
272 ht++;
273 hbe = ht;
274 wd = ACCESS_FBINFO(fbcon).var.xres_virtual * ACCESS_FBINFO(curr.final_bppShift) / 64;
275
276 hw->CRTCEXT[0] = 0;
277 hw->CRTCEXT[5] = 0;
278 if (m->interlaced) {
279 hw->CRTCEXT[0] = 0x80;
280 hw->CRTCEXT[5] = (hs + he - ht) >> 1;
281 if (!m->dblscan)
282 wd <<= 1;
283 vt &= ~1;
284 }
285 hw->CRTCEXT[0] |= (wd & 0x300) >> 4;
286 hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) |
287 ((hd & 0x100) >> 7) | /* blanking */
288 ((hs & 0x100) >> 6) | /* sync start */
289 (hbe & 0x040); /* end hor. blanking */
290 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */
291 if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1)
292 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
293 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
294 ((vd & 0x400) >> 8) | /* disp end */
295 ((vd & 0xC00) >> 7) | /* vblanking start */
296 ((vs & 0xC00) >> 5) |
297 ((lc & 0x400) >> 3);
298 hw->CRTCEXT[3] = (divider - 1) | 0x80;
299 hw->CRTCEXT[4] = 0;
300
301 hw->CRTC[0] = ht-4;
302 hw->CRTC[1] = hd;
303 hw->CRTC[2] = hd;
304 hw->CRTC[3] = (hbe & 0x1F) | 0x80;
305 hw->CRTC[4] = hs;
306 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F);
307 hw->CRTC[6] = vt & 0xFF;
308 hw->CRTC[7] = ((vt & 0x100) >> 8) |
309 ((vd & 0x100) >> 7) |
310 ((vs & 0x100) >> 6) |
311 ((vd & 0x100) >> 5) |
312 ((lc & 0x100) >> 4) |
313 ((vt & 0x200) >> 4) |
314 ((vd & 0x200) >> 3) |
315 ((vs & 0x200) >> 2);
316 hw->CRTC[8] = 0x00;
317 hw->CRTC[9] = ((vd & 0x200) >> 4) |
318 ((lc & 0x200) >> 3);
319 if (m->dblscan && !m->interlaced)
320 hw->CRTC[9] |= 0x80;
321 for (i = 10; i < 16; i++)
322 hw->CRTC[i] = 0x00;
323 hw->CRTC[16] = vs /* & 0xFF */;
324 hw->CRTC[17] = (ve & 0x0F) | 0x20;
325 hw->CRTC[18] = vd /* & 0xFF */;
326 hw->CRTC[19] = wd /* & 0xFF */;
327 hw->CRTC[20] = 0x00;
328 hw->CRTC[21] = vd /* & 0xFF */;
329 hw->CRTC[22] = (vt + 1) /* & 0xFF */;
330 hw->CRTC[23] = 0xC3;
331 hw->CRTC[24] = lc;
332 return 0;
333 };
334
335 void matroxfb_vgaHWrestore(WPMINFO2) {
336 int i;
337 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
338 CRITFLAGS
339
340 DBG(__FUNCTION__)
341
342 dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg);
343 dprintk(KERN_INFO "SEQ regs: ");
344 for (i = 0; i < 5; i++)
345 dprintk("%02X:", hw->SEQ[i]);
346 dprintk("\n");
347 dprintk(KERN_INFO "GDC regs: ");
348 for (i = 0; i < 9; i++)
349 dprintk("%02X:", hw->GCTL[i]);
350 dprintk("\n");
351 dprintk(KERN_INFO "CRTC regs: ");
352 for (i = 0; i < 25; i++)
353 dprintk("%02X:", hw->CRTC[i]);
354 dprintk("\n");
355 dprintk(KERN_INFO "ATTR regs: ");
356 for (i = 0; i < 21; i++)
357 dprintk("%02X:", hw->ATTR[i]);
358 dprintk("\n");
359
360 CRITBEGIN
361
362 mga_inb(M_ATTR_RESET);
363 mga_outb(M_ATTR_INDEX, 0);
364 mga_outb(M_MISC_REG, hw->MiscOutReg);
365 for (i = 1; i < 5; i++)
366 mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]);
367 mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F);
368 for (i = 0; i < 25; i++)
369 mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]);
370 for (i = 0; i < 9; i++)
371 mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]);
372 for (i = 0; i < 21; i++) {
373 mga_inb(M_ATTR_RESET);
374 mga_outb(M_ATTR_INDEX, i);
375 mga_outb(M_ATTR_INDEX, hw->ATTR[i]);
376 }
377 mga_outb(M_PALETTE_MASK, 0xFF);
378 mga_outb(M_DAC_REG, 0x00);
379 for (i = 0; i < 768; i++)
380 mga_outb(M_DAC_VAL, hw->DACpal[i]);
381 mga_inb(M_ATTR_RESET);
382 mga_outb(M_ATTR_INDEX, 0x20);
383
384 CRITEND
385 }
386
387 static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) {
388 unsigned int b0 = readb(pins);
389
390 if (b0 == 0x2E && readb(pins+1) == 0x41) {
391 unsigned int pins_len = readb(pins+2);
392 unsigned int i;
393 unsigned char cksum;
394 unsigned char* dst = bd->pins;
395
396 if (pins_len < 3 || pins_len > 128) {
397 return;
398 }
399 *dst++ = 0x2E;
400 *dst++ = 0x41;
401 *dst++ = pins_len;
402 cksum = 0x2E + 0x41 + pins_len;
403 for (i = 3; i < pins_len; i++) {
404 cksum += *dst++ = readb(pins+i);
405 }
406 if (cksum) {
407 return;
408 }
409 bd->pins_len = pins_len;
410 } else if (b0 == 0x40 && readb(pins+1) == 0x00) {
411 unsigned int i;
412 unsigned char* dst = bd->pins;
413
414 *dst++ = 0x40;
415 *dst++ = 0;
416 for (i = 2; i < 0x40; i++) {
417 *dst++ = readb(pins+i);
418 }
419 bd->pins_len = 0x40;
420 }
421 }
422
423 static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) {
424 unsigned int pcir_offset;
425
426 pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8);
427 if (pcir_offset >= 26 && pcir_offset < 0xFFE0 &&
428 readb(vbios + pcir_offset ) == 'P' &&
429 readb(vbios + pcir_offset + 1) == 'C' &&
430 readb(vbios + pcir_offset + 2) == 'I' &&
431 readb(vbios + pcir_offset + 3) == 'R') {
432 unsigned char h;
433
434 h = readb(vbios + pcir_offset + 0x12);
435 bd->version.vMaj = (h >> 4) & 0xF;
436 bd->version.vMin = h & 0xF;
437 bd->version.vRev = readb(vbios + pcir_offset + 0x13);
438 } else {
439 unsigned char h;
440
441 h = readb(vbios + 5);
442 bd->version.vMaj = (h >> 4) & 0xF;
443 bd->version.vMin = h & 0xF;
444 bd->version.vRev = 0;
445 }
446 }
447
448 static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) {
449 unsigned char b;
450
451 b = readb(vbios + 0x7FF1);
452 if (b == 0xFF) {
453 b = 0;
454 }
455 bd->output.state = b;
456 }
457
458 static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) {
459 unsigned int i;
460
461 /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */
462 bd->output.tvout = 0;
463 if (readb(vbios + 0x1D) != 'I' ||
464 readb(vbios + 0x1E) != 'B' ||
465 readb(vbios + 0x1F) != 'M' ||
466 readb(vbios + 0x20) != ' ') {
467 return;
468 }
469 for (i = 0x2D; i < 0x2D + 128; i++) {
470 unsigned char b = readb(vbios + i);
471
472 if (b == '(' && readb(vbios + i + 1) == 'V') {
473 if (readb(vbios + i + 6) == 'T' &&
474 readb(vbios + i + 7) == 'V' &&
475 readb(vbios + i + 8) == 'O') {
476 bd->output.tvout = 1;
477 }
478 return;
479 }
480 if (b == 0)
481 break;
482 }
483 }
484
485 static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) {
486 unsigned int pins_offset;
487
488 if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) {
489 return;
490 }
491 bd->bios_valid = 1;
492 get_bios_version(vbios, bd);
493 get_bios_output(vbios, bd);
494 get_bios_tvout(vbios, bd);
495 #if defined(__powerpc__)
496 /* On PowerPC cards, the PInS offset isn't stored at the end of the
497 * BIOS image. Instead, you must search the entire BIOS image for
498 * the magic PInS signature.
499 *
500 * This actually applies to all OpenFirmware base cards. Since these
501 * cards could be put in a MIPS or SPARC system, should the condition
502 * be something different?
503 */
504 for ( pins_offset = 0 ; pins_offset <= 0xFF80 ; pins_offset++ ) {
505 unsigned char header[3];
506
507 header[0] = readb(vbios + pins_offset);
508 header[1] = readb(vbios + pins_offset + 1);
509 header[2] = readb(vbios + pins_offset + 2);
510 if ( (header[0] == 0x2E) && (header[1] == 0x41)
511 && ((header[2] == 0x40) || (header[2] == 0x80)) ) {
512 printk(KERN_INFO "PInS data found at offset %u\n",
513 pins_offset);
514 get_pins(vbios + pins_offset, bd);
515 break;
516 }
517 }
518 #else
519 pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8);
520 if (pins_offset <= 0xFF80) {
521 get_pins(vbios + pins_offset, bd);
522 }
523 #endif
524 }
525
526 #define get_u16(x) (le16_to_cpu(get_unaligned((__u16*)(x))))
527 #define get_u32(x) (le32_to_cpu(get_unaligned((__u32*)(x))))
528 static int parse_pins1(WPMINFO const struct matrox_bios* bd) {
529 unsigned int maxdac;
530
531 switch (bd->pins[22]) {
532 case 0: maxdac = 175000; break;
533 case 1: maxdac = 220000; break;
534 default: maxdac = 240000; break;
535 }
536 if (get_u16(bd->pins + 24)) {
537 maxdac = get_u16(bd->pins + 24) * 10;
538 }
539 MINFO->limits.pixel.vcomax = maxdac;
540 MINFO->values.pll.system = get_u16(bd->pins + 28) ? get_u16(bd->pins + 28) * 10 : 50000;
541 /* ignore 4MB, 8MB, module clocks */
542 MINFO->features.pll.ref_freq = 14318;
543 MINFO->values.reg.mctlwtst = 0x00030101;
544 return 0;
545 }
546
547 static void default_pins1(WPMINFO2) {
548 /* Millennium */
549 MINFO->limits.pixel.vcomax = 220000;
550 MINFO->values.pll.system = 50000;
551 MINFO->features.pll.ref_freq = 14318;
552 MINFO->values.reg.mctlwtst = 0x00030101;
553 }
554
555 static int parse_pins2(WPMINFO const struct matrox_bios* bd) {
556 MINFO->limits.pixel.vcomax =
557 MINFO->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
558 MINFO->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
559 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
560 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
561 ((bd->pins[51] & 0x08) ? 0x00020000 : 0);
562 MINFO->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
563 MINFO->features.pll.ref_freq = 14318;
564 return 0;
565 }
566
567 static void default_pins2(WPMINFO2) {
568 /* Millennium II, Mystique */
569 MINFO->limits.pixel.vcomax =
570 MINFO->limits.system.vcomax = 230000;
571 MINFO->values.reg.mctlwtst = 0x00030101;
572 MINFO->values.pll.system = 50000;
573 MINFO->features.pll.ref_freq = 14318;
574 }
575
576 static int parse_pins3(WPMINFO const struct matrox_bios* bd) {
577 MINFO->limits.pixel.vcomax =
578 MINFO->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
579 MINFO->values.reg.mctlwtst = get_u32(bd->pins + 48) == 0xFFFFFFFF ? 0x01250A21 : get_u32(bd->pins + 48);
580 /* memory config */
581 MINFO->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
582 ((bd->pins[57] << 22) & 0x00C00000) |
583 ((bd->pins[56] << 1) & 0x000001E0) |
584 ( bd->pins[56] & 0x0000000F);
585 MINFO->values.reg.opt = (bd->pins[54] & 7) << 10;
586 MINFO->values.reg.opt2 = bd->pins[58] << 12;
587 MINFO->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
588 return 0;
589 }
590
591 static void default_pins3(WPMINFO2) {
592 /* G100, G200 */
593 MINFO->limits.pixel.vcomax =
594 MINFO->limits.system.vcomax = 230000;
595 MINFO->values.reg.mctlwtst = 0x01250A21;
596 MINFO->values.reg.memrdbk = 0x00000000;
597 MINFO->values.reg.opt = 0x00000C00;
598 MINFO->values.reg.opt2 = 0x00000000;
599 MINFO->features.pll.ref_freq = 27000;
600 }
601
602 static int parse_pins4(WPMINFO const struct matrox_bios* bd) {
603 MINFO->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
604 MINFO->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 38] * 4000;
605 MINFO->values.reg.mctlwtst = get_u32(bd->pins + 71);
606 MINFO->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
607 ((bd->pins[87] << 22) & 0x00C00000) |
608 ((bd->pins[86] << 1) & 0x000001E0) |
609 ( bd->pins[86] & 0x0000000F);
610 MINFO->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
611 ((bd->pins[53] << 22) & 0x10000000) |
612 ((bd->pins[53] << 7) & 0x00001C00);
613 MINFO->values.reg.opt3 = get_u32(bd->pins + 67);
614 MINFO->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
615 MINFO->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
616 return 0;
617 }
618
619 static void default_pins4(WPMINFO2) {
620 /* G400 */
621 MINFO->limits.pixel.vcomax =
622 MINFO->limits.system.vcomax = 252000;
623 MINFO->values.reg.mctlwtst = 0x04A450A1;
624 MINFO->values.reg.memrdbk = 0x000000E7;
625 MINFO->values.reg.opt = 0x10000400;
626 MINFO->values.reg.opt3 = 0x0190A419;
627 MINFO->values.pll.system = 200000;
628 MINFO->features.pll.ref_freq = 27000;
629 }
630
631 static int parse_pins5(WPMINFO const struct matrox_bios* bd) {
632 unsigned int mult;
633
634 mult = bd->pins[4]?8000:6000;
635
636 MINFO->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
637 MINFO->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 36] * mult;
638 MINFO->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? MINFO->limits.system.vcomax : bd->pins[ 37] * mult;
639 MINFO->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
640 MINFO->limits.system.vcomin = (bd->pins[121] == 0xFF) ? MINFO->limits.pixel.vcomin : bd->pins[121] * mult;
641 MINFO->limits.video.vcomin = (bd->pins[122] == 0xFF) ? MINFO->limits.system.vcomin : bd->pins[122] * mult;
642 MINFO->values.pll.system =
643 MINFO->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
644 MINFO->values.reg.opt = get_u32(bd->pins+ 48);
645 MINFO->values.reg.opt2 = get_u32(bd->pins+ 52);
646 MINFO->values.reg.opt3 = get_u32(bd->pins+ 94);
647 MINFO->values.reg.mctlwtst = get_u32(bd->pins+ 98);
648 MINFO->values.reg.memmisc = get_u32(bd->pins+102);
649 MINFO->values.reg.memrdbk = get_u32(bd->pins+106);
650 MINFO->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
651 MINFO->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
652 MINFO->values.memory.dll = (bd->pins[115] & 0x02) != 0;
653 MINFO->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
654 MINFO->values.reg.maccess = MINFO->values.memory.emrswen ? 0x00004000 : 0x00000000;
655 if (bd->pins[115] & 4) {
656 MINFO->values.reg.mctlwtst_core = MINFO->values.reg.mctlwtst;
657 } else {
658 u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 };
659 MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) |
660 wtst_xlat[MINFO->values.reg.mctlwtst & 7];
661 }
662 return 0;
663 }
664
665 static void default_pins5(WPMINFO2) {
666 /* Mine 16MB G450 with SDRAM DDR */
667 MINFO->limits.pixel.vcomax =
668 MINFO->limits.system.vcomax =
669 MINFO->limits.video.vcomax = 600000;
670 MINFO->limits.pixel.vcomin =
671 MINFO->limits.system.vcomin =
672 MINFO->limits.video.vcomin = 256000;
673 MINFO->values.pll.system =
674 MINFO->values.pll.video = 284000;
675 MINFO->values.reg.opt = 0x404A1160;
676 MINFO->values.reg.opt2 = 0x0000AC00;
677 MINFO->values.reg.opt3 = 0x0090A409;
678 MINFO->values.reg.mctlwtst_core =
679 MINFO->values.reg.mctlwtst = 0x0C81462B;
680 MINFO->values.reg.memmisc = 0x80000004;
681 MINFO->values.reg.memrdbk = 0x01001103;
682 MINFO->features.pll.ref_freq = 27000;
683 MINFO->values.memory.ddr = 1;
684 MINFO->values.memory.dll = 1;
685 MINFO->values.memory.emrswen = 1;
686 MINFO->values.reg.maccess = 0x00004000;
687 }
688
689 static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) {
690 unsigned int pins_version;
691 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
692
693 switch (ACCESS_FBINFO(chip)) {
694 case MGA_2064: default_pins1(PMINFO2); break;
695 case MGA_2164:
696 case MGA_1064:
697 case MGA_1164: default_pins2(PMINFO2); break;
698 case MGA_G100:
699 case MGA_G200: default_pins3(PMINFO2); break;
700 case MGA_G400: default_pins4(PMINFO2); break;
701 case MGA_G450:
702 case MGA_G550: default_pins5(PMINFO2); break;
703 }
704 if (!bd->bios_valid) {
705 printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
706 return -1;
707 }
708 if (bd->pins_len < 64) {
709 printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n");
710 return -1;
711 }
712 if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) {
713 pins_version = bd->pins[5];
714 if (pins_version < 2 || pins_version > 5) {
715 printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version);
716 return -1;
717 }
718 } else {
719 pins_version = 1;
720 }
721 if (bd->pins_len != pinslen[pins_version - 1]) {
722 printk(KERN_INFO "matroxfb: Invalid powerup info\n");
723 return -1;
724 }
725 switch (pins_version) {
726 case 1:
727 return parse_pins1(PMINFO bd);
728 case 2:
729 return parse_pins2(PMINFO bd);
730 case 3:
731 return parse_pins3(PMINFO bd);
732 case 4:
733 return parse_pins4(PMINFO bd);
734 case 5:
735 return parse_pins5(PMINFO bd);
736 default:
737 printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
738 return -1;
739 }
740 }
741
742 void matroxfb_read_pins(WPMINFO2) {
743 u32 opt;
744 u32 biosbase;
745 u32 fbbase;
746 struct pci_dev* pdev = ACCESS_FBINFO(pcidev);
747
748 memset(&ACCESS_FBINFO(bios), 0, sizeof(ACCESS_FBINFO(bios)));
749 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
750 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
751 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
752 pci_read_config_dword(pdev, ACCESS_FBINFO(devflags.fbResource), &fbbase);
753 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
754 parse_bios(vaddr_va(ACCESS_FBINFO(video).vbase), &ACCESS_FBINFO(bios));
755 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
756 pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
757 #ifdef CONFIG_X86
758 if (!ACCESS_FBINFO(bios).bios_valid) {
759 unsigned char __iomem* b;
760
761 b = ioremap(0x000C0000, 65536);
762 if (!b) {
763 printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n");
764 } else {
765 unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8);
766 unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8);
767
768 if (ven != pdev->vendor || dev != pdev->device) {
769 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
770 ven, dev, pdev->vendor, pdev->device);
771 } else {
772 parse_bios(b, &ACCESS_FBINFO(bios));
773 }
774 iounmap(b);
775 }
776 }
777 #endif
778 matroxfb_set_limits(PMINFO &ACCESS_FBINFO(bios));
779 printk(KERN_INFO "PInS memtype = %u\n",
780 (ACCESS_FBINFO(values).reg.opt & 0x1C00) >> 10);
781 }
782
783 EXPORT_SYMBOL(matroxfb_DAC_in);
784 EXPORT_SYMBOL(matroxfb_DAC_out);
785 EXPORT_SYMBOL(matroxfb_var2my);
786 EXPORT_SYMBOL(matroxfb_PLL_calcclock);
787 #ifndef CONFIG_FB_MATROX_MULTIHEAD
788 struct matrox_fb_info matroxfb_global_mxinfo;
789 EXPORT_SYMBOL(matroxfb_global_mxinfo);
790 #endif
791 EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */
792 EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */
793 EXPORT_SYMBOL(matroxfb_read_pins);
794
795 MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
796 MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards");
797 MODULE_LICENSE("GPL");
Linux with added FPC-III support