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Linux 2.6.17.7
[linux/fpc-iii.git] / drivers / video / tdfxfb.c
blob5e5328d682db52aee991d6b48fa11951395250ba
1 /*
2 *
3 * tdfxfb.c
4 *
5 * Author: Hannu Mallat <hmallat@cc.hut.fi>
6 *
7 * Copyright © 1999 Hannu Mallat
8 * All rights reserved
9 *
10 * Created : Thu Sep 23 18:17:43 1999, hmallat
11 * Last modified: Tue Nov 2 21:19:47 1999, hmallat
12 *
13 * Lots of the information here comes from the Daryll Strauss' Banshee
14 * patches to the XF86 server, and the rest comes from the 3dfx
15 * Banshee specification. I'm very much indebted to Daryll for his
16 * work on the X server.
17 *
18 * Voodoo3 support was contributed Harold Oga. Lots of additions
19 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
20 * Kesmarki. Thanks guys!
21 *
22 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
23 * behave very differently from the Voodoo3/4/5. For anyone wanting to
24 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
25 * located at http://www.sourceforge.net/projects/sstfb).
26 *
27 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
28 * I do wish the next version is a bit more complete. Without the XF86
29 * patches I couldn't have gotten even this far... for instance, the
30 * extensions to the VGA register set go completely unmentioned in the
31 * spec! Also, lots of references are made to the 'SST core', but no
32 * spec is publicly available, AFAIK.
33 *
34 * The structure of this driver comes pretty much from the Permedia
35 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
36 *
37 * TODO:
38 * - support for 16/32 bpp needs fixing (funky bootup penguin)
39 * - multihead support (basically need to support an array of fb_infos)
40 * - support other architectures (PPC, Alpha); does the fact that the VGA
41 * core can be accessed only thru I/O (not memory mapped) complicate
42 * things?
43 *
44 * Version history:
45 *
46 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
47 *
48 * 0.1.3 (released 1999-11-02) added Attila's panning support, code
49 * reorg, hwcursor address page size alignment
50 * (for mmaping both frame buffer and regs),
51 * and my changes to get rid of hardcoded
52 * VGA i/o register locations (uses PCI
53 * configuration info now)
54 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
55 * improvements
56 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
57 * 0.1.0 (released 1999-10-06) initial version
58 *
59 */
60
61 #include <linux/config.h>
62 #include <linux/module.h>
63 #include <linux/kernel.h>
64 #include <linux/errno.h>
65 #include <linux/string.h>
66 #include <linux/mm.h>
67 #include <linux/tty.h>
68 #include <linux/slab.h>
69 #include <linux/delay.h>
70 #include <linux/interrupt.h>
71 #include <linux/fb.h>
72 #include <linux/init.h>
73 #include <linux/pci.h>
74 #include <linux/nvram.h>
75 #include <asm/io.h>
76 #include <linux/timer.h>
77 #include <linux/spinlock.h>
78
79 #include <video/tdfx.h>
80
81 #undef TDFXFB_DEBUG
82 #ifdef TDFXFB_DEBUG
83 #define DPRINTK(a,b...) printk(KERN_DEBUG "fb: %s: " a, __FUNCTION__ , ## b)
84 #else
85 #define DPRINTK(a,b...)
86 #endif
87
88 #define BANSHEE_MAX_PIXCLOCK 270000
89 #define VOODOO3_MAX_PIXCLOCK 300000
90 #define VOODOO5_MAX_PIXCLOCK 350000
91
92 static struct fb_fix_screeninfo tdfx_fix __devinitdata = {
93 .id = "3Dfx",
94 .type = FB_TYPE_PACKED_PIXELS,
95 .visual = FB_VISUAL_PSEUDOCOLOR,
96 .ypanstep = 1,
97 .ywrapstep = 1,
98 .accel = FB_ACCEL_3DFX_BANSHEE
99 };
100
101 static struct fb_var_screeninfo tdfx_var __devinitdata = {
102 /* "640x480, 8 bpp @ 60 Hz */
103 .xres = 640,
104 .yres = 480,
105 .xres_virtual = 640,
106 .yres_virtual = 1024,
107 .bits_per_pixel =8,
108 .red = {0, 8, 0},
109 .blue = {0, 8, 0},
110 .green = {0, 8, 0},
111 .activate = FB_ACTIVATE_NOW,
112 .height = -1,
113 .width = -1,
114 .accel_flags = FB_ACCELF_TEXT,
115 .pixclock = 39722,
116 .left_margin = 40,
117 .right_margin = 24,
118 .upper_margin = 32,
119 .lower_margin = 11,
120 .hsync_len = 96,
121 .vsync_len = 2,
122 .vmode = FB_VMODE_NONINTERLACED
123 };
124
125 /*
126 * PCI driver prototypes
127 */
128 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
129 const struct pci_device_id *id);
130 static void __devexit tdfxfb_remove(struct pci_dev *pdev);
131
132 static struct pci_device_id tdfxfb_id_table[] = {
133 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
134 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
135 0xff0000, 0 },
136 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
137 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
138 0xff0000, 0 },
139 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
141 0xff0000, 0 },
142 { 0, }
143 };
144
145 static struct pci_driver tdfxfb_driver = {
146 .name = "tdfxfb",
147 .id_table = tdfxfb_id_table,
148 .probe = tdfxfb_probe,
149 .remove = __devexit_p(tdfxfb_remove),
150 };
151
152 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
153
154 /*
155 * Frame buffer device API
156 */
157 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb);
158 static int tdfxfb_set_par(struct fb_info *info);
159 static int tdfxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
160 u_int transp, struct fb_info *info);
161 static int tdfxfb_blank(int blank, struct fb_info *info);
162 static int tdfxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
163 static int banshee_wait_idle(struct fb_info *info);
164 #ifdef CONFIG_FB_3DFX_ACCEL
165 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
166 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
167 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image);
168 #endif /* CONFIG_FB_3DFX_ACCEL */
169
170 static struct fb_ops tdfxfb_ops = {
171 .owner = THIS_MODULE,
172 .fb_check_var = tdfxfb_check_var,
173 .fb_set_par = tdfxfb_set_par,
174 .fb_setcolreg = tdfxfb_setcolreg,
175 .fb_blank = tdfxfb_blank,
176 .fb_pan_display = tdfxfb_pan_display,
177 .fb_sync = banshee_wait_idle,
178 #ifdef CONFIG_FB_3DFX_ACCEL
179 .fb_fillrect = tdfxfb_fillrect,
180 .fb_copyarea = tdfxfb_copyarea,
181 .fb_imageblit = tdfxfb_imageblit,
182 #else
183 .fb_fillrect = cfb_fillrect,
184 .fb_copyarea = cfb_copyarea,
185 .fb_imageblit = cfb_imageblit,
186 #endif
187 };
188
189 /*
190 * do_xxx: Hardware-specific functions
191 */
192 static u32 do_calc_pll(int freq, int *freq_out);
193 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg);
194 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short);
195
196 /*
197 * Driver data
198 */
199 static int nopan = 0;
200 static int nowrap = 1; // not implemented (yet)
201 static char *mode_option __devinitdata = NULL;
202
203 /* -------------------------------------------------------------------------
204 * Hardware-specific funcions
205 * ------------------------------------------------------------------------- */
206
207 #ifdef VGA_REG_IO
208 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) { return inb(reg); }
209
210 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) { outb(val, reg); }
211 #else
212 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) {
213 return inb(par->iobase + reg - 0x300);
214 }
215 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) {
216 outb(val, par->iobase + reg - 0x300);
217 }
218 #endif
219
220 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) {
221 vga_outb(par, GRA_I, idx); vga_outb(par, GRA_D, val);
222 }
223
224 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) {
225 vga_outb(par, SEQ_I, idx); vga_outb(par, SEQ_D, val);
226 }
227
228 static inline u8 seq_inb(struct tdfx_par *par, u32 idx) {
229 vga_outb(par, SEQ_I, idx); return vga_inb(par, SEQ_D);
230 }
231
232 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) {
233 vga_outb(par, CRT_I, idx); vga_outb(par, CRT_D, val);
234 }
235
236 static inline u8 crt_inb(struct tdfx_par *par, u32 idx) {
237 vga_outb(par, CRT_I, idx); return vga_inb(par, CRT_D);
238 }
239
240 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
241 {
242 unsigned char tmp;
243
244 tmp = vga_inb(par, IS1_R);
245 vga_outb(par, ATT_IW, idx);
246 vga_outb(par, ATT_IW, val);
247 }
248
249 static inline void vga_disable_video(struct tdfx_par *par)
250 {
251 unsigned char s;
252
253 s = seq_inb(par, 0x01) | 0x20;
254 seq_outb(par, 0x00, 0x01);
255 seq_outb(par, 0x01, s);
256 seq_outb(par, 0x00, 0x03);
257 }
258
259 static inline void vga_enable_video(struct tdfx_par *par)
260 {
261 unsigned char s;
262
263 s = seq_inb(par, 0x01) & 0xdf;
264 seq_outb(par, 0x00, 0x01);
265 seq_outb(par, 0x01, s);
266 seq_outb(par, 0x00, 0x03);
267 }
268
269 static inline void vga_enable_palette(struct tdfx_par *par)
270 {
271 vga_inb(par, IS1_R);
272 vga_outb(par, ATT_IW, 0x20);
273 }
274
275 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
276 {
277 return readl(par->regbase_virt + reg);
278 }
279
280 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
281 {
282 writel(val, par->regbase_virt + reg);
283 }
284
285 static inline void banshee_make_room(struct tdfx_par *par, int size)
286 {
287 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
288 * won't quit if you ask for more. */
289 while((tdfx_inl(par, STATUS) & 0x1f) < size-1);
290 }
291
292 static int banshee_wait_idle(struct fb_info *info)
293 {
294 struct tdfx_par *par = info->par;
295 int i = 0;
296
297 banshee_make_room(par, 1);
298 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
299
300 while(1) {
301 i = (tdfx_inl(par, STATUS) & STATUS_BUSY) ? 0 : i + 1;
302 if(i == 3) break;
303 }
304 return 0;
305 }
306
307 /*
308 * Set the color of a palette entry in 8bpp mode
309 */
310 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
311 {
312 banshee_make_room(par, 2);
313 tdfx_outl(par, DACADDR, regno);
314 tdfx_outl(par, DACDATA, c);
315 }
316
317 static u32 do_calc_pll(int freq, int* freq_out)
318 {
319 int m, n, k, best_m, best_n, best_k, best_error;
320 int fref = 14318;
321
322 best_error = freq;
323 best_n = best_m = best_k = 0;
324
325 for (k = 3; k >= 0; k--) {
326 for (m = 63; m >= 0; m--) {
327 /*
328 * Estimate value of n that produces target frequency
329 * with current m and k
330 */
331 int n_estimated = (freq * (m + 2) * (1 << k) / fref) - 2;
332
333 /* Search neighborhood of estimated n */
334 for (n = max(0, n_estimated - 1);
335 n <= min(255, n_estimated + 1); n++) {
336 /*
337 * Calculate PLL freqency with current m, k and
338 * estimated n
339 */
340 int f = fref * (n + 2) / (m + 2) / (1 << k);
341 int error = abs (f - freq);
342
343 /*
344 * If this is the closest we've come to the
345 * target frequency then remember n, m and k
346 */
347 if (error < best_error) {
348 best_error = error;
349 best_n = n;
350 best_m = m;
351 best_k = k;
352 }
353 }
354 }
355 }
356
357 n = best_n;
358 m = best_m;
359 k = best_k;
360 *freq_out = fref*(n + 2)/(m + 2)/(1 << k);
361
362 return (n << 8) | (m << 2) | k;
363 }
364
365 static void do_write_regs(struct fb_info *info, struct banshee_reg* reg)
366 {
367 struct tdfx_par *par = info->par;
368 int i;
369
370 banshee_wait_idle(info);
371
372 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
373
374 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
375
376 banshee_make_room(par, 3);
377 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
378 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
379 #if 0
380 tdfx_outl(par, PLLCTRL1, reg->mempll);
381 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
382 #endif
383 tdfx_outl(par, PLLCTRL0, reg->vidpll);
384
385 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
386
387 for (i = 0; i < 5; i++)
388 seq_outb(par, i, reg->seq[i]);
389
390 for (i = 0; i < 25; i++)
391 crt_outb(par, i, reg->crt[i]);
392
393 for (i = 0; i < 9; i++)
394 gra_outb(par, i, reg->gra[i]);
395
396 for (i = 0; i < 21; i++)
397 att_outb(par, i, reg->att[i]);
398
399 crt_outb(par, 0x1a, reg->ext[0]);
400 crt_outb(par, 0x1b, reg->ext[1]);
401
402 vga_enable_palette(par);
403 vga_enable_video(par);
404
405 banshee_make_room(par, 11);
406 tdfx_outl(par, VGAINIT0, reg->vgainit0);
407 tdfx_outl(par, DACMODE, reg->dacmode);
408 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
409 tdfx_outl(par, HWCURPATADDR, 0);
410
411 tdfx_outl(par, VIDSCREENSIZE,reg->screensize);
412 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
413 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
414 tdfx_outl(par, VGAINIT1, reg->vgainit1);
415 tdfx_outl(par, MISCINIT0, reg->miscinit0);
416
417 banshee_make_room(par, 8);
418 tdfx_outl(par, SRCBASE, reg->srcbase);
419 tdfx_outl(par, DSTBASE, reg->dstbase);
420 tdfx_outl(par, COMMANDEXTRA_2D, 0);
421 tdfx_outl(par, CLIP0MIN, 0);
422 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
423 tdfx_outl(par, CLIP1MIN, 0);
424 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
425 tdfx_outl(par, SRCXY, 0);
426
427 banshee_wait_idle(info);
428 }
429
430 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
431 {
432 u32 draminit0;
433 u32 draminit1;
434 u32 miscinit1;
435
436 int num_chips;
437 int chip_size; /* in MB */
438 u32 lfbsize;
439 int has_sgram;
440
441 draminit0 = tdfx_inl(par, DRAMINIT0);
442 draminit1 = tdfx_inl(par, DRAMINIT1);
443
444 num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
445
446 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
447 /* Banshee/Voodoo3 */
448 has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
449 chip_size = has_sgram ? ((draminit0 & DRAMINIT0_SGRAM_TYPE) ? 2 : 1)
450 : 2;
451 } else {
452 /* Voodoo4/5 */
453 has_sgram = 0;
454 chip_size = 1 << ((draminit0 & DRAMINIT0_SGRAM_TYPE_MASK) >> DRAMINIT0_SGRAM_TYPE_SHIFT);
455 }
456 lfbsize = num_chips * chip_size * 1024 * 1024;
457
458 /* disable block writes for SDRAM */
459 miscinit1 = tdfx_inl(par, MISCINIT1);
460 miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
461 miscinit1 |= MISCINIT1_CLUT_INV;
462
463 banshee_make_room(par, 1);
464 tdfx_outl(par, MISCINIT1, miscinit1);
465 return lfbsize;
466 }
467
468 /* ------------------------------------------------------------------------- */
469
470 static int tdfxfb_check_var(struct fb_var_screeninfo *var,struct fb_info *info)
471 {
472 struct tdfx_par *par = info->par;
473 u32 lpitch;
474
475 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
476 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
477 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
478 return -EINVAL;
479 }
480
481 if (var->xres != var->xres_virtual)
482 var->xres_virtual = var->xres;
483
484 if (var->yres > var->yres_virtual)
485 var->yres_virtual = var->yres;
486
487 if (var->xoffset) {
488 DPRINTK("xoffset not supported\n");
489 return -EINVAL;
490 }
491
492 /* Banshee doesn't support interlace, but Voodoo4/5 and probably Voodoo3 do. */
493 /* no direct information about device id now? use max_pixclock for this... */
494 if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
495 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
496 DPRINTK("interlace not supported\n");
497 return -EINVAL;
498 }
499
500 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
501 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
502
503 if (var->xres < 320 || var->xres > 2048) {
504 DPRINTK("width not supported: %u\n", var->xres);
505 return -EINVAL;
506 }
507
508 if (var->yres < 200 || var->yres > 2048) {
509 DPRINTK("height not supported: %u\n", var->yres);
510 return -EINVAL;
511 }
512
513 if (lpitch * var->yres_virtual > info->fix.smem_len) {
514 var->yres_virtual = info->fix.smem_len/lpitch;
515 if (var->yres_virtual < var->yres) {
516 DPRINTK("no memory for screen (%ux%ux%u)\n",
517 var->xres, var->yres_virtual, var->bits_per_pixel);
518 return -EINVAL;
519 }
520 }
521
522 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
523 DPRINTK("pixclock too high (%ldKHz)\n",PICOS2KHZ(var->pixclock));
524 return -EINVAL;
525 }
526
527 switch(var->bits_per_pixel) {
528 case 8:
529 var->red.length = var->green.length = var->blue.length = 8;
530 break;
531 case 16:
532 var->red.offset = 11;
533 var->red.length = 5;
534 var->green.offset = 5;
535 var->green.length = 6;
536 var->blue.offset = 0;
537 var->blue.length = 5;
538 break;
539 case 24:
540 var->red.offset=16;
541 var->green.offset=8;
542 var->blue.offset=0;
543 var->red.length = var->green.length = var->blue.length = 8;
544 case 32:
545 var->red.offset = 16;
546 var->green.offset = 8;
547 var->blue.offset = 0;
548 var->red.length = var->green.length = var->blue.length = 8;
549 break;
550 }
551 var->height = var->width = -1;
552
553 var->accel_flags = FB_ACCELF_TEXT;
554
555 DPRINTK("Checking graphics mode at %dx%d depth %d\n", var->xres, var->yres, var->bits_per_pixel);
556 return 0;
557 }
558
559 static int tdfxfb_set_par(struct fb_info *info)
560 {
561 struct tdfx_par *par = info->par;
562 u32 hdispend, hsyncsta, hsyncend, htotal;
563 u32 hd, hs, he, ht, hbs, hbe;
564 u32 vd, vs, ve, vt, vbs, vbe;
565 struct banshee_reg reg;
566 int fout, freq;
567 u32 wd, cpp;
568
569 par->baseline = 0;
570
571 memset(&reg, 0, sizeof(reg));
572 cpp = (info->var.bits_per_pixel + 7)/8;
573
574 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | VIDCFG_CURS_X11 | ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
575
576 /* PLL settings */
577 freq = PICOS2KHZ(info->var.pixclock);
578
579 reg.dacmode = 0;
580 reg.vidcfg &= ~VIDCFG_2X;
581
582 hdispend = info->var.xres;
583 hsyncsta = hdispend + info->var.right_margin;
584 hsyncend = hsyncsta + info->var.hsync_len;
585 htotal = hsyncend + info->var.left_margin;
586
587 if (freq > par->max_pixclock/2) {
588 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
589 reg.dacmode |= DACMODE_2X;
590 reg.vidcfg |= VIDCFG_2X;
591 hdispend >>= 1;
592 hsyncsta >>= 1;
593 hsyncend >>= 1;
594 htotal >>= 1;
595 }
596
597 hd = wd = (hdispend >> 3) - 1;
598 hs = (hsyncsta >> 3) - 1;
599 he = (hsyncend >> 3) - 1;
600 ht = (htotal >> 3) - 1;
601 hbs = hd;
602 hbe = ht;
603
604 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
605 vbs = vd = (info->var.yres << 1) - 1;
606 vs = vd + (info->var.lower_margin << 1);
607 ve = vs + (info->var.vsync_len << 1);
608 vbe = vt = ve + (info->var.upper_margin << 1) - 1;
609 } else {
610 vbs = vd = info->var.yres - 1;
611 vs = vd + info->var.lower_margin;
612 ve = vs + info->var.vsync_len;
613 vbe = vt = ve + info->var.upper_margin - 1;
614 }
615
616 /* this is all pretty standard VGA register stuffing */
617 reg.misc[0x00] = 0x0f |
618 (info->var.xres < 400 ? 0xa0 :
619 info->var.xres < 480 ? 0x60 :
620 info->var.xres < 768 ? 0xe0 : 0x20);
621
622 reg.gra[0x00] = 0x00;
623 reg.gra[0x01] = 0x00;
624 reg.gra[0x02] = 0x00;
625 reg.gra[0x03] = 0x00;
626 reg.gra[0x04] = 0x00;
627 reg.gra[0x05] = 0x40;
628 reg.gra[0x06] = 0x05;
629 reg.gra[0x07] = 0x0f;
630 reg.gra[0x08] = 0xff;
631
632 reg.att[0x00] = 0x00;
633 reg.att[0x01] = 0x01;
634 reg.att[0x02] = 0x02;
635 reg.att[0x03] = 0x03;
636 reg.att[0x04] = 0x04;
637 reg.att[0x05] = 0x05;
638 reg.att[0x06] = 0x06;
639 reg.att[0x07] = 0x07;
640 reg.att[0x08] = 0x08;
641 reg.att[0x09] = 0x09;
642 reg.att[0x0a] = 0x0a;
643 reg.att[0x0b] = 0x0b;
644 reg.att[0x0c] = 0x0c;
645 reg.att[0x0d] = 0x0d;
646 reg.att[0x0e] = 0x0e;
647 reg.att[0x0f] = 0x0f;
648 reg.att[0x10] = 0x41;
649 reg.att[0x11] = 0x00;
650 reg.att[0x12] = 0x0f;
651 reg.att[0x13] = 0x00;
652 reg.att[0x14] = 0x00;
653
654 reg.seq[0x00] = 0x03;
655 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
656 reg.seq[0x02] = 0x0f;
657 reg.seq[0x03] = 0x00;
658 reg.seq[0x04] = 0x0e;
659
660 reg.crt[0x00] = ht - 4;
661 reg.crt[0x01] = hd;
662 reg.crt[0x02] = hbs;
663 reg.crt[0x03] = 0x80 | (hbe & 0x1f);
664 reg.crt[0x04] = hs;
665 reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
666 reg.crt[0x06] = vt;
667 reg.crt[0x07] = ((vs & 0x200) >> 2) |
668 ((vd & 0x200) >> 3) |
669 ((vt & 0x200) >> 4) | 0x10 |
670 ((vbs & 0x100) >> 5) |
671 ((vs & 0x100) >> 6) |
672 ((vd & 0x100) >> 7) |
673 ((vt & 0x100) >> 8);
674 reg.crt[0x08] = 0x00;
675 reg.crt[0x09] = 0x40 | ((vbs & 0x200) >> 4);
676 reg.crt[0x0a] = 0x00;
677 reg.crt[0x0b] = 0x00;
678 reg.crt[0x0c] = 0x00;
679 reg.crt[0x0d] = 0x00;
680 reg.crt[0x0e] = 0x00;
681 reg.crt[0x0f] = 0x00;
682 reg.crt[0x10] = vs;
683 reg.crt[0x11] = (ve & 0x0f) | 0x20;
684 reg.crt[0x12] = vd;
685 reg.crt[0x13] = wd;
686 reg.crt[0x14] = 0x00;
687 reg.crt[0x15] = vbs;
688 reg.crt[0x16] = vbe + 1;
689 reg.crt[0x17] = 0xc3;
690 reg.crt[0x18] = 0xff;
691
692 /* Banshee's nonvga stuff */
693 reg.ext[0x00] = (((ht & 0x100) >> 8) |
694 ((hd & 0x100) >> 6) |
695 ((hbs & 0x100) >> 4) |
696 ((hbe & 0x40) >> 1) |
697 ((hs & 0x100) >> 2) |
698 ((he & 0x20) << 2));
699 reg.ext[0x01] = (((vt & 0x400) >> 10) |
700 ((vd & 0x400) >> 8) |
701 ((vbs & 0x400) >> 6) |
702 ((vbe & 0x400) >> 4));
703
704 reg.vgainit0 = VGAINIT0_8BIT_DAC |
705 VGAINIT0_EXT_ENABLE |
706 VGAINIT0_WAKEUP_3C3 |
707 VGAINIT0_ALT_READBACK |
708 VGAINIT0_EXTSHIFTOUT;
709 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
710
711 reg.cursloc = 0;
712
713 reg.cursc0 = 0;
714 reg.cursc1 = 0xffffff;
715
716 reg.stride = info->var.xres * cpp;
717 reg.startaddr = par->baseline * reg.stride;
718 reg.srcbase = reg.startaddr;
719 reg.dstbase = reg.startaddr;
720
721 /* PLL settings */
722 freq = PICOS2KHZ(info->var.pixclock);
723
724 reg.dacmode &= ~DACMODE_2X;
725 reg.vidcfg &= ~VIDCFG_2X;
726 if (freq > par->max_pixclock/2) {
727 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
728 reg.dacmode |= DACMODE_2X;
729 reg.vidcfg |= VIDCFG_2X;
730 }
731 reg.vidpll = do_calc_pll(freq, &fout);
732 #if 0
733 reg.mempll = do_calc_pll(..., &fout);
734 reg.gfxpll = do_calc_pll(..., &fout);
735 #endif
736
737 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
738 reg.screensize = info->var.xres | (info->var.yres << 13);
739 reg.vidcfg |= VIDCFG_HALF_MODE;
740 reg.crt[0x09] |= 0x80;
741 } else {
742 reg.screensize = info->var.xres | (info->var.yres << 12);
743 reg.vidcfg &= ~VIDCFG_HALF_MODE;
744 }
745 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
746 reg.vidcfg |= VIDCFG_INTERLACE;
747 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
748
749 #if defined(__BIG_ENDIAN)
750 switch (info->var.bits_per_pixel) {
751 case 8:
752 case 24:
753 reg.miscinit0 &= ~(1 << 30);
754 reg.miscinit0 &= ~(1 << 31);
755 break;
756 case 16:
757 reg.miscinit0 |= (1 << 30);
758 reg.miscinit0 |= (1 << 31);
759 break;
760 case 32:
761 reg.miscinit0 |= (1 << 30);
762 reg.miscinit0 &= ~(1 << 31);
763 break;
764 }
765 #endif
766 do_write_regs(info, &reg);
767
768 /* Now change fb_fix_screeninfo according to changes in par */
769 info->fix.line_length = info->var.xres * ((info->var.bits_per_pixel + 7)>>3);
770 info->fix.visual = (info->var.bits_per_pixel == 8)
771 ? FB_VISUAL_PSEUDOCOLOR
772 : FB_VISUAL_TRUECOLOR;
773 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
774 return 0;
775 }
776
777 /* A handy macro shamelessly pinched from matroxfb */
778 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
779
780 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
781 unsigned blue,unsigned transp,struct fb_info *info)
782 {
783 struct tdfx_par *par = info->par;
784 u32 rgbcol;
785
786 if (regno >= info->cmap.len || regno > 255) return 1;
787
788 switch (info->fix.visual) {
789 case FB_VISUAL_PSEUDOCOLOR:
790 rgbcol =(((u32)red & 0xff00) << 8) |
791 (((u32)green & 0xff00) << 0) |
792 (((u32)blue & 0xff00) >> 8);
793 do_setpalentry(par, regno, rgbcol);
794 break;
795 /* Truecolor has no hardware color palettes. */
796 case FB_VISUAL_TRUECOLOR:
797 if (regno < 16) {
798 rgbcol = (CNVT_TOHW( red, info->var.red.length) <<
799 info->var.red.offset) |
800 (CNVT_TOHW( green, info->var.green.length) <<
801 info->var.green.offset) |
802 (CNVT_TOHW( blue, info->var.blue.length) <<
803 info->var.blue.offset) |
804 (CNVT_TOHW( transp, info->var.transp.length) <<
805 info->var.transp.offset);
806 par->palette[regno] = rgbcol;
807 }
808
809 break;
810 default:
811 DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
812 break;
813 }
814
815 return 0;
816 }
817
818 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
819 static int tdfxfb_blank(int blank, struct fb_info *info)
820 {
821 struct tdfx_par *par = info->par;
822 u32 dacmode, state = 0, vgablank = 0;
823
824 dacmode = tdfx_inl(par, DACMODE);
825
826 switch (blank) {
827 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
828 state = 0;
829 vgablank = 0;
830 break;
831 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
832 state = 0;
833 vgablank = 1;
834 break;
835 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
836 state = BIT(3);
837 vgablank = 1;
838 break;
839 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
840 state = BIT(1);
841 vgablank = 1;
842 break;
843 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
844 state = BIT(1) | BIT(3);
845 vgablank = 1;
846 break;
847 }
848
849 dacmode &= ~(BIT(1) | BIT(3));
850 dacmode |= state;
851 banshee_make_room(par, 1);
852 tdfx_outl(par, DACMODE, dacmode);
853 if (vgablank)
854 vga_disable_video(par);
855 else
856 vga_enable_video(par);
857 return 0;
858 }
859
860 /*
861 * Set the starting position of the visible screen to var->yoffset
862 */
863 static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
864 struct fb_info *info)
865 {
866 struct tdfx_par *par = info->par;
867 u32 addr;
868
869 if (nopan || var->xoffset || (var->yoffset > var->yres_virtual))
870 return -EINVAL;
871 if ((var->yoffset + var->yres > var->yres_virtual && nowrap))
872 return -EINVAL;
873
874 addr = var->yoffset * info->fix.line_length;
875 banshee_make_room(par, 1);
876 tdfx_outl(par, VIDDESKSTART, addr);
877
878 info->var.xoffset = var->xoffset;
879 info->var.yoffset = var->yoffset;
880 return 0;
881 }
882
883 #ifdef CONFIG_FB_3DFX_ACCEL
884 /*
885 * FillRect 2D command (solidfill or invert (via ROP_XOR))
886 */
887 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
888 {
889 struct tdfx_par *par = info->par;
890 u32 bpp = info->var.bits_per_pixel;
891 u32 stride = info->fix.line_length;
892 u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
893 int tdfx_rop;
894
895 if (rect->rop == ROP_COPY)
896 tdfx_rop = TDFX_ROP_COPY;
897 else
898 tdfx_rop = TDFX_ROP_XOR;
899
900 banshee_make_room(par, 5);
901 tdfx_outl(par, DSTFORMAT, fmt);
902 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
903 tdfx_outl(par, COLORFORE, rect->color);
904 } else { /* FB_VISUAL_TRUECOLOR */
905 tdfx_outl(par, COLORFORE, par->palette[rect->color]);
906 }
907 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
908 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
909 tdfx_outl(par, LAUNCH_2D, rect->dx | (rect->dy << 16));
910 }
911
912 /*
913 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
914 */
915 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
916 {
917 struct tdfx_par *par = info->par;
918 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
919 u32 bpp = info->var.bits_per_pixel;
920 u32 stride = info->fix.line_length;
921 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
922 u32 fmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
923
924 if (area->sx <= area->dx) {
925 //-X
926 blitcmd |= BIT(14);
927 sx += area->width - 1;
928 dx += area->width - 1;
929 }
930 if (area->sy <= area->dy) {
931 //-Y
932 blitcmd |= BIT(15);
933 sy += area->height - 1;
934 dy += area->height - 1;
935 }
936
937 banshee_make_room(par, 6);
938
939 tdfx_outl(par, SRCFORMAT, fmt);
940 tdfx_outl(par, DSTFORMAT, fmt);
941 tdfx_outl(par, COMMAND_2D, blitcmd);
942 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
943 tdfx_outl(par, DSTXY, dx | (dy << 16));
944 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
945 }
946
947 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
948 {
949 struct tdfx_par *par = info->par;
950 int size = image->height * ((image->width * image->depth + 7)>>3);
951 int fifo_free;
952 int i, stride = info->fix.line_length;
953 u32 bpp = info->var.bits_per_pixel;
954 u32 dstfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
955 u8 *chardata = (u8 *) image->data;
956 u32 srcfmt;
957
958 if (image->depth != 1) {
959 //banshee_make_room(par, 6 + ((size + 3) >> 2));
960 //srcfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13) | 0x400000;
961 cfb_imageblit(info, image);
962 return;
963 } else {
964 banshee_make_room(par, 8);
965 switch (info->fix.visual) {
966 case FB_VISUAL_PSEUDOCOLOR:
967 tdfx_outl(par, COLORFORE, image->fg_color);
968 tdfx_outl(par, COLORBACK, image->bg_color);
969 break;
970 case FB_VISUAL_TRUECOLOR:
971 default:
972 tdfx_outl(par, COLORFORE,
973 par->palette[image->fg_color]);
974 tdfx_outl(par, COLORBACK,
975 par->palette[image->bg_color]);
976 }
977 #ifdef __BIG_ENDIAN
978 srcfmt = 0x400000 | BIT(20);
979 #else
980 srcfmt = 0x400000;
981 #endif
982 }
983
984 tdfx_outl(par, SRCXY, 0);
985 tdfx_outl(par, DSTXY, image->dx | (image->dy << 16));
986 tdfx_outl(par, COMMAND_2D, COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
987 tdfx_outl(par, SRCFORMAT, srcfmt);
988 tdfx_outl(par, DSTFORMAT, dstfmt);
989 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
990
991 /* A count of how many free FIFO entries we've requested.
992 * When this goes negative, we need to request more. */
993 fifo_free = 0;
994
995 /* Send four bytes at a time of data */
996 for (i = (size >> 2) ; i > 0; i--) {
997 if(--fifo_free < 0) {
998 fifo_free=31;
999 banshee_make_room(par,fifo_free);
1000 }
1001 tdfx_outl(par, LAUNCH_2D,*(u32*)chardata);
1002 chardata += 4;
1003 }
1004
1005 /* Send the leftovers now */
1006 banshee_make_room(par,3);
1007 i = size%4;
1008 switch (i) {
1009 case 0: break;
1010 case 1: tdfx_outl(par, LAUNCH_2D,*chardata); break;
1011 case 2: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata); break;
1012 case 3: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata | ((chardata[3]) << 24)); break;
1013 }
1014 }
1015 #endif /* CONFIG_FB_3DFX_ACCEL */
1016
1017 #ifdef TDFX_HARDWARE_CURSOR
1018 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1019 {
1020 struct tdfx_par *par = info->par;
1021 unsigned long flags;
1022
1023 /*
1024 * If the cursor is not be changed this means either we want the
1025 * current cursor state (if enable is set) or we want to query what
1026 * we can do with the cursor (if enable is not set)
1027 */
1028 if (!cursor->set) return 0;
1029
1030 /* Too large of a cursor :-( */
1031 if (cursor->image.width > 64 || cursor->image.height > 64)
1032 return -ENXIO;
1033
1034 /*
1035 * If we are going to be changing things we should disable
1036 * the cursor first
1037 */
1038 if (info->cursor.enable) {
1039 spin_lock_irqsave(&par->DAClock, flags);
1040 info->cursor.enable = 0;
1041 del_timer(&(par->hwcursor.timer));
1042 tdfx_outl(par, VIDPROCCFG, par->hwcursor.disable);
1043 spin_unlock_irqrestore(&par->DAClock, flags);
1044 }
1045
1046 /* Disable the Cursor */
1047 if ((cursor->set && FB_CUR_SETCUR) && !cursor->enable)
1048 return 0;
1049
1050 /* fix cursor color - XFree86 forgets to restore it properly */
1051 if (cursor->set && FB_CUR_SETCMAP) {
1052 struct fb_cmap cmap = cursor->image.cmap;
1053 unsigned long bg_color, fg_color;
1054
1055 cmap.len = 2; /* Voodoo 3+ only support 2 color cursors */
1056 fg_color = ((cmap.red[cmap.start] << 16) |
1057 (cmap.green[cmap.start] << 8) |
1058 (cmap.blue[cmap.start]));
1059 bg_color = ((cmap.red[cmap.start+1] << 16) |
1060 (cmap.green[cmap.start+1] << 8) |
1061 (cmap.blue[cmap.start+1]));
1062 fb_copy_cmap(&cmap, &info->cursor.image.cmap);
1063 spin_lock_irqsave(&par->DAClock, flags);
1064 banshee_make_room(par, 2);
1065 tdfx_outl(par, HWCURC0, bg_color);
1066 tdfx_outl(par, HWCURC1, fg_color);
1067 spin_unlock_irqrestore(&par->DAClock, flags);
1068 }
1069
1070 if (cursor->set && FB_CUR_SETPOS) {
1071 int x, y;
1072
1073 x = cursor->image.dx;
1074 y = cursor->image.dy;
1075 y -= info->var.yoffset;
1076 info->cursor.image.dx = x;
1077 info->cursor.image.dy = y;
1078 x += 63;
1079 y += 63;
1080 spin_lock_irqsave(&par->DAClock, flags);
1081 banshee_make_room(par, 1);
1082 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1083 spin_unlock_irqrestore(&par->DAClock, flags);
1084 }
1085
1086 /* Not supported so we fake it */
1087 if (cursor->set && FB_CUR_SETHOT) {
1088 info->cursor.hot.x = cursor->hot.x;
1089 info->cursor.hot.y = cursor->hot.y;
1090 }
1091
1092 if (cursor->set && FB_CUR_SETSHAPE) {
1093 /*
1094 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1095 * The reason is so the card can fetch 8 words at a time
1096 * and are stored on chip for use for the next 8 scanlines.
1097 * This reduces the number of times for access to draw the
1098 * cursor for each screen refresh.
1099 * Each pattern is a bitmap of 64 bit wide and 64 bit high
1100 * (total of 8192 bits or 1024 Kbytes). The two patterns are
1101 * stored in such a way that pattern 0 always resides in the
1102 * lower half (least significant 64 bits) of a 128 bit word
1103 * and pattern 1 the upper half. If you examine the data of
1104 * the cursor image the graphics card uses then from the
1105 * begining you see line one of pattern 0, line one of
1106 * pattern 1, line two of pattern 0, line two of pattern 1,
1107 * etc etc. The linear stride for the cursor is always 16 bytes
1108 * (128 bits) which is the maximum cursor width times two for
1109 * the two monochrome patterns.
1110 */
1111 u8 *cursorbase = (u8 *) info->cursor.image.data;
1112 char *bitmap = (char *)cursor->image.data;
1113 char *mask = (char *) cursor->mask;
1114 int i, j, k, h = 0;
1115
1116 for (i = 0; i < 64; i++) {
1117 if (i < cursor->image.height) {
1118 j = (cursor->image.width + 7) >> 3;
1119 k = 8 - j;
1120
1121 for (;j > 0; j--) {
1122 /* Pattern 0. Copy the cursor bitmap to it */
1123 fb_writeb(*bitmap, cursorbase + h);
1124 bitmap++;
1125 /* Pattern 1. Copy the cursor mask to it */
1126 fb_writeb(*mask, cursorbase + h + 8);
1127 mask++;
1128 h++;
1129 }
1130 for (;k > 0; k--) {
1131 fb_writeb(0, cursorbase + h);
1132 fb_writeb(~0, cursorbase + h + 8);
1133 h++;
1134 }
1135 } else {
1136 fb_writel(0, cursorbase + h);
1137 fb_writel(0, cursorbase + h + 4);
1138 fb_writel(~0, cursorbase + h + 8);
1139 fb_writel(~0, cursorbase + h + 12);
1140 h += 16;
1141 }
1142 }
1143 }
1144 /* Turn the cursor on */
1145 cursor->enable = 1;
1146 info->cursor = *cursor;
1147 mod_timer(&par->hwcursor.timer, jiffies+HZ/2);
1148 spin_lock_irqsave(&par->DAClock, flags);
1149 banshee_make_room(par, 1);
1150 tdfx_outl(par, VIDPROCCFG, par->hwcursor.enable);
1151 spin_unlock_irqrestore(&par->DAClock, flags);
1152 return 0;
1153 }
1154 #endif
1155
1156 /**
1157 * tdfxfb_probe - Device Initializiation
1158 *
1159 * @pdev: PCI Device to initialize
1160 * @id: PCI Device ID
1161 *
1162 * Initializes and allocates resources for PCI device @pdev.
1163 *
1164 */
1165 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
1166 const struct pci_device_id *id)
1167 {
1168 struct tdfx_par *default_par;
1169 struct fb_info *info;
1170 int err, lpitch;
1171
1172 if ((err = pci_enable_device(pdev))) {
1173 printk(KERN_WARNING "tdfxfb: Can't enable pdev: %d\n", err);
1174 return err;
1175 }
1176
1177 info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
1178
1179 if (!info)
1180 return -ENOMEM;
1181
1182 default_par = info->par;
1183
1184 /* Configure the default fb_fix_screeninfo first */
1185 switch (pdev->device) {
1186 case PCI_DEVICE_ID_3DFX_BANSHEE:
1187 strcat(tdfx_fix.id, " Banshee");
1188 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1189 break;
1190 case PCI_DEVICE_ID_3DFX_VOODOO3:
1191 strcat(tdfx_fix.id, " Voodoo3");
1192 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1193 break;
1194 case PCI_DEVICE_ID_3DFX_VOODOO5:
1195 strcat(tdfx_fix.id, " Voodoo5");
1196 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1197 break;
1198 }
1199
1200 tdfx_fix.mmio_start = pci_resource_start(pdev, 0);
1201 tdfx_fix.mmio_len = pci_resource_len(pdev, 0);
1202 default_par->regbase_virt = ioremap_nocache(tdfx_fix.mmio_start, tdfx_fix.mmio_len);
1203 if (!default_par->regbase_virt) {
1204 printk("fb: Can't remap %s register area.\n", tdfx_fix.id);
1205 goto out_err;
1206 }
1207
1208 if (!request_mem_region(pci_resource_start(pdev, 0),
1209 pci_resource_len(pdev, 0), "tdfx regbase")) {
1210 printk(KERN_WARNING "tdfxfb: Can't reserve regbase\n");
1211 goto out_err;
1212 }
1213
1214 tdfx_fix.smem_start = pci_resource_start(pdev, 1);
1215 if (!(tdfx_fix.smem_len = do_lfb_size(default_par, pdev->device))) {
1216 printk("fb: Can't count %s memory.\n", tdfx_fix.id);
1217 release_mem_region(pci_resource_start(pdev, 0),
1218 pci_resource_len(pdev, 0));
1219 goto out_err;
1220 }
1221
1222 if (!request_mem_region(pci_resource_start(pdev, 1),
1223 pci_resource_len(pdev, 1), "tdfx smem")) {
1224 printk(KERN_WARNING "tdfxfb: Can't reserve smem\n");
1225 release_mem_region(pci_resource_start(pdev, 0),
1226 pci_resource_len(pdev, 0));
1227 goto out_err;
1228 }
1229
1230 info->screen_base = ioremap_nocache(tdfx_fix.smem_start,
1231 tdfx_fix.smem_len);
1232 if (!info->screen_base) {
1233 printk("fb: Can't remap %s framebuffer.\n", tdfx_fix.id);
1234 release_mem_region(pci_resource_start(pdev, 1),
1235 pci_resource_len(pdev, 1));
1236 release_mem_region(pci_resource_start(pdev, 0),
1237 pci_resource_len(pdev, 0));
1238 goto out_err;
1239 }
1240
1241 default_par->iobase = pci_resource_start(pdev, 2);
1242
1243 if (!request_region(pci_resource_start(pdev, 2),
1244 pci_resource_len(pdev, 2), "tdfx iobase")) {
1245 printk(KERN_WARNING "tdfxfb: Can't reserve iobase\n");
1246 release_mem_region(pci_resource_start(pdev, 1),
1247 pci_resource_len(pdev, 1));
1248 release_mem_region(pci_resource_start(pdev, 0),
1249 pci_resource_len(pdev, 0));
1250 goto out_err;
1251 }
1252
1253 printk("fb: %s memory = %dK\n", tdfx_fix.id, tdfx_fix.smem_len >> 10);
1254
1255 tdfx_fix.ypanstep = nopan ? 0 : 1;
1256 tdfx_fix.ywrapstep = nowrap ? 0 : 1;
1257
1258 info->fbops = &tdfxfb_ops;
1259 info->fix = tdfx_fix;
1260 info->pseudo_palette = default_par->palette;
1261 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1262 #ifdef CONFIG_FB_3DFX_ACCEL
1263 info->flags |= FBINFO_HWACCEL_FILLRECT |
1264 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_IMAGEBLIT;
1265 #endif
1266
1267 if (!mode_option)
1268 mode_option = "640x480@60";
1269
1270 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1271 if (!err || err == 4)
1272 info->var = tdfx_var;
1273
1274 /* maximize virtual vertical length */
1275 lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
1276 info->var.yres_virtual = info->fix.smem_len/lpitch;
1277 if (info->var.yres_virtual < info->var.yres)
1278 goto out_err;
1279
1280 #ifdef CONFIG_FB_3DFX_ACCEL
1281 /*
1282 * FIXME: Limit var->yres_virtual to 4096 because of screen artifacts
1283 * during scrolling. This is only present if 2D acceleration is
1284 * enabled.
1285 */
1286 if (info->var.yres_virtual > 4096)
1287 info->var.yres_virtual = 4096;
1288 #endif /* CONFIG_FB_3DFX_ACCEL */
1289
1290 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1291 printk(KERN_WARNING "tdfxfb: Can't allocate color map\n");
1292 goto out_err;
1293 }
1294
1295 if (register_framebuffer(info) < 0) {
1296 printk("tdfxfb: can't register framebuffer\n");
1297 fb_dealloc_cmap(&info->cmap);
1298 goto out_err;
1299 }
1300 /*
1301 * Our driver data
1302 */
1303 pci_set_drvdata(pdev, info);
1304 return 0;
1305
1306 out_err:
1307 /*
1308 * Cleanup after anything that was remapped/allocated.
1309 */
1310 if (default_par->regbase_virt)
1311 iounmap(default_par->regbase_virt);
1312 if (info->screen_base)
1313 iounmap(info->screen_base);
1314 framebuffer_release(info);
1315 return -ENXIO;
1316 }
1317
1318 #ifndef MODULE
1319 static void tdfxfb_setup(char *options)
1320 {
1321 char* this_opt;
1322
1323 if (!options || !*options)
1324 return;
1325
1326 while ((this_opt = strsep(&options, ",")) != NULL) {
1327 if (!*this_opt)
1328 continue;
1329 if(!strcmp(this_opt, "nopan")) {
1330 nopan = 1;
1331 } else if(!strcmp(this_opt, "nowrap")) {
1332 nowrap = 1;
1333 } else {
1334 mode_option = this_opt;
1335 }
1336 }
1337 }
1338 #endif
1339
1340 /**
1341 * tdfxfb_remove - Device removal
1342 *
1343 * @pdev: PCI Device to cleanup
1344 *
1345 * Releases all resources allocated during the course of the driver's
1346 * lifetime for the PCI device @pdev.
1347 *
1348 */
1349 static void __devexit tdfxfb_remove(struct pci_dev *pdev)
1350 {
1351 struct fb_info *info = pci_get_drvdata(pdev);
1352 struct tdfx_par *par = info->par;
1353
1354 unregister_framebuffer(info);
1355 iounmap(par->regbase_virt);
1356 iounmap(info->screen_base);
1357
1358 /* Clean up after reserved regions */
1359 release_region(pci_resource_start(pdev, 2),
1360 pci_resource_len(pdev, 2));
1361 release_mem_region(pci_resource_start(pdev, 1),
1362 pci_resource_len(pdev, 1));
1363 release_mem_region(pci_resource_start(pdev, 0),
1364 pci_resource_len(pdev, 0));
1365 pci_set_drvdata(pdev, NULL);
1366 framebuffer_release(info);
1367 }
1368
1369 static int __init tdfxfb_init(void)
1370 {
1371 #ifndef MODULE
1372 char *option = NULL;
1373
1374 if (fb_get_options("tdfxfb", &option))
1375 return -ENODEV;
1376
1377 tdfxfb_setup(option);
1378 #endif
1379 return pci_register_driver(&tdfxfb_driver);
1380 }
1381
1382 static void __exit tdfxfb_exit(void)
1383 {
1384 pci_unregister_driver(&tdfxfb_driver);
1385 }
1386
1387 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1388 MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1389 MODULE_LICENSE("GPL");
1390
1391 module_init(tdfxfb_init);
1392 module_exit(tdfxfb_exit);
Linux with added FPC-III support