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[S390] add __cpuinit to appldata cpu hotplug notifier.
[linux/fpc-iii.git] / drivers / pci / probe.c
blobf89dbc3738b7d73f54142e12d598c5759fa368d7
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25 #ifdef HAVE_PCI_LEGACY
26 /**
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
29 *
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
33 */
34 static void pci_create_legacy_files(struct pci_bus *b)
35 {
36 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
37 GFP_ATOMIC);
38 if (b->legacy_io) {
39 b->legacy_io->attr.name = "legacy_io";
40 b->legacy_io->size = 0xffff;
41 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
42 b->legacy_io->attr.owner = THIS_MODULE;
43 b->legacy_io->read = pci_read_legacy_io;
44 b->legacy_io->write = pci_write_legacy_io;
45 class_device_create_bin_file(&b->class_dev, b->legacy_io);
46
47 /* Allocated above after the legacy_io struct */
48 b->legacy_mem = b->legacy_io + 1;
49 b->legacy_mem->attr.name = "legacy_mem";
50 b->legacy_mem->size = 1024*1024;
51 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
52 b->legacy_mem->attr.owner = THIS_MODULE;
53 b->legacy_mem->mmap = pci_mmap_legacy_mem;
54 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
55 }
56 }
57
58 void pci_remove_legacy_files(struct pci_bus *b)
59 {
60 if (b->legacy_io) {
61 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
62 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
63 kfree(b->legacy_io); /* both are allocated here */
64 }
65 }
66 #else /* !HAVE_PCI_LEGACY */
67 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
68 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
69 #endif /* HAVE_PCI_LEGACY */
70
71 /*
72 * PCI Bus Class Devices
73 */
74 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
75 char *buf)
76 {
77 int ret;
78 cpumask_t cpumask;
79
80 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
81 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
82 if (ret < PAGE_SIZE)
83 buf[ret++] = '\n';
84 return ret;
85 }
86 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
87
88 /*
89 * PCI Bus Class
90 */
91 static void release_pcibus_dev(struct class_device *class_dev)
92 {
93 struct pci_bus *pci_bus = to_pci_bus(class_dev);
94
95 if (pci_bus->bridge)
96 put_device(pci_bus->bridge);
97 kfree(pci_bus);
98 }
99
100 static struct class pcibus_class = {
101 .name = "pci_bus",
102 .release = &release_pcibus_dev,
103 };
104
105 static int __init pcibus_class_init(void)
106 {
107 return class_register(&pcibus_class);
108 }
109 postcore_initcall(pcibus_class_init);
110
111 /*
112 * Translate the low bits of the PCI base
113 * to the resource type
114 */
115 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
116 {
117 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
118 return IORESOURCE_IO;
119
120 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
121 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
122
123 return IORESOURCE_MEM;
124 }
125
126 /*
127 * Find the extent of a PCI decode..
128 */
129 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
130 {
131 u32 size = mask & maxbase; /* Find the significant bits */
132 if (!size)
133 return 0;
134
135 /* Get the lowest of them to find the decode size, and
136 from that the extent. */
137 size = (size & ~(size-1)) - 1;
138
139 /* base == maxbase can be valid only if the BAR has
140 already been programmed with all 1s. */
141 if (base == maxbase && ((base | size) & mask) != mask)
142 return 0;
143
144 return size;
145 }
146
147 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
148 {
149 unsigned int pos, reg, next;
150 u32 l, sz;
151 struct resource *res;
152
153 for(pos=0; pos<howmany; pos = next) {
154 next = pos+1;
155 res = &dev->resource[pos];
156 res->name = pci_name(dev);
157 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
158 pci_read_config_dword(dev, reg, &l);
159 pci_write_config_dword(dev, reg, ~0);
160 pci_read_config_dword(dev, reg, &sz);
161 pci_write_config_dword(dev, reg, l);
162 if (!sz || sz == 0xffffffff)
163 continue;
164 if (l == 0xffffffff)
165 l = 0;
166 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
167 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
168 if (!sz)
169 continue;
170 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
171 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
172 } else {
173 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
174 if (!sz)
175 continue;
176 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
177 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
178 }
179 res->end = res->start + (unsigned long) sz;
180 res->flags |= pci_calc_resource_flags(l);
181 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
182 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
183 u32 szhi, lhi;
184 pci_read_config_dword(dev, reg+4, &lhi);
185 pci_write_config_dword(dev, reg+4, ~0);
186 pci_read_config_dword(dev, reg+4, &szhi);
187 pci_write_config_dword(dev, reg+4, lhi);
188 szhi = pci_size(lhi, szhi, 0xffffffff);
189 next++;
190 #if BITS_PER_LONG == 64
191 res->start |= ((unsigned long) lhi) << 32;
192 res->end = res->start + sz;
193 if (szhi) {
194 /* This BAR needs > 4GB? Wow. */
195 res->end |= (unsigned long)szhi<<32;
196 }
197 #else
198 if (szhi) {
199 printk(KERN_ERR "PCI: Unable to handle 64-bit BAR for device %s\n", pci_name(dev));
200 res->start = 0;
201 res->flags = 0;
202 } else if (lhi) {
203 /* 64-bit wide address, treat as disabled */
204 pci_write_config_dword(dev, reg, l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
205 pci_write_config_dword(dev, reg+4, 0);
206 res->start = 0;
207 res->end = sz;
208 }
209 #endif
210 }
211 }
212 if (rom) {
213 dev->rom_base_reg = rom;
214 res = &dev->resource[PCI_ROM_RESOURCE];
215 res->name = pci_name(dev);
216 pci_read_config_dword(dev, rom, &l);
217 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
218 pci_read_config_dword(dev, rom, &sz);
219 pci_write_config_dword(dev, rom, l);
220 if (l == 0xffffffff)
221 l = 0;
222 if (sz && sz != 0xffffffff) {
223 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
224 if (sz) {
225 res->flags = (l & IORESOURCE_ROM_ENABLE) |
226 IORESOURCE_MEM | IORESOURCE_PREFETCH |
227 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
228 res->start = l & PCI_ROM_ADDRESS_MASK;
229 res->end = res->start + (unsigned long) sz;
230 }
231 }
232 }
233 }
234
235 void __devinit pci_read_bridge_bases(struct pci_bus *child)
236 {
237 struct pci_dev *dev = child->self;
238 u8 io_base_lo, io_limit_lo;
239 u16 mem_base_lo, mem_limit_lo;
240 unsigned long base, limit;
241 struct resource *res;
242 int i;
243
244 if (!dev) /* It's a host bus, nothing to read */
245 return;
246
247 if (dev->transparent) {
248 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
249 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
250 child->resource[i] = child->parent->resource[i - 3];
251 }
252
253 for(i=0; i<3; i++)
254 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
255
256 res = child->resource[0];
257 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
258 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
259 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
260 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
261
262 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
263 u16 io_base_hi, io_limit_hi;
264 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
265 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
266 base |= (io_base_hi << 16);
267 limit |= (io_limit_hi << 16);
268 }
269
270 if (base <= limit) {
271 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
272 if (!res->start)
273 res->start = base;
274 if (!res->end)
275 res->end = limit + 0xfff;
276 }
277
278 res = child->resource[1];
279 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
280 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
281 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
282 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
283 if (base <= limit) {
284 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
285 res->start = base;
286 res->end = limit + 0xfffff;
287 }
288
289 res = child->resource[2];
290 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
291 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
292 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
293 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
294
295 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
296 u32 mem_base_hi, mem_limit_hi;
297 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
298 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
299
300 /*
301 * Some bridges set the base > limit by default, and some
302 * (broken) BIOSes do not initialize them. If we find
303 * this, just assume they are not being used.
304 */
305 if (mem_base_hi <= mem_limit_hi) {
306 #if BITS_PER_LONG == 64
307 base |= ((long) mem_base_hi) << 32;
308 limit |= ((long) mem_limit_hi) << 32;
309 #else
310 if (mem_base_hi || mem_limit_hi) {
311 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
312 return;
313 }
314 #endif
315 }
316 }
317 if (base <= limit) {
318 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
319 res->start = base;
320 res->end = limit + 0xfffff;
321 }
322 }
323
324 static struct pci_bus * __devinit pci_alloc_bus(void)
325 {
326 struct pci_bus *b;
327
328 b = kzalloc(sizeof(*b), GFP_KERNEL);
329 if (b) {
330 INIT_LIST_HEAD(&b->node);
331 INIT_LIST_HEAD(&b->children);
332 INIT_LIST_HEAD(&b->devices);
333 }
334 return b;
335 }
336
337 static struct pci_bus * __devinit
338 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
339 {
340 struct pci_bus *child;
341 int i;
342
343 /*
344 * Allocate a new bus, and inherit stuff from the parent..
345 */
346 child = pci_alloc_bus();
347 if (!child)
348 return NULL;
349
350 child->self = bridge;
351 child->parent = parent;
352 child->ops = parent->ops;
353 child->sysdata = parent->sysdata;
354 child->bus_flags = parent->bus_flags;
355 child->bridge = get_device(&bridge->dev);
356
357 child->class_dev.class = &pcibus_class;
358 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
359 class_device_register(&child->class_dev);
360 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
361
362 /*
363 * Set up the primary, secondary and subordinate
364 * bus numbers.
365 */
366 child->number = child->secondary = busnr;
367 child->primary = parent->secondary;
368 child->subordinate = 0xff;
369
370 /* Set up default resource pointers and names.. */
371 for (i = 0; i < 4; i++) {
372 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
373 child->resource[i]->name = child->name;
374 }
375 bridge->subordinate = child;
376
377 return child;
378 }
379
380 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
381 {
382 struct pci_bus *child;
383
384 child = pci_alloc_child_bus(parent, dev, busnr);
385 if (child) {
386 down_write(&pci_bus_sem);
387 list_add_tail(&child->node, &parent->children);
388 up_write(&pci_bus_sem);
389 }
390 return child;
391 }
392
393 static void pci_enable_crs(struct pci_dev *dev)
394 {
395 u16 cap, rpctl;
396 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
397 if (!rpcap)
398 return;
399
400 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
401 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
402 return;
403
404 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
405 rpctl |= PCI_EXP_RTCTL_CRSSVE;
406 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
407 }
408
409 static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
410 {
411 struct pci_bus *parent = child->parent;
412
413 /* Attempts to fix that up are really dangerous unless
414 we're going to re-assign all bus numbers. */
415 if (!pcibios_assign_all_busses())
416 return;
417
418 while (parent->parent && parent->subordinate < max) {
419 parent->subordinate = max;
420 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
421 parent = parent->parent;
422 }
423 }
424
425 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
426
427 /*
428 * If it's a bridge, configure it and scan the bus behind it.
429 * For CardBus bridges, we don't scan behind as the devices will
430 * be handled by the bridge driver itself.
431 *
432 * We need to process bridges in two passes -- first we scan those
433 * already configured by the BIOS and after we are done with all of
434 * them, we proceed to assigning numbers to the remaining buses in
435 * order to avoid overlaps between old and new bus numbers.
436 */
437 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
438 {
439 struct pci_bus *child;
440 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
441 u32 buses, i, j = 0;
442 u16 bctl;
443
444 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
445
446 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
447 pci_name(dev), buses & 0xffffff, pass);
448
449 /* Disable MasterAbortMode during probing to avoid reporting
450 of bus errors (in some architectures) */
451 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
452 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
453 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
454
455 pci_enable_crs(dev);
456
457 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
458 unsigned int cmax, busnr;
459 /*
460 * Bus already configured by firmware, process it in the first
461 * pass and just note the configuration.
462 */
463 if (pass)
464 goto out;
465 busnr = (buses >> 8) & 0xFF;
466
467 /*
468 * If we already got to this bus through a different bridge,
469 * ignore it. This can happen with the i450NX chipset.
470 */
471 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
472 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
473 pci_domain_nr(bus), busnr);
474 goto out;
475 }
476
477 child = pci_add_new_bus(bus, dev, busnr);
478 if (!child)
479 goto out;
480 child->primary = buses & 0xFF;
481 child->subordinate = (buses >> 16) & 0xFF;
482 child->bridge_ctl = bctl;
483
484 cmax = pci_scan_child_bus(child);
485 if (cmax > max)
486 max = cmax;
487 if (child->subordinate > max)
488 max = child->subordinate;
489 } else {
490 /*
491 * We need to assign a number to this bus which we always
492 * do in the second pass.
493 */
494 if (!pass) {
495 if (pcibios_assign_all_busses())
496 /* Temporarily disable forwarding of the
497 configuration cycles on all bridges in
498 this bus segment to avoid possible
499 conflicts in the second pass between two
500 bridges programmed with overlapping
501 bus ranges. */
502 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
503 buses & ~0xffffff);
504 goto out;
505 }
506
507 /* Clear errors */
508 pci_write_config_word(dev, PCI_STATUS, 0xffff);
509
510 /* Prevent assigning a bus number that already exists.
511 * This can happen when a bridge is hot-plugged */
512 if (pci_find_bus(pci_domain_nr(bus), max+1))
513 goto out;
514 child = pci_add_new_bus(bus, dev, ++max);
515 buses = (buses & 0xff000000)
516 | ((unsigned int)(child->primary) << 0)
517 | ((unsigned int)(child->secondary) << 8)
518 | ((unsigned int)(child->subordinate) << 16);
519
520 /*
521 * yenta.c forces a secondary latency timer of 176.
522 * Copy that behaviour here.
523 */
524 if (is_cardbus) {
525 buses &= ~0xff000000;
526 buses |= CARDBUS_LATENCY_TIMER << 24;
527 }
528
529 /*
530 * We need to blast all three values with a single write.
531 */
532 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
533
534 if (!is_cardbus) {
535 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
536 /*
537 * Adjust subordinate busnr in parent buses.
538 * We do this before scanning for children because
539 * some devices may not be detected if the bios
540 * was lazy.
541 */
542 pci_fixup_parent_subordinate_busnr(child, max);
543 /* Now we can scan all subordinate buses... */
544 max = pci_scan_child_bus(child);
545 /*
546 * now fix it up again since we have found
547 * the real value of max.
548 */
549 pci_fixup_parent_subordinate_busnr(child, max);
550 } else {
551 /*
552 * For CardBus bridges, we leave 4 bus numbers
553 * as cards with a PCI-to-PCI bridge can be
554 * inserted later.
555 */
556 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
557 struct pci_bus *parent = bus;
558 if (pci_find_bus(pci_domain_nr(bus),
559 max+i+1))
560 break;
561 while (parent->parent) {
562 if ((!pcibios_assign_all_busses()) &&
563 (parent->subordinate > max) &&
564 (parent->subordinate <= max+i)) {
565 j = 1;
566 }
567 parent = parent->parent;
568 }
569 if (j) {
570 /*
571 * Often, there are two cardbus bridges
572 * -- try to leave one valid bus number
573 * for each one.
574 */
575 i /= 2;
576 break;
577 }
578 }
579 max += i;
580 pci_fixup_parent_subordinate_busnr(child, max);
581 }
582 /*
583 * Set the subordinate bus number to its real value.
584 */
585 child->subordinate = max;
586 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
587 }
588
589 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
590
591 while (bus->parent) {
592 if ((child->subordinate > bus->subordinate) ||
593 (child->number > bus->subordinate) ||
594 (child->number < bus->number) ||
595 (child->subordinate < bus->number)) {
596 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) is "
597 "hidden behind%s bridge #%02x (-#%02x)%s\n",
598 child->number, child->subordinate,
599 bus->self->transparent ? " transparent" : " ",
600 bus->number, bus->subordinate,
601 pcibios_assign_all_busses() ? " " :
602 " (try 'pci=assign-busses')");
603 printk(KERN_WARNING "Please report the result to "
604 "linux-kernel to fix this permanently\n");
605 }
606 bus = bus->parent;
607 }
608
609 out:
610 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
611
612 return max;
613 }
614
615 /*
616 * Read interrupt line and base address registers.
617 * The architecture-dependent code can tweak these, of course.
618 */
619 static void pci_read_irq(struct pci_dev *dev)
620 {
621 unsigned char irq;
622
623 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
624 dev->pin = irq;
625 if (irq)
626 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
627 dev->irq = irq;
628 }
629
630 /**
631 * pci_setup_device - fill in class and map information of a device
632 * @dev: the device structure to fill
633 *
634 * Initialize the device structure with information about the device's
635 * vendor,class,memory and IO-space addresses,IRQ lines etc.
636 * Called at initialisation of the PCI subsystem and by CardBus services.
637 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
638 * or CardBus).
639 */
640 static int pci_setup_device(struct pci_dev * dev)
641 {
642 u32 class;
643
644 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
645 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
646
647 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
648 class >>= 8; /* upper 3 bytes */
649 dev->class = class;
650 class >>= 8;
651
652 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
653 dev->vendor, dev->device, class, dev->hdr_type);
654
655 /* "Unknown power state" */
656 dev->current_state = PCI_UNKNOWN;
657
658 /* Early fixups, before probing the BARs */
659 pci_fixup_device(pci_fixup_early, dev);
660 class = dev->class >> 8;
661
662 switch (dev->hdr_type) { /* header type */
663 case PCI_HEADER_TYPE_NORMAL: /* standard header */
664 if (class == PCI_CLASS_BRIDGE_PCI)
665 goto bad;
666 pci_read_irq(dev);
667 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
668 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
669 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
670 break;
671
672 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
673 if (class != PCI_CLASS_BRIDGE_PCI)
674 goto bad;
675 /* The PCI-to-PCI bridge spec requires that subtractive
676 decoding (i.e. transparent) bridge must have programming
677 interface code of 0x01. */
678 pci_read_irq(dev);
679 dev->transparent = ((dev->class & 0xff) == 1);
680 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
681 break;
682
683 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
684 if (class != PCI_CLASS_BRIDGE_CARDBUS)
685 goto bad;
686 pci_read_irq(dev);
687 pci_read_bases(dev, 1, 0);
688 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
689 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
690 break;
691
692 default: /* unknown header */
693 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
694 pci_name(dev), dev->hdr_type);
695 return -1;
696
697 bad:
698 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
699 pci_name(dev), class, dev->hdr_type);
700 dev->class = PCI_CLASS_NOT_DEFINED;
701 }
702
703 /* We found a fine healthy device, go go go... */
704 return 0;
705 }
706
707 /**
708 * pci_release_dev - free a pci device structure when all users of it are finished.
709 * @dev: device that's been disconnected
710 *
711 * Will be called only by the device core when all users of this pci device are
712 * done.
713 */
714 static void pci_release_dev(struct device *dev)
715 {
716 struct pci_dev *pci_dev;
717
718 pci_dev = to_pci_dev(dev);
719 kfree(pci_dev);
720 }
721
722 /**
723 * pci_cfg_space_size - get the configuration space size of the PCI device.
724 * @dev: PCI device
725 *
726 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
727 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
728 * access it. Maybe we don't have a way to generate extended config space
729 * accesses, or the device is behind a reverse Express bridge. So we try
730 * reading the dword at 0x100 which must either be 0 or a valid extended
731 * capability header.
732 */
733 int pci_cfg_space_size(struct pci_dev *dev)
734 {
735 int pos;
736 u32 status;
737
738 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
739 if (!pos) {
740 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
741 if (!pos)
742 goto fail;
743
744 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
745 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
746 goto fail;
747 }
748
749 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
750 goto fail;
751 if (status == 0xffffffff)
752 goto fail;
753
754 return PCI_CFG_SPACE_EXP_SIZE;
755
756 fail:
757 return PCI_CFG_SPACE_SIZE;
758 }
759
760 static void pci_release_bus_bridge_dev(struct device *dev)
761 {
762 kfree(dev);
763 }
764
765 /*
766 * Read the config data for a PCI device, sanity-check it
767 * and fill in the dev structure...
768 */
769 static struct pci_dev * __devinit
770 pci_scan_device(struct pci_bus *bus, int devfn)
771 {
772 struct pci_dev *dev;
773 u32 l;
774 u8 hdr_type;
775 int delay = 1;
776
777 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
778 return NULL;
779
780 /* some broken boards return 0 or ~0 if a slot is empty: */
781 if (l == 0xffffffff || l == 0x00000000 ||
782 l == 0x0000ffff || l == 0xffff0000)
783 return NULL;
784
785 /* Configuration request Retry Status */
786 while (l == 0xffff0001) {
787 msleep(delay);
788 delay *= 2;
789 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
790 return NULL;
791 /* Card hasn't responded in 60 seconds? Must be stuck. */
792 if (delay > 60 * 1000) {
793 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
794 "responding\n", pci_domain_nr(bus),
795 bus->number, PCI_SLOT(devfn),
796 PCI_FUNC(devfn));
797 return NULL;
798 }
799 }
800
801 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
802 return NULL;
803
804 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
805 if (!dev)
806 return NULL;
807
808 dev->bus = bus;
809 dev->sysdata = bus->sysdata;
810 dev->dev.parent = bus->bridge;
811 dev->dev.bus = &pci_bus_type;
812 dev->devfn = devfn;
813 dev->hdr_type = hdr_type & 0x7f;
814 dev->multifunction = !!(hdr_type & 0x80);
815 dev->vendor = l & 0xffff;
816 dev->device = (l >> 16) & 0xffff;
817 dev->cfg_size = pci_cfg_space_size(dev);
818
819 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
820 set this higher, assuming the system even supports it. */
821 dev->dma_mask = 0xffffffff;
822 if (pci_setup_device(dev) < 0) {
823 kfree(dev);
824 return NULL;
825 }
826
827 return dev;
828 }
829
830 void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
831 {
832 device_initialize(&dev->dev);
833 dev->dev.release = pci_release_dev;
834 pci_dev_get(dev);
835
836 dev->dev.dma_mask = &dev->dma_mask;
837 dev->dev.coherent_dma_mask = 0xffffffffull;
838
839 /* Fix up broken headers */
840 pci_fixup_device(pci_fixup_header, dev);
841
842 /*
843 * Add the device to our list of discovered devices
844 * and the bus list for fixup functions, etc.
845 */
846 INIT_LIST_HEAD(&dev->global_list);
847 down_write(&pci_bus_sem);
848 list_add_tail(&dev->bus_list, &bus->devices);
849 up_write(&pci_bus_sem);
850 }
851
852 struct pci_dev * __devinit
853 pci_scan_single_device(struct pci_bus *bus, int devfn)
854 {
855 struct pci_dev *dev;
856
857 dev = pci_scan_device(bus, devfn);
858 if (!dev)
859 return NULL;
860
861 pci_device_add(dev, bus);
862 pci_scan_msi_device(dev);
863
864 return dev;
865 }
866
867 /**
868 * pci_scan_slot - scan a PCI slot on a bus for devices.
869 * @bus: PCI bus to scan
870 * @devfn: slot number to scan (must have zero function.)
871 *
872 * Scan a PCI slot on the specified PCI bus for devices, adding
873 * discovered devices to the @bus->devices list. New devices
874 * will have an empty dev->global_list head.
875 */
876 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
877 {
878 int func, nr = 0;
879 int scan_all_fns;
880
881 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
882
883 for (func = 0; func < 8; func++, devfn++) {
884 struct pci_dev *dev;
885
886 dev = pci_scan_single_device(bus, devfn);
887 if (dev) {
888 nr++;
889
890 /*
891 * If this is a single function device,
892 * don't scan past the first function.
893 */
894 if (!dev->multifunction) {
895 if (func > 0) {
896 dev->multifunction = 1;
897 } else {
898 break;
899 }
900 }
901 } else {
902 if (func == 0 && !scan_all_fns)
903 break;
904 }
905 }
906 return nr;
907 }
908
909 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
910 {
911 unsigned int devfn, pass, max = bus->secondary;
912 struct pci_dev *dev;
913
914 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
915
916 /* Go find them, Rover! */
917 for (devfn = 0; devfn < 0x100; devfn += 8)
918 pci_scan_slot(bus, devfn);
919
920 /*
921 * After performing arch-dependent fixup of the bus, look behind
922 * all PCI-to-PCI bridges on this bus.
923 */
924 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
925 pcibios_fixup_bus(bus);
926 for (pass=0; pass < 2; pass++)
927 list_for_each_entry(dev, &bus->devices, bus_list) {
928 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
929 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
930 max = pci_scan_bridge(bus, dev, max, pass);
931 }
932
933 /*
934 * We've scanned the bus and so we know all about what's on
935 * the other side of any bridges that may be on this bus plus
936 * any devices.
937 *
938 * Return how far we've got finding sub-buses.
939 */
940 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
941 pci_domain_nr(bus), bus->number, max);
942 return max;
943 }
944
945 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
946 {
947 unsigned int max;
948
949 max = pci_scan_child_bus(bus);
950
951 /*
952 * Make the discovered devices available.
953 */
954 pci_bus_add_devices(bus);
955
956 return max;
957 }
958
959 struct pci_bus * __devinit pci_create_bus(struct device *parent,
960 int bus, struct pci_ops *ops, void *sysdata)
961 {
962 int error;
963 struct pci_bus *b;
964 struct device *dev;
965
966 b = pci_alloc_bus();
967 if (!b)
968 return NULL;
969
970 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
971 if (!dev){
972 kfree(b);
973 return NULL;
974 }
975
976 b->sysdata = sysdata;
977 b->ops = ops;
978
979 if (pci_find_bus(pci_domain_nr(b), bus)) {
980 /* If we already got to this bus through a different bridge, ignore it */
981 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
982 goto err_out;
983 }
984
985 down_write(&pci_bus_sem);
986 list_add_tail(&b->node, &pci_root_buses);
987 up_write(&pci_bus_sem);
988
989 memset(dev, 0, sizeof(*dev));
990 dev->parent = parent;
991 dev->release = pci_release_bus_bridge_dev;
992 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
993 error = device_register(dev);
994 if (error)
995 goto dev_reg_err;
996 b->bridge = get_device(dev);
997
998 b->class_dev.class = &pcibus_class;
999 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
1000 error = class_device_register(&b->class_dev);
1001 if (error)
1002 goto class_dev_reg_err;
1003 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
1004 if (error)
1005 goto class_dev_create_file_err;
1006
1007 /* Create legacy_io and legacy_mem files for this bus */
1008 pci_create_legacy_files(b);
1009
1010 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1011 if (error)
1012 goto sys_create_link_err;
1013
1014 b->number = b->secondary = bus;
1015 b->resource[0] = &ioport_resource;
1016 b->resource[1] = &iomem_resource;
1017
1018 return b;
1019
1020 sys_create_link_err:
1021 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1022 class_dev_create_file_err:
1023 class_device_unregister(&b->class_dev);
1024 class_dev_reg_err:
1025 device_unregister(dev);
1026 dev_reg_err:
1027 down_write(&pci_bus_sem);
1028 list_del(&b->node);
1029 up_write(&pci_bus_sem);
1030 err_out:
1031 kfree(dev);
1032 kfree(b);
1033 return NULL;
1034 }
1035 EXPORT_SYMBOL_GPL(pci_create_bus);
1036
1037 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1038 int bus, struct pci_ops *ops, void *sysdata)
1039 {
1040 struct pci_bus *b;
1041
1042 b = pci_create_bus(parent, bus, ops, sysdata);
1043 if (b)
1044 b->subordinate = pci_scan_child_bus(b);
1045 return b;
1046 }
1047 EXPORT_SYMBOL(pci_scan_bus_parented);
1048
1049 #ifdef CONFIG_HOTPLUG
1050 EXPORT_SYMBOL(pci_add_new_bus);
1051 EXPORT_SYMBOL(pci_do_scan_bus);
1052 EXPORT_SYMBOL(pci_scan_slot);
1053 EXPORT_SYMBOL(pci_scan_bridge);
1054 EXPORT_SYMBOL(pci_scan_single_device);
1055 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1056 #endif
Linux with added FPC-III support