include/asm-mips/emma2rh/markeins.h

   1 /*
   2  *  include/asm-mips/emma2rh/markeins.h
   3  *      This file is EMMA2RH board depended header.
   4  *
   5  *  Copyright (C) NEC Electronics Corporation 2005-2006
   6  *
   7  *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
   8  *          Copyright 2001 MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License as published by
  12  *  the Free Software Foundation; either version 2 of the License, or
  13  *  (at your option) any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful,
  16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *  GNU General Public License for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License
  21  *  along with this program; if not, write to the Free Software
  22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  */
  24
  25 #ifndef MARKEINS_H
  26 #define MARKEINS_H
  27
  28 #define NUM_EMMA2RH_IRQ_SW      32
  29 #define NUM_EMMA2RH_IRQ_GPIO    32
  30
  31 #define EMMA2RH_SW_CASCADE      (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
  32 #define EMMA2RH_GPIO_CASCADE    (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
  33
  34 #define EMMA2RH_SW_IRQ_BASE     (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
  35 #define EMMA2RH_GPIO_IRQ_BASE   (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
  36 #define CPU_IRQ_BASE            (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO)
  37
  38 #define EMMA2RH_SW_IRQ_INT0     (0+EMMA2RH_SW_IRQ_BASE)
  39 #define EMMA2RH_SW_IRQ_INT1     (1+EMMA2RH_SW_IRQ_BASE)
  40 #define EMMA2RH_SW_IRQ_INT2     (2+EMMA2RH_SW_IRQ_BASE)
  41 #define EMMA2RH_SW_IRQ_INT3     (3+EMMA2RH_SW_IRQ_BASE)
  42 #define EMMA2RH_SW_IRQ_INT4     (4+EMMA2RH_SW_IRQ_BASE)
  43 #define EMMA2RH_SW_IRQ_INT5     (5+EMMA2RH_SW_IRQ_BASE)
  44 #define EMMA2RH_SW_IRQ_INT6     (6+EMMA2RH_SW_IRQ_BASE)
  45 #define EMMA2RH_SW_IRQ_INT7     (7+EMMA2RH_SW_IRQ_BASE)
  46 #define EMMA2RH_SW_IRQ_INT8     (8+EMMA2RH_SW_IRQ_BASE)
  47 #define EMMA2RH_SW_IRQ_INT9     (9+EMMA2RH_SW_IRQ_BASE)
  48 #define EMMA2RH_SW_IRQ_INT10    (10+EMMA2RH_SW_IRQ_BASE)
  49 #define EMMA2RH_SW_IRQ_INT11    (11+EMMA2RH_SW_IRQ_BASE)
  50 #define EMMA2RH_SW_IRQ_INT12    (12+EMMA2RH_SW_IRQ_BASE)
  51 #define EMMA2RH_SW_IRQ_INT13    (13+EMMA2RH_SW_IRQ_BASE)
  52 #define EMMA2RH_SW_IRQ_INT14    (14+EMMA2RH_SW_IRQ_BASE)
  53 #define EMMA2RH_SW_IRQ_INT15    (15+EMMA2RH_SW_IRQ_BASE)
  54 #define EMMA2RH_SW_IRQ_INT16    (16+EMMA2RH_SW_IRQ_BASE)
  55 #define EMMA2RH_SW_IRQ_INT17    (17+EMMA2RH_SW_IRQ_BASE)
  56 #define EMMA2RH_SW_IRQ_INT18    (18+EMMA2RH_SW_IRQ_BASE)
  57 #define EMMA2RH_SW_IRQ_INT19    (19+EMMA2RH_SW_IRQ_BASE)
  58 #define EMMA2RH_SW_IRQ_INT20    (20+EMMA2RH_SW_IRQ_BASE)
  59 #define EMMA2RH_SW_IRQ_INT21    (21+EMMA2RH_SW_IRQ_BASE)
  60 #define EMMA2RH_SW_IRQ_INT22    (22+EMMA2RH_SW_IRQ_BASE)
  61 #define EMMA2RH_SW_IRQ_INT23    (23+EMMA2RH_SW_IRQ_BASE)
  62 #define EMMA2RH_SW_IRQ_INT24    (24+EMMA2RH_SW_IRQ_BASE)
  63 #define EMMA2RH_SW_IRQ_INT25    (25+EMMA2RH_SW_IRQ_BASE)
  64 #define EMMA2RH_SW_IRQ_INT26    (26+EMMA2RH_SW_IRQ_BASE)
  65 #define EMMA2RH_SW_IRQ_INT27    (27+EMMA2RH_SW_IRQ_BASE)
  66 #define EMMA2RH_SW_IRQ_INT28    (28+EMMA2RH_SW_IRQ_BASE)
  67 #define EMMA2RH_SW_IRQ_INT29    (29+EMMA2RH_SW_IRQ_BASE)
  68 #define EMMA2RH_SW_IRQ_INT30    (30+EMMA2RH_SW_IRQ_BASE)
  69 #define EMMA2RH_SW_IRQ_INT31    (31+EMMA2RH_SW_IRQ_BASE)
  70
  71 #define MARKEINS_PCI_IRQ_INTA   EMMA2RH_GPIO_IRQ_BASE+15
  72 #define MARKEINS_PCI_IRQ_INTB   EMMA2RH_GPIO_IRQ_BASE+16
  73 #define MARKEINS_PCI_IRQ_INTC   EMMA2RH_GPIO_IRQ_BASE+17
  74 #define MARKEINS_PCI_IRQ_INTD   EMMA2RH_GPIO_IRQ_BASE+18
  75
  76 #endif /* CONFIG_MARKEINS */