arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <linux/mmc/host.h>
  18 #include <linux/platform_data/gpio-omap.h>
  19 #include <linux/platform_data/hsmmc-omap.h>
  20
  21 #include "soc.h"
  22 #include "omap_device.h"
  23 #include "omap-pm.h"
  24
  25 #include "mux.h"
  26 #include "hsmmc.h"
  27 #include "control.h"
  28
  29 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  30
  31 static u16 control_pbias_offset;
  32 static u16 control_devconf1_offset;
  33
  34 #define HSMMC_NAME_LEN  9
  35
  36 static void omap_hsmmc1_before_set_reg(struct device *dev,
  37                                        int power_on, int vdd)
  38 {
  39         u32 reg, prog_io;
  40         struct omap_hsmmc_platform_data *mmc = dev->platform_data;
  41
  42         if (mmc->remux)
  43                 mmc->remux(dev, power_on);
  44
  45         /*
  46          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  47          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
  48          * 1.8V and 3.0V modes, controlled by the PBIAS register.
  49          *
  50          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  51          * is most naturally TWL VSIM; those pins also use PBIAS.
  52          *
  53          * FIXME handle VMMC1A as needed ...
  54          */
  55         if (power_on) {
  56                 if (cpu_is_omap2430()) {
  57                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  58                         if ((1 << vdd) >= MMC_VDD_30_31)
  59                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  60                         else
  61                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  62                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  63                 }
  64
  65                 if (mmc->internal_clock) {
  66                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  67                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  68                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  69                 }
  70
  71                 reg = omap_ctrl_readl(control_pbias_offset);
  72                 if (cpu_is_omap3630()) {
  73                         /* Set MMC I/O to 52Mhz */
  74                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  75                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  76                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  77                 } else {
  78                         reg |= OMAP2_PBIASSPEEDCTRL0;
  79                 }
  80                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  81                 omap_ctrl_writel(reg, control_pbias_offset);
  82         } else {
  83                 reg = omap_ctrl_readl(control_pbias_offset);
  84                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  85                 omap_ctrl_writel(reg, control_pbias_offset);
  86         }
  87 }
  88
  89 static void omap_hsmmc1_after_set_reg(struct device *dev, int power_on, int vdd)
  90 {
  91         u32 reg;
  92
  93         /* 100ms delay required for PBIAS configuration */
  94         msleep(100);
  95
  96         if (power_on) {
  97                 reg = omap_ctrl_readl(control_pbias_offset);
  98                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
  99                 if ((1 << vdd) <= MMC_VDD_165_195)
 100                         reg &= ~OMAP2_PBIASLITEVMODE0;
 101                 else
 102                         reg |= OMAP2_PBIASLITEVMODE0;
 103                 omap_ctrl_writel(reg, control_pbias_offset);
 104         } else {
 105                 reg = omap_ctrl_readl(control_pbias_offset);
 106                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 107                         OMAP2_PBIASLITEVMODE0);
 108                 omap_ctrl_writel(reg, control_pbias_offset);
 109         }
 110 }
 111
 112 static void hsmmc2_select_input_clk_src(struct omap_hsmmc_platform_data *mmc)
 113 {
 114         u32 reg;
 115
 116         reg = omap_ctrl_readl(control_devconf1_offset);
 117         if (mmc->internal_clock)
 118                 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 119         else
 120                 reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
 121         omap_ctrl_writel(reg, control_devconf1_offset);
 122 }
 123
 124 static void hsmmc2_before_set_reg(struct device *dev, int power_on, int vdd)
 125 {
 126         struct omap_hsmmc_platform_data *mmc = dev->platform_data;
 127
 128         if (mmc->remux)
 129                 mmc->remux(dev, power_on);
 130
 131         if (power_on)
 132                 hsmmc2_select_input_clk_src(mmc);
 133 }
 134
 135 static int am35x_hsmmc2_set_power(struct device *dev, int power_on, int vdd)
 136 {
 137         struct omap_hsmmc_platform_data *mmc = dev->platform_data;
 138
 139         if (power_on)
 140                 hsmmc2_select_input_clk_src(mmc);
 141
 142         return 0;
 143 }
 144
 145 static int nop_mmc_set_power(struct device *dev, int power_on, int vdd)
 146 {
 147         return 0;
 148 }
 149
 150 static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
 151                                   *mmc_controller, int controller_nr)
 152 {
 153         if (gpio_is_valid(mmc_controller->switch_pin) &&
 154             (mmc_controller->switch_pin < OMAP_MAX_GPIO_LINES))
 155                 omap_mux_init_gpio(mmc_controller->switch_pin,
 156                                    OMAP_PIN_INPUT_PULLUP);
 157         if (gpio_is_valid(mmc_controller->gpio_wp) &&
 158             (mmc_controller->gpio_wp < OMAP_MAX_GPIO_LINES))
 159                 omap_mux_init_gpio(mmc_controller->gpio_wp,
 160                                    OMAP_PIN_INPUT_PULLUP);
 161         if (cpu_is_omap34xx()) {
 162                 if (controller_nr == 0) {
 163                         omap_mux_init_signal("sdmmc1_clk",
 164                                 OMAP_PIN_INPUT_PULLUP);
 165                         omap_mux_init_signal("sdmmc1_cmd",
 166                                 OMAP_PIN_INPUT_PULLUP);
 167                         omap_mux_init_signal("sdmmc1_dat0",
 168                                 OMAP_PIN_INPUT_PULLUP);
 169                         if (mmc_controller->caps &
 170                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 171                                 omap_mux_init_signal("sdmmc1_dat1",
 172                                         OMAP_PIN_INPUT_PULLUP);
 173                                 omap_mux_init_signal("sdmmc1_dat2",
 174                                         OMAP_PIN_INPUT_PULLUP);
 175                                 omap_mux_init_signal("sdmmc1_dat3",
 176                                         OMAP_PIN_INPUT_PULLUP);
 177                         }
 178                         if (mmc_controller->caps &
 179                                                 MMC_CAP_8_BIT_DATA) {
 180                                 omap_mux_init_signal("sdmmc1_dat4",
 181                                         OMAP_PIN_INPUT_PULLUP);
 182                                 omap_mux_init_signal("sdmmc1_dat5",
 183                                         OMAP_PIN_INPUT_PULLUP);
 184                                 omap_mux_init_signal("sdmmc1_dat6",
 185                                         OMAP_PIN_INPUT_PULLUP);
 186                                 omap_mux_init_signal("sdmmc1_dat7",
 187                                         OMAP_PIN_INPUT_PULLUP);
 188                         }
 189                 }
 190                 if (controller_nr == 1) {
 191                         /* MMC2 */
 192                         omap_mux_init_signal("sdmmc2_clk",
 193                                 OMAP_PIN_INPUT_PULLUP);
 194                         omap_mux_init_signal("sdmmc2_cmd",
 195                                 OMAP_PIN_INPUT_PULLUP);
 196                         omap_mux_init_signal("sdmmc2_dat0",
 197                                 OMAP_PIN_INPUT_PULLUP);
 198
 199                         /*
 200                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
 201                          * need to be muxed in the board-*.c files
 202                          */
 203                         if (mmc_controller->caps &
 204                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 205                                 omap_mux_init_signal("sdmmc2_dat1",
 206                                         OMAP_PIN_INPUT_PULLUP);
 207                                 omap_mux_init_signal("sdmmc2_dat2",
 208                                         OMAP_PIN_INPUT_PULLUP);
 209                                 omap_mux_init_signal("sdmmc2_dat3",
 210                                         OMAP_PIN_INPUT_PULLUP);
 211                         }
 212                         if (mmc_controller->caps &
 213                                                         MMC_CAP_8_BIT_DATA) {
 214                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 215                                         OMAP_PIN_INPUT_PULLUP);
 216                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 217                                         OMAP_PIN_INPUT_PULLUP);
 218                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 219                                         OMAP_PIN_INPUT_PULLUP);
 220                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 221                                         OMAP_PIN_INPUT_PULLUP);
 222                         }
 223                 }
 224
 225                 /*
 226                  * For MMC3 the pins need to be muxed in the board-*.c files
 227                  */
 228         }
 229 }
 230
 231 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 232                                         struct omap_hsmmc_platform_data *mmc)
 233 {
 234         char *hc_name;
 235
 236         hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
 237         if (!hc_name) {
 238                 pr_err("Cannot allocate memory for controller slot name\n");
 239                 kfree(hc_name);
 240                 return -ENOMEM;
 241         }
 242
 243         if (c->name)
 244                 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
 245         else
 246                 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
 247                                                                 c->mmc, 1);
 248         mmc->name = hc_name;
 249         mmc->caps = c->caps;
 250         mmc->internal_clock = !c->ext_clock;
 251         mmc->reg_offset = 0;
 252
 253         mmc->switch_pin = c->gpio_cd;
 254         mmc->gpio_wp = c->gpio_wp;
 255
 256         mmc->remux = c->remux;
 257         mmc->init_card = c->init_card;
 258
 259         if (c->cover_only)
 260                 mmc->cover = 1;
 261
 262         if (c->nonremovable)
 263                 mmc->nonremovable = 1;
 264
 265         /*
 266          * NOTE:  MMC slots should have a Vcc regulator set up.
 267          * This may be from a TWL4030-family chip, another
 268          * controllable regulator, or a fixed supply.
 269          *
 270          * temporary HACK: ocr_mask instead of fixed supply
 271          */
 272         if (soc_is_am35xx())
 273                 mmc->ocr_mask = MMC_VDD_165_195 |
 274                                          MMC_VDD_26_27 |
 275                                          MMC_VDD_27_28 |
 276                                          MMC_VDD_29_30 |
 277                                          MMC_VDD_30_31 |
 278                                          MMC_VDD_31_32;
 279         else
 280                 mmc->ocr_mask = c->ocr_mask;
 281
 282         if (!soc_is_am35xx())
 283                 mmc->features |= HSMMC_HAS_PBIAS;
 284
 285         switch (c->mmc) {
 286         case 1:
 287                 if (mmc->features & HSMMC_HAS_PBIAS) {
 288                         /* on-chip level shifting via PBIAS0/PBIAS1 */
 289                         mmc->before_set_reg =
 290                                         omap_hsmmc1_before_set_reg;
 291                         mmc->after_set_reg =
 292                                         omap_hsmmc1_after_set_reg;
 293                 }
 294
 295                 if (soc_is_am35xx())
 296                         mmc->set_power = nop_mmc_set_power;
 297
 298                 /* OMAP3630 HSMMC1 supports only 4-bit */
 299                 if (cpu_is_omap3630() &&
 300                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
 301                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 302                         c->caps |= MMC_CAP_4_BIT_DATA;
 303                         mmc->caps = c->caps;
 304                 }
 305                 break;
 306         case 2:
 307                 if (soc_is_am35xx())
 308                         mmc->set_power = am35x_hsmmc2_set_power;
 309
 310                 if (c->ext_clock)
 311                         c->transceiver = 1;
 312                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 313                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 314                         c->caps |= MMC_CAP_4_BIT_DATA;
 315                 }
 316                 if (mmc->features & HSMMC_HAS_PBIAS) {
 317                         /* off-chip level shifting, or none */
 318                         mmc->before_set_reg = hsmmc2_before_set_reg;
 319                         mmc->after_set_reg = NULL;
 320                 }
 321                 break;
 322         case 3:
 323         case 4:
 324         case 5:
 325                 mmc->before_set_reg = NULL;
 326                 mmc->after_set_reg = NULL;
 327                 break;
 328         default:
 329                 pr_err("MMC%d configuration not supported!\n", c->mmc);
 330                 kfree(hc_name);
 331                 return -ENODEV;
 332         }
 333         return 0;
 334 }
 335
 336 static int omap_hsmmc_done;
 337
 338 void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
 339 {
 340         struct platform_device *pdev;
 341         struct omap_hsmmc_platform_data *mmc_pdata;
 342         int res;
 343
 344         if (omap_hsmmc_done != 1)
 345                 return;
 346
 347         omap_hsmmc_done++;
 348
 349         for (; c->mmc; c++) {
 350                 if (!c->deferred)
 351                         continue;
 352
 353                 pdev = c->pdev;
 354                 if (!pdev)
 355                         continue;
 356
 357                 mmc_pdata = pdev->dev.platform_data;
 358                 if (!mmc_pdata)
 359                         continue;
 360
 361                 mmc_pdata->switch_pin = c->gpio_cd;
 362                 mmc_pdata->gpio_wp = c->gpio_wp;
 363
 364                 res = omap_device_register(pdev);
 365                 if (res)
 366                         pr_err("Could not late init MMC %s\n",
 367                                c->name);
 368         }
 369 }
 370
 371 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 372
 373 static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
 374                                         int ctrl_nr)
 375 {
 376         struct omap_hwmod *oh;
 377         struct omap_hwmod *ohs[1];
 378         struct omap_device *od;
 379         struct platform_device *pdev;
 380         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
 381         struct omap_hsmmc_platform_data *mmc_data;
 382         struct omap_hsmmc_dev_attr *mmc_dev_attr;
 383         char *name;
 384         int res;
 385
 386         mmc_data = kzalloc(sizeof(*mmc_data), GFP_KERNEL);
 387         if (!mmc_data) {
 388                 pr_err("Cannot allocate memory for mmc device!\n");
 389                 return;
 390         }
 391
 392         res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
 393         if (res < 0)
 394                 goto free_mmc;
 395
 396         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 397
 398         name = "omap_hsmmc";
 399         res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
 400                      "mmc%d", ctrl_nr);
 401         WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
 402              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
 403
 404         oh = omap_hwmod_lookup(oh_name);
 405         if (!oh) {
 406                 pr_err("Could not look up %s\n", oh_name);
 407                 goto free_name;
 408         }
 409         ohs[0] = oh;
 410         if (oh->dev_attr != NULL) {
 411                 mmc_dev_attr = oh->dev_attr;
 412                 mmc_data->controller_flags = mmc_dev_attr->flags;
 413                 /*
 414                  * erratum 2.1.1.128 doesn't apply if board has
 415                  * a transceiver is attached
 416                  */
 417                 if (hsmmcinfo->transceiver)
 418                         mmc_data->controller_flags &=
 419                                 ~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
 420         }
 421
 422         pdev = platform_device_alloc(name, ctrl_nr - 1);
 423         if (!pdev) {
 424                 pr_err("Could not allocate pdev for %s\n", name);
 425                 goto free_name;
 426         }
 427         dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
 428
 429         od = omap_device_alloc(pdev, ohs, 1);
 430         if (IS_ERR(od)) {
 431                 pr_err("Could not allocate od for %s\n", name);
 432                 goto put_pdev;
 433         }
 434
 435         res = platform_device_add_data(pdev, mmc_data,
 436                               sizeof(struct omap_hsmmc_platform_data));
 437         if (res) {
 438                 pr_err("Could not add pdata for %s\n", name);
 439                 goto put_pdev;
 440         }
 441
 442         hsmmcinfo->pdev = pdev;
 443
 444         if (hsmmcinfo->deferred)
 445                 goto free_mmc;
 446
 447         res = omap_device_register(pdev);
 448         if (res) {
 449                 pr_err("Could not register od for %s\n", name);
 450                 goto free_od;
 451         }
 452
 453         goto free_mmc;
 454
 455 free_od:
 456         omap_device_delete(od);
 457
 458 put_pdev:
 459         platform_device_put(pdev);
 460
 461 free_name:
 462         kfree(mmc_data->name);
 463
 464 free_mmc:
 465         kfree(mmc_data);
 466 }
 467
 468 void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
 469 {
 470         if (omap_hsmmc_done)
 471                 return;
 472
 473         omap_hsmmc_done = 1;
 474
 475         if (cpu_is_omap2430()) {
 476                 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 477                 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 478         } else {
 479                 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 480                 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 481         }
 482
 483         for (; controllers->mmc; controllers++)
 484                 omap_hsmmc_init_one(controllers, controllers->mmc);
 485
 486 }
 487
 488 #endif