drivers/ata/ahci_xgene.c

   1 /*
   2  * AppliedMicro X-Gene SoC SATA Host Controller Driver
   3  *
   4  * Copyright (c) 2014, Applied Micro Circuits Corporation
   5  * Author: Loc Ho <lho@apm.com>
   6  *         Tuan Phan <tphan@apm.com>
   7  *         Suman Tripathi <stripathi@apm.com>
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * NOTE: PM support is not currently available.
  23  *
  24  */
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/ahci_platform.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/phy/phy.h>
  31 #include "ahci.h"
  32
  33 #define DRV_NAME "xgene-ahci"
  34
  35 /* Max # of disk per a controller */
  36 #define MAX_AHCI_CHN_PERCTR             2
  37
  38 /* MUX CSR */
  39 #define SATA_ENET_CONFIG_REG            0x00000000
  40 #define  CFG_SATA_ENET_SELECT_MASK      0x00000001
  41
  42 /* SATA core host controller CSR */
  43 #define SLVRDERRATTRIBUTES              0x00000000
  44 #define SLVWRERRATTRIBUTES              0x00000004
  45 #define MSTRDERRATTRIBUTES              0x00000008
  46 #define MSTWRERRATTRIBUTES              0x0000000c
  47 #define BUSCTLREG                       0x00000014
  48 #define IOFMSTRWAUX                     0x00000018
  49 #define INTSTATUSMASK                   0x0000002c
  50 #define ERRINTSTATUS                    0x00000030
  51 #define ERRINTSTATUSMASK                0x00000034
  52
  53 /* SATA host AHCI CSR */
  54 #define PORTCFG                         0x000000a4
  55 #define  PORTADDR_SET(dst, src) \
  56                 (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
  57 #define PORTPHY1CFG             0x000000a8
  58 #define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
  59                 (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
  60 #define PORTPHY2CFG                     0x000000ac
  61 #define PORTPHY3CFG                     0x000000b0
  62 #define PORTPHY4CFG                     0x000000b4
  63 #define PORTPHY5CFG                     0x000000b8
  64 #define SCTL0                           0x0000012C
  65 #define PORTPHY5CFG_RTCHG_SET(dst, src) \
  66                 (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
  67 #define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
  68                 (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
  69 #define PORTAXICFG                      0x000000bc
  70 #define PORTAXICFG_OUTTRANS_SET(dst, src) \
  71                 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
  72 #define PORTRANSCFG                     0x000000c8
  73 #define PORTRANSCFG_RXWM_SET(dst, src)          \
  74                 (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
  75
  76 /* SATA host controller AXI CSR */
  77 #define INT_SLV_TMOMASK                 0x00000010
  78
  79 /* SATA diagnostic CSR */
  80 #define CFG_MEM_RAM_SHUTDOWN            0x00000070
  81 #define BLOCK_MEM_RDY                   0x00000074
  82
  83 /* Max retry for link down */
  84 #define MAX_LINK_DOWN_RETRY 3
  85
  86 struct xgene_ahci_context {
  87         struct ahci_host_priv *hpriv;
  88         struct device *dev;
  89         u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/
  90         u32 class[MAX_AHCI_CHN_PERCTR]; /* tracking the class of device */
  91         void __iomem *csr_core;         /* Core CSR address of IP */
  92         void __iomem *csr_diag;         /* Diag CSR address of IP */
  93         void __iomem *csr_axi;          /* AXI CSR address of IP */
  94         void __iomem *csr_mux;          /* MUX CSR address of IP */
  95 };
  96
  97 static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
  98 {
  99         dev_dbg(ctx->dev, "Release memory from shutdown\n");
 100         writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
 101         readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
 102         msleep(1);      /* reset may take up to 1ms */
 103         if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
 104                 dev_err(ctx->dev, "failed to release memory from shutdown\n");
 105                 return -ENODEV;
 106         }
 107         return 0;
 108 }
 109
 110 /**
 111  * xgene_ahci_poll_reg_val- Poll a register on a specific value.
 112  * @ap : ATA port of interest.
 113  * @reg : Register of interest.
 114  * @val : Value to be attained.
 115  * @interval : waiting interval for polling.
 116  * @timeout : timeout for achieving the value.
 117  */
 118 static int xgene_ahci_poll_reg_val(struct ata_port *ap,
 119                                    void __iomem *reg, unsigned
 120                                    int val, unsigned long interval,
 121                                    unsigned long timeout)
 122 {
 123         unsigned long deadline;
 124         unsigned int tmp;
 125
 126         tmp = ioread32(reg);
 127         deadline = ata_deadline(jiffies, timeout);
 128
 129         while (tmp != val && time_before(jiffies, deadline)) {
 130                 ata_msleep(ap, interval);
 131                 tmp = ioread32(reg);
 132         }
 133
 134         return tmp;
 135 }
 136
 137 /**
 138  * xgene_ahci_restart_engine - Restart the dma engine.
 139  * @ap : ATA port of interest
 140  *
 141  * Waits for completion of multiple commands and restarts
 142  * the DMA engine inside the controller.
 143  */
 144 static int xgene_ahci_restart_engine(struct ata_port *ap)
 145 {
 146         struct ahci_host_priv *hpriv = ap->host->private_data;
 147         struct ahci_port_priv *pp = ap->private_data;
 148         void __iomem *port_mmio = ahci_port_base(ap);
 149         u32 fbs;
 150
 151         /*
 152          * In case of PMP multiple IDENTIFY DEVICE commands can be
 153          * issued inside PxCI. So need to poll PxCI for the
 154          * completion of outstanding IDENTIFY DEVICE commands before
 155          * we restart the DMA engine.
 156          */
 157         if (xgene_ahci_poll_reg_val(ap, port_mmio +
 158                                     PORT_CMD_ISSUE, 0x0, 1, 100))
 159                   return -EBUSY;
 160
 161         ahci_stop_engine(ap);
 162         ahci_start_fis_rx(ap);
 163
 164         /*
 165          * Enable the PxFBS.FBS_EN bit as it
 166          * gets cleared due to stopping the engine.
 167          */
 168         if (pp->fbs_supported) {
 169                 fbs = readl(port_mmio + PORT_FBS);
 170                 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
 171                 fbs = readl(port_mmio + PORT_FBS);
 172         }
 173
 174         hpriv->start_engine(ap);
 175
 176         return 0;
 177 }
 178
 179 /**
 180  * xgene_ahci_qc_issue - Issue commands to the device
 181  * @qc: Command to issue
 182  *
 183  * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot
 184  * clear the BSY bit after receiving the PIO setup FIS. This results in the dma
 185  * state machine goes into the CMFatalErrorUpdate state and locks up. By
 186  * restarting the dma engine, it removes the controller out of lock up state.
 187  *
 188  * Due to H/W errata, the controller is unable to save the PMP
 189  * field fetched from command header before sending the H2D FIS.
 190  * When the device returns the PMP port field in the D2H FIS, there is
 191  * a mismatch and results in command completion failure. The
 192  * workaround is to write the pmp value to PxFBS.DEV field before issuing
 193  * any command to PMP.
 194  */
 195 static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
 196 {
 197         struct ata_port *ap = qc->ap;
 198         struct ahci_host_priv *hpriv = ap->host->private_data;
 199         struct xgene_ahci_context *ctx = hpriv->plat_data;
 200         int rc = 0;
 201         u32 port_fbs;
 202         void *port_mmio = ahci_port_base(ap);
 203
 204         /*
 205          * Write the pmp value to PxFBS.DEV
 206          * for case of Port Mulitplier.
 207          */
 208         if (ctx->class[ap->port_no] == ATA_DEV_PMP) {
 209                 port_fbs = readl(port_mmio + PORT_FBS);
 210                 port_fbs &= ~PORT_FBS_DEV_MASK;
 211                 port_fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
 212                 writel(port_fbs, port_mmio + PORT_FBS);
 213         }
 214
 215         if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) ||
 216             (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET) ||
 217             (ctx->last_cmd[ap->port_no] == ATA_CMD_SMART)))
 218                 xgene_ahci_restart_engine(ap);
 219
 220         rc = ahci_qc_issue(qc);
 221
 222         /* Save the last command issued */
 223         ctx->last_cmd[ap->port_no] = qc->tf.command;
 224
 225         return rc;
 226 }
 227
 228 static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
 229 {
 230         void __iomem *diagcsr = ctx->csr_diag;
 231
 232         return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&
 233                 readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);
 234 }
 235
 236 /**
 237  * xgene_ahci_read_id - Read ID data from the specified device
 238  * @dev: device
 239  * @tf: proposed taskfile
 240  * @id: data buffer
 241  *
 242  * This custom read ID function is required due to the fact that the HW
 243  * does not support DEVSLP.
 244  */
 245 static unsigned int xgene_ahci_read_id(struct ata_device *dev,
 246                                        struct ata_taskfile *tf, u16 *id)
 247 {
 248         u32 err_mask;
 249
 250         err_mask = ata_do_dev_read_id(dev, tf, id);
 251         if (err_mask)
 252                 return err_mask;
 253
 254         /*
 255          * Mask reserved area. Word78 spec of Link Power Management
 256          * bit15-8: reserved
 257          * bit7: NCQ autosence
 258          * bit6: Software settings preservation supported
 259          * bit5: reserved
 260          * bit4: In-order sata delivery supported
 261          * bit3: DIPM requests supported
 262          * bit2: DMA Setup FIS Auto-Activate optimization supported
 263          * bit1: DMA Setup FIX non-Zero buffer offsets supported
 264          * bit0: Reserved
 265          *
 266          * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
 267          */
 268         id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
 269
 270         return 0;
 271 }
 272
 273 static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
 274 {
 275         void __iomem *mmio = ctx->hpriv->mmio;
 276         u32 val;
 277
 278         dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
 279                 mmio, channel);
 280         val = readl(mmio + PORTCFG);
 281         val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
 282         writel(val, mmio + PORTCFG);
 283         readl(mmio + PORTCFG);  /* Force a barrier */
 284         /* Disable fix rate */
 285         writel(0x0001fffe, mmio + PORTPHY1CFG);
 286         readl(mmio + PORTPHY1CFG); /* Force a barrier */
 287         writel(0x28183219, mmio + PORTPHY2CFG);
 288         readl(mmio + PORTPHY2CFG); /* Force a barrier */
 289         writel(0x13081008, mmio + PORTPHY3CFG);
 290         readl(mmio + PORTPHY3CFG); /* Force a barrier */
 291         writel(0x00480815, mmio + PORTPHY4CFG);
 292         readl(mmio + PORTPHY4CFG); /* Force a barrier */
 293         /* Set window negotiation */
 294         val = readl(mmio + PORTPHY5CFG);
 295         val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
 296         writel(val, mmio + PORTPHY5CFG);
 297         readl(mmio + PORTPHY5CFG); /* Force a barrier */
 298         val = readl(mmio + PORTAXICFG);
 299         val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
 300         val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
 301         writel(val, mmio + PORTAXICFG);
 302         readl(mmio + PORTAXICFG); /* Force a barrier */
 303         /* Set the watermark threshold of the receive FIFO */
 304         val = readl(mmio + PORTRANSCFG);
 305         val = PORTRANSCFG_RXWM_SET(val, 0x30);
 306         writel(val, mmio + PORTRANSCFG);
 307 }
 308
 309 /**
 310  * xgene_ahci_do_hardreset - Issue the actual COMRESET
 311  * @link: link to reset
 312  * @deadline: deadline jiffies for the operation
 313  * @online: Return value to indicate if device online
 314  *
 315  * Due to the limitation of the hardware PHY, a difference set of setting is
 316  * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
 317  * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
 318  * report disparity error and etc. In addition, during COMRESET, there can
 319  * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
 320  * SERR_10B_8B_ERR, the PHY receiver line must be reseted. Also during long
 321  * reboot cycle regression, sometimes the PHY reports link down even if the
 322  * device is present because of speed negotiation failure. so need to retry
 323  * the COMRESET to get the link up. The following algorithm is followed to
 324  * proper configure the hardware PHY during COMRESET:
 325  *
 326  * Alg Part 1:
 327  * 1. Start the PHY at Gen3 speed (default setting)
 328  * 2. Issue the COMRESET
 329  * 3. If no link, go to Alg Part 3
 330  * 4. If link up, determine if the negotiated speed matches the PHY
 331  *    configured speed
 332  * 5. If they matched, go to Alg Part 2
 333  * 6. If they do not matched and first time, configure the PHY for the linked
 334  *    up disk speed and repeat step 2
 335  * 7. Go to Alg Part 2
 336  *
 337  * Alg Part 2:
 338  * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
 339  *    reported in the register PORT_SCR_ERR, then reset the PHY receiver line
 340  * 2. Go to Alg Part 4
 341  *
 342  * Alg Part 3:
 343  * 1. Check the PORT_SCR_STAT to see whether device presence detected but PHY
 344  *    communication establishment failed and maximum link down attempts are
 345  *    less than Max attempts 3 then goto Alg Part 1.
 346  * 2. Go to Alg Part 4.
 347  *
 348  * Alg Part 4:
 349  * 1. Clear any pending from register PORT_SCR_ERR.
 350  *
 351  * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
 352  *       and until the underlying PHY supports an method to reset the receiver
 353  *       line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
 354  *       an warning message will be printed.
 355  */
 356 static int xgene_ahci_do_hardreset(struct ata_link *link,
 357                                    unsigned long deadline, bool *online)
 358 {
 359         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
 360         struct ata_port *ap = link->ap;
 361         struct ahci_host_priv *hpriv = ap->host->private_data;
 362         struct xgene_ahci_context *ctx = hpriv->plat_data;
 363         struct ahci_port_priv *pp = ap->private_data;
 364         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 365         void __iomem *port_mmio = ahci_port_base(ap);
 366         struct ata_taskfile tf;
 367         int link_down_retry = 0;
 368         int rc;
 369         u32 val, sstatus;
 370
 371         do {
 372                 /* clear D2H reception area to properly wait for D2H FIS */
 373                 ata_tf_init(link->device, &tf);
 374                 tf.command = ATA_BUSY;
 375                 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 376                 rc = sata_link_hardreset(link, timing, deadline, online,
 377                                  ahci_check_ready);
 378                 if (*online) {
 379                         val = readl(port_mmio + PORT_SCR_ERR);
 380                         if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
 381                                 dev_warn(ctx->dev, "link has error\n");
 382                         break;
 383                 }
 384
 385                 sata_scr_read(link, SCR_STATUS, &sstatus);
 386         } while (link_down_retry++ < MAX_LINK_DOWN_RETRY &&
 387                  (sstatus & 0xff) == 0x1);
 388
 389         /* clear all errors if any pending */
 390         val = readl(port_mmio + PORT_SCR_ERR);
 391         writel(val, port_mmio + PORT_SCR_ERR);
 392
 393         return rc;
 394 }
 395
 396 static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
 397                                 unsigned long deadline)
 398 {
 399         struct ata_port *ap = link->ap;
 400         struct ahci_host_priv *hpriv = ap->host->private_data;
 401         void __iomem *port_mmio = ahci_port_base(ap);
 402         bool online;
 403         int rc;
 404         u32 portcmd_saved;
 405         u32 portclb_saved;
 406         u32 portclbhi_saved;
 407         u32 portrxfis_saved;
 408         u32 portrxfishi_saved;
 409
 410         /* As hardreset resets these CSR, save it to restore later */
 411         portcmd_saved = readl(port_mmio + PORT_CMD);
 412         portclb_saved = readl(port_mmio + PORT_LST_ADDR);
 413         portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
 414         portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
 415         portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
 416
 417         ahci_stop_engine(ap);
 418
 419         rc = xgene_ahci_do_hardreset(link, deadline, &online);
 420
 421         /* As controller hardreset clears them, restore them */
 422         writel(portcmd_saved, port_mmio + PORT_CMD);
 423         writel(portclb_saved, port_mmio + PORT_LST_ADDR);
 424         writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
 425         writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
 426         writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
 427
 428         hpriv->start_engine(ap);
 429
 430         if (online)
 431                 *class = ahci_dev_classify(ap);
 432
 433         return rc;
 434 }
 435
 436 static void xgene_ahci_host_stop(struct ata_host *host)
 437 {
 438         struct ahci_host_priv *hpriv = host->private_data;
 439
 440         ahci_platform_disable_resources(hpriv);
 441 }
 442
 443 /**
 444  * xgene_ahci_pmp_softreset - Issue the softreset to the drives connected
 445  *                            to Port Multiplier.
 446  * @link: link to reset
 447  * @class: Return value to indicate class of device
 448  * @deadline: deadline jiffies for the operation
 449  *
 450  * Due to H/W errata, the controller is unable to save the PMP
 451  * field fetched from command header before sending the H2D FIS.
 452  * When the device returns the PMP port field in the D2H FIS, there is
 453  * a mismatch and results in command completion failure. The workaround
 454  * is to write the pmp value to PxFBS.DEV field before issuing any command
 455  * to PMP.
 456  */
 457 static int xgene_ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
 458                           unsigned long deadline)
 459 {
 460         int pmp = sata_srst_pmp(link);
 461         struct ata_port *ap = link->ap;
 462         u32 rc;
 463         void *port_mmio = ahci_port_base(ap);
 464         u32 port_fbs;
 465
 466         /*
 467          * Set PxFBS.DEV field with pmp
 468          * value.
 469          */
 470         port_fbs = readl(port_mmio + PORT_FBS);
 471         port_fbs &= ~PORT_FBS_DEV_MASK;
 472         port_fbs |= pmp << PORT_FBS_DEV_OFFSET;
 473         writel(port_fbs, port_mmio + PORT_FBS);
 474
 475         rc = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
 476
 477         return rc;
 478 }
 479
 480 /**
 481  * xgene_ahci_softreset - Issue the softreset to the drive.
 482  * @link: link to reset
 483  * @class: Return value to indicate class of device
 484  * @deadline: deadline jiffies for the operation
 485  *
 486  * Due to H/W errata, the controller is unable to save the PMP
 487  * field fetched from command header before sending the H2D FIS.
 488  * When the device returns the PMP port field in the D2H FIS, there is
 489  * a mismatch and results in command completion failure. The workaround
 490  * is to write the pmp value to PxFBS.DEV field before issuing any command
 491  * to PMP. Here is the algorithm to detect PMP :
 492  *
 493  * 1. Save the PxFBS value
 494  * 2. Program PxFBS.DEV with pmp value send by framework. Framework sends
 495  *    0xF for both PMP/NON-PMP initially
 496  * 3. Issue softreset
 497  * 4. If signature class is PMP goto 6
 498  * 5. restore the original PxFBS and goto 3
 499  * 6. return
 500  */
 501 static int xgene_ahci_softreset(struct ata_link *link, unsigned int *class,
 502                           unsigned long deadline)
 503 {
 504         int pmp = sata_srst_pmp(link);
 505         struct ata_port *ap = link->ap;
 506         struct ahci_host_priv *hpriv = ap->host->private_data;
 507         struct xgene_ahci_context *ctx = hpriv->plat_data;
 508         void *port_mmio = ahci_port_base(ap);
 509         u32 port_fbs;
 510         u32 port_fbs_save;
 511         u32 retry = 1;
 512         u32 rc;
 513
 514         port_fbs_save = readl(port_mmio + PORT_FBS);
 515
 516         /*
 517          * Set PxFBS.DEV field with pmp
 518          * value.
 519          */
 520         port_fbs = readl(port_mmio + PORT_FBS);
 521         port_fbs &= ~PORT_FBS_DEV_MASK;
 522         port_fbs |= pmp << PORT_FBS_DEV_OFFSET;
 523         writel(port_fbs, port_mmio + PORT_FBS);
 524
 525 softreset_retry:
 526         rc = ahci_do_softreset(link, class, pmp,
 527                                deadline, ahci_check_ready);
 528
 529         ctx->class[ap->port_no] = *class;
 530         if (*class != ATA_DEV_PMP) {
 531                 /*
 532                  * Retry for normal drives without
 533                  * setting PxFBS.DEV field with pmp value.
 534                  */
 535                 if (retry--) {
 536                         writel(port_fbs_save, port_mmio + PORT_FBS);
 537                         goto softreset_retry;
 538                 }
 539         }
 540
 541         return rc;
 542 }
 543
 544 static struct ata_port_operations xgene_ahci_ops = {
 545         .inherits = &ahci_ops,
 546         .host_stop = xgene_ahci_host_stop,
 547         .hardreset = xgene_ahci_hardreset,
 548         .read_id = xgene_ahci_read_id,
 549         .qc_issue = xgene_ahci_qc_issue,
 550         .softreset = xgene_ahci_softreset,
 551         .pmp_softreset = xgene_ahci_pmp_softreset
 552 };
 553
 554 static const struct ata_port_info xgene_ahci_port_info = {
 555         .flags = AHCI_FLAG_COMMON | ATA_FLAG_PMP,
 556         .pio_mask = ATA_PIO4,
 557         .udma_mask = ATA_UDMA6,
 558         .port_ops = &xgene_ahci_ops,
 559 };
 560
 561 static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
 562 {
 563         struct xgene_ahci_context *ctx = hpriv->plat_data;
 564         int i;
 565         int rc;
 566         u32 val;
 567
 568         /* Remove IP RAM out of shutdown */
 569         rc = xgene_ahci_init_memram(ctx);
 570         if (rc)
 571                 return rc;
 572
 573         for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
 574                 xgene_ahci_set_phy_cfg(ctx, i);
 575
 576         /* AXI disable Mask */
 577         writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
 578         readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
 579         writel(0, ctx->csr_core + INTSTATUSMASK);
 580         val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
 581         dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
 582                 INTSTATUSMASK, val);
 583
 584         writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
 585         readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
 586         writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
 587         readl(ctx->csr_axi + INT_SLV_TMOMASK);
 588
 589         /* Enable AXI Interrupt */
 590         writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
 591         writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
 592         writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
 593         writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
 594
 595         /* Enable coherency */
 596         val = readl(ctx->csr_core + BUSCTLREG);
 597         val &= ~0x00000002;     /* Enable write coherency */
 598         val &= ~0x00000001;     /* Enable read coherency */
 599         writel(val, ctx->csr_core + BUSCTLREG);
 600
 601         val = readl(ctx->csr_core + IOFMSTRWAUX);
 602         val |= (1 << 3);        /* Enable read coherency */
 603         val |= (1 << 9);        /* Enable write coherency */
 604         writel(val, ctx->csr_core + IOFMSTRWAUX);
 605         val = readl(ctx->csr_core + IOFMSTRWAUX);
 606         dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
 607                 IOFMSTRWAUX, val);
 608
 609         return rc;
 610 }
 611
 612 static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
 613 {
 614         u32 val;
 615
 616         /* Check for optional MUX resource */
 617         if (!ctx->csr_mux)
 618                 return 0;
 619
 620         val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
 621         val &= ~CFG_SATA_ENET_SELECT_MASK;
 622         writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
 623         val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
 624         return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
 625 }
 626
 627 static struct scsi_host_template ahci_platform_sht = {
 628         AHCI_SHT(DRV_NAME),
 629 };
 630
 631 static int xgene_ahci_probe(struct platform_device *pdev)
 632 {
 633         struct device *dev = &pdev->dev;
 634         struct ahci_host_priv *hpriv;
 635         struct xgene_ahci_context *ctx;
 636         struct resource *res;
 637         int rc;
 638
 639         hpriv = ahci_platform_get_resources(pdev);
 640         if (IS_ERR(hpriv))
 641                 return PTR_ERR(hpriv);
 642
 643         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 644         if (!ctx)
 645                 return -ENOMEM;
 646
 647         hpriv->plat_data = ctx;
 648         ctx->hpriv = hpriv;
 649         ctx->dev = dev;
 650
 651         /* Retrieve the IP core resource */
 652         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 653         ctx->csr_core = devm_ioremap_resource(dev, res);
 654         if (IS_ERR(ctx->csr_core))
 655                 return PTR_ERR(ctx->csr_core);
 656
 657         /* Retrieve the IP diagnostic resource */
 658         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 659         ctx->csr_diag = devm_ioremap_resource(dev, res);
 660         if (IS_ERR(ctx->csr_diag))
 661                 return PTR_ERR(ctx->csr_diag);
 662
 663         /* Retrieve the IP AXI resource */
 664         res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
 665         ctx->csr_axi = devm_ioremap_resource(dev, res);
 666         if (IS_ERR(ctx->csr_axi))
 667                 return PTR_ERR(ctx->csr_axi);
 668
 669         /* Retrieve the optional IP mux resource */
 670         res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
 671         if (res) {
 672                 void __iomem *csr = devm_ioremap_resource(dev, res);
 673                 if (IS_ERR(csr))
 674                         return PTR_ERR(csr);
 675
 676                 ctx->csr_mux = csr;
 677         }
 678
 679         dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
 680                 hpriv->mmio);
 681
 682         /* Select ATA */
 683         if ((rc = xgene_ahci_mux_select(ctx))) {
 684                 dev_err(dev, "SATA mux selection failed error %d\n", rc);
 685                 return -ENODEV;
 686         }
 687
 688         if (xgene_ahci_is_memram_inited(ctx)) {
 689                 dev_info(dev, "skip clock and PHY initialization\n");
 690                 goto skip_clk_phy;
 691         }
 692
 693         /* Due to errata, HW requires full toggle transition */
 694         rc = ahci_platform_enable_clks(hpriv);
 695         if (rc)
 696                 goto disable_resources;
 697         ahci_platform_disable_clks(hpriv);
 698
 699         rc = ahci_platform_enable_resources(hpriv);
 700         if (rc)
 701                 goto disable_resources;
 702
 703         /* Configure the host controller */
 704         xgene_ahci_hw_init(hpriv);
 705 skip_clk_phy:
 706         hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ;
 707
 708         rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info,
 709                                      &ahci_platform_sht);
 710         if (rc)
 711                 goto disable_resources;
 712
 713         dev_dbg(dev, "X-Gene SATA host controller initialized\n");
 714         return 0;
 715
 716 disable_resources:
 717         ahci_platform_disable_resources(hpriv);
 718         return rc;
 719 }
 720
 721 static const struct of_device_id xgene_ahci_of_match[] = {
 722         {.compatible = "apm,xgene-ahci"},
 723         {},
 724 };
 725 MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
 726
 727 static struct platform_driver xgene_ahci_driver = {
 728         .probe = xgene_ahci_probe,
 729         .remove = ata_platform_remove_one,
 730         .driver = {
 731                 .name = DRV_NAME,
 732                 .of_match_table = xgene_ahci_of_match,
 733         },
 734 };
 735
 736 module_platform_driver(xgene_ahci_driver);
 737
 738 MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
 739 MODULE_AUTHOR("Loc Ho <lho@apm.com>");
 740 MODULE_LICENSE("GPL");
 741 MODULE_VERSION("0.4");