drivers/gpu/drm/nouveau/dispnv04/tvnv17.h

   1 /*
   2  * Copyright (C) 2009 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef __NV17_TV_H__
  28 #define __NV17_TV_H__
  29
  30 struct nv17_tv_state {
  31         uint8_t tv_enc[0x40];
  32
  33         uint32_t hfilter[4][7];
  34         uint32_t hfilter2[4][7];
  35         uint32_t vfilter[4][7];
  36
  37         uint32_t ptv_200;
  38         uint32_t ptv_204;
  39         uint32_t ptv_208;
  40         uint32_t ptv_20c;
  41         uint32_t ptv_304;
  42         uint32_t ptv_500;
  43         uint32_t ptv_504;
  44         uint32_t ptv_508;
  45         uint32_t ptv_600;
  46         uint32_t ptv_604;
  47         uint32_t ptv_608;
  48         uint32_t ptv_60c;
  49         uint32_t ptv_610;
  50         uint32_t ptv_614;
  51 };
  52
  53 enum nv17_tv_norm{
  54         TV_NORM_PAL,
  55         TV_NORM_PAL_M,
  56         TV_NORM_PAL_N,
  57         TV_NORM_PAL_NC,
  58         TV_NORM_NTSC_M,
  59         TV_NORM_NTSC_J,
  60         NUM_LD_TV_NORMS,
  61         TV_NORM_HD480I = NUM_LD_TV_NORMS,
  62         TV_NORM_HD480P,
  63         TV_NORM_HD576I,
  64         TV_NORM_HD576P,
  65         TV_NORM_HD720P,
  66         TV_NORM_HD1080I,
  67         NUM_TV_NORMS
  68 };
  69
  70 struct nv17_tv_encoder {
  71         struct nouveau_encoder base;
  72
  73         struct nv17_tv_state state;
  74         struct nv17_tv_state saved_state;
  75
  76         int overscan;
  77         int flicker;
  78         int saturation;
  79         int hue;
  80         enum nv17_tv_norm tv_norm;
  81         int subconnector;
  82         int select_subconnector;
  83         uint32_t pin_mask;
  84 };
  85 #define to_tv_enc(x) container_of(nouveau_encoder(x),           \
  86                                   struct nv17_tv_encoder, base)
  87
  88 extern char *nv17_tv_norm_names[NUM_TV_NORMS];
  89
  90 extern struct nv17_tv_norm_params {
  91         enum {
  92                 TV_ENC_MODE,
  93                 CTV_ENC_MODE,
  94         } kind;
  95
  96         union {
  97                 struct {
  98                         int hdisplay;
  99                         int vdisplay;
 100                         int vrefresh; /* mHz */
 101
 102                         uint8_t tv_enc[0x40];
 103                 } tv_enc_mode;
 104
 105                 struct {
 106                         struct drm_display_mode mode;
 107
 108                         uint32_t ctv_regs[38];
 109                 } ctv_enc_mode;
 110         };
 111
 112 } nv17_tv_norms[NUM_TV_NORMS];
 113 #define get_tv_norm(enc) (&nv17_tv_norms[to_tv_enc(enc)->tv_norm])
 114
 115 extern const struct drm_display_mode nv17_tv_modes[];
 116
 117 static inline int interpolate(int y0, int y1, int y2, int x)
 118 {
 119         return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50;
 120 }
 121
 122 void nv17_tv_state_save(struct drm_device *dev, struct nv17_tv_state *state);
 123 void nv17_tv_state_load(struct drm_device *dev, struct nv17_tv_state *state);
 124 void nv17_tv_update_properties(struct drm_encoder *encoder);
 125 void nv17_tv_update_rescaler(struct drm_encoder *encoder);
 126 void nv17_ctv_update_rescaler(struct drm_encoder *encoder);
 127
 128 /* TV hardware access functions */
 129
 130 static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg,
 131                                 uint32_t val)
 132 {
 133         struct nvif_device *device = &nouveau_drm(dev)->device;
 134         nvif_wr32(device, reg, val);
 135 }
 136
 137 static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg)
 138 {
 139         struct nvif_device *device = &nouveau_drm(dev)->device;
 140         return nvif_rd32(device, reg);
 141 }
 142
 143 static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg,
 144                                    uint8_t val)
 145 {
 146         nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
 147         nv_write_ptv(dev, NV_PTV_TV_DATA, val);
 148 }
 149
 150 static inline uint8_t nv_read_tv_enc(struct drm_device *dev, uint8_t reg)
 151 {
 152         nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
 153         return nv_read_ptv(dev, NV_PTV_TV_DATA);
 154 }
 155
 156 #define nv_load_ptv(dev, state, reg) \
 157         nv_write_ptv(dev, NV_PTV_OFFSET + 0x##reg, state->ptv_##reg)
 158 #define nv_save_ptv(dev, state, reg) \
 159         state->ptv_##reg = nv_read_ptv(dev, NV_PTV_OFFSET + 0x##reg)
 160 #define nv_load_tv_enc(dev, state, reg) \
 161         nv_write_tv_enc(dev, 0x##reg, state->tv_enc[0x##reg])
 162
 163 #endif