ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nv10_fence.c
blob5e1ea1cdce75e907ccc75b25830be9b969daa339
1 /*
2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
25 #include "nouveau_drm.h"
26 #include "nouveau_dma.h"
27 #include "nv10_fence.h"
29 int
30 nv10_fence_emit(struct nouveau_fence *fence)
32 struct nouveau_channel *chan = fence->channel;
33 int ret = RING_SPACE(chan, 2);
34 if (ret == 0) {
35 BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
36 OUT_RING (chan, fence->base.seqno);
37 FIRE_RING (chan);
39 return ret;
43 static int
44 nv10_fence_sync(struct nouveau_fence *fence,
45 struct nouveau_channel *prev, struct nouveau_channel *chan)
47 return -ENODEV;
50 u32
51 nv10_fence_read(struct nouveau_channel *chan)
53 return nvif_rd32(chan, 0x0048);
56 void
57 nv10_fence_context_del(struct nouveau_channel *chan)
59 struct nv10_fence_chan *fctx = chan->fence;
60 int i;
61 nouveau_fence_context_del(&fctx->base);
62 for (i = 0; i < ARRAY_SIZE(fctx->head); i++)
63 nvif_object_fini(&fctx->head[i]);
64 nvif_object_fini(&fctx->sema);
65 chan->fence = NULL;
66 nouveau_fence_context_free(&fctx->base);
69 int
70 nv10_fence_context_new(struct nouveau_channel *chan)
72 struct nv10_fence_chan *fctx;
74 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
75 if (!fctx)
76 return -ENOMEM;
78 nouveau_fence_context_new(chan, &fctx->base);
79 fctx->base.emit = nv10_fence_emit;
80 fctx->base.read = nv10_fence_read;
81 fctx->base.sync = nv10_fence_sync;
82 return 0;
85 void
86 nv10_fence_destroy(struct nouveau_drm *drm)
88 struct nv10_fence_priv *priv = drm->fence;
89 nouveau_bo_unmap(priv->bo);
90 if (priv->bo)
91 nouveau_bo_unpin(priv->bo);
92 nouveau_bo_ref(NULL, &priv->bo);
93 drm->fence = NULL;
94 kfree(priv);
97 int
98 nv10_fence_create(struct nouveau_drm *drm)
100 struct nv10_fence_priv *priv;
102 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
103 if (!priv)
104 return -ENOMEM;
106 priv->base.dtor = nv10_fence_destroy;
107 priv->base.context_new = nv10_fence_context_new;
108 priv->base.context_del = nv10_fence_context_del;
109 priv->base.contexts = 31;
110 priv->base.context_base = fence_context_alloc(priv->base.contexts);
111 spin_lock_init(&priv->lock);
112 return 0;