ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nv50_fbcon.c
blob394c89abcc97d92cf1b0352ea6e060b9ee011027
1 /*
2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs
25 #include "nouveau_drm.h"
26 #include "nouveau_dma.h"
27 #include "nouveau_fbcon.h"
29 int
30 nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
32 struct nouveau_fbdev *nfbdev = info->par;
33 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
34 struct nouveau_channel *chan = drm->channel;
35 int ret;
37 ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11);
38 if (ret)
39 return ret;
41 if (rect->rop != ROP_COPY) {
42 BEGIN_NV04(chan, NvSub2D, 0x02ac, 1);
43 OUT_RING(chan, 1);
45 BEGIN_NV04(chan, NvSub2D, 0x0588, 1);
46 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
47 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
48 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
49 else
50 OUT_RING(chan, rect->color);
51 BEGIN_NV04(chan, NvSub2D, 0x0600, 4);
52 OUT_RING(chan, rect->dx);
53 OUT_RING(chan, rect->dy);
54 OUT_RING(chan, rect->dx + rect->width);
55 OUT_RING(chan, rect->dy + rect->height);
56 if (rect->rop != ROP_COPY) {
57 BEGIN_NV04(chan, NvSub2D, 0x02ac, 1);
58 OUT_RING(chan, 3);
60 FIRE_RING(chan);
61 return 0;
64 int
65 nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
67 struct nouveau_fbdev *nfbdev = info->par;
68 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
69 struct nouveau_channel *chan = drm->channel;
70 int ret;
72 ret = RING_SPACE(chan, 12);
73 if (ret)
74 return ret;
76 BEGIN_NV04(chan, NvSub2D, 0x0110, 1);
77 OUT_RING(chan, 0);
78 BEGIN_NV04(chan, NvSub2D, 0x08b0, 4);
79 OUT_RING(chan, region->dx);
80 OUT_RING(chan, region->dy);
81 OUT_RING(chan, region->width);
82 OUT_RING(chan, region->height);
83 BEGIN_NV04(chan, NvSub2D, 0x08d0, 4);
84 OUT_RING(chan, 0);
85 OUT_RING(chan, region->sx);
86 OUT_RING(chan, 0);
87 OUT_RING(chan, region->sy);
88 FIRE_RING(chan);
89 return 0;
92 int
93 nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
95 struct nouveau_fbdev *nfbdev = info->par;
96 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
97 struct nouveau_channel *chan = drm->channel;
98 uint32_t width, dwords, *data = (uint32_t *)image->data;
99 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
100 uint32_t *palette = info->pseudo_palette;
101 int ret;
103 if (image->depth != 1)
104 return -ENODEV;
106 ret = RING_SPACE(chan, 11);
107 if (ret)
108 return ret;
110 width = ALIGN(image->width, 32);
111 dwords = (width * image->height) >> 5;
113 BEGIN_NV04(chan, NvSub2D, 0x0814, 2);
114 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
115 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
116 OUT_RING(chan, palette[image->bg_color] | mask);
117 OUT_RING(chan, palette[image->fg_color] | mask);
118 } else {
119 OUT_RING(chan, image->bg_color);
120 OUT_RING(chan, image->fg_color);
122 BEGIN_NV04(chan, NvSub2D, 0x0838, 2);
123 OUT_RING(chan, image->width);
124 OUT_RING(chan, image->height);
125 BEGIN_NV04(chan, NvSub2D, 0x0850, 4);
126 OUT_RING(chan, 0);
127 OUT_RING(chan, image->dx);
128 OUT_RING(chan, 0);
129 OUT_RING(chan, image->dy);
131 while (dwords) {
132 int push = dwords > 2047 ? 2047 : dwords;
134 ret = RING_SPACE(chan, push + 1);
135 if (ret)
136 return ret;
138 dwords -= push;
140 BEGIN_NI04(chan, NvSub2D, 0x0860, push);
141 OUT_RINGp(chan, data, push);
142 data += push;
145 FIRE_RING(chan);
146 return 0;
150 nv50_fbcon_accel_init(struct fb_info *info)
152 struct nouveau_fbdev *nfbdev = info->par;
153 struct nouveau_framebuffer *fb = &nfbdev->nouveau_fb;
154 struct drm_device *dev = nfbdev->dev;
155 struct nouveau_drm *drm = nouveau_drm(dev);
156 struct nouveau_channel *chan = drm->channel;
157 int ret, format;
159 switch (info->var.bits_per_pixel) {
160 case 8:
161 format = 0xf3;
162 break;
163 case 15:
164 format = 0xf8;
165 break;
166 case 16:
167 format = 0xe8;
168 break;
169 case 32:
170 switch (info->var.transp.length) {
171 case 0: /* depth 24 */
172 case 8: /* depth 32, just use 24.. */
173 format = 0xe6;
174 break;
175 case 2: /* depth 30 */
176 format = 0xd1;
177 break;
178 default:
179 return -EINVAL;
181 break;
182 default:
183 return -EINVAL;
186 ret = nvif_object_init(chan->object, NULL, 0x502d, 0x502d, NULL, 0,
187 &nfbdev->twod);
188 if (ret)
189 return ret;
191 ret = RING_SPACE(chan, 59);
192 if (ret) {
193 nouveau_fbcon_gpu_lockup(info);
194 return ret;
197 BEGIN_NV04(chan, NvSub2D, 0x0000, 1);
198 OUT_RING(chan, nfbdev->twod.handle);
199 BEGIN_NV04(chan, NvSub2D, 0x0184, 3);
200 OUT_RING(chan, chan->vram.handle);
201 OUT_RING(chan, chan->vram.handle);
202 OUT_RING(chan, chan->vram.handle);
203 BEGIN_NV04(chan, NvSub2D, 0x0290, 1);
204 OUT_RING(chan, 0);
205 BEGIN_NV04(chan, NvSub2D, 0x0888, 1);
206 OUT_RING(chan, 1);
207 BEGIN_NV04(chan, NvSub2D, 0x02ac, 1);
208 OUT_RING(chan, 3);
209 BEGIN_NV04(chan, NvSub2D, 0x02a0, 1);
210 OUT_RING(chan, 0x55);
211 BEGIN_NV04(chan, NvSub2D, 0x08c0, 4);
212 OUT_RING(chan, 0);
213 OUT_RING(chan, 1);
214 OUT_RING(chan, 0);
215 OUT_RING(chan, 1);
216 BEGIN_NV04(chan, NvSub2D, 0x0580, 2);
217 OUT_RING(chan, 4);
218 OUT_RING(chan, format);
219 BEGIN_NV04(chan, NvSub2D, 0x02e8, 2);
220 OUT_RING(chan, 2);
221 OUT_RING(chan, 1);
222 BEGIN_NV04(chan, NvSub2D, 0x0804, 1);
223 OUT_RING(chan, format);
224 BEGIN_NV04(chan, NvSub2D, 0x0800, 1);
225 OUT_RING(chan, 1);
226 BEGIN_NV04(chan, NvSub2D, 0x0808, 3);
227 OUT_RING(chan, 0);
228 OUT_RING(chan, 0);
229 OUT_RING(chan, 1);
230 BEGIN_NV04(chan, NvSub2D, 0x081c, 1);
231 OUT_RING(chan, 1);
232 BEGIN_NV04(chan, NvSub2D, 0x0840, 4);
233 OUT_RING(chan, 0);
234 OUT_RING(chan, 1);
235 OUT_RING(chan, 0);
236 OUT_RING(chan, 1);
237 BEGIN_NV04(chan, NvSub2D, 0x0200, 2);
238 OUT_RING(chan, format);
239 OUT_RING(chan, 1);
240 BEGIN_NV04(chan, NvSub2D, 0x0214, 5);
241 OUT_RING(chan, info->fix.line_length);
242 OUT_RING(chan, info->var.xres_virtual);
243 OUT_RING(chan, info->var.yres_virtual);
244 OUT_RING(chan, upper_32_bits(fb->vma.offset));
245 OUT_RING(chan, lower_32_bits(fb->vma.offset));
246 BEGIN_NV04(chan, NvSub2D, 0x0230, 2);
247 OUT_RING(chan, format);
248 OUT_RING(chan, 1);
249 BEGIN_NV04(chan, NvSub2D, 0x0244, 5);
250 OUT_RING(chan, info->fix.line_length);
251 OUT_RING(chan, info->var.xres_virtual);
252 OUT_RING(chan, info->var.yres_virtual);
253 OUT_RING(chan, upper_32_bits(fb->vma.offset));
254 OUT_RING(chan, lower_32_bits(fb->vma.offset));
256 return 0;