drivers/gpu/drm/nouveau/nvkm/core/ramht.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include <core/ramht.h>
  23 #include <core/engine.h>
  24
  25 #include <subdev/bar.h>
  26
  27 static u32
  28 nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle)
  29 {
  30         u32 hash = 0;
  31
  32         while (handle) {
  33                 hash ^= (handle & ((1 << ramht->bits) - 1));
  34                 handle >>= ramht->bits;
  35         }
  36
  37         hash ^= chid << (ramht->bits - 4);
  38         hash  = hash << 3;
  39         return hash;
  40 }
  41
  42 int
  43 nvkm_ramht_insert(struct nvkm_ramht *ramht, int chid, u32 handle, u32 context)
  44 {
  45         struct nvkm_bar *bar = nvkm_bar(ramht);
  46         u32 co, ho;
  47
  48         co = ho = nvkm_ramht_hash(ramht, chid, handle);
  49         do {
  50                 if (!nv_ro32(ramht, co + 4)) {
  51                         nv_wo32(ramht, co + 0, handle);
  52                         nv_wo32(ramht, co + 4, context);
  53                         if (bar)
  54                                 bar->flush(bar);
  55                         return co;
  56                 }
  57
  58                 co += 8;
  59                 if (co >= nv_gpuobj(ramht)->size)
  60                         co = 0;
  61         } while (co != ho);
  62
  63         return -ENOMEM;
  64 }
  65
  66 void
  67 nvkm_ramht_remove(struct nvkm_ramht *ramht, int cookie)
  68 {
  69         struct nvkm_bar *bar = nvkm_bar(ramht);
  70         nv_wo32(ramht, cookie + 0, 0x00000000);
  71         nv_wo32(ramht, cookie + 4, 0x00000000);
  72         if (bar)
  73                 bar->flush(bar);
  74 }
  75
  76 static struct nvkm_oclass
  77 nvkm_ramht_oclass = {
  78         .handle = 0x0000abcd,
  79         .ofuncs = &(struct nvkm_ofuncs) {
  80                 .ctor = NULL,
  81                 .dtor = _nvkm_gpuobj_dtor,
  82                 .init = _nvkm_gpuobj_init,
  83                 .fini = _nvkm_gpuobj_fini,
  84                 .rd32 = _nvkm_gpuobj_rd32,
  85                 .wr32 = _nvkm_gpuobj_wr32,
  86         },
  87 };
  88
  89 int
  90 nvkm_ramht_new(struct nvkm_object *parent, struct nvkm_object *pargpu,
  91                u32 size, u32 align, struct nvkm_ramht **pramht)
  92 {
  93         struct nvkm_ramht *ramht;
  94         int ret;
  95
  96         ret = nvkm_gpuobj_create(parent, parent->engine ?
  97                                  &parent->engine->subdev.object : parent, /* <nv50 ramht */
  98                                  &nvkm_ramht_oclass, 0, pargpu, size,
  99                                  align, NVOBJ_FLAG_ZERO_ALLOC, &ramht);
 100         *pramht = ramht;
 101         if (ret)
 102                 return ret;
 103
 104         ramht->bits = order_base_2(nv_gpuobj(ramht)->size >> 3);
 105         return 0;
 106 }