ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvkm / engine / cipher / g84.c
blob13f30428a30518dacc0b904d82bb5e9061f7d19a
1 /*
2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs
24 #include <engine/cipher.h>
25 #include <engine/fifo.h>
27 #include <core/client.h>
28 #include <core/engctx.h>
29 #include <core/enum.h>
31 struct g84_cipher_priv {
32 struct nvkm_engine base;
35 /*******************************************************************************
36 * Crypt object classes
37 ******************************************************************************/
39 static int
40 g84_cipher_object_ctor(struct nvkm_object *parent,
41 struct nvkm_object *engine,
42 struct nvkm_oclass *oclass, void *data, u32 size,
43 struct nvkm_object **pobject)
45 struct nvkm_gpuobj *obj;
46 int ret;
48 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
49 16, 16, 0, &obj);
50 *pobject = nv_object(obj);
51 if (ret)
52 return ret;
54 nv_wo32(obj, 0x00, nv_mclass(obj));
55 nv_wo32(obj, 0x04, 0x00000000);
56 nv_wo32(obj, 0x08, 0x00000000);
57 nv_wo32(obj, 0x0c, 0x00000000);
58 return 0;
61 static struct nvkm_ofuncs
62 g84_cipher_ofuncs = {
63 .ctor = g84_cipher_object_ctor,
64 .dtor = _nvkm_gpuobj_dtor,
65 .init = _nvkm_gpuobj_init,
66 .fini = _nvkm_gpuobj_fini,
67 .rd32 = _nvkm_gpuobj_rd32,
68 .wr32 = _nvkm_gpuobj_wr32,
71 static struct nvkm_oclass
72 g84_cipher_sclass[] = {
73 { 0x74c1, &g84_cipher_ofuncs },
77 /*******************************************************************************
78 * PCIPHER context
79 ******************************************************************************/
81 static struct nvkm_oclass
82 g84_cipher_cclass = {
83 .handle = NV_ENGCTX(CIPHER, 0x84),
84 .ofuncs = &(struct nvkm_ofuncs) {
85 .ctor = _nvkm_engctx_ctor,
86 .dtor = _nvkm_engctx_dtor,
87 .init = _nvkm_engctx_init,
88 .fini = _nvkm_engctx_fini,
89 .rd32 = _nvkm_engctx_rd32,
90 .wr32 = _nvkm_engctx_wr32,
94 /*******************************************************************************
95 * PCIPHER engine/subdev functions
96 ******************************************************************************/
98 static const struct nvkm_bitfield
99 g84_cipher_intr_mask[] = {
100 { 0x00000001, "INVALID_STATE" },
101 { 0x00000002, "ILLEGAL_MTHD" },
102 { 0x00000004, "ILLEGAL_CLASS" },
103 { 0x00000080, "QUERY" },
104 { 0x00000100, "FAULT" },
108 static void
109 g84_cipher_intr(struct nvkm_subdev *subdev)
111 struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
112 struct nvkm_engine *engine = nv_engine(subdev);
113 struct nvkm_object *engctx;
114 struct g84_cipher_priv *priv = (void *)subdev;
115 u32 stat = nv_rd32(priv, 0x102130);
116 u32 mthd = nv_rd32(priv, 0x102190);
117 u32 data = nv_rd32(priv, 0x102194);
118 u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff;
119 int chid;
121 engctx = nvkm_engctx_get(engine, inst);
122 chid = pfifo->chid(pfifo, engctx);
124 if (stat) {
125 nv_error(priv, "%s", "");
126 nvkm_bitfield_print(g84_cipher_intr_mask, stat);
127 pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
128 chid, (u64)inst << 12, nvkm_client_name(engctx),
129 mthd, data);
132 nv_wr32(priv, 0x102130, stat);
133 nv_wr32(priv, 0x10200c, 0x10);
135 nvkm_engctx_put(engctx);
138 static int
139 g84_cipher_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
140 struct nvkm_oclass *oclass, void *data, u32 size,
141 struct nvkm_object **pobject)
143 struct g84_cipher_priv *priv;
144 int ret;
146 ret = nvkm_engine_create(parent, engine, oclass, true,
147 "PCIPHER", "cipher", &priv);
148 *pobject = nv_object(priv);
149 if (ret)
150 return ret;
152 nv_subdev(priv)->unit = 0x00004000;
153 nv_subdev(priv)->intr = g84_cipher_intr;
154 nv_engine(priv)->cclass = &g84_cipher_cclass;
155 nv_engine(priv)->sclass = g84_cipher_sclass;
156 return 0;
159 static int
160 g84_cipher_init(struct nvkm_object *object)
162 struct g84_cipher_priv *priv = (void *)object;
163 int ret;
165 ret = nvkm_engine_init(&priv->base);
166 if (ret)
167 return ret;
169 nv_wr32(priv, 0x102130, 0xffffffff);
170 nv_wr32(priv, 0x102140, 0xffffffbf);
171 nv_wr32(priv, 0x10200c, 0x00000010);
172 return 0;
175 struct nvkm_oclass
176 g84_cipher_oclass = {
177 .handle = NV_ENGINE(CIPHER, 0x84),
178 .ofuncs = &(struct nvkm_ofuncs) {
179 .ctor = g84_cipher_ctor,
180 .dtor = _nvkm_engine_dtor,
181 .init = g84_cipher_init,
182 .fini = _nvkm_engine_fini,