drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 #include <core/client.h>
  27 #include <core/gpuobj.h>
  28 #include <subdev/fb.h>
  29
  30 #include <nvif/class.h>
  31 #include <nvif/unpack.h>
  32
  33 struct nv50_dmaobj_priv {
  34         struct nvkm_dmaobj base;
  35         u32 flags0;
  36         u32 flags5;
  37 };
  38
  39 static int
  40 nv50_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
  41                  struct nvkm_gpuobj **pgpuobj)
  42 {
  43         struct nv50_dmaobj_priv *priv = (void *)dmaobj;
  44         int ret;
  45
  46         if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
  47                 switch (nv_mclass(parent->parent)) {
  48                 case NV40_CHANNEL_DMA:
  49                 case NV50_CHANNEL_GPFIFO:
  50                 case G82_CHANNEL_GPFIFO:
  51                 case NV50_DISP_CORE_CHANNEL_DMA:
  52                 case G82_DISP_CORE_CHANNEL_DMA:
  53                 case GT206_DISP_CORE_CHANNEL_DMA:
  54                 case GT200_DISP_CORE_CHANNEL_DMA:
  55                 case GT214_DISP_CORE_CHANNEL_DMA:
  56                 case NV50_DISP_BASE_CHANNEL_DMA:
  57                 case G82_DISP_BASE_CHANNEL_DMA:
  58                 case GT200_DISP_BASE_CHANNEL_DMA:
  59                 case GT214_DISP_BASE_CHANNEL_DMA:
  60                 case NV50_DISP_OVERLAY_CHANNEL_DMA:
  61                 case G82_DISP_OVERLAY_CHANNEL_DMA:
  62                 case GT200_DISP_OVERLAY_CHANNEL_DMA:
  63                 case GT214_DISP_OVERLAY_CHANNEL_DMA:
  64                         break;
  65                 default:
  66                         return -EINVAL;
  67                 }
  68         }
  69
  70         ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
  71         if (ret == 0) {
  72                 nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
  73                 nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
  74                 nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
  75                 nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
  76                                         upper_32_bits(priv->base.start));
  77                 nv_wo32(*pgpuobj, 0x10, 0x00000000);
  78                 nv_wo32(*pgpuobj, 0x14, priv->flags5);
  79         }
  80
  81         return ret;
  82 }
  83
  84 static int
  85 nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  86                  struct nvkm_oclass *oclass, void *data, u32 size,
  87                  struct nvkm_object **pobject)
  88 {
  89         struct nvkm_dmaeng *dmaeng = (void *)engine;
  90         union {
  91                 struct nv50_dma_v0 v0;
  92         } *args;
  93         struct nv50_dmaobj_priv *priv;
  94         u32 user, part, comp, kind;
  95         int ret;
  96
  97         ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
  98         *pobject = nv_object(priv);
  99         if (ret)
 100                 return ret;
 101         args = data;
 102
 103         nv_ioctl(parent, "create nv50 dma size %d\n", size);
 104         if (nvif_unpack(args->v0, 0, 0, false)) {
 105                 nv_ioctl(parent, "create nv50 dma vers %d priv %d part %d "
 106                                  "comp %d kind %02x\n", args->v0.version,
 107                          args->v0.priv, args->v0.part, args->v0.comp,
 108                          args->v0.kind);
 109                 user = args->v0.priv;
 110                 part = args->v0.part;
 111                 comp = args->v0.comp;
 112                 kind = args->v0.kind;
 113         } else
 114         if (size == 0) {
 115                 if (priv->base.target != NV_MEM_TARGET_VM) {
 116                         user = NV50_DMA_V0_PRIV_US;
 117                         part = NV50_DMA_V0_PART_256;
 118                         comp = NV50_DMA_V0_COMP_NONE;
 119                         kind = NV50_DMA_V0_KIND_PITCH;
 120                 } else {
 121                         user = NV50_DMA_V0_PRIV_VM;
 122                         part = NV50_DMA_V0_PART_VM;
 123                         comp = NV50_DMA_V0_COMP_VM;
 124                         kind = NV50_DMA_V0_KIND_VM;
 125                 }
 126         } else
 127                 return ret;
 128
 129         if (user > 2 || part > 2 || comp > 3 || kind > 0x7f)
 130                 return -EINVAL;
 131         priv->flags0 = (comp << 29) | (kind << 22) | (user << 20);
 132         priv->flags5 = (part << 16);
 133
 134         switch (priv->base.target) {
 135         case NV_MEM_TARGET_VM:
 136                 priv->flags0 |= 0x00000000;
 137                 break;
 138         case NV_MEM_TARGET_VRAM:
 139                 priv->flags0 |= 0x00010000;
 140                 break;
 141         case NV_MEM_TARGET_PCI:
 142                 priv->flags0 |= 0x00020000;
 143                 break;
 144         case NV_MEM_TARGET_PCI_NOSNOOP:
 145                 priv->flags0 |= 0x00030000;
 146                 break;
 147         default:
 148                 return -EINVAL;
 149         }
 150
 151         switch (priv->base.access) {
 152         case NV_MEM_ACCESS_VM:
 153                 break;
 154         case NV_MEM_ACCESS_RO:
 155                 priv->flags0 |= 0x00040000;
 156                 break;
 157         case NV_MEM_ACCESS_WO:
 158         case NV_MEM_ACCESS_RW:
 159                 priv->flags0 |= 0x00080000;
 160                 break;
 161         default:
 162                 return -EINVAL;
 163         }
 164
 165         return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
 166 }
 167
 168 static struct nvkm_ofuncs
 169 nv50_dmaobj_ofuncs = {
 170         .ctor =  nv50_dmaobj_ctor,
 171         .dtor = _nvkm_dmaobj_dtor,
 172         .init = _nvkm_dmaobj_init,
 173         .fini = _nvkm_dmaobj_fini,
 174 };
 175
 176 static struct nvkm_oclass
 177 nv50_dmaeng_sclass[] = {
 178         { NV_DMA_FROM_MEMORY, &nv50_dmaobj_ofuncs },
 179         { NV_DMA_TO_MEMORY, &nv50_dmaobj_ofuncs },
 180         { NV_DMA_IN_MEMORY, &nv50_dmaobj_ofuncs },
 181         {}
 182 };
 183
 184 struct nvkm_oclass *
 185 nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
 186         .base.handle = NV_ENGINE(DMAOBJ, 0x50),
 187         .base.ofuncs = &(struct nvkm_ofuncs) {
 188                 .ctor = _nvkm_dmaeng_ctor,
 189                 .dtor = _nvkm_dmaeng_dtor,
 190                 .init = _nvkm_dmaeng_init,
 191                 .fini = _nvkm_dmaeng_fini,
 192         },
 193         .sclass = nv50_dmaeng_sclass,
 194         .bind = nv50_dmaobj_bind,
 195 }.base;