drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 static void
  27 pwr_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
  28                  struct nvkm_perfctr *ctr)
  29 {
  30         u32 mask = 0x00000000;
  31         u32 ctrl = 0x00000001;
  32         int i;
  33
  34         for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++)
  35                 mask |= 1 << (ctr->signal[i] - dom->signal);
  36
  37         nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask);
  38         nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl);
  39         nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003);
  40 }
  41
  42 static void
  43 pwr_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
  44                  struct nvkm_perfctr *ctr)
  45 {
  46         ctr->ctr = ppm->pwr[ctr->slot];
  47         ctr->clk = ppm->pwr[ppm->last];
  48 }
  49
  50 static void
  51 pwr_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
  52 {
  53         int i;
  54
  55         for (i = 0; i <= ppm->last; i++) {
  56                 ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
  57                 nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000);
  58         }
  59 }
  60
  61 static const struct nvkm_funcdom
  62 pwr_perfctr_func = {
  63         .init = pwr_perfctr_init,
  64         .read = pwr_perfctr_read,
  65         .next = pwr_perfctr_next,
  66 };
  67
  68 const struct nvkm_specdom
  69 gt215_pm_pwr[] = {
  70         { 0x20, (const struct nvkm_specsig[]) {
  71                         { 0x00, "pwr_gr_idle" },
  72                         { 0x04, "pwr_bsp_idle" },
  73                         { 0x05, "pwr_vp_idle" },
  74                         { 0x06, "pwr_ppp_idle" },
  75                         { 0x13, "pwr_ce0_idle" },
  76                         {}
  77                 }, &pwr_perfctr_func },
  78         {}
  79 };
  80
  81 const struct nvkm_specdom
  82 gf100_pm_pwr[] = {
  83         { 0x20, (const struct nvkm_specsig[]) {
  84                         { 0x00, "pwr_gr_idle" },
  85                         { 0x04, "pwr_bsp_idle" },
  86                         { 0x05, "pwr_vp_idle" },
  87                         { 0x06, "pwr_ppp_idle" },
  88                         { 0x13, "pwr_ce0_idle" },
  89                         { 0x14, "pwr_ce1_idle" },
  90                         {}
  91                 }, &pwr_perfctr_func },
  92         {}
  93 };
  94
  95 const struct nvkm_specdom
  96 gk104_pm_pwr[] = {
  97         { 0x20, (const struct nvkm_specsig[]) {
  98                         { 0x00, "pwr_gr_idle" },
  99                         { 0x04, "pwr_bsp_idle" },
 100                         { 0x05, "pwr_vp_idle" },
 101                         { 0x06, "pwr_ppp_idle" },
 102                         { 0x13, "pwr_ce0_idle" },
 103                         { 0x14, "pwr_ce1_idle" },
 104                         { 0x15, "pwr_ce2_idle" },
 105                         {}
 106                 }, &pwr_perfctr_func },
 107         {}
 108 };