ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvkm / engine / sw / nv10.c
blobc61153a3fb8ba410ba08f4f1f388cd6e62de412a
1 /*
2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs
24 #include <engine/sw.h>
26 struct nv10_sw_priv {
27 struct nvkm_sw base;
30 struct nv10_sw_chan {
31 struct nvkm_sw_chan base;
34 /*******************************************************************************
35 * software object classes
36 ******************************************************************************/
38 static int
39 nv10_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
41 struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent);
42 if (chan->base.flip)
43 return chan->base.flip(chan->base.flip_data);
44 return -EINVAL;
47 static struct nvkm_omthds
48 nv10_sw_omthds[] = {
49 { 0x0500, 0x0500, nv10_sw_flip },
53 static struct nvkm_oclass
54 nv10_sw_sclass[] = {
55 { 0x016e, &nvkm_object_ofuncs, nv10_sw_omthds },
59 /*******************************************************************************
60 * software context
61 ******************************************************************************/
63 static int
64 nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
65 struct nvkm_oclass *oclass, void *data, u32 size,
66 struct nvkm_object **pobject)
68 struct nv10_sw_chan *chan;
69 int ret;
71 ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
72 *pobject = nv_object(chan);
73 if (ret)
74 return ret;
76 return 0;
79 static struct nvkm_oclass
80 nv10_sw_cclass = {
81 .handle = NV_ENGCTX(SW, 0x04),
82 .ofuncs = &(struct nvkm_ofuncs) {
83 .ctor = nv10_sw_context_ctor,
84 .dtor = _nvkm_sw_context_dtor,
85 .init = _nvkm_sw_context_init,
86 .fini = _nvkm_sw_context_fini,
90 /*******************************************************************************
91 * software engine/subdev functions
92 ******************************************************************************/
94 static int
95 nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
96 struct nvkm_oclass *oclass, void *data, u32 size,
97 struct nvkm_object **pobject)
99 struct nv10_sw_priv *priv;
100 int ret;
102 ret = nvkm_sw_create(parent, engine, oclass, &priv);
103 *pobject = nv_object(priv);
104 if (ret)
105 return ret;
107 nv_engine(priv)->cclass = &nv10_sw_cclass;
108 nv_engine(priv)->sclass = nv10_sw_sclass;
109 nv_subdev(priv)->intr = nv04_sw_intr;
110 return 0;
113 struct nvkm_oclass *
114 nv10_sw_oclass = &(struct nvkm_oclass) {
115 .handle = NV_ENGINE(SW, 0x10),
116 .ofuncs = &(struct nvkm_ofuncs) {
117 .ctor = nv10_sw_ctor,
118 .dtor = _nvkm_sw_dtor,
119 .init = _nvkm_sw_init,
120 .fini = _nvkm_sw_fini,