drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c

   1 /*
   2  * Copyright 2012 Nouveau Community
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Martin Peres
  23  */
  24 #include <subdev/bios.h>
  25 #include <subdev/bios/bit.h>
  26 #include <subdev/bios/volt.h>
  27
  28 u16
  29 nvbios_volt_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
  30 {
  31         struct bit_entry bit_P;
  32         u16 volt = 0x0000;
  33
  34         if (!bit_entry(bios, 'P', &bit_P)) {
  35                 if (bit_P.version == 2)
  36                         volt = nv_ro16(bios, bit_P.offset + 0x0c);
  37                 else
  38                 if (bit_P.version == 1)
  39                         volt = nv_ro16(bios, bit_P.offset + 0x10);
  40
  41                 if (volt) {
  42                         *ver = nv_ro08(bios, volt + 0);
  43                         switch (*ver) {
  44                         case 0x12:
  45                                 *hdr = 5;
  46                                 *cnt = nv_ro08(bios, volt + 2);
  47                                 *len = nv_ro08(bios, volt + 1);
  48                                 return volt;
  49                         case 0x20:
  50                                 *hdr = nv_ro08(bios, volt + 1);
  51                                 *cnt = nv_ro08(bios, volt + 2);
  52                                 *len = nv_ro08(bios, volt + 3);
  53                                 return volt;
  54                         case 0x30:
  55                         case 0x40:
  56                         case 0x50:
  57                                 *hdr = nv_ro08(bios, volt + 1);
  58                                 *cnt = nv_ro08(bios, volt + 3);
  59                                 *len = nv_ro08(bios, volt + 2);
  60                                 return volt;
  61                         }
  62                 }
  63         }
  64
  65         return 0x0000;
  66 }
  67
  68 u16
  69 nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
  70                   struct nvbios_volt *info)
  71 {
  72         u16 volt = nvbios_volt_table(bios, ver, hdr, cnt, len);
  73         memset(info, 0x00, sizeof(*info));
  74         switch (!!volt * *ver) {
  75         case 0x12:
  76                 info->vidmask = nv_ro08(bios, volt + 0x04);
  77                 break;
  78         case 0x20:
  79                 info->vidmask = nv_ro08(bios, volt + 0x05);
  80                 break;
  81         case 0x30:
  82                 info->vidmask = nv_ro08(bios, volt + 0x04);
  83                 break;
  84         case 0x40:
  85                 info->base    = nv_ro32(bios, volt + 0x04);
  86                 info->step    = nv_ro16(bios, volt + 0x08);
  87                 info->vidmask = nv_ro08(bios, volt + 0x0b);
  88                 /*XXX*/
  89                 info->min     = 0;
  90                 info->max     = info->base;
  91                 break;
  92         case 0x50:
  93                 info->vidmask = nv_ro08(bios, volt + 0x06);
  94                 info->min     = nv_ro32(bios, volt + 0x0a);
  95                 info->max     = nv_ro32(bios, volt + 0x0e);
  96                 info->base    = nv_ro32(bios, volt + 0x12) & 0x00ffffff;
  97                 info->step    = nv_ro16(bios, volt + 0x16);
  98                 break;
  99         }
 100         return volt;
 101 }
 102
 103 u16
 104 nvbios_volt_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len)
 105 {
 106         u8  hdr, cnt;
 107         u16 volt = nvbios_volt_table(bios, ver, &hdr, &cnt, len);
 108         if (volt && idx < cnt) {
 109                 volt = volt + hdr + (idx * *len);
 110                 return volt;
 111         }
 112         return 0x0000;
 113 }
 114
 115 u16
 116 nvbios_volt_entry_parse(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len,
 117                         struct nvbios_volt_entry *info)
 118 {
 119         u16 volt = nvbios_volt_entry(bios, idx, ver, len);
 120         memset(info, 0x00, sizeof(*info));
 121         switch (!!volt * *ver) {
 122         case 0x12:
 123         case 0x20:
 124                 info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
 125                 info->vid     = nv_ro08(bios, volt + 0x01);
 126                 break;
 127         case 0x30:
 128                 info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
 129                 info->vid     = nv_ro08(bios, volt + 0x01) >> 2;
 130                 break;
 131         case 0x40:
 132         case 0x50:
 133                 break;
 134         }
 135         return volt;
 136 }