drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c

   1 /*
   2  * Copyright 2012 Nouveau Community
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Martin Peres <martin.peres@labri.fr>
  23  *          Ben Skeggs
  24  */
  25 #include "nv04.h"
  26
  27 #include <subdev/timer.h>
  28
  29 static int
  30 g94_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
  31 {
  32         struct nv50_bus_priv *priv = (void *)pbus;
  33         int i;
  34
  35         nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
  36         nv_wr32(pbus, 0x001304, 0x00000000);
  37         nv_wr32(pbus, 0x001318, 0x00000000);
  38         for (i = 0; i < size; i++)
  39                 nv_wr32(priv, 0x080000 + (i * 4), data[i]);
  40         nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
  41         nv_wr32(pbus, 0x00130c, 0x00000001);
  42
  43         return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
  44 }
  45
  46 struct nvkm_oclass *
  47 g94_bus_oclass = &(struct nv04_bus_impl) {
  48         .base.handle = NV_SUBDEV(BUS, 0x94),
  49         .base.ofuncs = &(struct nvkm_ofuncs) {
  50                 .ctor = nv04_bus_ctor,
  51                 .dtor = _nvkm_bus_dtor,
  52                 .init = nv50_bus_init,
  53                 .fini = _nvkm_bus_fini,
  54         },
  55         .intr = nv50_bus_intr,
  56         .hwsq_exec = g94_bus_hwsq_exec,
  57         .hwsq_size = 128,
  58 }.base;